Dram with improved bit line contact and method of manufacturing the same

TWI936043BActive Publication Date: 2026-08-11POWERCHIP SEMICON MFG CORP
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Patent Information

Application Number
TW114147756
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-02-19
Publication Date
2026-08-11
Estimated Expiration
2045-02-18

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Abstract

This invention proposes a method for manufacturing dynamic random access memory with improved bit line contacts, comprising forming a contact hole in each active region, the contact hole being recessed into the active region and having shallow trench isolation structures on both sides; forming a sacrificial layer on the sidewall of the contact hole; filling the contact hole with a polysilicon layer; performing a photolithography process to pattern the polysilicon layer into a bit line contact and a bit line, each bit line contact being located in a contact hole and in direct contact with the active region; removing the sacrificial layer to form a gap between the bit line contact and the surrounding shallow trench isolation structures; and performing an oxygen annealing process to oxidize the portion of the bit line contact exposed in the gap into an isolation oxide layer.
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Claims

1. A method for manufacturing dynamic random access memory (DRAM) with improved bitline contacts, comprising: providing a substrate having a plurality of active regions defined by shallow trench isolation structures; forming a contact hole in each active region, the contact hole being recessed into the active region and having the shallow trench isolation structures on both sides; forming a sacrificial layer on the sidewall of the contact hole; filling the contact hole with a polysilicon layer, the bottom surface and side surface of the polysilicon layer being in direct contact with the active region and the sacrificial layer, respectively; performing a photolithography process to pattern the polysilicon layer into a bitline contact and a bitline, each bitline contact being located in a contact hole and in direct contact with the active region; removing the sacrificial layer, thereby forming a gap between the bitline contact and the surrounding shallow trench isolation structures, with a portion of the bitline contact exposed from the gap; An oxygen annealing process is performed to oxidize the portion of the bit line contact exposed in the gap into an insulating oxide layer; and a storage node contact is formed on another active region adjacent to the bit line contact, wherein the storage node contact and the bit line contact are separated by the shallow trench isolation structure, the gap, and the insulating oxide layer.

2. The method for manufacturing dynamic random access memory with improved bit line contacts as described in claim 1 further includes sequentially forming a metal layer and a hard mask layer on the polysilicon layer, wherein the photolithography process simultaneously patterns the hard mask layer, the metal layer and the polysilicon layer, wherein the polysilicon layer portion located in the contact hole is patterned into the bit line contact, and the polysilicon layer portion located outside the contact hole and the metal layer are patterned into the bit line.

3. The method for manufacturing dynamic random access memory with improved bit line contacts as described in claim 1 further includes forming a gap-filling insulating layer in the remaining space of the contact hole and forming a first spacer wall on the sidewall of the bit line after the bit line contacts are formed and before the sacrificial layer is removed, and the sacrificial layer is not covered by the gap-filling insulating layer and the first spacer wall.

4. The method for manufacturing a dynamic random access memory with improved bit line contacts as described in claim 3 further includes forming a second spacer wall on the first spacer wall after the isolation oxide layer is formed and before the storage node contacts are formed, and the second spacer wall seals the top opening of the gap.

5. A method for manufacturing dynamic random access memory with improved bit line contacts as described in claim 1, wherein the material of the sacrificial layer is organic amorphous carbon, and the step of removing the sacrificial layer includes selectively removing the sacrificial layer by performing an oxygen ashing process.

6. A method for manufacturing dynamic random access memory with improved bit line contacts as described in claim 1, wherein the sacrificial layer is made of metal, and the step of removing the sacrificial layer includes selectively removing the sacrificial layer using a sulfuric acid / hydrogen peroxide mixture (SPM) or an ammonium hydroxide / hydrogen peroxide mixture (APM).

Citation Information

Patent Citations

  • Semiconductor device structure with air gap structure and method for preparing the same

    TWI786612B

  • Semiconductor device with air gap and method for fabricating the same

    US20190103302A1