Method relating to the design of an electronic circuit

Abstract

Ultra-wideband (UWB) wireless technology transmits digital data as modulated coded pulses over a wide spectrum and short distances with very low power. To support extended operation, particularly via battery power, the inventors have developed UWB devices that support wake-up from deep sleep mode when utilizing ultra-low-power, low-frequency clock sources. Furthermore, power consumption can be reduced by utilizing transistors or so-called composite MOSFET structures (whose effective gain and output resistance exceed that of any single transistor, regardless of length) or by providing a very high-gain, low-power amplification stage within a transconductance operational amplifier using an unbiased, low-power differential (exponential) transconductance stage. Additionally, the inventors have developed voltage reference sources consuming very low current (a few nA) and ultra-low-power, low-dropout regulators.

Description

Technical Field

[0001] This invention pertains to ultra-wideband wireless communication systems, and more specifically to ultra-wideband transmitters and ultra-wideband receivers used in such ultra-wideband wireless communication systems. Prior Technology

[0002] Ultra Wideband (UWB) technology is a wireless technology that transmits large amounts of digital data as modulated-coded pulses over a wide spectrum and short distances at very low power. This type of pulse-based transmission is an alternative to transmission using sine waves, which are then switched on or off to represent a digital state, as is used in current wireless communication standards and systems such as IEEE 802.11 (Wi-Fi), IEEE 802.15 Wireless Personal Area Network (PAN), IEEE 802.16 (WiMAX), Universal Mobile Telecommunications System (UMTS), Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), and those networks accessing the Industrial, Scientific, and Medical (ISM) bands, as well as International Mobile Telecommunications 2000 (IMT-2000).

[0003] UWB systems are well-suited for short-range applications in a variety of environments, such as those depicted in Figure 1, including peripheral and device interconnection exemplified by the first residential environment 110, sensor networks exemplified by the second residential environment 120, control and communication exemplified by the industrial environment 130, medical systems exemplified by medical imaging 150, and PANs exemplified by Personal Area Networks (PANs) 140. Due to the low emission levels permitted by regulatory bodies, such UWB systems tend to be suited for short-range indoor applications; however, it is clear that a variety of other applications could be considered in the absence of such regulatory restrictions, addressing military and civilian needs such as communication between individuals, electronic devices, control centers, and electronic systems.

[0004] Therefore, it is beneficial for UWB transmitters, UWB receivers, and UWB transceivers to know precisely when to wake up from deep sleep mode, even if these devices use low-frequency clock sources to achieve ultra-low power consumption.

[0005] Advantageously, where possible, electronic circuitry that generates wireless radio waves can support low-power operation by utilizing transistors or so-called compound MOSFET structures (whose effective gain and output resistance exceed that of any single transistor, regardless of length).

[0006] Advantageously, by employing an unbiased, low-power differential (exponential) transconductance stage within operational transconductance amplifiers to provide a low-power amplification stage with very high gain, electronic circuits and other devices that form radio waves can support low-power operation.

[0007] Advantageously, by employing a voltage reference source that consumes very low current (a few nA), the electronic circuitry that generates radio waves supports low-power operation.

[0008] The advantage is that by employing ultra-low power, low-dropout regulators, the electronic circuitry that generates radio waves supports low-power operation.

[0009] Other aspects and features of the invention will become apparent to those skilled in the art when the following description of specific embodiments of the invention is read in conjunction with the accompanying drawings. Summary of the Invention

[0010] One object of the present invention is to alleviate the limitations of the prior art regarding ultra-wideband wireless communication systems, and more specifically, ultra-wideband transmitters and ultra-wideband receivers used in such ultra-wideband wireless communication systems.

[0011] According to an embodiment of the present invention, a method is provided, comprising: Provide electronic circuitry that includes at least a DC-DC converter; Establish sleep signals associated with entering sleep mode by disconnecting electronic circuits; The DC-DC converter is turned off based on the establishment of the sleep signal; Establish a PLL clock counter to count the number of PLL clock cycles between the rise of the sleep signal and the turn-off of the DC-DC converter; Maintain the value of the PLL clock counter during sleep mode; Subtract the time value established based on the held PLL clock counter value from the predetermined delay related to when the electronic circuit exits sleep mode.

[0012] According to an embodiment of the present invention, a circuit is provided, comprising: The port is used to receive the first signal and is coupled to the circuit. The PMOS gate and NMOS gate are connected to the port in parallel and are also connected to each other. The first part of the circuit is electrically connected to the PMOS gate; and The second part of the circuit is electrically connected to the NMOS gate; wherein, The port functions in the same way as if there were no PMOS gate or NMOS gate; and The first and second parts of the circuit now have twice the voltage threshold of the port.

[0013] According to an embodiment of the present invention, a method is provided, comprising: Provides a port for receiving the first signal and coupled to the circuit; Provides PMOS and NMOS gates that are connected in parallel to the port and are interconnected with each other; The first portion of the circuit is electrically connected to the PMOS gate; and The second part of the circuit is electrically connected to the NMOS gate; wherein, For the slow rise transition within the first signal, the actual input voltage has already risen above the threshold voltage of the NMOS gate before the voltage rises at the first node between the NMOS gate and the second part of the circuit and then turns on; When the gate connection of the NMOS gate is connected to the drain connection of the PMOS gate, the voltage of the first node lags behind the voltage of the second node between the PMOS gate and the first part of the circuit; The interaction between the NMOS gate and the PMOS gate is the down-conversion within the first signal.

[0014] According to an embodiment of the present invention, a method is provided, comprising: A first MOSFET is provided, comprising a first drain, a first gate, a first source, and a first substrate connection portion; A second MOSFET is provided, comprising a second drain, a second gate, a second source, and a connection to a second substrate; A first port is provided that is electrically connected to the first gate, the second gate, and the first substrate connection portion; Provides electrical connection to the second port of the first drain; and A third port is provided that is electrically connected to the connection between the second source electrode and the second substrate; wherein, The first MOSFET and the second MOSFET are identical, and are either an n-channel MOSFET or a p-channel MOSFET.

[0015] According to an embodiment of the present invention, a transconductance operational amplifier is provided, comprising: At least one differential pair of composite MOSFETs, each composite MOSFET comprising: The first MOSFET includes a first drain, a first gate, a first source, and a first substrate connection portion; The second MOSFET includes a second drain, a second gate, a second source, and a connection portion to a second substrate; The first port is electrically connected to the first gate, the second gate, and the first substrate connection portion; The second port is electrically connected to the first drain. The third port is electrically connected to the second source electrode and the connection portion of the second substrate; and The electrical connection is located between the first source and the second drain; wherein, The first MOSFET and the second MOSFET are of the same type and are at least one of an n-channel MOSFET and a PMOS MOSFET.

[0016] According to an embodiment of the present invention, a current mirror is provided, comprising: The first to fourth composite MOSFETs, each composite MOSFET comprising: The first MOSFET includes a first drain, a first gate, a first source, and a first substrate connection portion; The second MOSFET includes a second drain, a second gate, a second source, and a second substrate connection portion; and The third MOSFET is disposed between the first MOSFET and the second MOSFET, and includes a third drain, a third gate, a third source, and a third substrate connection portion; wherein, The first port is electrically connected to the first gate, the second gate, the third gate, and the first substrate connection portion; The second port is connected to the first drain. The third port is electrically connected to the second source electrode and the connection portion of the second substrate. The third drain is connected to the first source; The third source is connected to the second drain; and The third substrate connection portion is connected to the third drain, such that the bias voltage of the third n-channel MOSFET is between the bias voltages of the first n-channel MOSFET and the second n-channel MOSFET; wherein, The first MOSFET, the second MOSFET, and the third MOSFET are all n-channel MOSFETs or p-channel MOSFETs.

[0017] According to an embodiment of the present invention, a circuit is provided, comprising: Unbiased differential (exponential) transconductance stages include: A pair of differential signal input ports; The first NMOS gate and the second NMOS gate are both coupled to one of the differential signal input ports; The first PMOS gate and the second PMOS gate are both coupled to one of the differential signal input ports; wherein, or: The source of each of the first NMOS transistor and the second NMOS transistor, as well as the source of the first PMOS gate and the second PMOS gate, are all connected together; or The sources of the first NMOS transistor and the second NMOS transistor are connected together at the first node of the circuit, and the gates of the first PMOS transistor and the source of the second PMOS gate are connected together at the second node of the circuit.

[0018] According to an embodiment of the present invention, an operational amplifier including a biasless differential (exponential) transconductance stage is provided, the transconductance stage comprising: A pair of differential signal input ports; The first NMOS gate and the second NMOS gate are both coupled to one of the differential signal input ports; The first PMOS gate and the second PMOS gate are both coupled to one of the differential signal input ports; wherein, or: The source of each of the first NMOS transistor and the second NMOS transistor, as well as the source of the first PMOS gate and the second PMOS gate, are all connected together; or The sources of the first NMOS transistor and the second NMOS transistor are connected together at the first node of the circuit, and the gates of the first PMOS transistor and the source of the second PMOS gate are connected together at the second node of the circuit.

[0019] According to an embodiment of the present invention, a voltage source forming part of an electronic circuit is provided, comprising: Current source; and Multiple transistors are arranged in a stepped configuration along N electrical nodes; where, Node 0 is grounded; The gate of the i-th transistor among multiple transistors is connected to node (i-1); The source of the i-th transistor in a plurality of transistors is connected to node i; The drain of the i-th transistor in a plurality of transistors is connected to node (i+1); and The current source is placed in the gap left in the current path between node 0 and node 1.

[0020] According to an embodiment of the present invention, a method for providing a voltage source forming part of an electronic circuit is provided, comprising: Multiple N native transistors are provided in a series array; where, The source of a primary transistor i among N primary transistors is coupled to the drain of a primary transistor (i-1) among N active transistors, where i = 2, …, N; The source of the first of a plurality of N native transistors is coupled to ground; The substrate of one of N primary transistors, transistor j, is coupled to ground, where j = 1, …, N; and The gate of a primary crystal k among a plurality of N primary crystals is coupled to a node located between the source of a crystal (k-1) among a plurality of N active crystals and the drain of a primary crystal (k-2) among a plurality of N active crystals, where k=3, …, N and k is an integer.

[0021] According to an embodiment of the present invention, a method for providing a low-dropout regulator for electronic circuits is provided, comprising: Provides a high-impedance reference voltage source; A pair of first transistors is provided to isolate the output of the reference voltage circuit from any digital noise fed from the source of the second transistor to the gate of the second transistor; wherein, The first power-on transistor and the first power-off transistor are connected in series between the upper power rail and ground. The drain of the first powered-on transistor is connected to the upper power rail, and the source of the first powered-off transistor is connected to ground; The gate of the second transistor, the source of the first upper transistor, and the drain of the first lower transistor are all coupled to a common node; and A high-impedance reference voltage source is coupled to the gate of the first power-down transistor and the gate of the first power-up transistor.

[0022] According to an embodiment of the present invention, an electronic circuit is provided, comprising: Multiple electronic circuit elements; and A dynamically biased preamplifier with a latch comparator includes: NMOS input differential pairs are configured between a pair of differential input ports; The PMOS input differential pair is configured between the two differential input ports; and The dynamic bias circuit is coupled to the source of the PMOS input differential pair.

[0023] Other aspects and features of the invention will become apparent to those skilled in the art from the following description of specific embodiments of the invention in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0024] Figure 1 illustrates the application of the UWB transmitter, receiver, and system according to an embodiment of the present invention; Figure 2 is a block diagram of a UWB transmitter according to an embodiment of the present invention; Figure 3A is a block diagram of a UWB transmitter supporting biphase phase scrambling according to an embodiment of the present invention; Figure 3B is a block diagram of a UWB transmitter employing dynamically configurable and programmable pulse sequences according to an embodiment of the present invention; Figure 3C illustrates the multi-pulse symbol UWB protocol according to an embodiment of the present invention. Figure 4 is a block diagram of the UWB receiver according to an embodiment of the present invention; Figure 5 is a schematic diagram of the receiver circuit of the UWB receiver / transceiver according to an embodiment of the present invention; Figure 6 is a circuit diagram of the UWB transceiver according to an embodiment of the present invention; Figure 7 illustrates the use of a counter maintained during deep sleep levels, subtracted from the additional delay, in an exemplary timing scenario of UWB radio waves according to an embodiment of the present invention. Figure 8 shows a CMOS cross-current reduction stage connected to a conventional Schmitt trigger according to an embodiment of the present invention; Figure 9A shows a UWB receiver according to an embodiment of the present invention; Figure 9B shows a "composite MOSFET" according to an embodiment of the present invention; Figure 10 is a schematic diagram of a current mirror using the composite MOSFET of Figure 9 according to an embodiment of the present invention; Figure 11 is a complete circuit diagram of a custom current source including a reference circuit according to an embodiment of the present invention; Figures 12 and 13 illustrate the spread of the custom current source of Figure 11 in an embodiment of the present invention and the final desired "flatness"; Figure 14 shows the hysteresis transfer function of an embodiment of the present invention relative to a small differential input signal from a transconductance operational amplifier (OTA) employing the composite MOSFET depicted in Figure 10; Figures 15 and 16 show the simulation results of the transconductance operational amplifier in unity-gain configuration according to an embodiment of the present invention; Figure 17 shows the output of the OTA according to an embodiment of the present invention, wherein there is a DC voltage offset between the inputs; Figure 18 shows the simulation results of the transconductance operational amplifier according to an embodiment of the present invention. The transconductance operational amplifier exhibits an open-loop gain of 76 dB and a gain-bandwidth product of 25 MHz. Figure 19 shows the power spectral density of the noise analog of the transconductance operational amplifier according to an embodiment of the present invention; Figure 20 shows the simulation results of the rise time / fall time of the transconductance operational amplifier according to an embodiment of the present invention; Figure 21 is an exemplary schematic diagram of an operational amplifier employing an unbiased low-power differential (exponential) transconductance stage according to an embodiment of the present invention; Figure 22 shows the DC transfer function of the operational amplifier with an unbiased low-power differential (exponential) transconductance stage as shown in Figure 21, according to an embodiment of the present invention. The open-loop DC gain is ~85dB, and the input range is between V_SS+0.2V and V_DD-0.7V. Figure 23 shows the continuous current results of the operational amplifier using an unbiased low-power differential (exponential) transconductance stage as shown in Figure 21, according to an embodiment of the present invention; Figures 24 to 27 show the transient operation results of the operational amplifier using an unbiased low-power differential (exponential) transconductance stage as shown in Figure 21, according to an embodiment of the present invention; Figure 28 shows the transient power consumption of the transconductance stage in Figure 21 of this embodiment of the invention; Figure 29 shows a MOSFET circuit according to an embodiment of the present invention; Figure 30 shows an exemplary circuit layout using a native / negative threshold MOSFET pattern according to an embodiment of the present invention; Figures 31 and 32 show the DC response and DC analysis of the native / negative threshold MOSFET pattern shown in Figure 30; Figure 33 shows a resistor ladder with a power supply that depends on a reference ladder according to an embodiment of the present invention; Figure 34 shows the relationship between the reference voltage spread and temperature of the native / negative threshold MOSFET pattern in an embodiment of the present invention; Figure 35 shows the transient noise performance of the exemplary native / negative MOSFET pattern shown in Figure 33; Figure 36 is an exemplary schematic diagram of an ultra-low power low dropout voltage regulator according to an embodiment of the present invention; Figure 37A shows a self-contained dynamic comparator circuit according to an embodiment of the present invention; and Figure 37B shows a regenerative latch according to an embodiment of the present invention, providing context for an innovative ultra-low power low dropout regulator. Implementation

[0025] To enable the Examiner Committee to understand the technical features, content, advantages, and effects of this invention, the invention is hereby described in detail with reference to the accompanying drawings and attachments, and in the form of embodiments. The drawings used are for illustrative purposes only and to assist in the description, and may not represent the actual proportions and precise configurations after the implementation of this invention. Therefore, the proportions and configurations of the attached drawings should not be used to interpret or limit the scope of this invention in actual implementation.

[0026] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0027] This invention pertains to ultra-wideband wireless communication systems, and more specifically to ultra-wideband transmitters and ultra-wideband receivers used in such ultra-wideband wireless communication systems.

[0028] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with enabling descriptions for implementing the exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope set forth in the appended claims.

[0029] 0. Pulse Radio Ultra Wideband System

[0030] As mentioned above, UWB offers many potential advantages, such as high data rates, low-cost implementation, low transmit power, ranging, multipath immunity, and low interference. The U.S. Federal Communications Commission (FCC) regulations on UWB reserve unlicensed frequency bands between 3.1 GHz and 10.6 GHz for indoor UWB wireless communication systems, where low-adjustment transmit power allows such UWB systems to coexist with other licensed and unlicensed narrowband systems. Therefore, limited spectrum resources can be utilized more efficiently. On the other hand, UWB systems with their ultra-wide bandwidth offer significantly greater capacity for short-range applications than current narrowband systems. Two possible technologies for implementing UWB communication are pulse radio (IR) UWB and multi-carrier or multi-band (MB) UWB. IR-UWB utilizes the transmission of ultra-short (nanosecond-level) pulses, but in some cases, more than one pulse represents one symbol to increase processing gain. Conversely, MB-UWB systems use orthogonal frequency division multiplexing (OFDM) technology to transmit information on each sub-band within a sub-band. While OFDM possesses several desirable characteristics, including high spectral efficiency and robustness against RF and multipath interference, it also suffers from several drawbacks. These include the need for up-conversion and down-conversion, the requirement for mixers and their associated high power consumption, and extreme sensitivity to inaccuracies in frequency, clock, and phase. Similarly, nonlinear amplification disrupts the orthogonality of OFDM. Therefore, MB-UWB is not suitable for low-power and low-cost applications.

[0031] In contrast, IR-UWB offers several advantages, including unlicensed use of several gigahertz of spectrum, providing great flexibility in spectrum usage, and self-tuning transceiver designs that can optimize system performance based on data rate, operating range, available power, desired quality of service, and user preferences. Furthermore, multi-Gb / s data rate transmission over very short distances is possible, and due to the ultrashort pulses within IR-UWB, it is highly robust to multipath interference, and in some implementations, more multipath components can be resolved at the receiver, resulting in higher performance. Additionally, ultrashort pulses support sub-centimeter ranging, while the lack of up-conversion and down-conversion allows for reduced implementation costs and lower-power transceiver implementations. Advantageously, the ultrashort pulses and low-power transmission make IR-UWB communications difficult to eavesdrop on.

[0032] As described below with reference to Figures 2 and 3 regarding embodiments of the invention, the IR-UWB transmitter utilizes a pulse generator followed by an on-demand oscillator to upconvert pulses from the generated pulses, thus avoiding the need for a separate mixer. Both the pulse generator and the on-demand oscillator can be digitally tuned, provided they can be implemented in standard CMOS logic, to offer control over the pulse bandwidth and center frequency. Furthermore, by utilizing a digitally controlled ring oscillator for the on-demand oscillator, the IR-UWB transmitter is designed to allow very fast frequency adjustments on the order of pulse repetition rate (PRR). Advantageously, this technique offers the same advantages as MB-OFDM in terms of spectral configurability, achieved by sequentially changing the transmit spectrum using a frequency hopping scheme, while retaining the advantages of IR-UWB. Moreover, by providing a high duty cycle with fast power-up time combined with on-off shift keying (OOK) modulation, the IR-UWB according to embodiments of the invention allows for significant power reduction by utilizing the low duty cycle of UWB symbols and the fact that only half of the symbols require transmit energy.

[0033] In addition to defining the operating frequency range of UWB systems, different regulatory agencies specify and implement specific power spectral density (PSD) masks for UWB communications. The PSD mask that may be used in embodiments of this invention is the FCC mask, for which Table 1 below summarizes masking data in the 3100MHz-10600MHz (3.1GHz-10.6GHz) range. Frequency range Indoor EIRP limit (dBm / MHz) Outdoor EIRP limit (dBm / MHz) <960 -49.2 -49.2 960-1610MHz -75.3 -75.3 1610-1990MHz -53.3 -63.3 1990-3100MHz -51.3 -61.3 3100-10600MHz -41.3 -41.3 >10600MHz -51.3 -61.3 Table 1: Indoor and Outdoor FCC Coverage in Different Frequency Bands

[0034] Therefore, it is clear that the upper limit of -41.3 dB / MHz in the 3.1 GHz–10.6 GHz frequency range is the same as the limit imposed on unintentional radiation at a given frequency to avoid interfering with other radios. Essentially, for a given frequency, UWB radios operate at permissible noise levels, which in Transmit energy per pulse, maximum spectral power ,bandwidth Bit rate and the number of pulses per bit The relationship presented in formula (1) is generated between them.

[0035] (1)

[0036] IEEE has published several standards for the physical layer (PHY) of UWB radio in Personal Area Networks (IEEE 802.15.4a-2007), Body Area Networks (IEEE 802.15.4a-2007), and Radio Frequency Identification (IEEE 802.15.4f-2012). These standards primarily use relatively large pulses, resulting in a relatively narrow bandwidth, which is up-converted to a specific center frequency to fill a predetermined channel. Data is encoded using Pulse Position Modulation (PPM), and Biphasic Phase Shift Keying (BPSK) is used to encode redundant data. Each bit consists of one or more pulses phase-scrambled according to the target data rate. These standards allow considerable flexibility in terms of channel availability and data rate. The standard also defines the packet preamble, header, and ranging protocol.

[0037] These IEEE standards are designed with multiple users in mind, using different channels to transmit data, thus imposing strict constraints on pulse bandwidth and limiting the transmitted energy. Existing technology for non-standard transmitters attempts to make better use of the available spectrum by using narrow pulses, thus having a wider bandwidth and increasing the maximum transmit energy according to formula (1). Therefore, these transmitters are non-standard and are designed for different data rates, frequencies, pulse widths, etc. In addition, they use various coding schemes, most notably PPM, OOK, or BPSK.

[0038] In the work described below, the inventors have developed improvements to UWB systems, UWB transmitters, and energy-based UWB receivers that generate and adapt to a variety of IR-UWB pulses and bit coding schemes, thereby supporting communication from both IEEE-compliant and non-standard IR-UWB transmitters. These improvements are made for UWB transmitters, UWB receivers, UWB transceivers, and UWB systems, such as those described and depicted by the inventors in the following documents: WO / 2019 / 000075 UWB “High-Efficiency Ultra-Wideband Pulse Radio System and Method” (PCT / CA2018 / 000,135, filed June 29, 2018); WO 2016 / 191851 “System and Method of Spectrum-Efficient and High-Efficiency Ultra-Wideband Pulse Radio with Scalable Data Rate” (PCT / CA2016 / 000,161, filed May 31, 2016); and WO / 2015 / 103,692 “System and Method Related to Ultra-Wideband Broadcasting Including Dynamic Frequency and Bandwidth Jumps” (PCT / CA2015 / 000,007, filed January 7, 2015).

[0039] 1. IR-UWB transmitter circuit

[0040] Referring to Figure 2, an exemplary architecture of an IR-UWB transmitter 200 according to an embodiment of the present invention is schematically depicted, consisting of five main blocks plus an antenna. First, when a data signal from gate 210 is high based on a control signal provided to gate 210, pulse generator 230 generates programmable pulses at clock intervals. Then, the pulses from pulse generator 230 are up-converted by a programmable multi-ring digitally controlled ring oscillator (DCRO 240). The output from DCRO 240 is then coupled to a variable gain amplifier (VGA 250) to compensate for any frequency dependence of the pulse amplitude. Finally, driver 260 feeds antenna 270, thereby overcoming typical package parasitic effects, such as those resulting from encapsulating the transceiver within a quad flat no-lead (QFN) package. To further reduce the power consumption of the IR-UWB transmitter 200 (IR-UWB-Tx) according to an embodiment of the present invention, the power loop controller 220 dynamically turns these function blocks on or off when the data signal is low.

[0041] Referring now to FIG. 3A, a block diagram 300 of an exemplary IR-UWB transmitter supporting biphasic phase scrambling according to an embodiment of the present invention is schematically depicted. Compared to the non-biphasic phase-shifted IR-UWB transmitter 200 for IR-UWB according to an embodiment of the present invention in FIG. 2, the biphasic phase-shifted IR-UWB (BPS-IR-UWB) transmitter comprises six main blocks instead of five main blocks plus an antenna. First, when the data signal from gate 310 is high based on a control signal provided to gate 310, pulse generator 330 generates programmable pulses at clock intervals. Then, a programmable multi-ring digitally controlled ring oscillator (DCRO 340) is used to up-convert the pulses from pulse generator 330. The output from DCRO 340 is then coupled to a VGA 350 dual-output amplifier to compensate for any frequency dependence of the pulse amplitude, and also generates a dual-phase-shifted output signal coupled to switch 360, which, under the action of a switch control signal “S” applied to switch 360, selects to couple one of the two signals to output power amplifier 380 (driver). Note that a similar phase selection scheme can be achieved by influencing the startup conditions of DCRO 340 to provide two phases. This would eliminate the need for switch 360 at the cost of adding a startup condition control signal to DCRO 340.

[0042] Output power amplifier 380 feeds antenna 370, thereby overcoming typical packaging parasitic effects, such as those resulting from encapsulating the transceiver in a quad flat no-lead (QFN) package. To reduce power consumption of the BPS-IR-UWB transmitter represented by block diagram 300 according to an embodiment of the invention, power loop controller 320 dynamically turns these functional blocks on or off when the data signal "PC" is low. Therefore, the BPS-IR-UWB transmitter according to an embodiment of the invention transmits pulses with or without phase shift based on a control signal "S" applied to switch 360. If this control signal is now fed from a scrambled data generator or a pseudo-scrambled data generator, the resulting pulse coupled to the antenna of the BPS-IR-UWB transmitter will be pseudo-randomly or randomly phase-shifted.

[0043] Referring now to FIG. 3B, a block diagram 3000 of an exemplary IR-UWB transmitter according to an embodiment of the present invention is schematically depicted. As depicted, a pulse mode block 3010 maintains a configuration for the pulses representing the current symbol. Multiple phases are generated by a delay-locked loop (DLL 3030) according to the symbol rate clock (i.e., 20 MHz). The rising edge of each clock phase indicates the start of a pulse in the symbol pulse beam. A multiplexer 3020 is triggered by the edge of the clock phase and selects the configuration of the current pulse from the pulse mode block 3010. A pulse generator 3050 (Pulser) generates pulses having pulse widths set by the multiplexer 3020 and enables a digitally controlled oscillator (DCO 3040) and a power amplifier (PA 3060). When enabled, the DCO 3040 generates a Gaussian-shaped pulse with a frequency set by the multiplexer 3020, which is then amplified by the PA 3060 and radiated by the antenna 3070.

[0044] Therefore, the pulse mode block 3010 establishes pulses for symbols or symbol sequences. In this way, the pulse mode block 3010 is updated to adjust the pulse sequence for each symbol, and thus, the pulse mode block 3010 can be dynamically updated based on one or more factors, including but not limited to network environment information, predetermined sequence, date, time, geographical location, signal-to-noise ratio (SNR) of the received signal, and regulatory masking.

[0045] Referring to FIG3C, a multi-pulse symbol UWB protocol according to an embodiment of the present invention is schematically depicted. Referring to the first image 3100A, a bit 3160 is depicted comprising a series of sub-pulses 3160A to 3160C, each sub-pulse being at a frequency Therefore, the multipulse spectrum 3180 of the symbol (bit 3160) is depicted in the second image 3100B, which is conceptually obtained by adding the individual pulse spectra of sub-pulses 3160A to 3160C (phase scrambling is omitted for clarity). This increases bandwidth while increasing the total symbol duration compared to existing single-pulse methods, while maintaining maximum power below the UWB mask 3120. This allows for maximizing symbol energy while relaxing the timing requirements and synchronization levels required by the receiver. Any number of pulses with different parameter sets can be included in the bundle to tailor the pulse spectrum to meet given requirements.

[0046] 2. IR-UWB receiver

[0047] Referring to Figure 4, the architecture of an IR-UWB receiver 400 according to an embodiment of the present invention is schematically depicted. Thus, a signal from an IR-UWB transmitter is received via antenna 410 and coupled to a low-noise amplifier (LNA 420), and then coupled to a first amplifier 430, where the resulting signal is squared by a squaring circuit 440 to assess the amount of energy in the signal. The output of the squaring circuit 440 is then amplified by a second amplifier 450, integrated by an integrator circuit 460, and evaluated by a flash memory ADC 470 to generate an output signal. A power loop controller 480 is also depicted, which dynamically powers on and off the LNA 420, the first amplifier 430 and the second amplifier 450, the squaring circuit 440, and the flash memory (ADC 470) in a manner similar to the power loop controller 220 of the IR-UWB transmitter 200 in Figure 2, respectively, to further reduce power consumption according to circuit requirements.

[0048] Referring to Figure 5, a schematic diagram of a receiver 500 according to an embodiment of the present invention is depicted. The RF signal from antenna 510 is initially amplified by a low-noise amplifier (LNA 520) and then passed to a two-stage RF amplifier (AMP1 530). A first square mixer (MIX1 540) multiplies the signal by itself to convert it to an intermediate frequency (IF). A three-stage variable gain amplifier (VGA 550) further amplifies the signal and implements a bandpass filter function. The output of VGA 550 is then coupled to a second square mixer (MIX2 560), which downconverts the signal to a baseband frequency. Processing circuitry 580 includes a pair of parallel integrators (INT1 and INT2) that sum the signal energy, which is then digitized within a digital document processor by analog-to-digital converters (ADC1 and ADC2) (not depicted for clarity).

[0049] 3. IR-UWB receiver

[0050] As described in WO / 2019 / 000075 and WO 2016 / 191851, the inventors established design parameters for a startup time in the millisecond range from sleep mode and a startup time in the microsecond range from idle mode by creating a custom integrated DC / DC converter and duty cycle transceiver circuit. The custom integrated DC / DC converter and duty cycle transceiver circuit can achieve low (… ) and medium data rate ( To achieve fast circuit startup / shutdown for optimal power consumption.

[0051] To maintain good energy efficiency, the components of the total UWB transceiver (such as the transceiver 600 depicted in FIG. 6 according to an embodiment of the invention) have been designed for low quiescent sleep current and fast start / sleep time. Referring to FIG. 6, the battery ( (Not depicted for clarity) The low-frequency crystal oscillator 615, sleep counter 620, and bandgap reference 610 are powered. Although the bandgap reference 610 may have a duty cycle in other embodiments of the invention without changing the scope of the claimed invention, the low-frequency crystal oscillator, sleep counter, and bandgap reference are all generally always operational. Their power consumption limits the minimum power consumption of the system to the sub-microwatt level. When the system is not in sleep mode, the integrated buck DC-DC converter 605 is battery powered, and this provides the power supply voltage to the rest of the system with high conversion efficiency. The startup time of the DC-DC converter 605 is on the order of several symbol cycles to minimize wasted energy. Between sleep cycles, the PLL 655 starts up to provide the base clock for the system. The receiver 625 and DLL 660 have dedicated power-down controllers and are only activated during frame transmission / reception. In addition, the transmitter also performs power cycling through its all-digital architecture, which is not described as having a separate controller. Due to the low base clock (e.g., 20 MHz), the power consumption of the digital synthesis module is low.

[0052] In principle, the power cyclic transceiver (PLL) achieves constant energy efficiency by linearly scaling power consumption with the data rate. With a fixed frame size, multiple data rates are obtained by adjusting the length of the sleep cycle, where the maximum achievable data rate is determined by the symbol rate within the frame itself. To conserve energy efficiency, power consumption during sleep must be lower than the average power consumption. For high data rates, the PLL does not need to be powered down when its power consumption does not significantly reduce overall efficiency. For low data rates, the entire system, except for the bandgap reference, crystal oscillator, and sleep counter, can be shut down during sleep mode. In this case, the millisecond-range startup time of the PLL may be negligible compared to the sleep cycle, and overall efficiency will not decrease significantly.

[0053] As depicted, the UWB transceiver 600 also includes a receive / transmit switch 690 coupled to an antenna to selectively couple the transmitter 6000 or the receiver 625 to the antenna during transmission and reception, respectively. The UWB transceiver 600 also includes spectrum configuration circuitry 665 (equivalent to the pulse mode block 3010 in the transmitter 3000 of FIG. 3B), PHY processing circuitry 650, link controller 645, buffer and interface circuitry 640, analog-to-digital converter (ADC 630), multiplexer (MUX 670), pulse generator 675, mixer 680, and power amplifier (PA 685), as well as PHY formatting circuitry 635. The UWB transceiver 600 communicates with the user terminal 695 via the link controller 645. Thus, the link controller 645 can communicate with the user terminal 695, for example, using a wired protocol.

[0054] 4. Crystal clock drift compensation

[0055] In the UWB transmitter, UWB receiver, and UWB transceiver described in WO / 2019 / 000075 and WO 2016 / 191851, the inventors achieve ultra-low power consumption by means of basic design considerations of the electronic circuit itself, utilization of low-frequency clocks, and active sleep cycles of parts of the electronic circuit according to the state of the device and the parts of the electronic circuit required to perform specific functions in each state.

[0056] In these devices, a phase-locked loop (PLL) generates a high-speed clock, which operates significantly faster than a crystal oscillator, providing the underlying fundamental frequency for the electronic circuitry. Therefore, the electronic circuitry utilizes the PLL to up-convert a low-power, low-frequency clock to generate the desired sub-clock, rather than using a high-power, high-frequency clock and dividing it to produce the desired sub-clock.

[0057] However, when the electronic circuitry enters a low-power mode, where even the DC-DC converter (such as DC-DC converter 605 in Figure 6) is powered down in what the inventors call "DCDC sleep," the PLL clock signal does not propagate to the digital portion of the electronic circuitry and therefore cannot be used to determine when to wake up the electronic circuitry and thus the radio waves that include it. In this DCDC sleep, the only clock propagating is a 32kHz crystal clock signal, which, if used alone, will provide an error of potentially more than 30 seconds regarding when to wake up the electronic circuitry and the radio waves. While other "deep" sleep power modes of the wireless circuitry according to embodiments of the invention may exist, the solution described herein addresses the current situation and these deep sleep modes. The limitation is that in the sleep mode described in this invention, there is no longer a PLL clock implementing the digital circuitry containing the PLL clock counter.

[0058] Therefore, to alleviate this problem, a PLL clock counter is implemented that counts the number of PLL clock cycles between the rising moment of the sleep signal and the actual moment the DC-DC converter turns off. Due to the design of the electronic circuitry, this is always at a predetermined edge of the next crystal oscillator clock cycle, such as the rising edge depicted in Figure 7. The value of this counter is retained during the deep sleep level and is subtracted from the additional delays marked as transceiver wake-up delay 710 under scenario #1 in Figure 7 and delay 720 under scenario #2 in Figure 7 after the DC-DC converter wakes up. Thus, the sleep duration of the electronic circuitry and radio waves is now independent of the point within the crystal clock cycle when the sleep signal rises, and the electronic circuitry and radio waves turn off. Although embodiments of the invention have been described with respect to a 32kHz clock as described in WO / 2019 / 000075 and WO 2016 / 191851, it is apparent that other basic clock frequencies can be used, and the described method is also independent of the phase of the clock (e.g., a crystal clock). The DC-DC converter turns off at a predetermined edge of the crystal clock cycle.

[0059] 5. CMOS Cross Current Reduction Stage

[0060] In UWB transmitters, receivers, and transceivers utilizing Complementary Metal-Oxide-Semiconductor (CMOS) technology, it is advantageous for many applications to provide ultra-low power consumption as required. Therefore, minimizing current within the CMOS circuitry is a requirement, and any reduction benefits the entire electronic circuitry. According to an embodiment of the invention, a dual transistor structure, identified as transistors M8 and M9 in FIG8, is inserted into the input to increase the required fraction of any voltage transition, thereby turning on the transistor of the connected digital input. The dual transistor structure is used to double the effective voltage threshold of the digital input, the benefit of which is reduced cross-current at the input during long voltage transitions. This circuit is also advantageous for Schmitt triggers and can replace them, although placing this circuit before the Schmitt trigger is beneficial.

[0061] Therefore, referring to Figure 8, the digital input works in the same way, but now it appears as if the transistors (i.e., M0 and M1) it was previously connected to have twice the voltage threshold. However, the dual transistor structure does not actually reduce the leakage current beyond its nominal level. At that time, it adjusts energy efficiency during any voltage transition. Therefore, the voltage difference between the electrical nodes pmos_gate and nmos_gate is approximately twice the voltage threshold of the transistors (i.e., M8 and M9) used in the dual-transistor structure. Thus, as long as the result is above 0 volts, the voltage of transistors M0 and M1 will be adjusted. Reduce the voltage threshold by one. In Figure 8, the body contacts of M8 and M9 do not need to be connected to... or These body contacts can alternatively be connected to the corresponding source or drain terminals of transistors M8 and M9.

[0062] Therefore, the result is that for each (slow) rise transition, the actual input voltage will have to rise to the threshold voltage of NMOS M9 before the node nmos_gate begins to rise, because transistor M9 must first become on. Then, because its gate is connected to the drain of M8 through node pmos_gate, the voltage at node nmos_gate "lags" behind the voltage at pmos_gate. This is because it must wait for the pmos_gate node to further charge the gate of M9 to allow node nmos_gate to maintain its voltage rise during the transition. For fall transitions, the roles are simply interchanged between M8 and M9, and the basic concept remains the same.

[0063] Therefore, the main benefit of this design is that when the input voltage is in the middle of the transition and both M0 and M1 are on, the cross current is reduced, as if the power supply voltage had one less transistor. Similarly, less energy is wasted during slow digital state transitions. A secondary benefit of this dual-transistor layout is that no transistor gate is directly electrically connected to the input node IN. Transistors M4 and M5 in Figure 8 do not play any role in the input-pair dual-transistor structure. Furthermore, by connecting only the transistor source contacts to the outside of the electronics module, this design is also more robust to ESD damage.

[0064] 6. Body contact cross-coupled transistor stack body pair

[0065] At a higher level, the basic concepts described in the following detailed description in this section can be applied to any pair of matched transistors to significantly improve their effective drain impedance, generally to near infinity, and in some regions into the realm of negative impedance. Applications of the inventive concept include, but are not limited to: A current mirror / reference, wherein the quality factor of such a circuit element is defined by how small the overdrive required for the current mirror to reach its saturation (high impedance) region and how flat the current response is for any given voltage (i.e., how high the impedance); and B) Operational amplifiers (OpAmps), which are designed to achieve high gain and high energy efficiency.

[0066] This invention is based on two core ideas: 1) Stack a pair of transistors with the same voltage threshold, and connect the body contact and gate contact of the drain-side transistor of the stack together, while connecting the well contact of the source-side transistor to its source or ground; and 2) Adjust the body contacts to generate an unbiased cascode transistor structure with higher output impedance.

[0067] One compromise in the conception of this invention is that they cannot be used for large... Essentially, the present invention is conceived for near-threshold transistor operation.

[0068] 6A. Overview

[0069] Referring to Figure 9A, a UWB receiver 900A according to an embodiment of the present invention is depicted, allowing the UWB receiver 900A to detect pulses received by an antenna 905, which have been transmitted by a transmitter according to an embodiment of the present invention. Therefore, the antenna receives a pulsed UWB signal, which consists of a carrier signal pulsed according to a fast envelope. The received signal is initially coupled to a low-noise amplifier 910, which amplifies the signal, wherein the amplified signal is bandpass filtered by a first filter 915 to suppress out-of-band interference. Optionally, other amplifiers may be present in this RF stage before the mixer 920. For example, the first filter 915 may be a bandpass filter.

[0070] Next, the in-phase quadrature mixer 920 multiplies the received filtered and amplified signal with a square clock, thereby downconverting the pulse to an uncertain intermediate frequency IF1, where IF1 is the difference between the pulse carrier frequency and the clock frequency. Since the UWB receiver 900A is an energy receiver, path quadrature (90 degrees out of phase) is required to preserve the total energy of the pulse while separating the in-phase signal I and the quadrature signal Q between the two paths based on the phase difference between the RF signal and the clock. Even if the UWB receiver 900A were not an energy receiver, two paths are needed to avoid scenarios using a single path I or Q, and the received RF signal and clock are out of phase to prevent signal generation in a single path.

[0071] The IF1 signals in the I-arm and Q-arm are processed by a first signal processing circuit 940 and a second signal processing circuit 950, respectively. Each of these filters includes an amplifier 925, such that the mixed and down-converted IF1 signals are amplified, and these signals are then filtered by a second filter 930, which is, for example, a sharpening low-pass filter or a band-pass filter based on the UWB band in which the receiver is currently operating. The output of each second filter 930 is then squared by a squaring operation performed by a first squarer 935 to extract the transient power along that path. The outputs from the first signal processing circuit 940 and the second signal processing circuit 950 are summed by a summing circuit 945 to obtain the total transient power. The output of the summing circuit 945 is then coupled to an amplification stage 955. The amplified signal is then filtered by a third filter 960, squared by a squaring operation performed by a second squarer 965, and then integrated by an integrator 970. The amplifier stage 955, the third filter 960, the second squarer 965, and the integrator 970 form the third signal processing circuit 980.

[0072] The signal from the summing circuit 945 follows the envelope of the pulse signal of the RF carrier after it has been removed. Therefore, even without knowing the exact pulse carrier frequency, the signal can still be received while applying sharpening filtering. The amplifiers in each of the first signal processing circuit 940 and the second signal processing circuit 950, as well as the amplifier in the third signal processing circuit 980, can be fixed-gain amplifiers or variable-gain amplifiers. In embodiments of the invention employing variable gain, variable gain can be used to amplify the signal to full strength, which, combined with bandpass filtering, allows for the removal of narrowband interference signals.

[0073] Each of the first signal processing circuit 940 and the second signal processing circuit 950 requires an amplifier 925 to amplify the low signal from the mixer 920 for subsequent processing. Therefore, for a UWB receiver according to an embodiment of the invention, the amplifier 925 has performance requirements such as those listed in Table 2 below. In the following description, an implementation of the amplifier 925 using a transconductance operational amplifier (OTA) designed for use in a commercial-fabrication CMOS process utilizing 0.13µm technology is described. parameter value unit power supply voltage 1.2 V Common mode voltage 0.5 V Output load 500 fF DC gain >60 dB Harmonic distortion <0.2 %, for a 600mVpp input (unity-gain configuration) Input reference power spectral density (PSD) noise <100 (at 1MHz) Static power consumption <200 µW Table 2: Target OTA Performance

[0074] An additional design objective is to establish dominant Laplace poles at approximately 10 kHz and 100 MHz in an open-loop configuration, although the actual pole locations are merely guidelines, as the only practical requirement of this criterion is stability and the equivalent gain-bandwidth (GBW) product (which, in this case, should be higher than 10 MHz). Furthermore, the primary criterion for establishing the relative quality factor of this design is power consumption, making it a key differentiating parameter. In the description below, this criterion, along with the absence of strict silicon area requirements, motivates the design decisions for OTA.

[0075] 6B. Selected Operational Amplifier (Op-Amp) Circuit

[0076] It is evident that there are different methods to construct circuits that meet the standards listed in Table 1. The conventional model for an OTA to meet these requirements is a typical two-stage amplifier, where a PMOS differential input pair is connected to an NMOS current-manipulated mirror, followed by a simple common-source NMOS voltage amplifier. However, using multiple stages in different current branches involves considering and placing at least two poles already specified in the standard list, and involves compensating with passive components, thus introducing design stability issues. Attempting to drive the pole of the last stage of such a two-stage amplifier requires minimizing the output resistance as much as possible, since the output capacitance should be at least 500 fF. Since the frequency of the output pole follows the simple RC constant law given in Equation (1), the frequency of the second pole should be at least 100 MHz (i.e., Mrad / s) and the capacitor should be at least 500 fF, and the output transistor drain has some additional capacitance. It must be below 3183Ω, which means there are strict constraints on power-limited designs. (2)

[0077] A 3 kΩ output impedance means that for every 1 volt charged or discharged at the output node, the output current must change (linearly) by 1 / 3000 of an ampere. Given a supply voltage of 1.2V, this would require the output current to vary by approximately 400 µA between rails. This is physically impossible without a nominal current source with a minimum quiescent current of 200 µA, which would generate a maximum source current of 200 µA when the final stable voltage is 0.6V and the onset voltage is 0V. The gain of the final stage must be very low, necessitating the replacement of the PMOS used as the current source with a resistor. Even then, the required 200 µA quiescent current necessitates a quiescent power dissipation of 240 µW, exceeding the OTA's entire power budget. Given that conventional operational amplifier designs cannot simultaneously meet the targets in Table 1, new architectures capable of satisfying all these criteria must be explored.

[0078] The simplest and most straightforward adjustment to meet speed requirements for a conventional operational amplifier is to insert a common drain as a third stage between a 500 fF load and the last voltage amplification stage. This produces a much lower output impedance for a given current. Early simulations showed that the required current for each of the last two stages could be reduced to approximately 40 µA, ensuring that the performance standard combination regarding pole frequency and quiescent power dissipation was no longer out of reach. However, the highly nonlinear impedance of the common-drain stage's output is suitable for voltage operational amplifiers, but not for the required transconductance operational amplifiers. The difference lies in the nature of the output signal; one output signal is voltage, the other is current, therefore the current response must be more or less linear with respect to at least half of the supply voltage. Furthermore, placing three poles instead of two for a common-drain stage complicates the stability requirements of a unity-gain configuration.

[0079] One approach to addressing all multipole instability issues and the necessary power requirements that follow is to design the OTA as a single current branch. For this purpose, the OTA must consist of a single differential pair with only one dominant pole. Therefore, this pole must be set as the sole dominant pole at only 10 kHz, rather than as a secondary pole at 100 MHz, which makes a significant difference in terms of power requirements and acceptable capacitive loads. Furthermore, in principle, a passive compensation network is not required to achieve stability. The requirement of a 10 kHz pole and a minimum DC gain of 60 dB is due to the need for a gain-bandwidth product of at least 10 MHz. This value becomes the system's switching frequency, and in the case of capacitive loads, the bias current of the differential pair is narrowed to a finite range from which the initial design can be developed. The switching frequency is always limited by Equation (2). (3)

[0080] Therefore, due to the parasitic capacitance of the OTA itself... Slightly greater than 500 fF and Significantly higher than 62.83 MHz (2π×10 MHz), 40 μA / V is sufficient. This transconductance specification can be achieved with a total bias current of less than 5 µA for the differential pair, due to the sharpened current transfer function of the MOSFET when operating in subthreshold mode. However, due to concerns about noise constraints and distortion, an incremental search for optimized designs should begin with a bias current of 8 µA.

[0081] New challenges arise when building everything from a single current branch (or cascade). The DC gain easily achievable with two cascaded stages now becomes more challenging with only differential pairs and a 1.2V supply voltage. Further complicating matters is that half the supply voltage range must fall within the linear operating range of the output, and the OTA distortion limit must be below 0.2%.

[0082] Basically, there is a way to make the transistor (in its) The gain (in a fixed-state configuration) is multiplied beyond what a long MOSFET channel can achieve, i.e., by increasing the effective drain impedance of the transistor (this is the effect of cascading). However, conventional cascaded structures provide very small voltage swings during low-voltage processes because they have very high overdrive voltages. Furthermore, conventional cascaded stages require additional bias voltages, which, in the case of differential pairs, must be different from the input signal and must closely follow the common-mode voltage of the input signal to always have the maximum available output voltage. A common trade-off for the overdrive problem is to stack two or more transistors in series and connect them to share the same gate voltage. Although the overdrive voltage of this structure is not significantly higher than the overdrive voltage of its individual transistor equivalent, the benefit of this technique is small and insufficient to meet the target OTA requirements. This ineffective increase in gain is because only the transistor whose drain is directly connected to the output does not operate squarely in its transistor bias region; the drain-source voltages of all other transistors in the stack are too low. If multiple transistors in the same stack must share the same gate voltage (which is necessary for differential pairs in OTA), the benefits of stacked transistors will inevitably be limited by the aforementioned effect unless they all have different voltage thresholds. Therefore, it is a convenient and common practice to connect the drain of the first transistor in series with the source of a second transistor with a lower voltage threshold than the first transistor. In this case, the drain-source voltage of the first transistor is much higher, allowing it to operate in or near its saturation region and obtain most of the benefits of cascading without additional bias voltage and with almost no additional overdrive to the structure.

[0083] However, this method uses additional photolithographic masks for additional doping steps, which are typically highly variable and will lead to multiple The threshold voltage difference between transistors in a stack varies significantly, which consequently makes cascaded performance unreliable and increases manufacturing costs. However, an alternative is for all transistors to operate at low overdrive voltages, allowing for precise and reliable shifting of the voltage threshold of any transistor in the stack. Transistor body contacts have various uses, most of which involve the back-gate effect. This effect produces a shift in the voltage threshold, and connecting two transistors (what the inventors call the composite MOSFET 900B), as depicted in Figure 9B, allows for a composite MOSFET structure with an effective gain and output resistance exceeding that of any single transistor, regardless of length. Polarizing a transistor in this way does cause a forward polarization of the pn junction in the second transistor, but because the bias current is always limited to a very low value under the conditions under which this structure will be used, the forward voltage rarely exceeds 0.2 volts, and the junction leakage is typically less than or approximately equal to the gate leakage of the same transistor, thus having no negative impact on circuit performance. As depicted in Figure 9B, the composite MOSFET consists of a pair of N-channel MOSFETs.

[0084] The inventors have demonstrated through simulations that this is effective in improving effective gain and output impedance; however, replacing each individual transistor of the OTA differential pair with the equivalent in Figure 9B still results in an OTA below the target 60 dB gain requirement. Therefore, the composite MOSFET 900B can be further tuned to significantly increase gain without significantly increasing the minimum drain-source operating voltage. This tuning is only applicable to transistors that are paired in some way with another identical transistor (which is used for both differential pairs and any current mirror). Therefore, to further increase the drain impedance of the composite MOSFET 900B in Figure 9B without increasing its minimum channel operating voltage, a third transistor is introduced in the middle of the stack, where the body-source bias voltage of the third transistor must also be between the body-source bias voltages of the two other transistors already present in the stack. To achieve this, the inventors connected the body contact of the intermediate transistor to its drain, and since its drain voltage is not much higher than its source voltage (because they are squeezed between two other transistors), the body-source junction voltage of the intermediate transistor is not high enough for any significant leakage. However, connecting the body contact to the drain of the same transistor makes it behave as weakly as a transistor connected to a diode, because the body contact behaves like a weak gate, and a transistor connected to a diode does not present high impedance through its drain, which defeats the purpose of having a third transistor in this case. This is where paired transistors come into play, and the disadvantage of the effect of connecting to a diode becomes an advantage. Since paired transistors refer to their behavior relative to each other, connecting the body contact of the intermediate transistor to the drain of the intermediate transistor on the opposite side of the stack of paired transistors, as depicted in FIG10, makes the effect of connecting to a diode favorable, rather than unfavorable, for higher drain impedance.

[0085] For the current mirror shown in Figure 10, it acts on changes in drain voltage in the following way. An increase in the drain-to-source voltage of transistor M6B causes a slight increase in the current response of that transistor until its source voltage also decreases, because M5B and M4B do not provide the same current at this moment. So far, this is the principle behind each cascaded branch. This slight decrease in the absolute source voltage of M6B directly involves an equal increase in the body-to-source voltage of transistor M5A, which has the effect of slightly lowering the effective voltage threshold of M5A and slightly increasing its conductivity. Therefore, when the conductivity of M5A increases, the current flow in the transistor stack M4A to M6A temporarily increases until its gate-to-source voltage connected to the diode decreases to compensate for it, which in turn equally decreases the gate-to-source voltage of the transistor stack M4B to M6b. Therefore, an increase in the drain-source voltage on the output side of this current mirror should cause a proportional decrease in the gate-source voltage of the entire current mirror, compensating for the channel modulation effect of transistor M6B and allowing the transistor stacks M4B to M6B to exhibit an effective output impedance closer to infinity. In fact, the inventors have experimentally determined that, given the correct device dimensions, this output impedance can even be negative. The differential input pair employs the same overall idea, as depicted in Figure 10, and operates based on the same fundamental principles. The transistor dimensions in exemplary embodiments of the invention are given in Table 3 below. transistor M1 M2 M3 M4 M5 M6 W(µm) 96 200 192 128 80 160 L(nm) 240 300 400 120 120 360 The number of fingers 8 8 8 8 8 8 transistor M7A M7B M8A M8B M9A M9B W(µm) 32 4 32 4 48 6 L(nm) 200 200 310 310 410 410 The number of fingers 16 2 16 2 16 2 transistor M10 M11 M12 M13 M14 M15 W(µm) 4 4 2 2 2 2 L(nm) 300 300 300 300 500 500 The number of fingers 4 4 2 2 2 2 transistor M16 M17 M18 M19 W(µm) 16 16 4 4 L(nm) 500 500 300 300 The number of fingers 16 16 4 4 Table 3: Exemplary Transistor Parameters for OTA

[0086] The decision to use an NMOS differential pair instead of a PMOS is based on the following facts: the OTA has no second current branch, NMOS performs better, and simulations have shown that a lower drain-source voltage is required to achieve linear behavior with NMOS. Therefore, a differential pair including NMOS transistors is part of a current branch that places two NMOS transistors and only one PMOS transistor in the current path, while a PMOS differential pair would be in the opposite situation and, in principle, require a higher operating voltage.

[0087] Therefore, Figure 11 depicts the full circuit schematic of a custom current source including a reference circuit, which also uses the same concept inspired by differential pair designs, as they are suitable for most low-polarization, low-speed transistor applications. This provides a current reference with excellent output resistance and a very small minimum operating voltage, which is impossible to achieve with any existing current mirror circuit. Table 2 above lists the dimensions of each MOSFET in the two circuits of Figures 10 and 11, where instance names M1 to M6 refer to two cells with tail codes A and B, the two cells being matched and implying they are identical, and therefore the same values ​​are maintained in the table. “W” refers to the total width.

[0088] 6C. Current Source Analysis

[0089] To benefit from the maximum input and output voltage swing necessary to achieve a good total harmonic distortion (THD) index, a current OTA must have a minimum operating voltage. On the other hand, to benefit from optimal common-mode rejection ratio (which may also lead to distortion), the same current source must draw as constant a current as possible across its output voltage, which equates to the highest impedance. These two conflicting requirements necessitate a demand for high-quality current sources.

[0090] Entering Figure 11 The terminal current is primarily absorbed by the transistor stacks M7A through M9A via a composite MOSFET structure of the same type, now a hallmark of this OTA. However, simulations revealed that, at the lowest possible operating voltage, the most “linear” current response to the output voltage is not the flattest response (closest to infinite impedance). In other words, the device parameters that keep the impedance constant over the widest voltage range are not the highest possible impedance, but fortunately, a negative impedance of approximately -20 MΩ is achieved. Therefore, a current branch presenting a total of +20 MΩ when connected to the output can be paralleled with a –20 MΩ main current source. Since the current branch does not need to provide the same current as the main current source, but can be a much smaller current source, achieving an impedance of ~20 MΩ is not difficult. These secondary current sources absorb approximately 95 nA through transistor M14 and output approximately 400 nA through M13, these currents varying slightly to compensate for the negative impedance generated by the drain of M9A, which absorbs approximately 7.2 µA.

[0091] When evaluating an OTA design, bias sensitivity to external factors is not part of the solution. Transistors M16 through M19 and an ideal 1 MΩ resistor constitute the basic bias source, which limits the current in all other branches of the entire OTA but does not vary significantly over the supply voltage range. Figure 12 shows the range of the custom current source for all supply voltage values ​​and the ultimately desired "flatness". Figure 13 depicts the extent of current variation over the output voltage range, with a variation of less than 3 nA (<400 ppm of nominal current) from 120 mV to 1 V, demonstrating the high performance of this current source within a 0.13µm CMOS. Extremely low overdrive voltage is crucial for achieving sufficient output voltage swing and a significant distortion index at low frequencies.

[0092] 6D. DC Analysis

[0093] Given that the ultra-high impedance structure constructed by the custom current source also constitutes the entire OTA, the optimized MOSFET parameters put the OTA in a state where its output impedance is also negative. Therefore, resistors Ro1 and Ro2 are added at the output of the OTA in Figure 10 to compensate for the negative impedance, but the resistors are left with undefined values ​​because their optimal values ​​vary according to the gain factor β of the feedback path. However, for β=1 (in a unity-gain configuration), the optimal resistive network impedance is approximately 15 MΩ, and the neutral voltage is 0.3 V, at which the net current leaving the voltage divider is zero. These two values ​​represent Equations (3) and (4) for Ro1 and Ro2 at a desired supply voltage of 1.2 V. (4) (5)

[0094] In formula (3), replacing “1 / Ro1” with “3 / Ro2” yields “4 / Ro2=1 / 15 MΩ”, thus obtaining Ro2=60 MΩ and Ro1=20 MΩ. Thereafter, unless otherwise stated, for all simulation results, by making Ro1 and Ro2 20 MΩ and 60 MΩ respectively, the total impedance of this voltage divider is Ro=15 MΩ.

[0095] The OTA's inherent negative output impedance in open-loop operation prevents its large-signal transfer function from exhibiting a definite, identifiable DC gain. Instead, Figure 14 depicts the hysteresis transfer function for a small differential input signal near Vcm = 0.5V, which, fortunately, only appears in open-loop operation. This is because the OTA is not intended to operate in open loop, as the design is based on the assumption that the OTA will not need to operate in open loop. While not defined as a standard for OTA design, a given desired open-loop gain must be any value above 60 dB and not within a narrow range, which inherently implies that some form of negative feedback should exist around the OTA so that it functions as expected once integrated into another circuit; therefore, the above assumption is reasonable. Even without compensation resistors Ro1 and Ro2, the hysteresis "opening" in the transfer function spans a differential input signal of less than 2 mV, and is completely suppressed even with a weak feedback coefficient (β < 0.01).

[0096] The two relatively constant voltages labeled “PMOS mirror gate” and “differential pair source” in Figure 14 can be used to directly provide clues to the available input common-mode range. Fast simulations at various common-mode voltages up to a nominal value of 0.5 V show that the hysteresis spread is insensitive to the common-mode voltage; therefore, the results in Figure 14 hold true as long as the operating input voltage range is within which, regardless of Vcm. Furthermore, Figures 15 and 16 show in more detail the performance of the OTA in a unity-gain configuration and the extent of its “strict” and “relaxed” operating ranges. The OTA enters its optimal operating range, where the current is maximized and stabilizes somewhere above 0.3 V common-mode, because the PMOS mirror gate voltage is constant beyond this point, and the voltage at the source terminals of the differential input pair faithfully follows the changes in the input signal. This voltage range ends near 1 V, where the transfer function in Figure 15 inevitably begins to decline.

[0097] Furthermore, Figure 16, by plotting the derivative of the output curve in Figure 15, more accurately determines the start and end points of the optimal operating range of the OTA. Finally, it is shown that the compensation resistor slightly narrows this optimal range, but this is due to a more accurate reproduction of the input signal at the output, as the curve “RO=15 MΩ” is within 50 ppm of the ideal unity-gain transfer curve. Aside from the hysteresis effect, Figure 16 shows that the open-loop gain exceeds 20 kV / V, i.e., exceeds 86 dB. This is simply achieved by separating the values ​​in Equation (5). get. (6)

[0098] Without the need for analog open-loop gain adjustment via compensation resistors, the voltage range is slightly wider; at least from 0.3 V to 0.92 V, with the lower limit decreasing to 0.32 V, and the output resistance compensation is 15 MΩ. This leaves sufficient range for the half-supply voltage sine wave required to evaluate the distortion index.

[0099] Regarding the effective offset, due to the hysteresis effect, the effective offset cannot be accurately determined using only the transfer function in Figure 14. Therefore, Figure 17 shows the voltage difference between the two inputs under the exact same conditions as in Figures 13 and 14. It can be predicted that the offset is a constant +0.4 mV throughout the entire optimal range of 15 MΩ compensation.

[0100] 6E. Communication Analysis

[0101] Without a stable DC bias point at the optimal DC propagation slope, open-loop AC analysis may seem irrelevant. However, to meet the distribution requirements and still perform gain-bandwidth product simulations, small-signal AC simulations were performed with a 0.4 mV signal offset (and an output compensation resistor of 15 MΩ) to obtain a reasonable bias point. These simulation results are depicted in Figure 18, where the open-loop gain is 76 dB and the GBW is 25 MHz. Pole placement was not strictly adhered to, but the low-frequency poles at approximately 4 kHz (around 10 kHz) were compensated for by very high DC gain and a GBW above 10 MHz. Using a phase lattice plot just below its corresponding amplitude, the phase margin is observed to be just below 74 degrees, which is just above the ideal phase margin and is typically obtained using an OTA with only one dominant pole instead of two.

[0102] The power spectral density of the noise simulation is depicted in Figure 19, showing that the results it produces are below the maximum allowable value of 100 nV / √Hz at 1 MHz.

[0103] 6F. Transient Analysis

[0104] All transient analyses of this OTA were performed in a unity-gain configuration with a compensated output resistance of 15 MΩ. For the slew rate, Figure 20 shows that the rise time (~20 ns) is significantly shorter than the fall time (~200 ns), which is the opposite of the performance of conventionally designed OTAs. This OTA also has a much slower slew rate because a trade-off must be made to achieve an ultra-low current consumption exponent regardless. Therefore, given that power consumption is specified as the primary (and only) differentiating parameter, and no constraints are specified on the slew rate, the trade-off between slew rate and power consumption is relatively straightforward.

[0105] These slew rate indices also show the extent of voltage swing, as shown in Figure 15. The main difference here is that Figure 20 shows the speed at which a given voltage can be reached. Therefore, without timing constraints, it is reasonable to expect the output signal to swing from ~25 mV to ~1.08 V without compensation resistors, or from ~85 mV to ~1.08 V with 15 MΩ compensation. With timing constraints, the lower bound can be raised to ~0.2 V. This always responds to the full-supply range input signal and discount distortion. Frequency (kHz) 0.01 10 1000 10000 THD (ppm) 2.183 5.18 3214 301500 Table 4: THD Results Based on Distortion Analysis

[0106] Regarding the distortion index, Table 4 lists the total harmonic distortion (THD) values ​​at key signal frequencies when the signal is a 600 mVpp sine wave centered at 620 mV. The value at 10 Hz is used to indicate that the DC transfer function's contribution to distortion is negligible, and only high-frequency effects are the cause of distortion. THD at 10 kHz is of most interest because, in the open loop, THD is most significant near the edges of the operational amplifier's bandwidth. Therefore, the nominal THD index (the index considered by the standard OTA) is approximately 0.000518%. Although the open-loop bandwidth is below 10 kHz, the expected bandwidth and frequency of interest for THD remain at 10 kHz. This small index is due to the very high gain of the OTA itself (even with compensation resistors). For the last two data points, they indicate that without sufficient gain and slew rate, the THD index drops sharply.

[0107] 6G. Summary

[0108] A potential limitation of this OTA is that the output voltage range may be variable and limited to the input common-mode voltage, but fortunately, this is not always the case. In a unity-gain configuration, since the output voltage is directly connected to the input voltage, the OTA produces an excellent THD index, making it physically impossible to pull the output voltage below the input voltage. It is evident that different candidate topologies yield OTAs that exceed the minimum requirements at a moderate silicon area cost, although this is not a design parameter.

[0109] 7. Unbiased low-power differential (exponential) transconductance stage

[0110] This innovative concept involves generating differential current solely from the voltage difference between two inputs.

[0111] Figure 21 illustrates an exemplary schematic diagram of an embodiment of the present invention using transistors M0, M1, M4, and M7. In Figure 21, it is noted that the NMOS transistor is a native transistor; therefore, in… It remains conductive even when the voltage is close to 0 volts.

[0112] The circuit operates similarly to two Class AB power amplifier stages with their outputs shorted together. When one input has a higher voltage than the other, the transistors connected to it tend to pull the voltage higher at their sources; in this case, the NMOS transistor will conduct more current, while the PMOS transistor will conduct less current. For the lower voltage input, the opposite is true; if the transistors are perfectly matched, the PMOS of one input will always draw the exact current from the NMOS of the other input source. If this symmetry exists, in the first configuration, all four transistor sources can be shorted together, as in the center node (net023) of Figure 26, since the voltage between all four transistor sources is the same anyway. In the second embodiment of the invention, the source of M4 is only connected to the source (and block) of M1, and the sources of M7 and M0 will be part of a separate node.

[0113] In an embodiment of the invention, this configuration can be implemented within the operational amplifier depicted in FIG21. It is performed as follows: when the voltage of the positive input is higher than the voltage of the negative input, the currents in transistors M4 and M1 become negligible, while the currents in M7 and M0 increase exponentially. This pulls node net15 low and node net07 high, causing the PMOS current mirror to starve (or deplete) and the NMOS current mirror to overfeed. Both net15 and net13 have lower voltages to turn off the output NMOS and turn on the output PMOS.

[0114] The advantage of this idea compared to existing technologies is that... First and foremost, it has a very low quiescent current, yet provides high gain and a strong current response to large voltage differences. Furthermore, it does this without requiring a bias circuit.

[0115] Figures 22 to 28 depict simulation results of embodiments of the present invention, wherein these simulation results include: Figure 22 depicts the DC transfer function, with an open-loop DC gain of ~85 dB and an input range of... +0.2V to between; Figure 23 illustrates the continuous current results at output saturation, with a maximum quiescent current of 500 nA and a typical current of only 6 nA. Figures 24 through 27 depict transient operation, where the nonlinear current allows for a very steep transition from 1V to 2V and vice versa (large-signal response), where the operational amplifier is optimized through a series resistor with a capacitive load; and Figure 28 depicts transient power consumption, where the power consumption is more efficient for a given load.

[0116] 8. Native / Negative Threshold MOSFET Totem

[0117] In exemplary UWB transmitter circuits, UWB receiver circuits, and UWB transceiver circuits according to embodiments of the present invention, there is a requirement for a voltage reference. However, prior art, such as that employing a "bandgap" reference module, consumes current as low as hundreds of nA. Therefore, it is advantageous to provide a reference voltage source that consumes only a few nA. Exemplary embodiments of the present invention utilize the capability of native (and depletion mode, i.e., negative Vth) transistors, even when their When it is negative, it can still conduct low but usable current.

[0118] This concept is based on stacking native (or depleted) transistors along a “ladder” of electrical nodes, from ground voltage level to the highest reference voltage required by the circuit. If each node of the ladder is a “step” numbered from 0 to N (where node 0 is ground), then for a native transistor, the electrical node at its gate is i–1, the electrical node at its source is i, and the electrical node at its drain is i+1, where i is the transistor number from 1 to N. Next, a tunable current source is placed in the gap left in the current path between nodes (steps) 0 and 1, since there is no -1 node for the gate contact of another native transistor. Tuning the current source allows a calibration reference voltage source to pull more or less current through the transistor “ladder,” which can be implemented digitally depending on the design of the current source. Clearly, a tunable current source can be implemented through a series of designs. Advantageously, this design is insensitive to power supply variations due to the significant transistor stacking and is also insensitive to temperature variations, as long as the current source is affected in a similar way to the native transistors within the ladder. Therefore, all that is needed is a change in the calibration process.

[0119] Given the initial problem, the digital domain transistor is large at high voltages (i.e., 3.3V), due to the need for large, thick oxide transistors, which is necessary to keep the quiescent current leakage at a reasonable level (~100s nA instead of ~10s uA). Therefore, deep sleep power consumption is dominated by the bandgap voltage reference circuit, and sometimes by the activity and clock (when in use) on the serial-to-parallel (SPI) interface. A preliminary solution to this problem is to replace the 3.3V input / output transistor with a 1.8V input / output transistor, which has the smallest channel length (almost half that of the 3.3V transistor) while still having the same... This results in the same low-channel leakage.

[0120] Therefore, in addition to reducing the die area, which also results in lower parasitic capacitance, dynamic power consumption and propagation delay are reduced, the latter allowing for the use of faster SPI clocks. Consequently, even with the digit circuit power supply regulated by a linear regulator, the low voltage swing and minimal charge required to charge the voltage node per unit capacitance further reduce power consumption. Furthermore, the lower voltage also means reduced quiescent current leakage. However, the chip's operating voltage range must now be limited to ~1.8V, or must be regulated for thick oxide digit circuits to allow for a wider operating range (e.g., up to ~3.6V).

[0121] Therefore, without a voltage regulation solution that consumes only tens of nA or less of quiescent current, there is practically no saving in the overall energy budget, and without proper care, the design may even waste more energy through the solution. Benefically, the requirements for the regulator are relaxed, namely:

[0122] It requires extremely low voltage accuracy (it powers digital circuits).

[0123] It requires an extremely low current supply (average tens of μA when the radio waves are operating at full speed with SPI and modem).

[0124] Initially, discrete transistors were chosen because the drain current is insensitive to the drain voltage when the transistor is in saturation and best suited for connection to an external voltage source. Furthermore, due to the very low source impedance, it is well-suited to meet a wide range of current requirements. Additionally, by fixing the gate voltage, the source voltage can be suppressed to within a few hundred mV. An exemplary circuit layout employing this concept is depicted in Figure 29.

[0125] However, this simple solution also has some drawbacks, which are: The channel modulation effect is added to each additional stage; Temperature changes within the range of 0 to 85°C induce current variations of multiple orders of magnitude in subthreshold transistors and tend to cause significant changes in the reference voltage; and The output voltage varies significantly with the process (or technology) (~±40%).

[0126] Therefore, the inventors conceived of a native transistor totem where, instead of using a separate current branch for each "boost" of the voltage, and because each native transistor for a voltage boost requires a minimum non-overlapping voltage drop, they can be connected in series and share the same current. The final voltage of the node depends entirely on the voltage threshold of the native transistor and the current source of the branch. Furthermore, in At this time, no external voltage reference or precise voltage supply is required. The circuit is depicted in Figure 30, while Figures 31 and 32 illustrate its various functions. hour DC response and DC analysis.

[0127] Typical simulation design problems to consider include: Transient operating stability: Minimal capacitive decoupling is sufficient; Transient noise: Ultra-low due to transistor source drive; Sensitivity to voltage supply variations (Power Supply Rejection Ratio, PSRR): prevented through a compound cascade effect; Temperature changes: These changes are largely compensated for by temperature effects that act in the opposite direction to each change, and thus most are canceled out; Process changes: These changes cannot be addressed using this method, therefore a solution needs to be designed; Component matching: can be resolved in die layout; and Component aging: This is not a problem, as it is caused by components being subjected to high voltage stress over a long period of time.

[0128] However, process variation is a fixed characteristic and does not change throughout the entire lifetime of the integrated circuit, which can be used to address process variation. An exemplary embodiment for addressing the process variation problem is a resistor ladder with a power supply that depends on the reference ladder itself. Such a circuit is depicted in Figure 33. This provides several benefits, including: Because the current of the bottom transistor follows an exponential curve of the required control voltage, it covers a wide tuning range; No factory calibration is required; it can be automatically calibrated upon radio wave initiation of the circuit. Independent of power supply voltage; This includes a negative feedback loop, which further reduces the changes caused by residual temperature.

[0129] Figure 34 illustrates the relationship between reference voltage spread and temperature for the exemplary native / negative MOSFET pattern depicted in Figure 33 according to an embodiment of the present invention, while Figure 35 illustrates the transient noise performance of the exemplary native / negative MOSFET pattern depicted in Figure 33. Therefore, the compiled characteristics of the exemplary native / negative MOSFET pattern depicted in Figure 33 are as follows: The maximum reference voltage is extended to ~26 mV / 1 V; Transient noise is typically ~1 mVpp, and 2-3 mVpp at 85°C; DC current consumption is typically 12 nA, with a maximum current of <300 nA; and The die area used for decoupling (excluding the tuning branch) is ~11 x ~22 m.

[0130] 9. Ultra-low power, low differential pressure regulator

[0131] The radio wave devices according to embodiments of the present invention (UWB receiver, UWB transmitter, and UWB transceiver circuitry as described above) support active dual-cycle operation to provide a very low-power design. To achieve this active power reduction, internal voltage converters (such as linear voltage reference buffers and DC-DC converters) must also be powered down to achieve sleep-state power consumption below one microamp, while ensuring that the SPI interface and all critical digital portions of the circuitry remain powered. Therefore, these circuit portions on the always-on digital circuitry are limited to extremely low leakage current (~100 nA), thus requiring the inclusion of thick gate oxide input / output transistors. However, since the main operating voltage of the chip ranges from 1.8V to 3.6V, the unregulated digital transistors must be large, thus occupying a significant die area and exhibiting excessive dynamic power consumption. Therefore, the inventors have developed an innovative feedback-free low-dropout (LDO) regulator that does not require explicit voltage regulation, but whose output voltage is low enough and sufficiently independent of the main chip power supply, so that the transistors used for always-on digital cores are small enough.

[0132] Furthermore, the lower supply voltage reduces the charging and discharging of all parasitic capacitances required for each digital signal transition, resulting in very low dynamic power consumption. Additionally, to achieve practical overall energy savings, the LDO should have a very low quiescent current (on the order of a few nanoamps), thus requiring no or no feedback. Referring to the circuit depicted in Figure 36, the output may vary well beyond one hundred millivolts depending on operating conditions, the digitizer clock rate, and activity; however, since this only powers the digitizer circuitry, output voltage accuracy is not particularly important for normal circuit operation, as long as it does not degrade to a level that would slow down the circuitry. In Figure 36, the LDO is shown in context and consists of transistors M15, M31, and M32. As depicted, these transistors are positioned between the reference bandgap circuitry and the rest of the digitizer circuitry.

[0133] Therefore, similar to the unbiased low-power differential (exponential) transconductance stage described in Section 7 above, the first two transistors, M15 and M31, embody an equivalent of a CMOS Class AB power amplifier that isolates the sensitive high-impedance node at the bandgap output from any digital noise fed from the source of the large transistor M32 to its gate, aided by capacitive decoupling (C28). Apart from this noise, the intermediate current branches of transistors M15 and M31 are inactive, with only quiescent current consumption (typically 3 nA). This is the only current preventing the LDO from reaching 100% current efficiency, but it isolates the sensitive input node and allows for a slight voltage increase from the 1.3V bandgap output voltage due to the much lower threshold voltage of the native NMOS M31 compared to M15. In this case, the M32 transistor operates in the subthreshold or near-threshold region, where the source of the large transistor M32 is fed to its gate. The transfer function to the current is essentially exponential, allowing the current demand to change by several orders of magnitude from one transient to another without producing a voltage drop of no more than a few hundred mV, although the circuit using the output is not sensitive to this.

[0134] 10. Dynamically biased preamplifier with latch comparator

[0135] In Figure 37A, the innovative circuit is depicted as a self-contained circuit, where the regenerative latch depicted in Figure 37B is only used to provide context for the new innovative circuit and explain its function.

[0136] When designing dynamic preamplifier stages, circuit designers consistently face a trade-off between power consumption and accuracy. Due to unavoidable current noise sources in MOSFETs, especially thermal noise, it is necessary to draw a significant amount of current through differential-pair NMOS and PMOS transistors (both in this example) to "average out" the current noise and provide accurate comparisons. However, the more current drawn, the higher the energy consumption.

[0137] Therefore, it is beneficial that the total current in the differential pair will be less than the total current in the differential pair. (Transconductance factor) is maximized. Therefore, referring to Figure 37A, this problem is solved by providing NMOS and PMOS input differential pairs (i.e., M0 / M1 and M4 / M5, respectively) that together form a structure similar to an undercurrent inverter. Initially, the PMOS transistors are intended to be directly connected to VDD and made slightly weaker than the NMOS transistors, so that the output node is eventually pulled low enough to turn on the input transistors of the latch (including M33 and M35). This results in a certain amount of quiescent current being wasted waiting for the regenerative latch to "make a decision" after the input PMOS transistors of the latch are turned on.

[0138] Therefore, to address this issue and the need to adjust the strength (effective width) of various supply / reference voltages, a "dynamic bias" technique is implemented for the PMOS differential pair (M4 / M5) instead of the NMOS differential pair (M0 / M1). This limits the amount of charge absorbed unevenly (by default) between the two PMOS transistors when the differential input voltage (INp-INn) is non-zero, thereby reducing energy consumption and facilitating further amplification of the difference between the preamplifier outputs. With this dynamic bias, as long as the PMOS transistor's startup is stronger than the NMOS transistor's, the voltages at nodes OUTp and OUTn will remain high until sufficient current is drawn from the dynamic bias capacitor C10. When C10 is sufficiently consumed and there is insufficient current... To maintain a stronger conduction state for a PMOS transistor than an NMOS transistor, the PMOS transistor will change its state from transistor to saturation. Even the slightest voltage difference between PMOS transistors will cause one PMOS to saturate slightly before the other, allowing the drain voltage to be pulled down more quickly. To further amplify the difference between the outputs, the drain (preamplifier output) voltage will be pulled down faster than its corresponding voltage because of the lower voltage difference of the PMOS. This means that NMOS has a higher Because they share the same gate voltage, this is a "fighting" current. Therefore, one node starts to drop before the other and is consumed at a faster rate than its corresponding node, which helps to create comparator circuits that make more accurate decisions.

[0139] Referring to Figure 37A, no node has been reached. and The explicit drive connection, since it can be optionally connected to any common voltage node or biased, clearly indicates that there are several options available to achieve this, which can be implemented in combination with the circuit of Figure 37A. Furthermore, transistors M20 and M21 are optional, provided that their drains are shorted to their respective sources before removal, and their sole purpose is to prevent the OUTp and OUTn nodes from entering their saturation state in the PMOS differential pair (at which point...). The voltage drops too low before reaching approximately >100mV (at which point the differential pair effectively amplifies the differential signal). It will be apparent to those skilled in the art that, for clarity, it is not described that nodes OUTp and OUTn are recharged to [value missing] after the comparison. The required pair of PMOS transistors should have their gates connected to the clock "clk" node.

[0140] Alternatively, in another embodiment of the invention, the common source node for the PMOS transistor can be divided into two separate nodes with two separate but equal capacitors. The advantage of this alternative configuration is that the NMOS transistor, possibly without dynamic bias, effectively determines how much current is drawn from each output node. In this way, a larger output voltage difference, or at least an equivalent output voltage difference, can be achieved by separating the charge that must be drawn between the two NMOS transistors, so that the NMOS transistor that draws more current does not inadvertently draw more charge than is intended to be drawn by the other, slower NMOS. Therefore, dumping more charge at a node where the voltage drops before the other node would be counterproductive.

[0141] Specific details are set forth in the foregoing description to provide a thorough understanding of the embodiments. However, it should be understood that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure the embodiments with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0142] The aforementioned technologies, blocks, steps, and devices can be implemented in various ways. For example, these technologies, blocks, steps, and devices can be implemented in hardware, software, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the aforementioned functions, and / or combinations thereof.

[0143] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications or equivalent substitutions made to the present invention without departing from the spirit and scope thereof should be covered within the protection scope of the patent application of the present invention.

[0144] 110: First Residential Environment 120: Second residential environment 130: Industrial Environment 140: Personal Area Network (PAN) 150: Medical Imaging 200: IR-UWB Transmitter 210: and gate 220: Power Cyclic Controller 230: Pulse Generator 240:DCRO 250: VGA 260: Driver 270: Antenna 300: Flowchart 310: and gate 320: Power Cyclic Controller 330: Pulse Generator 340:DCRO 350: VGA 360: Switch 370: Antenna 380: Power Amplifier 3000: Flowchart 3010: Pulse Mode Block 3020: Multiplexer 3030:DLL 3040:DCO 3050: Pulse Generator 3060:PA 3070: Antenna 3100A: First Image 3100B: Second Image 3120:UWB mask 3160: bits 3160A: Pulse 3160B: Pulse 3160C: Pulse 3180: Multipulse Spectrum 400: IR-UWB Receiver 410: Antenna 420:LNA 430: First Amplifier 440: Square circuit 450: Second Amplifier 460: Integrating Circuit 470:ADC 480: Power Cyclic Controller 500: Receiver 510: Antenna 520:LNA 530:AMP1 540:MIX1 550: VGA 560:MIX2 580: Processing Circuit 600: Transceiver 605: DC-DC Converter 610: Bandgap reference 615: Low-frequency crystal oscillator 620: Sleep Counter 625: Receiver 630:ADC 635: PHY formatting circuit 640: Buffer and Interface Circuit 645: Link Controller 650: PHY processing circuit 655:PLL 660:DLL 665: Spectrum Configuration Circuit 670:MUX 675: Pulse Generator 680: Mixer 685:PA 690: Switch 695: Client 6000: Transmitter 710: Transceiver wake-up delay 720: Delay 900A: UWB Receiver 900B: Composite MOSFET 905: Antenna 910: Low-noise amplifier 915: First Filter 920: Mixer 925: Amplifier 930: Second Filter 935: First Square Analyzer 940: First signal processing circuit 945: Summation Circuit 950: Second signal processing circuit 955: Magnification stage 960: Third Filter 965: Second Squarer 970: Integrator 980: Third signal processing circuit

Claims

1. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes: a current source; and multiple transistors arranged in a stepped configuration of N electrical nodes; node 0 is grounded; the gate of the i-th transistor is connected to node (i-1); the source of the i-th transistor is connected to node i; the drain of the i-th transistor is connected to node (i+1); and the current source is disposed within a gap left in the current path between node 0 and node 1.

2. The method for designing electronic circuits as described in claim 1, wherein, At least one of the following: Each transistor is a native transistor or a depletion-mode transistor; and the voltage source also includes tuning circuitry for tuning the current source to allow calibration of the voltage source.

3. The method for designing electronic circuits as described in claim 1, wherein, The current source in the current path between node 0 and node 1 is controlled by a control voltage; the control voltage is established based on the selected tap of a multi-tap voltage divider, wherein the voltage divider is coupled between one end of a linear transistor array and ground; and the linear transistor array includes a plurality of other transistors equal in number to the plurality of transistors, and the other end of the linear transistor array is coupled to the source voltage.

4. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals, wherein the electronic circuit includes: a port for receiving a first signal and coupled to the electronic circuit; a PMOS gate and an NMOS gate, electrically connected in parallel to the port and respectively connected to each other; a first portion of the electronic circuit electrically connected to the PMOS gate; and a second portion of the electronic circuit electrically connected to the NMOS gate; the port functions in the same manner as if the PMOS gate and NMOS gate were not present; and the first and second portions of the electronic circuit now have twice the voltage threshold of the port.

5. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes: a port for receiving a first signal and coupled to the circuit; a PMOS gate and an NMOS gate, electrically connected in parallel to the port and respectively connected to each other; a first portion of the circuit electrically connected to the PMOS gate; and a second portion of the electronic circuit electrically connected to the NMOS gate; for a slow rising transition within the first signal, the actual input voltage has risen above the threshold voltage of the NMOS gate before the voltage at the first node between the NMOS gate and the second portion of the electronic circuit begins to rise and then becomes on; when the gate connection of the NMOS gate is connected to the drain connection of the PMOS gate, the voltage at the first node lags behind the voltage at the second node between the PMOS gate and the first portion of the electronic circuit; and for a falling transition within the first signal, the voltage at the second node lags behind the voltage at the first node.

6. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes: a first MOSFET comprising a first drain, a first gate, a first source, and a first substrate connection; a second MOSFET comprising a second drain, a second gate, a second source, and a second substrate connection; a first port electrically connected to the first gate, the second gate, and the first substrate connection; a second port electrically connected to the first drain; and a third port electrically connected to the second source and the second substrate connection. The first and second MOSFETs are of the same type and are either n-channel or p-channel MOSFETs.

7. The method for designing electronic circuits as described in claim 6, wherein, The electronic circuit further includes: a third MOSFET disposed between the first MOSFET and the second MOSFET, and including a third drain, a third gate, a third source, and a third substrate connection portion; a first port is also coupled to the third gate; the third drain is connected to the first source; the third source is connected to the second drain; the third substrate connection portion is connected to the third drain, such that the bias voltage of the third MOSFET is between the bias voltages of the first MOSFET and the second MOSFET; and the third MOSFET is of the same type as the first MOSFET.

8. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes: at least one differential pair of composite MOSFETs, each composite MOSFET including: a first MOSFET comprising a first drain, a first gate, a first source, and a first substrate connection; and a second MOSFET comprising a second drain, a second gate, a second source, and a second substrate connection; a first port electrically connected to the first gate, the second gate, and the first substrate connection; a second port electrically connected to the first drain; a third port electrically connected to the second source and the second substrate connection; and an electrical connection located between the first source and the second drain; and the first MOSFET and the second MOSFET are of the same type and are one of an n-channel MOSFET and a PMOS MOSFET.

9. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes: at least one differential pair of composite MOSFETs, each composite MOSFET including: a first MOSFET including a first drain, a first gate, a first source, and a first substrate connection; and a second MOSFET including a second drain, a second gate, a second source, and a second substrate connection; a first port electrically connected to the first gate, the second gate, and the first substrate connection; a second port electrically connected to the first drain; a third port electrically connected to the second source and the second substrate connection; and an electrical connection located between the first source and the second drain; the first MOSFET and the second MOSFET are of the same type and are one of an n-channel MOSFET and a PMOS MOSFET; a third MOSFET disposed between the first n-channel MOSFET and the second MOSFET, and including a third drain, a third gate, a third source, and a third substrate connection; the first port is also coupled to the third gate; the third drain is connected to the first source; and the third source is connected to the second drain. The third substrate connection portion is connected to the third drain, such that the bias voltage of the third MOSFET is between the bias voltages of the first MOSFET and the second MOSFET; and the third MOSFET is of the same type as the first MOSFET.

10. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes first to fourth composite MOSFETs, each composite MOSFET comprising: a first MOSFET including a first drain, a first gate, a first source, and a first substrate connection; a second MOSFET including a second drain, a second gate, a second source, and a second substrate connection; and a third MOSFET disposed between the first and second MOSFETs, including a third drain, a third gate, a third source, and a third substrate connection; a first port electrically connected to the first gate, the second gate, the third gate, and the first substrate connection; a second port electrically connected to the first drain; a third port electrically connected to the second source and the second substrate connection; a third drain connected to the first source; a third source connected to the second drain; and a third substrate connection connected to the third drain, such that the bias voltage of the third n-channel MOSFET is between the bias voltages of the first n-channel MOSFET and the second n-channel MOSFET; and the first, second, and third MOSFETs are all n-channel MOSFETs or p-channel MOSFETs.

11. The method of designing electronic circuits as described in claim 10, wherein, The second ports of the first and second composite MOSFETs are coupled to the upper power rail; the third ports of the third and fourth composite MOSFETs are coupled to the lower power rail via a current source; the first ports of the third and fourth composite MOSFETs are coupled to the differential input port; the third ports of the first and second composite MOSFETs are coupled to the first ports of the third and fourth composite MOSFETs. The first port of the first composite MOSFET is coupled to the third port of the first composite MOSFET; The first port of the second composite MOSFET is coupled to the third port of the first composite MOSFET; The output is coupled to the third output port of the second composite MOSFET and the second output port of the third composite MOSFET.

12. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes an unbiased differential (exponential) transconductance stage comprising: a pair of differential signal input ports; a first NMOS gate and a second NMOS gate, both coupled to one of the differential signal input ports; and a first PMOS gate and a second PMOS gate, both coupled to one of the differential signal input ports; wherein, either: the source of each of the first NMOS transistor and the second NMOS transistor, and the sources of the first PMOS gate and the second PMOS gate are all connected together; or: the sources of the first NMOS transistor and the second NMOS transistor are connected together at a first node of the electronic circuit, and the sources of the first PMOS gate and the second PMOS gate are connected together at a second node of the electronic circuit.

13. A method relating to designing electronic circuits, comprising: An electronic circuit is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuit includes a voltage source comprising: a plurality of N transistors in a series array; the source of a primary transistor i among the plurality of N primary transistors is coupled to the drain of a primary transistor (i-1) among the plurality of N active transistors, where i = 2, …, N; the source of a first primary transistor among the plurality of N primary transistors is coupled to ground; the substrate of a primary transistor j among the plurality of N primary transistors is coupled to ground, where j = 1, …, N; and the gate of a primary transistor k among the plurality of N primary transistors is coupled to a node located between the source of transistor (k-1) among the plurality of N active transistors and the drain of a primary transistor (k-2) among the plurality of N active transistors, where k = 3, …, N and k is an integer.

14. A method relating to designing electronic circuits, comprising: Electronic circuitry is provided as part of a wireless transmitter circuit, a wireless receiver circuit, and a wireless transceiver circuit for processing wireless signals. The electronic circuitry includes a low-dropout regulator comprising: a high-impedance reference voltage source; and a pair of first transistors that isolate the output of the reference voltage circuit from any digital noise fed from the source of a second transistor to the gate of the second transistor; wherein a first upper transistor and a first lower transistor of the pair of first transistors are connected in series between an upper power rail and ground; the drain of the first upper transistor is connected to the upper power rail, and the source of the first lower transistor is connected to ground; the gate of the second transistor, the source of the first upper transistor, and the drain of the first lower transistor are all coupled to a common node; and the high-impedance reference voltage source is coupled to the gate of the first lower transistor and the gate of the first upper transistor.

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