Nonvolatile semiconductor memory

Abstract

An embodiment of the present invention provides a memory system for a neural network, a memory controller, and a semiconductor memory device. The memory system of the embodiment includes: a control unit that transmits a first instruction set containing first data; and a semiconductor memory device that, by receiving the first instruction set from the control unit, transmits second data based on the first instruction set to the control unit.

Claims

1. A non-volatile semiconductor memory comprising: a first memory string; a first wiring connected to one end of the first memory string; a second wiring connected to the other end of the first memory string; a first circuit capable of controlling the first wiring according to first data; a second circuit connected to the second wiring, including a current mirror circuit, and outputting second data based on the amount of current flowing to the second wiring; a second memory string, one end of which is connected to the second wiring; a third wiring connected to the other end of the second memory string; and a fourth wiring commonly connected to a first transistor included in the first memory string and a second transistor included in the second memory string. The first circuit described above can perform: a first readout operation, which applies a first voltage to the fourth wiring; and a second readout operation, which is performed after the first readout operation, applying a second voltage higher than the first voltage to the fourth wiring; the first wiring is: pre-charged to a third voltage before the first readout operation is performed, and becomes a fourth voltage lower than the third voltage when the first readout operation is performed; in the second readout operation, the first wiring is not pre-charged.

2. The non-volatile semiconductor memory of claim 1, wherein the first memory string has a plurality of memory cells connected in series.

3. The non-volatile semiconductor memory of claim 2, wherein the first memory circuit has a first select transistor between the first wiring and the plurality of memory cells, and a second select transistor between the second wiring and the plurality of memory cells.

4. The non-volatile semiconductor memory of claim 1, wherein the fourth wiring is subjected to a voltage corresponding to the first data, and the first circuit can control the first wiring and the third wiring.

5. The non-volatile semiconductor memory as claimed in claim 1, wherein the fourth wiring described above is a word line.

6. The non-volatile semiconductor memory of claim 1, wherein the third wiring is: pre-charged to the third voltage before the first read operation is performed, and the third wiring does not change to the fourth voltage when the first read operation is performed, and the third wiring is pre-charged during the second read operation.

7. The non-volatile semiconductor memory of claim 1, wherein a fifth voltage is applied to the first wiring according to the first data described above, and a sixth voltage different from the fifth voltage is applied to the third wiring.

8. The non-volatile semiconductor memory as claimed in claim 1, wherein the second data mentioned above is the value after converting the current quantity into a digital value.

9. The non-volatile semiconductor memory as described in claim 8, wherein the second data mentioned above is converted into a digital value by a binary search.

10. The non-volatile semiconductor memory as claimed in claim 1, wherein the first memory cell contained in the first memory string is a NAND flash memory.

11. The non-volatile semiconductor memory as claimed in claim 1, wherein the first wiring is a bit line and the second wiring is a source line.

12. The non-volatile semiconductor memory of claim 1, wherein the second circuit has a comparator comprising: a first terminal input to a first voltage based on the current quantity; and a second terminal input to a second voltage.

13. The non-volatile semiconductor memory as claimed in claim 12, wherein the second data is output from the comparator.

14. The non-volatile semiconductor memory of claim 12, wherein the second circuit further comprises: a third transistor, one end of which and its gate are connected to the first terminal; and a fourth transistor, one end of which is connected to the second terminal, and the gate of the third transistor is connected to its gate.

15. The non-volatile semiconductor memory of claim 1, wherein the second circuit described above has a diode connection.

16. The non-volatile semiconductor memory of claim 1, wherein the current mirror circuit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected to the gate of the sixth transistor, and the gate width of the sixth transistor is different from the gate width of the fifth transistor.

17. The non-volatile semiconductor memory of claim 16, wherein one end of the fifth transistor is connected to the second wiring, and the current is reflected by the current mirror circuit.

18. The non-volatile semiconductor memory of claim 1, wherein the second circuit comprises: a third circuit including a comparator having: a first terminal for receiving an input reference voltage and a second terminal connected to the second wiring; and a fourth circuit that converts the current quantity into a digital value.

Images