Memory system and operation method thereof

Abstract

This case discloses a memory system. The memory system includes a memory array and a controller. The controller performs a refresh operation on the memory array at a first refresh cycle rate. The first refresh cycle rate is derived from a first refresh time in a lookup table. The lookup table stores the refresh time and the refresh temperature corresponding to the refresh time, respectively.

Description

Methods and systems for updating memory devices none Compared to other non-volatile memories, magnetoresistive random access memory (MRAM) can be rewritten at high speed. Therefore, we consider applying MRAM to working memory such as main memory and cache memory. When the magnetic tunnel junction (MTJ) element, which serves as the storage element of MRAM, is enabled for high-speed access in order to apply MRAM to cache memory, data retention characteristics may degrade, and data retention time may shorten under high temperature conditions. none The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely exemplary and in no way intended to limit an embodiment of this disclosure or the scope and meaning of any illustrative terms. Similarly, this disclosure does not limit the various embodiments given in this specification. Although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and similar terms should be understood as open-ended, meaning including but not limited to. As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, where the approximation varies depending on the various techniques to which it pertains, and the range of the approximation should conform to the broadest interpretation understood by one skilled in the art in order to encompass all such modifications and similar structures. In some embodiments, it should generally mean within 20% of a given value or range, preferably within 10% of a given value or range, and more preferably within 5% of a given value or range. The numerical quantities given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially,” or refer to other approximations, can be inferred. Referring now to Figure 1A. Figure 1A is a schematic diagram of a wafer 100 including a plurality of integrated circuit chips / dies 110 according to various embodiments of this disclosure. As illustrated in Figure 1A, the integrated circuit die 110 includes a memory device 111. In some embodiments, the memory device 111 is implemented as a data storage device for writing and / or reading electronic data. In various embodiments, the data storage device is implemented as volatile memory such as random-access memory (RAM), which conventionally requires power to maintain the information it stores, or as non-volatile memory such as read-only memory (ROM), which can maintain the information it stores even when not powered. RAM can be configured as dynamic random-access memory (DRAM), static random-access memory (SRAM), and / or non-volatile random-access memory (commonly referred to as flash memory). Electronic data can be written to and / or read from an array of memory cells, which can be accessed via various control lines. In some embodiments, magnetic random access memory (MRAM) and resistive random access memory (RRAM) are two types of memory devices developed in recent years. MRAM and RRAM can be used in embedded memory, DRAM replacements, flash memory replacements, and other applications. MRAM and RRAM devices are inherently sensitive to process variations during device manufacturing. Therefore, inter-die memory performance differences on the semiconductor wafer 100 can be observed during testing. Different dies at different wafer locations (e.g., central die versus edge die) typically have extremely different read / write windows, and the failure rate for read / write window margin performance tests is very high, which may limit the effectiveness of MRAM and RRAM devices. Referring now to Figure 1B. Figure 1B is a schematic graph including curve C1, which illustrates the inter-die distribution relative to its normalized refresh time according to various embodiments of this disclosure. The refresh time represents the moment when the data stored in the MRAM is lost or disappears. For illustrative purposes, the inter-die distribution has a Gaussian distribution. In some embodiments, different MRAM cells / arrays on different dies may have different refresh times and different hold times for retaining data in the MRAM cells / arrays. In other words, the data stored in the MRAM cells / arrays may be lost or disappear after the hold time has elapsed or after the refresh time has been reached. Therefore, a refresh operation is performed on the MRAM cells / arrays before the refresh time to retain the stored data. However, as discussed above, there are significant differences in the hold times of different MRAM cells / arrays on different dies, so in some methods, performing refresh operations on all MRAM arrays on different dies at a consistent refresh cycle rate is inefficient (too frequent or too infrequent for some dies). Furthermore, rewriting negatively impacts memory performance and power dissipation. First, the memory controller stops making normal read and write requests to the rewritten portion of the memory. Second, rewriting consumes energy because rewriting memory involves operations such as reading and restoring data. As the speed and size of memory devices continue to increase with each new technology, the performance and power management burden of rewriting increases significantly. This disclosure provides a memory system and method for automatically and digitally setting the refresh cycle rate of memory arrays on different chips based on their refresh time-temperature characteristics. In some embodiments, a memory controller included in the memory system acquires refresh time data of the memory arrays on the memory devices based on the operating temperature sensed by temperature sensors on a plurality of memory devices (chips). The refresh time data is stored in a lookup table in a storage unit. In some embodiments, the lookup table is generated by counting the refresh time cycles of the memory array. Based on the acquired refresh time data, the memory controller further sets the refresh cycle rate of the refresh operation to be performed on the memory array. Therefore, the refresh cycle rate of the memory arrays on different memory devices can be set separately and optimized based on the temperature-dependent characteristics of the individual memory devices. Referring now to Figure 2. Figure 2 is a schematic diagram of a memory system 200 according to another embodiment of this disclosure. As illustrated in Figure 2, the memory system 200 includes a memory controller 210, a storage unit 220, and at least one memory device 230. In some embodiments, the memory device 230 is configured relative to the memory device 111 in Figure 1A and is located on one of a plurality of chips in the memory system 200. For illustrative purposes, the memory device 230 is coupled to the memory controller 210. The memory controller 210 is further coupled to the storage unit 220. For illustrative purposes, as shown in Figure 2, the memory controller 210 includes a processing unit 212, a timer (scheduler) 214, and a refresh controller 216. The memory device 230 includes a memory array 230a and a temperature sensor (sensing circuit) TS. Detailed configuration and operation of the components in the memory system 200 will be discussed in the following paragraphs with reference to Figures 3 through 6. In some embodiments, memory controller 210 is implemented by one or more memory controller circuits or devices of memory system 200. Memory controller 210 is used to generate memory access commands and access one or more memory devices 230 and storage units 220. In various embodiments, memory controller 210 includes I / O interface logic (not shown) coupled to a memory bus (not shown). I / O interface logic includes pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or combinations thereof. In various embodiments, I / O interface logic includes hardware interfaces or drivers, receivers, transceivers, or terminals, or other circuitry or combinations thereof for exchanging signals on signal lines between devices. Signal exchange includes at least one of transmission or reception. Although shown as a memory controller 210 coupled to a memory device 230, it should be understood that in the implementation of the memory system 200 with multiple groups of memory devices 230 accessing each other in parallel, multiple memory devices are implemented as having an I / O interface that includes the same interface to the memory controller 210. In some embodiments, storage unit 220 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage unit 220 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disc. In one or more embodiments using optical discs, storage unit 220 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD). In some embodiments, memory device 230 is implemented by an MRAM device as described above. In various embodiments, memory device 230 serves as a memory resource for memory system 200. In one embodiment, multiple memory devices 230 reside on separate memory dies. Each memory device 230 includes I / O interface logic (not shown) having a bandwidth determined by the implementation of the device, and enables each memory device 230 to interface with memory controller 210. In one embodiment, multiple memory devices 230 are connected in parallel to the same command and data buses. In another embodiment, multiple memory devices 230 are connected in parallel to the same command bus and to different data buses. For write operations, individual memory devices 230 write a portion of a total data word, and for read operations, individual memory devices 230 retrieve a portion of the total data word. For illustrative purposes, the configuration of Figure 2 is shown. Various implementations are within the scope of one embodiment of this disclosure. For example, in some embodiments, the memory controller 210 is included in the processor. In various embodiments, the memory controller 210 receives instructions from the processor coupled thereto. Referring now to Figure 3. Figure 3 is a flowchart of method 300 according to some embodiments of this disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in Figure 3, and some of the operations described below may be substituted or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable. Similar element symbols are used to identify similar elements throughout the various views and illustrative embodiments. Method 300 includes operations 310-370 described below with reference to Figures 2 and 4. In operation 310, a test system (not shown) counts the refresh time cycles of the memory array 230a on the memory device (die) 230. In some embodiments, the refresh time cycle counting is performed by a timer 214 on each memory device 230 at different operating temperatures. For example, a temperature sensor TS on the memory device 230 is used to sense the operating temperature associated with the memory array 230a on the memory device 230. In some embodiments, the sensed operating temperature is configured as the refresh temperature for the refresh operation of the memory array 230a. In operation 320, the count refresh time period of memory array 230a is recorded. For example, when an error or loss of data stored in memory array 230a is detected, the timer in the test system stops counting, and the processor unit in the test system records the count refresh time period at different operating temperatures into a lookup table. In operation 330, a lookup table for storing the recurrence interval and operating temperature is generated and stored in storage unit 220. In some embodiments, the lookup table is represented as follows: Table I. Exemplary lookup table for memory array 230a on memory device (die) 230 In some embodiments, multiple lookup tables are generated, and each lookup table corresponds to one of the memory devices (dies) 230. Due to inter-die differences in the memory devices 230, the lookup tables for different memory devices 230 are different. In various embodiments, the lookup tables are referred to as inter-die difference tables. In some embodiments, the memory device 230 and storage unit 220 are further disconnected from the test system prior to shipment. In other words, the lookup table of the memory device 230 is generated / pre-static. Referring again to Figure 3, in operation 340, memory devices 230 are operated within memory system 200, and a temperature sensor TS in each memory device 230 is used to sense the operating temperature. For example, the temperature sensor TS senses an operating temperature of approximately 85°C. In some embodiments, multiple memory devices 230 operate at similar temperatures. In various embodiments, memory devices 230 are operated at different temperatures, which are sensed by the temperature sensor TS on each memory device 230. In operation 350, the memory controller 210 looks up a value in a lookup table based on the operating temperature. For example, the memory controller 210 receives a data signal D1 having a sensed operating temperature of 85°C associated with a memory array 230a on a memory device 230. By sending a control signal CM1 to the storage unit 220, the memory controller 210 looks up a value in the lookup table based on the operating temperature of 85°C. In some embodiments, the processing unit 212 of the memory controller 210 executes instructions corresponding to operation 350. In some embodiments, method 300 further includes memory controller 210 receiving data signal D2 from storage unit 220 and retrieving a refresh time of approximately 100 seconds from a lookup table. In some embodiments, memory controller 210 searches a lookup table associated with memory arrays 230a on all memory devices 230 in memory system 200 and retrieves the corresponding refresh times for all memory arrays 230a. In some embodiments, processing unit 212 of memory controller 210 executes instructions corresponding to the retrieved information. Referring again to Figure 3, in operation 360, the memory controller 210 sets a refresh cycle rate for performing a refresh operation on the memory array 230a on the memory device 230. In some embodiments, the refresh cycle rate is determined to be a duration shorter than the corresponding refresh time. For example, referring to lookup table I above, the refresh time corresponding to an operating temperature of approximately 25°C is approximately 1.4 years, and the refresh cycle rate is set to approximately 1.39 years. The refresh time corresponding to an operating temperature of approximately 50°C is approximately 2.6 days, and the refresh cycle rate is set to approximately 2.5 days. The refresh time corresponding to an operating temperature of approximately 85°C is approximately 100 seconds, and the refresh cycle rate is set to approximately 99 seconds. The refresh time corresponding to an operating temperature of approximately 105°C is approximately 1 second, and the refresh cycle rate is set to approximately 0.9 seconds. Therefore, a refresh operation will be performed on the memory array 230a before the stored data is lost. In some embodiments, after setting the renew cycle rate, the memory controller 210 initializes the timer 214 to perform a count of renew time cycles. In operation 370, when the counted refresh time period meets a refresh cycle rate of approximately 99 seconds, the refresh controller 216 of the memory controller 210 performs a refresh operation on the memory array 230a. In other words, the memory controller 210 refreshes the data stored in the memory array 230a at a refresh cycle rate of approximately 99 seconds. In some embodiments, the memory controller 210 performs the refresh operation via a control signal CM2 sent to the bit lines or word lines in the memory array 230a. In some embodiments, method 300 further includes calculating the refresh cycle rate using the memory controller 210 based on an inter-die difference table. As shown in Figure 4, which is a schematic graph including regression line C2, the refresh / operating temperature of a memory array according to various embodiments of this disclosure is relative to its refresh time (corresponding to lookup table I). For illustrative purposes, given regression line C2, a corresponding regression equation is obtained. Therefore, the expected refresh time at a specific operating temperature is calculated using the regression equation, and the corresponding refresh cycle rate is determined. For example, in the embodiment shown in Figure 4 and Lookup Table I, based on the regression equation corresponding to regression line C2, the calculated recycle rate corresponding to a given operating temperature of approximately 70°C is approximately 12.5 minutes. In various embodiments, the calculated recycle rate corresponding to a given operating temperature of approximately 40°C is approximately 8.89 days. For illustrative purposes, the configurations in Figures 3 and 4 are shown. Various implementations are within the scope of one embodiment of this disclosure. For example, in some embodiments, instead of the memory controller 210 setting the refresh rate, the refresh rate is determined after a lookup table is generated and stored in storage unit 220. In other words, operations 310-330 are performed before the memory system 200 is shipped, and operation 360 is replaced by retrieving a preset refresh rate from a lookup table including the refresh rate, for example, as shown in Lookup Table II below: Table II. Lookup table for memory array 230a on memory device (chip) 230 In some embodiments, method 300 further includes detailed operations. Referring now to Figure 5. Figure 5 is a flowchart illustrating detailed operations of method 300 corresponding to Figure 3 according to some embodiments of this disclosure. For illustrative purposes, method 300 further includes operations 341-345 described below with reference to Figures 2 and 4. Continuing with operation 340 in Figure 3, after sensing the operating temperature, the memory controller 210 further determines whether the operating temperature has changed. In some embodiments, if it is determined that the operating temperature has not changed, operation 342 is executed. Conversely, if the operating temperature changes, operation 343 is executed. In operation 342, because the operating temperature remains constant, the memory controller 210 continues to use the refresh controller 216 to refresh the data stored in the memory array 230a at the original refresh cycle rate. For example, when the operating temperature of the memory array 230a on a memory device 230 is maintained at about 50°C, the memory controller 210 continues to refresh the memory array 230a at the original refresh cycle rate of about 2.5 days corresponding to the operating temperature of about 50°C for several refresh cycles until the operating temperature changes. When the operating temperature changes, operation 343 is executed. In operation 343, the memory controller 210 further acquires another refresh time corresponding to the changed operating temperature. For example, in some embodiments, when the operating temperature changes from about 50°C to about 85°C, the memory controller 210 acquires a refresh time of about 100 seconds. In various embodiments, method 300 further includes determining whether the changed operating temperature is lower than the original operating temperature. When the changed operating temperature is lower than the original operating temperature, timer 214 maintains a count of the current refresh time period until a refresh operation is performed. In some embodiments, after performing a refresh operation, memory controller 210 performs operation 343 to obtain another refresh time corresponding to the changed operating temperature. In other words, the refresh cycle rate is set or determined based on the refresh time corresponding to the highest operating temperature detected in the current refresh interval. Following operation 343, in operation 344, the memory controller 210 further sets another refresh cycle rate corresponding to the changed operating temperature. For example, as discussed in the embodiments above, the memory controller 210 sets a new refresh cycle rate of approximately 99 seconds corresponding to the changed operating temperature of 85°C. In other words, as the operating temperature increases (i.e., from approximately 50°C to approximately 85°C), the duration of the refresh cycle rate decreases (i.e., from approximately 2.5 days to approximately 99 seconds). In other words, when the operating temperature increases, the refresh cycle rate is faster than the original refresh cycle rate. Similarly, in various embodiments, when the operating temperature decreases (i.e., from approximately 50°C to approximately 25°C), the duration of the refresh cycle rate increases (i.e., from approximately 2.5 days to approximately 1.39 years). In other words, when the operating temperature decreases, the refresh cycle rate is slower than the original refresh cycle rate. Referring again to Figure 5, after performing operation 344, operation 345 is performed. In operation 345, the memory controller 210 resets timer 214 to count new time cycles. For example, in some embodiments, when the new time cycle counted by timer 214 is 1.5 days, the operating temperature of memory array 230a changes from about 50°C to about 85°C. In response to the changed operating temperature, timer 214 is reset to 0, and timer 214 counts new time cycles at about 85°C. In some embodiments, after performing operation 345, operation 370 of Figure 3 is performed, and operation 340 continues to be performed. In some methods, the refresh cycle rate of the entire memory array is the same at different operating temperatures. Furthermore, to prevent data loss at higher temperatures, the refresh cycle rate is fixed at higher temperatures. Therefore, when the memory device operates at lower temperatures, refresh operations are performed too frequently, impacting the memory device's performance and power consumption. Conversely, with the configuration of an embodiment of this disclosure, the refresh cycle rate of the memory array can be automatically adjusted according to the operating temperature. Additionally, memory arrays on various chips are refreshed based on die-dependent refresh time characteristics. Furthermore, the performance and power consumption of the memory device are improved. Furthermore, the memory devices within the memory system experience various ambient temperatures. For example, airflow within the memory system 200, through which the memory device 230 operates, blows from the left side of the memory system 200 to the right side. Based on the airflow direction within the memory system 200, the temperature of the memory device 230 on the left side of the memory system 200 is lower than the temperature of the memory device 230 on the right side of the memory system 200. With the configuration shown in Figure 5, the memory device 230, operating at different changed operating temperatures, can be refreshed at different refresh rates. Therefore, the refresh operation of the memory device 230 is optimized. For illustrative purposes, the configuration in Figure 5 is shown. Various implementations are within the scope of one embodiment of this disclosure. For example, in some embodiments, the memory controller 210 does not adjust the refresh cycle rate when the operating temperature drops significantly. In some embodiments, method 300 further includes detailed operations. Referring now to Figure 6. Figure 6 is a flowchart illustrating detailed operations of method 300 corresponding to Figure 3 according to some embodiments of this disclosure. For illustrative purposes, compared to Figure 5, method 300 further includes operation 346 preceding operation 343 described below with reference to Figures 2 and 4. Similar elements and operations in Figure 6 are labeled with the same element symbols for ease of understanding, relative to the embodiments of Figures 3 through 5. For illustrative purposes, as shown in Figure 6, after determining that the operating temperature has changed, operation 346 is executed. In operation 346, the memory controller 210 further determines whether the original temperature T1 and the changed temperature T2 are within the same temperature interval. When temperatures T1-T2 are within the same temperature interval, operation 342 is executed. When temperatures T1-T2 are within different temperature intervals, operation 343 is executed. For example, in some embodiments, the lookup table III stored in storage unit 220 is shown below. Table III. Lookup Table for Memory Array 230a on Memory Device (Die) 230. For illustrative purposes, Lookup Table III includes multiple refresh temperature intervals and corresponding refresh times. For operating temperatures in refresh temperature intervals of 1-25°C, the corresponding refresh time is determined to be approximately 1.4 years. For operating temperatures in refresh temperature intervals of 26-50°C, the corresponding refresh time is determined to be approximately 2.6 days. For operating temperatures in refresh temperature intervals of 51-85°C, the corresponding refresh time is determined to be approximately 100 seconds. For operating temperatures in refresh temperature intervals of 86-105°C, the corresponding refresh time is determined to be approximately 1 second. As discussed above, in some embodiments, when temperature T1 is about 38°C and temperature T2 is about 45°C, the memory controller 210 determines that temperatures T1 and T2 are within the same temperature interval. Therefore, operation 342 is performed, and the memory controller 210 maintains the data stored in the refresh memory array 230a at a refresh cycle rate corresponding to about 38°C (e.g., about 2.5 days). In various embodiments, in some embodiments, when temperature T1 is approximately 58°C and temperature T2 is approximately 45°C, the memory controller 210 determines that temperatures T1 and T2 are not within the same temperature interval. Therefore, operation 343 is performed. The memory controller 210 obtains another refresh time corresponding to 45°C and accordingly sets a refresh time cycle of approximately 2.5 days. Furthermore, lookup table III is generated by comparing lookup table III with lookup table I, and determining the refresh time of the highest temperature in the temperature interval as the refresh time of the temperature interval. For example, the refresh time of temperature 50°C in lookup table I is the refresh time of the temperature interval from 26 to 50°C in lookup table III. Therefore, in some embodiments, memory controller 210 is used to monitor the highest operating temperature among the sensed operating temperatures and to set a refresh cycle rate corresponding to the highest operating temperature. For illustrative purposes, the configuration in Figure 6 is shown. Various implementations are within the scope of one embodiment of this disclosure. For example, in some embodiments, the temperature interval range differs from the range of lookup table III. Referring now to Figure 7. Figure 7 is a schematic diagram of a computer system 700 according to various embodiments of the present disclosure. The computer system 700 includes a processor 710 and a memory system 720 coupled to the processor 710. In some embodiments, the memory system 720 is configured relative to, for example, the memory system 200 of Figure 2. The processor 710 is capable of accessing data stored in the memory cells of the memory system 720. In some embodiments, the processor 710 is a processing unit, a central processing unit, a digital signal processor, or other processor suitable for accessing data in the memory system 720. In some embodiments, the processor 710 transmits instructions for performing, for example, the methods 300 of Figures 3 and 5 to 6 via the memory controller 210. In some embodiments, the processor 710 and memory system 720 are formed in a system that can be physically and electrically coupled to a printed circuit board (PCB) to form an electronic assembly. The electronic assembly may be part of an electronic system such as a computer, wireless communication device, computer-related peripherals, entertainment device, etc. In some embodiments, a computer system 700 including a memory system 720 provides a complete system in an integrated circuit (IC) device (referred to as a system on a chip (SOC) or system on integrated circuit (SOIC) device). Such an SOC device can provide, for example, all the circuitry needed for a mobile phone, personal data assistant (PDA), digital camcorder, digital video camera, MP3 player, etc., to be implemented in a single integrated circuit. As discussed above, a memory system in one embodiment of this disclosure utilizes refresh time data stored in a lookup table of the memory device to determine the refresh cycle time for performing a refresh operation on the memory array on the memory device. Therefore, optimized error retention reduces the error rate of the memory array, refresh energy used for performing the refresh operation is conserved, and the refresh management burden is minimized. In some embodiments, a memory system is disclosed. The memory system includes a memory array and a controller. The controller is configured to perform a refresh operation on the memory array at a first refresh cycle rate. The first refresh cycle rate is derived from a first refresh time in a lookup table. The lookup table is configured to store the refresh time and the refresh temperature corresponding to the refresh time, respectively. In some embodiments, the memory system further includes sensing circuitry for sensing the operating temperature associated with the memory array. The sensed operating temperature is configured as one of the refresh temperatures. In some embodiments, the memory system further includes sensing circuitry for sensing an operating temperature associated with the memory array. When the first operating temperature changes to a second operating temperature, the controller further acquires a second refresh time corresponding to the second operating temperature and performs a refresh operation on the memory array at a second refresh cycle rate. In some embodiments, the controller includes a timer circuit for counting refresh time cycles. The controller is further configured to reset the timer circuit to count refresh time cycles after the controller acquires a second refresh time. In some embodiments, the memory system further includes a storage unit for storing lookup tables that include a refresh time and a refresh temperature interval corresponding to the refresh time. The controller is further configured to set a second refresh cycle rate by determining whether a first operating temperature and a second operating temperature associated with the memory array are within different intervals of the refresh temperature interval. In some embodiments, the controller is further configured to select the highest operating temperature among the operating temperatures associated with the memory array, and to set a second recycle rate corresponding to the highest operating temperature. A method is also disclosed. The method includes the following operations: counting refresh time cycles for a plurality of memory arrays on a plurality of dies; recording the counted refresh time cycles to generate a temperature-dependent inter-die difference table; looking up the refresh time in the inter-die difference table based on the operating temperature associated with the memory array; setting a refresh cycle rate for performing a refresh operation on the memory arrays on the plurality of dies; and performing the refresh operation on the memory arrays on the plurality of dies by a controller. In some embodiments, the method further includes: sensing an operating temperature associated with the memory array; and configuring the sensed operating temperature as a temperature in a grain-to-grain difference table. In some embodiments, the method further includes: determining whether the operating temperature has changed; and in response to the determination, obtaining other refresh times corresponding to the changed operating temperature. In some embodiments, the method further includes: when one of the operating temperatures changes, determining whether a changed operating temperature and a corresponding original operating temperature are within the same temperature interval; when a changed operating temperature and a corresponding original operating temperature are within different temperature intervals and a changed operating temperature is lower than the original operating temperature, maintaining a count of refresh time periods until a refresh operation is performed; and obtaining another refresh time corresponding to the changed operating temperature. In some embodiments, the method further includes: setting another renewal cycle rate corresponding to another renewal time for performing a renewal operation on memory arrays on corresponding dies of a plurality of dies; and resetting a timer to count the renewal time cycles of memory arrays on corresponding dies of a plurality of dies. In some embodiments, the method further includes increasing the duration of the regeneration cycle rate when the operating temperature decreases. In some embodiments, the method further includes: calculating the recycle rate based on a grain-to-grain difference table. It also discloses a method including the following operations: sensing a first operating temperature associated with a memory array on a die; obtaining a first refresh time corresponding to the memory array from a lookup table based on the first operating temperature; and refreshing the data stored in the memory array at a first refresh cycle rate corresponding to the first refresh time. In some embodiments, the method further includes generating a lookup table by counting the refresh time cycles of memory arrays operating at different temperatures. In some embodiments, the method further includes: sensing a second operating temperature different from a first operating temperature; obtaining a second refresh time from a lookup table based on the second operating temperature; and refreshing the data stored in the memory array at a second refresh cycle rate corresponding to the second refresh time. In some embodiments, the method further includes: in response to sensing a second operating temperature higher than a first operating temperature associated with the memory array, renewing data in the memory array at a second renewal cycle rate faster than a first renewal cycle rate. In some embodiments, the method further includes: sensing a second operating temperature different from a first operating temperature; determining whether the first operating temperature and the second operating temperature are within the same temperature interval; and in response to the determination, maintaining data in the memory array that is refreshed at a first refresh cycle rate. In some embodiments, the method further includes: resetting a timer for counting new time cycles of the memory array when the first operating temperature and the second operating temperature are in different temperature intervals and the second operating temperature is higher than the first operating temperature. In some embodiments, the duration of the first renew cycle rate is shorter than the duration of the first renew time. The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use one embodiment of this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this disclosure, but rather various changes, substitutions, and modifications can be made without departing from the spirit and scope of one embodiment of this disclosure. 100: Semiconductor wafer; 110: Integrated circuit die / IC die; 111: Memory device; C1: Curve; C2: Curve / Regression line; 200: Memory system; 210: Memory controller; 212: Processing unit; 214: Timer (scheduler); 216: Refresh controller; 220: Storage unit; 230: Memory device; 230a: Memory array; CM1: Control signal; CM2: Control signal; D1: Data signal; D2: Data signal; TS: Temperature sensor (sensing circuit); 300: Method; 310: Operation; 320: Operation; 330: Operation; 340: Operation; 341: Operation; 342: Operation; 343: Operation; 344: Operation; 345: Operation; 346: Operation; 350: Operation; 360: Operation; 370: Operation; 700: Computer system; 710: Processor; 720: Memory system. When read in conjunction with the accompanying drawings, the various aspects of this disclosure are best understood in the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1A is a schematic diagram of a wafer including multiple integrated circuits (wafers / dies) according to various embodiments of this disclosure. Figure 1B is a schematic graph showing the inter-die distribution relative to its normalized refresh time according to various embodiments of this disclosure. Figure 2 is a schematic diagram of a memory system according to other embodiments of this disclosure. Figure 3 is a flowchart of a method according to some embodiments of this disclosure. Figure 4 is a schematic graph showing the refresh / operating temperature of a memory array relative to its refresh time according to various embodiments of this disclosure. Figure 5 is a flowchart showing detailed operation of the method corresponding to Figure 3 according to some embodiments of this disclosure. Figure 6 is a flowchart showing detailed operation of the method corresponding to Figure 3 according to some embodiments of this disclosure. Figure 7 is a schematic diagram of a computer system according to various embodiments of this disclosure. 200: Memory System 210: Memory controller 212: Processing Unit 214: Timer (Scheduler) 216: New Controller 220: Storage unit 230: Memory device 230a: Memory Array CM1: Control signal CM2: Control signal D1: Data Signal D2: Data Signal TS: Temperature sensor

Claims

1. A memory system, comprising: One memory array; A storage unit for storing a plurality of refresh times and a plurality of refresh temperatures in a lookup table; The controller is configured to compare a temperature of the memory array with the refresh temperatures, obtain a corresponding refresh time from the refresh times in the lookup table, set a first refresh cycle rate less than the refresh time based on the corresponding refresh time, and then perform a refresh operation on the memory array at the first refresh cycle rate, the first refresh cycle rate corresponding to the time period for refreshing the memory array; wherein each of the refresh times corresponds to the time period under a corresponding refresh temperature at which data stored in the memory array will be lost, wherein the controller is further configured to monitor a highest operating temperature among a plurality of operating temperatures associated with the memory array, and to set a second refresh cycle rate corresponding to the highest operating temperature for refreshing the memory array, wherein the second refresh cycle rate increases as the highest operating temperature decreases.

2. The memory system as described in claim 1, further comprising: A sensing circuit for sensing one of the operating temperatures, wherein the sensed operating temperature is used as one of the refresh temperatures.

3. The memory system as described in claim 1, further comprising: A sensing circuit for sensing the operating temperatures; When a first operating temperature among the operating temperatures changes to a second operating temperature among the operating temperatures, the controller further acquires a third refresh time corresponding to the second operating temperature to refresh the memory array, and performs the refresh operation on the memory array at a third refresh cycle rate.

4. The memory system as described in claim 3, wherein the controller comprises: A timer circuit for counting a refresh time period, wherein the controller is further configured to reset the timer circuit for counting another refresh time period after the controller acquires the third refresh time.

5. A method of operating a memory system, comprising the steps of: counting a plurality of refresh time cycles for a plurality of memory arrays on a plurality of dies; recording the counted refresh time cycles to generate a plurality of inter-die difference tables dependent on a plurality of temperatures; comparing a plurality of operating temperatures associated with the memory arrays with the temperatures in the inter-die difference tables to obtain a plurality of refresh times stored in the inter-die difference tables; setting a corresponding of a plurality of refresh cycle rates for performing a refresh operation on the memory arrays on the dies based on each of the stored refresh times, wherein one of the refresh cycle rates is less than the corresponding of the refresh times; and a controller performing the refresh operation on the memory arrays on the dies based on the refresh cycle rates; wherein the operating temperatures are negatively correlated with the refresh cycle rates.

6. The method as described in claim 5 further includes the steps of: sensing the operating temperatures associated with the memory arrays; and configuring the sensed operating temperatures as the temperatures in the inter-die difference table.

7. The method as described in claim 5 further includes the steps of: determining whether the operating temperatures have changed; and in response to the determination, obtaining other refresh times corresponding to the changed operating temperatures.

8. The method as described in claim 5, further comprising the following steps: when one of the operating temperatures changes, determining whether the changed operating temperature is within the same temperature interval as a corresponding original operating temperature; when the changed operating temperature is within a different temperature interval from the corresponding original operating temperature and the changed operating temperature is lower than the original operating temperature, maintaining the count of the refresh time period until the refresh operation is performed; obtaining another refresh time corresponding to the changed operating temperature; setting another refresh cycle rate corresponding to the other refresh time for performing the refresh operation on the memory arrays on a corresponding die of the dies; and resetting a timer to count the refresh time periods of the memory arrays on the corresponding die of the dies.

9. A method of operating a memory system, comprising the steps of: sensing a first operating temperature associated with a plurality of memory arrays on a die; obtaining, based on the first operating temperature, a first refresh time stored in a lookup table corresponding to the memory arrays, wherein the first refresh time corresponds to a time period during which stored data in the memory arrays will be lost at the first operating temperature; obtaining, based on the lookup table, a first refresh cycle rate stored in the lookup table corresponding to the first refresh time, and refreshing the stored data in the memory arrays at the first refresh cycle rate, wherein the first refresh cycle rate corresponds to a time period for refreshing the memory arrays; and when the first operating temperature decreases, obtaining, based on the lookup table, a second refresh cycle rate stored in the lookup table, and refreshing the stored data in the memory arrays at the second refresh cycle rate, wherein a period of the first refresh cycle rate is shorter than a period of the first refresh time.

10. The method as described in claim 9 further includes the step of: generating the lookup table by counting a plurality of refresh time cycles of the memory arrays operating at different temperatures.

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