Method for fabricating 3D NAND using a nickel or cobalt alloy

Abstract

This invention relates to a process for metallizing semiconductor substrates, particularly intended for the manufacture of 3D NAND memory. This metallization process includes activating the surface of a dielectric material with a noble metal such as palladium, followed by depositing a nickel or cobalt alloy using an electrodeless process with a solution containing metal ions.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to three-dimensional devices such as three-dimensional vertical NAND memory. Prior Technology

[0002] A 3D NAND memory device consists of a semiconductor substrate and insulating material layers. Alternating stacks of conductive material layers (called "word lines") are disposed on the semiconductor substrate. These conductive material layers are essentially metallic, while the insulating material layers are made of inorganic dielectrics. On the side of the device, the stack can be etched in a "step" pattern, wherein the length and number of the layers decrease from one level to the next in the upward direction.

[0003] In the region with the largest number of layers, the conductor / insulator stack is perforated by polycrystalline silicon semiconductor channels across its entire height. Pads consisting of tunneling dielectric (typically SiO2), charge storage materials (such as silicon nitride), and inorganic oxide barrier dielectrics are inserted between each semiconductor channel and the conductor / insulator stack to create a three-dimensional array of memory cells, each located at the intersection of a channel and a word line.

[0004] NAND flash memory manufacturers are hoping to increase the storage capacity of NAND flash memory by increasing the number of word lines and thus the number of memory cells. However, this presents a significant challenge as the stacking height increases. In fact, as the number of layers increases, the thickness necessarily decreases.

[0005] In current manufacturing processes, word lines are created by simultaneously filling several long, thin horizontal cavities separated by an insulating layer, with tungsten being the most commonly used conductive material. Tungsten is typically deposited in two steps: atomic layer deposition (ALD) to create a thin adhesion layer, followed by chemical vapor deposition (PECVD) to completely fill the cavities. However, the deeper the stack, the more difficult it becomes to completely fill the cavities. This problem is amplified when the word lines to be manufactured become thinner and the cavity openings are smaller. As a result, material voids form within the tungsten deposit, leading to a loss of conductivity and memory failure. This filling technique has demonstrated its limitations, especially for stacks containing 96 or 128 word lines.

[0006] Furthermore, prior art vapor deposition processes often deform silicon wafers, causing them to bend after annealing at the end of the process. To avoid this deformation, it has been proposed to deposit a layer on the back side of the wafer (the front side is covered by a stack) by performing a plasma-enhanced chemical vapor deposition (PECVD) process followed by EOS GS® etching. However, this method has the disadvantage of adding at least two steps to the memory device manufacturing process, and requires control of the back side processing without damaging the front side in the following steps.

[0007] Therefore, there is a need to provide improved 3D NAND memory, and in particular, to manufacture 3D NAND memory in which word lines have higher conductivity than prior art word lines with the same number of levels. The increased conductivity is achieved by adjusting at least one of the following two parameters: reducing the material voids in the lines and / or optimizing the conductor volume available to produce the lines.

[0008] In prior art, especially when word lines are based on tungsten, it is necessary to insert a thin layer of so-called "barrier" material between the metal line and the barrier dielectric (usually SiO2 associated with alumina Al2O3, depending on the case) to prevent elements contained in the metal from migrating toward the dielectric. The barrier material layer reduces the space available for the metal, and the height of the space to be filled is imposed. An example of prior art material combinations inserted between polysilicon channels and tungsten lines is: polySi / SiO / SiN / SiO2 / Al2O3 / TiN / W. The product of the number of consecutive layers deposited to produce the word lines significantly limits the volume of the tungsten conductor. Furthermore, the deposition of additional material adds a step to the fabrication of memory devices.

[0009] Therefore, there is still a need for a method for manufacturing semiconductor devices such as 3D NAND memory that includes fewer steps, particularly fewer steps for depositing material between semiconductor channels and conductive metal.

[0010] In 3D NAND memory devices, contacts also exist between the polysilicon channels and the copper bit lines. As with the word lines mentioned above, the contacts are typically made of tungsten, and it is necessary to insert a thin layer of so-called "barrier material" between the contacts and the polysilicon. It is also necessary to insert barrier material between the copper bit lines and the tungsten contacts. The problems associated with manufacturing word lines therefore also apply to the production of contacts and bit lines. Therefore, it is still necessary to manufacture 3D NAND memory where the conductivity between word lines and bit lines is improved by limiting or eliminating the use of barrier materials such as titanium nitride and tantalum nitride. Summary of the Invention

[0011] The present invention responds to these various requirements by replacing metals such as tungsten used in the prior art to manufacture 3D NAND devices with nickel or cobalt alloys containing elements selected from boron, phosphorus, tungsten or mixtures thereof.

[0012] This invention also responds to these various needs by providing a process for manufacturing 3D NAND memory, wherein a wet process is used in the steps of establishing word lines, depositing conductive metal in the bit lines or contacts between semiconductor channels and bit lines, which is obtained only by the dry process in the prior art. Specifically, the conductive metal deposition step is performed in two steps: in the first step, an inorganic oxide is activated on a noble metal surface; then in the second step, the metal is deposited on the activated inorganic oxide surface by contacting the surface with an electrodeless solution containing metal ions and a reducing agent of metal ions without polarization.

[0013] This process involves depositing nickel and boron alloys using an electrodeless process (without electrodeposition of the substrate). The process of this invention is characterized by producing metal deposits via a wet process using an aqueous electrolyte, rather than a dry process as in prior art. This process makes it possible to create large-scale line-filled structures. The specific filling kinetics observed in this process allow for metal growth rates suitable for these new dimensions. This result is particularly due to the properties of the chemical composition of the electrolyte.

[0014] The process of this invention makes it possible to deposit a metal layer directly above an inorganic dielectric material. The process also makes it possible to avoid depositing a barrier layer, typically titanium nitride or tantalum nitride, with titanium nitride being more common. The absence of a barrier material offers two advantages: eliminating a step in the process without reducing the conductivity of the metal wire. The inventors have discovered that nickel-boron alloys do not diffuse into the dielectric. Nickel-boron alloys used as conductors, rather than tungsten, not only possess barrier properties but also exhibit higher conductivity than tungsten. [Detailed Description] []

[0015] Therefore, the present invention provides a method for manufacturing 3D NAND memory, comprising at least one process of selectively metallizing an inorganic oxide surface in a solvent phase, the metallization being performed by depositing an alloy of nickel or cobalt having elements selected from boron, phosphorus, and tungsten, the metallization process comprising - The step of activating the surface of the inorganic oxide using precious metals, followed by the activation step... - The step of contacting the surface with an electrodeless solution without polarization to form a nickel or cobalt alloy deposit, the electrodeless solution comprising nickel or cobalt metal ions, at least one reducing agent comprising a metal ion selected from at least one member of boron, phosphorus and tungsten, and a polyamine.

[0016] "Alloy" refers to a solid solution in which elements are uniformly dispersed in nickel or cobalt.

[0017] The alloy deposition step can be advantageously performed by subjecting the inorganic oxide surface to ultrasound. Elements selected from boron, phosphorus, and tungsten are preferably represented as between 1 atomic% and 10 atomic% in the alloy. The metal deposit is preferably composed of a nickel alloy having at least one element selected from boron, phosphorus, and tungsten, wherein the element may be between 1 atomic% and 10 atomic%. According to one embodiment of the invention, the metal is composed of a nickel-boron alloy containing 6 atomic% boron.

[0018] The inorganic oxide that the electrodeless solution comes into contact with can be SiO2 or Al2O3.

[0019] Nickel or cobalt alloy deposits can be formed at various stages of the 3D NAND memory manufacturing process. For example, alloys are deposited to form word lines, contacts between polysilicon channels and bit lines, or barrier layers for bit lines.

[0020] The precious metal may be ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). In a specific embodiment, palladium is used as the precious metal for activating the inorganic oxide surface.

[0021] Another object of the present invention is a 3D NAND device comprising a nickel or cobalt alloy having at least one element selected from boron, phosphorus and tungsten, which can be manufactured by any of the methods described above.

[0022] This application also describes a process for metallizing a semiconductor substrate, the substrate including at least one horizontal cavity leading to a vertical cavity, the horizontal cavity having an opening size smaller than that of the vertical cavity, the cavities defining a surface comprising at least one region of an inorganic oxide, the metallization process including a step of selectively activating the inorganic oxide surface, followed by a step of depositing metal on the activated inorganic oxide surface by contacting the surface with an electrodeless solution without polarization, the electrodeless solution comprising metal ions, a reducing agent of the plasma, an inhibitor suitable for the horizontal cavity, and an inhibitor suitable for the vertical cavity.

[0023] The present invention also provides an electrolyte for filling a cavity with an opening size of less than 1 micrometer or even 100 nm.

[0024] This invention also provides an electrolyte for manufacturing 3D NAND memory. This electrolyte makes it possible to produce metal deposits on substrates with very different surface morphologies in terms of both size and protrusion. Therefore, it is not necessary to use different metallization techniques depending on the starting substrate to be covered: this simplifies the manufacturing process of memory devices. Specifically, the electrolyte allows a complex substrate containing several cavities of different sizes (especially different widths (or dimensions) at the openings) to simultaneously fill all cavities, wherein a single solution contains metal ions and a reducing agent for the metal ions to deposit metal into the cavities. This process makes it possible to obtain metal deposits without material defects on surfaces with highly irregular surface morphologies and protrusions.

[0025] This invention produces a dielectric / metallic multilayer structure with excellent interlayer adhesion.

[0026] The electrolyte and metallization process of this invention also make it possible to form metal deposits of uniform quality on complex geometries. The conductivity of the network of conductive lines in the device is improved by eliminating the barrier layer between the conductive metal and the dielectric, which was necessary in the prior art to ensure proper operation of the device. Simple Explanation of the Diagram

[0027] Figure 1 shows a schematic portion of a 3D NAND memory according to prior art.

[0028] Figure 2A shows a substrate used to implement a metallization process of the prior art or a metallization process according to the present invention to form word lines.

[0029] Figure 2B shows the steps of etching the substrate of Figure 2A.

[0030] Figure 2C shows a substrate covered with a nickel or cobalt alloy obtained by performing the metallization process according to the present invention.

[0031] Figure 2D shows a nickel or cobalt alloy word line of a 3D NAND device obtained by implementing the metallization process according to the present invention.

[0032] Figure 3 shows a cross-section of a prior art 3D NAND device along axis B-B' of Figure 1.

[0033] Figure 4A shows a substrate to be metallized with a nickel or cobalt alloy using the process of the present invention.

[0034] Figure 4B shows the substrate of Figure 4A, which has been metallized according to the process of the present invention to obtain a nickel or cobalt alloy deposit that fills the cavity to form word lines.

[0035] Figure 5 shows the substrate of Figure 4A, which has been metallized according to the process of the present invention to obtain a nickel or cobalt alloy deposit covering the cavity wall without filling the cavity wall.

[0036] Figure 6 shows a substrate used to manufacture peripheral contacts according to the process of the present invention or according to prior art processes.

[0037] Figure 7 shows the substrate of Figure 6, which has been etched upstream of the metallization.

[0038] Figure 8 shows the substrate of Figure 7, which is metallized by a nickel or cobalt alloy according to the present invention.

[0039] Figure 9 shows the substrate of Figure 7, which is metallized with barrier material and tungsten according to prior art processes.

[0040] Figure 10 shows a substrate used to manufacture contacts between semiconductor channels and bit lines using the process of the present invention or a prior art process.

[0041] Figure 11 shows the substrate of Figure 10, which has been etched to define cavities to be filled with metal according to the process of the present invention or prior art.

[0042] Figure 12 shows the substrate of Figure 11, which is metallized by a nickel or cobalt alloy according to the present invention.

[0043] Figure 13 shows the substrate of Figure 11, which is metallized with barrier material and tungsten according to prior art processes.

[0044] Figure 14 shows a detailed schematic diagram of a 3D NAND device containing bit lines based on a nickel or cobalt alloy obtained according to the process of the present invention.

[0045] Figure 15 shows a detailed schematic diagram of a 3D NAND device containing copper-based bit lines according to prior art.

[0046] Figure 16 shows that, compared with prior art metallized silicon substrates, the metallized silicon substrate obtained according to the process of the present invention does not have bending.

[0047] Figure 17 shows the EELS curve of the nickel-boron alloy obtained by the process according to the present invention. Implementation

[0048] The first objective of this invention is a method for manufacturing 3D NAND memory, comprising a process of selectively metallizing an inorganic oxide surface in a solvent phase by an alloy of nickel or cobalt having elements selected from boron, phosphorus, and tungsten or mixtures thereof, wherein the metallization process includes... - The step of activating the surface of the inorganic oxide using precious metals, followed by the activation step... - The step of contacting the surface with an electrodeless solution containing nickel or cobalt metal ions without polarization, wherein at least one reducing agent of the metal ions comprises an element selected from boron, phosphorus and tungsten and a polyamine to form a nickel or cobalt alloy deposit.

[0049] The manufacturing method of this invention can be part of a more comprehensive integration scheme for 3D NAND memory, wherein conductive and dielectric materials are assembled and deposited according to a specific geometry, making it possible to produce functional elements, including word lines, contacts between polysilicon channels and bit lines, peripheral contacts between word lines and source lines, and bit lines. Therefore, in the manufacturing method of this invention, nickel or cobalt alloys can be used in the composition of various functional elements and deposited at various stages of the 3D NAND memory integration scheme.

[0050] In a first embodiment of the first objective of the present invention, a nickel or cobalt alloy deposit is included in the word line composition of a 3D NAND memory.

[0051] In this context, alloy deposition can thus be achieved via a solvent-phase metallization process on a semiconductor substrate intended for the manufacture of 3D NAND memory. This substrate defines a horizontal plane and has at least two series of horizontal cavities leading to vertical cavities. These cavities define a surface containing at least one region of inorganic oxide. The metallization process includes… - The step of activating the inorganic oxide region by contacting the surface with an activation solution containing at least one palladium complex, at least one organosilicon compound, and at least one solvent, followed by... - A step of depositing metal on an activated region of an inorganic oxide by contacting the surface of the cavities with an electrodeless solution containing metal ions and at least one reducing agent containing metal ions without polarization. The electrodeless solution may further contain at least one first inhibitor suitable for horizontal cavities and at least one second inhibitor suitable for vertical cavities.

[0052] The first inhibitor may be an aliphatic polyamine with a number average molecular weight of less than 500 g / mol, such as diallyltriamine. The second inhibitor may be polyethyleneimine with a number average molecular weight greater than or equal to 500 g / mol. The reducing agent may be hypophosphorous acid, and the electrodeless solution may contain at least two reducing agents, with hypophosphorous acid as the first reducing agent and dimethylamineborane as the second reducing agent.

[0053] According to one embodiment, the concentration of the metal ion is between 10⁻³ M and 1 M, and the concentration of the first inhibitor is in the range of 5 mg / L to 100 mg / L. The horizontal cavity, for example, has an average diameter ranging from 10 nm to 50 nm and a depth ranging from 30 nm to 80 nm at the opening. Furthermore, the inorganic oxide is composed of SiO2 and / or Al2O3.

[0054] This invention also provides a process for manufacturing 3D NAND memory, comprising... - A step in fabricating a semiconductor substrate, the semiconductor substrate defining a horizontal plane and comprising at least one surface of an inorganic oxide, the inorganic oxide comprising at least two series of horizontal cavities leading to vertical cavities. - The step of activating the surface of the inorganic oxide using an activation solution containing at least one palladium complex, an organosilicon compound, and a solvent. - The step of depositing metal on an activated inorganic oxide surface by contacting the surface without polarization with an electrodeless solution containing metal ions, at least one reducing agent containing metal ions, at least one first aliphatic polyamine with a molecular weight in the range of 500 g / mol to 25000 g / mol, and at least one second aliphatic polyamine with a molecular weight lower than the first polyamine.

[0055] Finally, the present invention provides a solvent phase and electrodeless metallization process for a semiconductor substrate comprising cavities, wherein the cavities have an average width of less than 1 micrometer at their openings, and the cavities define a surface comprising at least one region of insulating material, the metallization process comprising... - The step of activating the surface of the insulating material by contacting the surface with an activation solution containing at least one palladium complex, at least one bifunctional adhesive and at least one solvent, followed by... - A step of depositing the metal onto an activated surface by contacting the metal with a solution containing metal ions (such as Ni(II) or Co(II) ions), hypophosphorous acid, and dipropylenetriamine without polarization.

[0056] The molar concentration ratio between the metal ions and diallyltriamine is preferably greater than 10:1.

[0057] In this process, the width of the cavity opening is preferably less than 500 nm, for example less than the value selected from the group consisting of 400 nm, 300 nm, 200 nm, 100 nm and 50 nm.

[0058] In all specific forms and embodiments of the present invention, the process of the present invention includes the step of activating the surface of an inorganic dielectric material, followed by depositing metal on the surface.

[0059] The dielectric material can be an inorganic oxide, preferably selected from silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide, zirconium oxide and their silicates.

[0060] According to a specific embodiment of the present invention, the substrate includes cavities, the usable surface area of ​​which includes insulating regions, all of which are composed of silicon oxide and / or aluminum oxide. All insulating regions have a silicon oxide surface or an aluminum oxide surface. Alternatively, some of the insulating regions have a silicon oxide surface, while other portions of the insulating regions have an aluminum oxide surface.

[0061] The surface of dielectric materials (especially inorganic oxides) can be activated in the solvent phase in a step prior to the metal coating deposited in the solvent phase by an electrodeless method.

[0062] Surface activation can be achieved, for example, by grafting noble metals such as palladium according to the teachings of FR 2 950 063-A1 or FR 2 950 634-A1. The principle of grafting is to make palladium in solution, in the presence of a bifunctional ligand, a complex. The properties of the ligand used depend on the properties of the dielectric material to be activated.

[0063] Surface activation of the insulating layer can also be performed by depositing metal nanoparticles such as nickel-boron nanoparticles as described in WO 2010 / 001054.

[0064] According to one embodiment, when the dielectric is an inorganic oxide, especially SiO2 or Al2O3, surface activation is performed by means of an activation solution containing a solvent, a palladium complex used as an activator, and a bifunctional adhesive (such as an organosilicon compound) that satisfies the function of a tackifier.

[0065] Therefore, the activator can be composed of one or more palladium complexes, such as (NH4)2 (PdCl4); Pd(NH3)4 or complexes of formula (I). in: - R1 and R2 are the same and represent H; CH2 CH2 NH2; CH2 CH2 OH; or R1 represents H and R2 represents CH2 CH2 NH2; or R1 represents CH2 CH2 NHCH2 CH2 NH2; or R1 represents H and R2 represents CH2 CH2 NHCH2 CH2 NHCH2 CH2 NH2 - The X series is selected from the following groups of ligands: Cl-; Br-; I-; H2O, NO3-; CH3SO3-; CF3SO3-; CH3-Ph-SO3-; CH3COO-;

[0066] According to a specific feature of the invention, the solution contains the aforementioned activator at a concentration of 10⁻⁶ M to 10⁻² M, preferably 10⁻⁵ M to 10⁻³ M, and more preferably 5.10⁻⁵ M to 5.10⁻⁴ M.

[0067] A tackifier composed of one or more organosilicon compounds in an activated solution ensures adhesion between the metal top layer and the inorganic oxide.

[0068] According to a specific feature of the present invention, the organosilicon compound has the general formula (Va): {X-(L)}3-n Si(OR)n (Va) - Where X represents a functional group selected from the group consisting of thiols, pyridyl, epoxy (oxocyclopropane), glycidyl, and primary amines, and capable of reacting with a single palladium compound or a compound of formula (I); - L indicates a spacer arm selected from the following groups: CH2; CH2 CH2; CH2 CH2 CH2-; CH2 CH2 CH2 CH2-; CH2 CH2 NHCH2 CH2; CH2 CH2 CH2 NHCH2 CH2; CH2 CH2 CH2 NHCH2 CH2 NHCH2 CH2; CH2 CH2 CH2 NHCH2 CH2 CH2 CH2 CH2; Ph; Ph-CH2; and CH2 CH2-Ph-CH2; (Ph represents a phenyl ring) - R represents a group selected from the following groups: CH3, CH3CH2, CH3CH2CH2, (CH3)2CH; and - n is an integer equal to 2 or 3.

[0069] Organosilicon compounds can also have the formula (Vb). (OR)3 Si-(L)-Si(OR)3 (Vb) - Where L represents a spacer arm selected from the following groups: CH2 CH2 CH2 NHCH2 CH2 NHCH2 CH2 CH2 and CH2 CH2 CH2 -SS-CH2 CH2 CH2 - R indicates a group selected from the following groups: CH3, CH3CH2, CH3CH2CH2, (CH3)2CH.

[0070] Compounds of formula (Va) or (Vb) are selected, for example, from the following compounds: (3-aminopropyl)triethoxysilane; (3-aminopropyl)trimethoxysilane; m-aminophenyltrimethoxysilane; p-aminophenyltrimethoxysilane; p,m-aminophenyltrimethoxysilane; 4-aminobutyltriethoxysilane; m,p (aminoethylaminomethyl)phenethyltrimethoxysilane; N-(2-aminoethyl)-3-aminopropyltriethoxysilane; N-(2-aminoethyl)-3-aminopropyltrimethoxysilane; 2-(4-pyridylethyl)triethoxysilane; bis(3-trimethoxysilylpropyl)ethylenediamine; (3-trimethoxysilylpropyl)diethylenetriamine; N-(3-trimethoxysilylethylenediamine; N-(6-aminohexyl)aminopropyltrimethoxy 5,6-Epoxyhexyltriethoxysilane; (3-mercaptopropyl)trimethoxysilane; (3-mercaptopropyl)triethoxysilane; bis[3-(triethoxysilyl)propyl]dithio; 3-chloropropyltrimethoxysilane; 3-chloropropyltriethoxysilane; (p-chloromethyl)phenyltrimethoxysilane; m,p((chloromethyl)phenethyl)trimethoxysilane.

[0071] As preferred organosilicon compounds that can be used in the context of this invention, compounds of formula (Va) are particularly mentioned, wherein: X represents an NH2 group and L represents CH2 CH2 CH2 - and R represents CH3 (a compound named (3-aminopropyl)-trimethoxy-silane or APTMS); or L represents CH2 CH2 CH2 - and R represents CH3 CH2 (a compound named (3-aminopropyl)-triethoxy-silane or APTES); or L represents CH2 CH2 NHCH2 CH2 and R represents CH3 (a compound named [3-(2-aminoethyl)aminopropyl]trimethoxy-silane or DATMS or DAMO). X represents SH; L represents CH2 CH2 CH2 - and R represents CH2 -CH3 (a compound named (3-mercaptopropyl)trimethoxysilane or MPTES); or X represents C6 H5 N; L represents CH2 CH2 - and R represents CH2 -CH3 (a compound named 2-(4-pyridylethyl)triethoxysilane or PETES); or X represents CHCH2 O; L represents CH2 CH2 CH2 and R represents CH3 (a compound named (3-glycidoxypropyl)trimethoxysilane or EPTMS); or X represents Cl; L represents CH2 CH2 CH2 and R represents CH3 (a compound named 3-chloropropyltrimethoxysilane or CPTMS).

[0072] In the context of this invention, a particularly preferred organosilane compound is (3-aminopropyl)-trimethoxysilane (APTMS).

[0073] Advantageously, the concentration of the organosilanes is between 10⁻⁵ M and 10⁻¹ M, more preferably between 10⁻⁴ M and 10⁻² M, and even more preferably between 5.10⁻⁴ M and 5.10⁻³ M.

[0074] Due to a particularly advantageous feature, the aforementioned activation solution contains a very small amount of water. Therefore, water can be present at a concentration of less than 1% by volume, preferably less than 0.5%, and even more preferably less than 0.2%.

[0075] The solvent of the solution must be capable of dissolving the activator and binder as defined above. This solvent system may consist of one or more solvents selected from the group consisting of: N-methylpyrrolidone (NMP), dimethyl sulfoxide (DMSO), alcohols, ethylene glycol ethers (such as monoethyl-diethylene glycol (EDEG)), propylene glycol ethers, dialkylene, and toluene. Generally, the solvent system advantageously consists of a mixture of a solvent capable of dissolving palladium compounds and a solvent such as ethylene glycol ether or propylene glycol ether. In the context of this invention, a particularly preferred solvent system is, especially due to its extremely low toxicity, a mixture of only dimethyl sulfoxide (DMSO) or dimethyl sulfoxide (DMSO) and diethylene glycol monoethyl ether (EDEG). These compounds can be used at a volume ratio between 1:200 and 1:5, preferably about 1:10.

[0076] According to a particular embodiment, aminopropyltrimethoxysilane can be used as a bifunctional organic adhesive to activate the surface of an insulating substrate containing silicon dioxide or aluminum oxide by means of palladium complexes (such as palladium-diethyl ether triamine complexes).

[0077] The process of this invention includes the step of metallizing an inorganic oxide substrate. This step is performed after activating the substrate using a bifunctional palladium / coordination complex system, or by depositing metal nanoparticles.

[0078] Preferably, a metal selected from precious metals and transition metals, and alloys thereof, will be used. Palladium is a specific example of this invention.

[0079] Metal ion systems, such as nickel(II) ions or cobalt(II) ions.

[0080] This metal can be alloyed with at least one other element selected from phosphorus and boron. One specific embodiment of the invention uses nickel alloyed with boron.

[0081] In the context of this invention, the coating of the surface activated in the preceding steps is performed, as appropriate, by bringing the surface into contact with a liquid, preferably an aqueous solution containing the following: - At least one metal salt, preferably with a concentration between 10⁻³ M and 1 M; - A mixture of reducing agents, preferably in an amount between 10⁻⁶ M and 1 M; - A reagent used to adjust and maintain the pH value between 6 and 11, preferably between 8 and 10; - A reagent that inhibits vertical cavities, preferably at a concentration between 0.5 ppm and 100 ppm, and - A reagent or mixture of reagents that has an inhibitory effect on horizontal cavities, preferably at a concentration between 0.5 ppm and 100 ppm.

[0082] The electrolyte contains, as appropriate, at least one stabilizer of metal ions, preferably in an amount between 10⁻³ M and 1 M.

[0083] The contact between the electrodeless solution and the surface is performed, for example, under conditions that result in the formation of a metal film with a thickness of at least 5 nanometers, such as under conditions that result in the formation of a metal film with a thickness of at least 30 nanometers, preferably between 30 nanometers and 100 nanometers, and more preferably between 30 nanometers and 200 nanometers. According to one embodiment, the film thickness is at least equal to the depth of the cavity, preferably between 30 nanometers and 100 nanometers. When the substrate includes a horizontal cavity leading to the vertical cavity, the metal film advantageously has a thickness at least equal to the depth of the horizontal cavity and less than half the diameter of the vertical cavity, such that the latter is not completely filled.

[0084] The metal salt of the aforementioned metal is preferably water-soluble and selected from the group consisting of: acetate, acetylacetonate, hexafluorophosphate, nitrate, perchlorate, sulfate, or tetrafluoroborate of the metal. In the context of this invention, the preferred metal salt is nickel sulfate hexahydrate.

[0085] Advantageously, the reducing agent can be selected from phosphorus derivatives and borane derivatives. The phosphorus derivative can be hypophosphite or its salt, while the borane derivative can be selected from dimethylaminoborane, pyridineborane, morpholineborane, or tributylamineborane.

[0086] In the context of this invention, a preferred mixture of reducing agents includes borane derivatives, particularly such as dimethylamine borane (DMAB); and phosphorus derivatives, particularly such as hypophosphoric acid.

[0087] The nature and amount of the stabilizer (if present) are selected to cause the metal ions in the solution to complex. Preferably, the electrodeless solution contains a complex of the metal ion and the ligand, also referred to as a stabilizer. The stabilizer for the metal ion can be selected from the group consisting of: ethylenediamine, citric acid, acetic acid, succinic acid, malonic acid, aminoacetic acid, malic acid, or alkali metal salts of such compounds. In the context of this invention, citric acid is a preferred stabilizer, and it forms a complex with the metal ion in solution.

[0088] Aqueous electrodeless solutions may include reagents to adjust the pH to a value between 6 and 11. When the solution contains amines that do not misculate with metal ions, it is preferable to choose a pH such that not all amine functional groups of these amines are protonated. When the solution contains polyamines that, where appropriate, act as inhibitors of horizontal cavities (e.g., poly(ethylenediamine)), the pH of the aqueous solution will preferably be in the range of 8 to 10. Specifically, it may be in the range of 9.0 to 9.5. The pH adjuster may be selected from aminoethanol, N-methylaminoethanol, and N,N-dimethylaminoethanol. N-methylaminoethanol is preferred as the pH adjuster.

[0089] According to one embodiment of the invention, the electrodeless solution contains a poly(ethylene imine) homopolymer or copolymer, which functions as an inhibitor capable of adsorbing onto nickel or cobalt alloys, and is particularly selectively suited to vertical cavities. "Selectively suited" means an inhibitor unsuitable for horizontal cavities. The inhibitory agent for vertical cavities can also be selected from polymers and copolymers derived from polyglucosamine, poly(allylamine), poly(vinylamine), poly(vinylpyridine), poly(aminostyrene), poly(L-lysine), and acidic (or protonated) forms of such polymers.

[0090] For example, linear poly(ethylene ethyleneimine) with a number average molecular weight Mn of 500 g / mol to 25000 g / mol is selected, which contains -(CH2-CH2-NH)- units or branched polyethyleneimine with a number average molecular weight Mn of 500 g / mol to 70000 g / mol, which contains primary amine, secondary amine and tertiary amine units.

[0091] Poly(ethylene imide) can be poly(ethylene imide) with CAS number 25987-06-8, having a number average molecular weight Mn, for example, between 500 and 700 g / mol, and sold by Sigma-Aldrich with product code 408719; or poly(ethylene imide) with CAS number 9002-98-6, having a number average molecular weight Mn, for example, between 500 and 700 g / mol, and sold by Polysciences with product code 02371.

[0092] A preferred reagent for inhibiting vertical cavities is a branched-chain poly(ethylene ethylimide) with a mass Mn of approximately 600 g / mol.

[0093] Aliphatic polyamines with a molecular weight less than 500 g / mol can be used in electrodeless solutions. They can function as inhibitors that adsorb onto nickel or cobalt alloys, and are particularly selectively suited to horizontal cavities, or to cavities with an average opening size less than 100 nm. "Selectively suited" means that they are not suitable for inhibitors of cavities with an average opening size greater than 100 nm.

[0094] The reagent or mixture of reagents that inhibits horizontal cavities may be selected from the aliphatic polyamines listed above. Examples include ethylenediamine, diethylenetriamine, triethylenetetramine, dipropylenetriamine, 1,3-diaminopropane, 2-(aminomethyl)-2-methyl-1,3-propanediamine, and N,N,N,N-tetramethyl-1,3-butanediamine. The following can also be used as inhibitors of horizontal cavities: 1,4,8,11-tetraazacyclotetradecane; aliphatic alcohols, such as ethylene glycol, diethylene glycol, triethylene glycol, tetraethylene glycol, propylene glycol, dipropylene glycol, tripropylene glycol, and tetrapropylene glycol; or amino acids (alanine; arginine; aspartic acid; aspartate or aspartic acid; cysteine; glutamate or glutamate; glutamate; glycine; histidine; isoleucine; leucine; lysine; methionine; phenylalanine; proline; pyrrolidine; serine; threonine; tryptophan; tyrosine; valine). A specific agent with inhibitory effects on horizontal cavities is diallyltriamine.

[0095] Generally, the substrate can be brought into contact with the electrodeless solution by immersing it in the solution at a temperature between 40°C and 90°C, preferably 70°C, for a period of 30 seconds to 20 minutes (depending on the required thickness of the layer).

[0096] According to an advantageous embodiment, this layer can be annealed in an inert or reducing atmosphere (4% hydrogen in nitrogen) at a temperature between 200°C and 400°C, preferably 250°C, for a period of 1 min to 30 min, preferably about 10 min.

[0097] The deposition of alloy metal layers can be performed under various conditions. For example, the substrate to be coated can be rotated. Recycling of the electrodeless solution can be forced within a reactor. The substrate can be brought into contact with the electrodeless solution by spraying a wetted solution under high pressure. Other methods can be used in complementary ways, such as by stirring the substrate and / or solution with an ultrasonic or ultrasonic gun. In any case, contact can be performed under vacuum.

[0098] The method for manufacturing 3D NAND memory according to the present invention may include, in addition to the selective metallization process, other steps necessary to provide a functional memory device. Alternatively, the method of the present invention may include steps other than those described above to provide only a portion of the memory device.

[0099] A first example of a 3D NAND memory obtained by the method of the present invention includes a semiconductor substrate defining a horizontal plane, at least one semiconductor channel disposed along a vertical axis, and a number of word lines comprising a nickel or cobalt alloy.

[0100] In addition to the metallization process, the method for manufacturing such memory may also include at least one other step. For example, the method of the present invention may include the following steps prior to the activation and electrodeless deposition steps of the nickel or cobalt alloy: - The step of manufacturing or providing a stack of parallel layers disposed on a semiconductor substrate and comprising at least two sacrificial material layers (such as SiN or polysilicon) separated by a first insulating material (such as SiO2), the stack having a vertical surface leading to a cavity, the maximum dimension of which is along a vertical axis. - A step of selectively etching sacrificial material to form at least two horizontal cavities leading to a cavity in which the axis is vertical.

[0101] These two steps are followed by the selective deposition of nickel or cobalt alloy into the horizontal cavity using the electrodeless process described above. The selective deposition step ensures that the vertical cavity is not filled with nickel or cobalt alloy after this step is completed.

[0102] The vertical cavity may have an average opening diameter ranging from 80 nm to 150 nm and a depth greater than 1 micrometer, and the horizontal cavity may have an average width along the vertical axis that is smaller than the average opening diameter of the vertical cavity.

[0103] The method of the present invention provides a particularly advantageous alternative for manufacturing 3D NAND, which comprises more than 90 tungsten lines or other solidly deposited metals. The substrate used to manufacture such 3D NAND (which is in contact with the electrodeless solution (also known as the electrolyte) described above) may contain a layer count greater than or equal to a value selected from the group consisting of: 32, 48, 64, 96, 128, 192, 256, preferably 96 or 128.

[0104] In this substrate, the vertical cavity has an average diameter of less than 1 micrometer at the opening, for example in the range of 50 nm to 150 nm, and a depth of more than 1 micrometer, and the horizontal cavity has an average width of less than 100 nanometers along the vertical axis and an average depth of less than 100 nanometers along the horizontal axis.

[0105] According to a second embodiment of the process of the present invention, a nickel or cobalt alloy deposit forms at least a portion of electrical contacts between different functional conductive elements of a 3D NAND device. These contacts may be located between bit lines and semiconductor channels (referred to as "contacts" in this specification). These contacts may also be located between power supply lines and word lines (referred to as "peripheral contacts" in this specification).

[0106] According to a third example, the 3D NAND memory obtained by the method of the present invention includes a semiconductor substrate defining a horizontal plane, at least one semiconductor channel arranged along a vertical axis, and at least one bit line comprising a nickel or cobalt alloy deposited according to the metallization process of the present invention.

[0107] The features of the metallization process described above are applied to all three embodiments of the method according to the present invention, including the features of implementing the step of activation by noble metal and the step of contacting the activated substrate with an electrodeless solution.

[0108] In addition to the metallization process, the manufacturing method according to the present invention may also include at least one other step. For example, the method of the present invention may include a step of depositing a dielectric material layer before the activation and electrodeless deposition steps of a nickel or cobalt alloy, followed by a step of etching cavities in the dielectric material by photolithography. The walls of the dielectric cavities are then activated by a noble metal and metallized by a nickel or boron alloy as described above. [Detailed Explanation of the Diagram] []

[0109] The 3D NAND memory reproduced in Figure 1 according to prior art includes: - A silicon substrate 4, which is covered with a dielectric coating 6b and a stack of layers located in a horizontal plane, the stack alternating layers of silicon dioxide 1 and conductive metal layers constituting tungsten zigzag lines 23. - At least one polycrystalline silicon channel 5, which vertically penetrates the stack of layers, and - At least one copper bit line 406, which is located in a plane parallel to and above the stack of layers. The polysilicon channel 5 and the copper bit line 406 are electrically connected via a tungsten metal contact 305b. The polysilicon channel 5 and word line 23 are separated by the ONO charge storage region, and The copper bit line 406 is separated from the metal contact 305b by a copper diffusion barrier material 404, which typically contains tantalum nitride or titanium nitride. The metal contact 305b is separated from the polycrystalline silicon channel 5 by a layer of barrier material 304a, typically comprising tantalum nitride or titanium nitride, and The letter line 23 is separated from silicon dioxide 1 by a layer of barrier material 21, which typically contains tantalum nitride or titanium nitride.

[0110] Figures 2A to 2D, 4A to 4B and 5 illustrate a first example of a 3D NAND memory manufacturing method according to the present invention, which generates word lines containing nickel or cobalt alloy by metallizing the surface of a silicon dioxide structure. These figures only show a few levels of dielectric / conductor stacking. It should be remembered that the 3D NAND memory of this invention can contain dozens, especially 96, 128, or 196 layers. Figures 2A to 2D only show eight layers. According to the method of the present invention, a substrate is provided, which is etched to form horizontal cavities, which are then metallized by a nickel or cobalt alloy. The substrate in FIG2A includes a semiconductor substrate 4 and a semiconductor channel 5 (only a portion of which is shown). Two layers parallel to the substrate 4 are stacked alternately, consisting of a sacrificial material 1 such as silicon nitride and an insulating material 2 such as SiO2, and are separated by a vertical cavity 30. The sacrificial layer 1 located at the bottom is separated from the semiconductor channel 5 by a dielectric ring 6a and from the substrate 4 by a dielectric coating 6b. The so-called "ONO" charge storage region separates the semiconductor channel 5 from the stacked layers. The ONO region includes charge storage material 8 that is separated from the semiconductor channel 5 and the stack by an insulating region containing a barrier dielectric layer 7 and a tunneling dielectric layer 9.

[0111] The barrier dielectric layer 7 may comprise a single dielectric material layer or an array of dielectric material layers. In one embodiment, the barrier dielectric layer 7 comprises aluminum oxide, silicon oxide, silicon oxynitride, or combinations thereof. The thickness of the dielectric layer 7 may range from 1 nm to 20 nm. The charge storage region 8 may be a continuous layer or an array of discrete portions. In FIG. 2A, the charge storage region 8 is shown as a continuous layer comprising a dielectric charge trapping material such as silicon nitride. In an embodiment not shown, the sacrificial material layer 1 may be laterally recessed from the sidewall of the insulating layer 2, and the charge storage layer 8 may be in the form of a plurality of spaced-apart portions. The charge storage layer 8 may be formed from a single material or comprise a stack of several charge storage materials. The thickness of the charge storage layer 8 may range from 2 nm to 20 nm. It may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Specifically, the charge storage layer 8 may contain metals such as ruthenium, metal silicides such as nickel silicide, and / or semiconductor materials. The tunneling dielectric layer 9 contains at least one dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In one embodiment, the tunneling dielectric layer 9 may comprise a silicon dioxide / silicon oxynitride / silicon dioxide stack. The thickness of the tunneling dielectric layer 9 may be in the range of 2 nm to 20 nm.

[0112] The sacrificial material 1 of the substrate in Figure 2A is etched to obtain the structure shown in Figure 2B. Selective etching of the volume of the sacrificial material 1 is performed to create cavities 3. In the case where the sacrificial material layer 1 contains silicon nitride, the etching process can be performed by wet etching by immersing the structure in a reservoir containing phosphoric acid. Cavities 3 are horizontal cavities. In the sense of the present invention, a horizontal cavity is a cavity having a smaller size located in the plane of Figure 2B and a larger size located in a plane perpendicular to it. The ratio of the maximum size to the minimum size of the cavity 3 is greater than 1 and can be as high as 10 or even 100. Each cavity 3 is defined by the upper horizontal surface of the underlying insulating layer 2, the lower horizontal surface of the underlying insulating layer 2, and the lateral vertical surface of the dielectric material (preferably, the material blocking the dielectric layer 7). In the context of this invention, the cavity 3 is filled with a nickel or cobalt alloy using an electrodeless process to create word lines for an integral three-dimensional NAND device. In Figure 2C, a nickel or cobalt alloy metal deposit 20 can be seen filling the horizontal cavity 3 and covering the insulating material 2. The metal deposit is obtained in two steps by sequentially contacting the substrate of Figure 2B with an activation solution containing a noble metal to obtain an activated silicon dioxide surface, and subsequently contacting the activated surface with an electrolyte as described above without electrodeization. The deposited metal 20 fills the entire volume of the horizontal cavity 3 and may also cover all or part of the sidewalls of the insulating layer 2. The structure obtained after etching excess metal 20 located outside the cavity 3 and covering the dielectric blocks 2 is shown in Figure 2D. This structure includes nickel or cobalt alloy word lines 20a.

[0113] Figure 3 illustrates an intermediate structure obtained using a prior art process for fabricating tungsten dot lines 23 in 3D NAND memory. This structure is obtained from the same substrate shown in Figure 2B, which includes a cavity 3 and an insulating layer 2 defining a free dielectric surface, including a surface blocking the dielectric layer 7, a bottom and walls of the cavity 3, and a flush surface of the dielectric layer 2. According to prior art processes, a tungsten diffusion barrier layer 21 is deposited on the dielectric surface using a CVD or ALD process; this barrier layer comprises a metal nitride such as TiN or TaN. Examples of prior art barrier layers consist of a stack of three consecutive layers: titanium nitride / tungsten / titanium nitride, each of which may have a thickness in the range of 1 nm to 3 nm. After depositing the barrier layer 21, the hollow volume of the barrier-covered cavity is filled with tungsten using CVD or ALD to form a metal deposit 23. In the prior art 3D NAND memory obtained by this process, material voids 22 were observed in the metal layer, the frequency of which was inversely proportional to the size of the opening of the cavity 3.

[0114] Figures 4A, 4B, and 5 illustrate a variant of the metallized alumina (Al₂O₃) instead of silicon dioxide in the process of this invention. In this embodiment, a thin alumina layer can be intercalated between the insulating layer 2 and the nickel or cobalt alloy 20 in the final device. Its thickness can range from 1 nm to 15 nm, for example, between 2 and 6 nm. The process then includes another step: depositing a thin alumina layer 10 on the surface defined by the cavity 3 and by means of the protruding insulating layer 2 of the substrate conforming to Figure 2B to obtain the pattern conforming to Figure 4A. The surface of the alumina layer 10 is then contacted with an activation solution containing a noble metal to obtain an activated alumina surface, which is then contacted with an electrolyte as described above without polarization to induce the deposition of the nickel or cobalt alloy. The result of this process is the substrate shown in Figure 4B or Figure 5.

[0115] According to a preferred embodiment of the present invention, the apparatus is obtained by activating the surface of the insulating layer 2 and / or the thin alumina layer 10 using an aqueous solution containing a noble metal (such as palladium). Following this activation, the structure containing the cavity 3 is immersed in a solution containing nickel ions and a reducing agent containing nickel ions (preferably borane, and more preferably dimethylamine borane) to deposit a nickel-boron alloy as a metal on the bottom and walls of the cavity 3. The alloy may completely fill the cavity and form deposit 20b (Figure 4B) or cover the walls and bottom of the cavity without completely filling it to form deposit 20c (Figure 5).

[0116] In the manufacturing process of this invention, it is advantageous to fill all horizontal cavities 3 without completely filling the vertical cavity 30.

[0117] In detail, Figures 4A and 4B illustrate one embodiment of the present invention for forming a nickel-boron alloy deposit 20b from a silicon substrate. The silicon substrate includes i) a vertical cavity 30 having an opening of approximately 100 nm and a height of approximately 4 micrometers; ii) a horizontal cavity 3 having a height of 30 nm (dimension c) and a depth of 50 nm (dimension a); and protrusions corresponding to the silicon dioxide of the insulating layer 2. The horizontal cavity 3 and the surface of the silicon dioxide are covered with an aluminum oxide layer 10 with a thickness of approximately 5 nm (dimension b). The nickel-boron alloy deposit 20b fills the horizontal cavity 3 and covers the aluminum oxide layer 10.

[0118] In Figure 5, the nickel-boron alloy deposit 20c is in the form of a thin layer covering the entire surface of the alumina layer 10 without filling the horizontal cavity 3.

[0119] In the embodiments of the invention shown in Figures 2, 4, and 5, the barrier material layer may be inserted between the barrier dielectric 7 and the nickel or cobalt alloy 20, or between the alumina layer 10 and the nickel or cobalt alloy 20b. However, this embodiment of the invention is not preferred because the process of the invention has the advantage of avoiding this step. This is advantageous because barrier materials such as metal nitrides have lower conductivity than metals, and the addition of a barrier layer reduces the available cavity space for metal filling. Not depositing a barrier layer makes it possible to create conductive lines with conductivity at least equal to or even higher than that of prior art lines. Furthermore, depositing a barrier material implies efficiency improvements in the additional steps of the 3D NAND manufacturing process.

[0120] According to a variation of the process of the present invention, and according to a process known to those skilled in the art, in the intermediate step between the step of forming cavity 3 and the step of depositing the nickel or cobalt alloy 20 shown in FIG. 2C, a barrier material layer may thus be inserted between the surface of the barrier dielectric layer 7 shown in FIG. 2B and the nickel or cobalt alloy layer 20a. According to another variation of the process of the present invention, a diffusion barrier material layer known to those skilled in the art may be inserted between the surface of the alumina layer 10 shown in FIG. 4B and the metal layer 20b. In both variations, the barrier material may be deposited in one or more steps. The barrier layer may be a single metal nitride layer or a stack of multiple layers of different materials, including at least one metal nitride layer. The metal nitride may be TiN, TaN, or WN. For example, a continuous layer of tantalum nitride or titanium nitride with a thickness of 1 nm to 6 nm may be deposited.

[0121] A second example of the method for manufacturing 3D NAND memory according to the present invention produces peripheral contacts comprising a nickel or cobalt alloy. This embodiment is illustrated in Figures 6 to 8. This variation of the present invention, by implementing the metallization process of the present invention, produces vertical lines connecting word lines to power supply lines, these vertical lines comprising a nickel or cobalt alloy.

[0122] Figures 6 to 8 illustrate a second example of the manufacturing method of the present invention, by which a 3D NAND memory is obtained, comprising a semiconductor substrate defining a horizontal plane, a stack of layers deposited on the semiconductor substrate alternating between an insulating layer 1 and word lines 24, a vertical semiconductor channel 5, and peripheral contacts 203 connecting power supply lines to the word lines. At least a portion of the peripheral contacts 203 is formed by a nickel or cobalt alloy deposit, i.e., contacts located at the periphery 200 of the device, wherein the center of the device is occupied by the vertical semiconductor channel 5. The peripheral contacts 203 connect the word lines 24 to conductive power supply lines (not shown). To produce these peripheral contacts 203, a substrate (such as the substrate shown in FIG. 6) may be manufactured or obtained, which includes a horizontal stack of insulating layer 1 and word lines 24 and a vertical semiconductor channel 5 surrounded by an ONO assembly. The substrate may have prior art and include tungsten-based word lines 24. Alternatively, the substrate can be obtained by a metallization process incorporating the present invention, and the word line 24 comprises a nickel or cobalt alloy. The stack of insulating layer 1 and word line 24 is covered on its upper portion by an insulating capping layer 1a (which may be made of silicon dioxide), and on its lateral portions by dielectric blocks 1b covering all steps of the stepped stack. Dielectric blocks 1b may be made of silicon dioxide, which may be doped with elements such as boron, phosphorus, or fluorine, depending on the situation. The capping layer 1a and dielectric blocks 1b are coplanar and covered by a contact dielectric layer 1c. Two regions can be defined: a central region 100 comprising the vertical semiconductor channel 5, and a peripheral region 200 comprising the word line 24 and dielectric blocks 1b. Two types of contacts can be generated on this substrate: a first series of contacts located on the central region 100, which are in the form of blocks disposed on the upper portion of the semiconductor channel 5; and a second series of contacts located on the peripheral region 200, which are in the form of vertical lines intended to connect word lines 24 to a power source not shown in FIG. 6 and located on the upper portion of the substrate.

[0123] As shown in Figure 7, a photolithography mask 201 is deposited on the substrate shown in Figure 6 to etch contact cavities 202 in dielectric blocks 1b. Etching is performed using a highly selective etching solution that is highly selective for the metal constituting the word lines 24, stopping etching once the etching solution contacts the word lines 24. This etching step forms vertical contact cavities 202 with a depth increasing from the top to the bottom of the dielectric blocks 1b, i.e., from the top to the bottom of the stepped stack. After removing the polymer deposited by photolithography and cleaning the substrate, the substrate is contacted with an activation solution to selectively graft noble metals onto the walls of the contact cavities 202 constituting the dielectric surface of the etched dielectric blocks 1b. The dielectric surface activated by the noble metals is then contacted with an electrodeless solution containing nickel or cobalt ions to form a nickel or cobalt alloy deposit according to the process of the present invention. Chemical mechanical polishing removes excess alloy deposited on the outside of the contact cavity 202 and provides a peripheral contact 203 made of nickel or cobalt alloy, as shown in Figure 8.

[0124] According to the prior art process illustrated in Figure 9 for producing the peripheral tungsten contact 205, except that the vertical direct contact cavity 202 includes tungsten letter lines 23, the vertical direct contact cavity is etched by photolithography on a previously described substrate similar to the substrates of Figures 6 and 7. After cleaning the substrate and the photolithographically deposited polymer, a TiN or TaN barrier layer 204 is applied to the surface of the etched substrate, and then the cavity is filled with tungsten. Excess metal deposited outside the vertical direct contact cavity 202 is then removed by chemical mechanical polishing to obtain the peripheral tungsten contact 205. The process of the present invention advantageously makes it possible to omit the step of depositing the TiN or TaN barrier layer 204, which is necessarily interposed between the tungsten and the dielectric 1b.

[0125] Figures 10 to 12 illustrate a third example of an embodiment of the process of the present invention, which makes it possible to obtain a 3D NAND memory having contacts between semiconductor channels and bit lines, the contacts comprising a nickel or cobalt alloy. The substrate shown in Figure 10, comprising an insulating layer 1 and word lines 25, is manufactured or obtained. The substrate may have prior art features and include tungsten word lines 25 and tungsten-based peripheral contacts 206. When the word lines and peripheral contacts are tungsten, a titanium nitride or tantalum nitride barrier layer is interposed between the tungsten and the dielectric block 1b and the dielectric layer 1a. Alternatively, the substrate may have word lines 25 comprising a nickel or cobalt alloy, or vertical peripheral contacts 206 comprising a nickel or cobalt alloy, or both, wherein the nickel or cobalt alloy has been formed by performing the previously described metallization process. The contact dielectric layer 1c is covered by another dielectric layer 1d.

[0126] As shown in Figure 11, a photomask 301 has been deposited on the substrate shown in Figure 10 to etch contact cavities 302a and 302b into the dielectric layer 1d. The etching is performed using an etching solution that has high selectivity for the metal and semiconductor channels 5 of the peripheral contact 206.

[0127] After cleaning the polymer deposited by photolithography, the substrate is contacted with an activation solution to selectively graft noble metals onto the walls and the surface of layer 1d of contact cavities 302a and 302b, thereby forming a dielectric surface. The dielectric surface activated by the noble metal is then contacted with an electrodeless solution containing nickel or cobalt ions to form a nickel or cobalt alloy deposit according to the process of the present invention. Chemical mechanical polishing removes excess alloy deposited on the exterior of contact cavities 302a and 302b, and as shown in FIG12, peripheral contacts 303a in the form of blocks on top of peripheral contacts 206 and contacts 303b in the form of blocks on top of semiconductor channels 5 are produced, these contacts 303a and 303b comprising nickel or cobalt alloys. Contacts 303a thus manufactured will connect peripheral contacts 206 to power supply lines to be formed later, while contacts 303b will connect semiconductor channels 5 to bit lines to be formed in later steps.

[0128] According to a prior art process (illustrated in Figure 13) used to produce tungsten contacts 305a and 305b, vertical contact cavities are etched on a previously described substrate similar to that in Figure 10 by photolithography. This substrate includes tungsten word lines 23 and tungsten peripheral contacts 206; the tungsten in the word lines and peripheral contacts is insulated from adjacent dielectric materials by a barrier material. Cavities are formed on top of the semiconductor channel 5 and on top of the peripheral contacts 206 by etching. After cleaning the substrate and the photolithographically deposited polymer, the etched substrate surface is covered with barrier layers 304a and 304b of tantalum nitride or titanium nitride, and then the cavities having walls covered with the barrier material are filled with tungsten. Excess metal deposited outside the contact cavities is subsequently removed by chemical mechanical polishing to obtain peripheral tungsten contacts 305a and tungsten contacts 305b. The process of this invention advantageously makes it possible to omit the step of depositing barrier layers 304a and 304b, which are necessarily inserted between tungsten and the dielectric material of elements 1c and 1d.

[0129] Figure 14 illustrates a structure comprising bit lines 403 based on a nickel or cobalt alloy obtained according to the process of the present invention. Starting from the substrate of Figure 12 obtained according to the process of the present invention, or from the substrate of Figure 13 which is available in the prior art, a dielectric 1e is deposited. This dielectric is etched by photolithography to form cavities, the bottom of which reaches the upper surface of contacts 306. These contacts may be made of tungsten or a nickel or cobalt alloy, depending on the starting substrate used. The portion of the etched substrate leaving flush dielectric material 1e is activated by a noble metal and then contacted with an electrodeless solution containing nickel or cobalt ions according to the process of the present invention to form bit lines 403 based on a nickel or cobalt alloy.

[0130] According to the prior art process illustrated in Figure 15, the substrate of Figure 13 is covered with a layer of dielectric material 1e, which is formed by photolithography to reach the upper surface of the tungsten contact 305b. The walls of the cavity flush with the dielectric material 1e (the bottom being the top surface of the contact 305b) and the surface of the dielectric material outside the cavity are covered by a thin layer of barrier material 404, and then by a thin layer of copper 405. The remaining volume of the cavity is then filled with copper 406. Advantageously, the process of the present invention makes it possible to omit the steps of depositing the barrier layer 404 and the copper seed layer 405. electrolytes

[0131] The electrolyte according to the present invention is an electrolyte used in the manufacture of 3D NAND memory devices, comprising: - Metal ions, preferably nickel or cobalt ions, with a concentration between 10⁻³ M and 1 M; - At least two reducing agents for these metal ions, preferably in amounts between 10⁻⁴ M and 1 M; - A reagent used to adjust and maintain the pH value between 6 and 11, preferably between 8 and 10; - At least one polyamine reagent, preferably in an amount between 1 and 100 mg / L.

[0132] The characteristics of the metallization process have been described and are applicable to this electrolyte.

[0133] In this embodiment, the electrolyte contains two reducing agents. The two reducing agents may be hypophosphorous acid and dimethylaminoborane.

[0134] EP 2 705 172 A1 proposes depositing nickel-boron alloys in vertical trenches with a diameter of approximately 1 to 5 micrometers at the opening and a depth of approximately 30 micrometers. However, the inventors have demonstrated that this prior art electrolyte does not allow for the simultaneous filling of structures with different geometries, such as those used in the fabrication of 3D NAND. Specifically, the following comparative examples demonstrate that the electrolyte according to EP 2 705 172 A1 does not make it possible to obtain conformal deposits at the bottom of structures with openings as small as 100 nm and depths as large as 4 micrometers.

[0135] The DMAB reducing agent in the prior art was insufficient to induce reduction at the bottom and sides of the tank and stage. Surprisingly, the inventors have discovered that adding a second reducing agent can accelerate the growth of alloys in structures that are difficult to access and achieve conformal deposition without affecting alloy quality.

[0136] The electrolyte may contain two polyamine reagents, namely a first polyamine reagent and a second polyamine reagent, preferably an aliphatic polyamine.

[0137] The concentration of the first polyamine reagent can be between 0.5 ppm and 100 ppm, and the concentration of the second polyamine reagent can also be between 0.5 ppm and 100 ppm. Preferably, the molecular weight of the first polyamine reagent is lower than that of the second polyamine. The molecular weight of the second polyamine reagent can be in the range of 500 g / mol to 25000 g / mol, and the molecular weight of the first polyamine reagent can be in the range of 50 g / mol to 500 g / mol, excluding values ​​of 50 g / mol and 500 g / mol.

[0138] Specific electrolytes include: - At least one metal salt of nickel or cobalt ions between 10⁻² M and 1 M; - At least one first reducing agent of nickel or cobalt ions between 10⁻⁴ M and 1 M; - At least one second reducing agent, different from the first reducing agent, with a concentration between 10 and 100 mg / L; - At least one primary polyamine between 1 and 5 mg / L; - At least one second aliphatic polyamine, ranging from 1 to 100 mg / l, preferably from 1 to 10 mg / l, having a molecular weight lower than that of the first polyamine.

[0139] The first and second reducing agents can be selected from the reducing agents described above.

[0140] This application also discloses an electrolyte for manufacturing 3D NAND memory devices, the electrolyte comprising: - At least one metal salt, preferably with a concentration between 10⁻³ M and 1 M; - At least one reducing agent of the metal salt, preferably in an amount between 10⁻⁴ M and 1 M; - A reagent used to adjust and maintain the pH value between 6 and 11, preferably between 8 and 10; - A first polyamine reagent and a second polyamine reagent different from the first polyamine reagent.

[0141] This application discloses an electrolyte for coating the surface of a dielectric material, the electrolyte comprising: - At least one metal salt, preferably with a concentration between 10⁻³ M and 1 M; - A mixture of reducing agents, preferably expressed in amounts between 10⁻⁴ M and 1 M; - A reagent used to adjust and maintain the pH value between 6 and 11, preferably between 8 and 10; - At least two reagents capable of adsorbing onto a metal oxide, specifically, the first reagent having an inhibitory effect and preferably having a concentration between 0.5 ppm and 100 ppm, and the second reagent having an inhibitory effect and preferably having a concentration between 0.5 ppm and 100 ppm.

[0142] This application further discloses an electrolyte for manufacturing 3D NAND memory devices, comprising: - At least one metal salt, preferably with a concentration between 10⁻³ M and 1 M; - A mixture of at least two reducing agents, preferably expressed in an amount between 10⁻⁴ M and 1 M; - A reagent used to adjust and maintain the pH value between 6 and 11, preferably between 8 and 10; - At least two reagents capable of adsorbing onto a metal oxide, specifically, the first reagent having an inhibitory effect and preferably having a concentration between 0.5 ppm and 100 ppm, and the second reagent having an inhibitory effect and preferably having a concentration between 0.5 ppm and 100 ppm.

[0143] The first reagent may be diallyltriamine, and the second reagent may be polyethylenediimide. The electrolyte may contain two reducing agents, namely hypophosphorous acid and dimethylamineborane.

[0144] The ratio of metal ions to the second polyamine reagent is preferably greater than 1.

[0145] The specific electrolyte of the present invention comprises nickel ions between 10⁻² M and 1 M, DMAB between 10⁻⁴ M and 1 M, H₂PO₃ between 10 and 100 mg / L, PEI between 1 and 5 mg / L, and dipropylenetriamine between 1 and 100 mg / L, preferably 1 to 10 mg / L.

[0146] In one particular embodiment of the present invention, the first reducing agent is preferably dimethylamine borane, and the second reducing agent is preferably hypophosphoric acid.

[0147] The first and second polyamines may be selected from the polyamines described above. In a particular embodiment, the first polyamine is a polyethyleneimine with a molecular weight in the range of 500 g / mol to 25000 g / mol, and the second aliphatic polyamine may be diallyltriamine.

[0148] To facilitate the filling of horizontal cavities above trenches in a stage or the main trenches in a 3D NAND structure, this particular combination of two aliphatic polyamines is preferred. In the following comparative examples, it has been demonstrated that, without diallyl-triamine, the metal deposits formed at the bottom of cavities are not conformally preserved, which can cause problems during subsequent etching steps involving excessive metal deposition, especially at the level of vertical cavities. Without being bound by any theory, it is believed that the combination of the two polyamines promotes lateral growth of metal in a 30 nm high stage without affecting the conformability of deposits in vertical structures with openings of approximately 100 nm. It appears that polyamines with a molecular weight greater than 500 g / mol do not allow for selective filling when used alone, possibly due to their hydrodynamic volume and low diffusivity into the stage.

[0149] In one particular embodiment, the electrolyte comprises: - At least one metallic salt of nickel(II), with a concentration between 100 mM and 200 mM; - At least one reducing agent for nickel ions, in an amount between 400 mM and 550 mM; - A stabilizer, preferably citric acid, in an amount sufficient to cause nickel ions to misalign; - Poly(ethylene ethylene imide), with a number-average molecular weight Mn of approximately 600 g / mol, and a concentration ranging from 1 mg / L to 5 mg / L. - Aliphatic polyamines with a molecular weight less than 500 g / mol and an amount ranging from 1 mg / L to 100 mg / L, and - A reagent used to adjust the pH to a value between 9.0 and 9.5.

[0150] In this particular embodiment, two reducing agents may be used, including dimethylaminoborane at a concentration of 450 mM to 500 mM and hypophosphite at an amount of 10 mg / L to 100 mg / L.

[0151] The electrolyte is prepared upstream of the metallization step, and if necessary, certain components constituting the electrolyte are stored. Preferably, at least two different solutions are prepared and stored just before the electrodeless solution comes into contact with the substrate. A first solution containing metal ions and a second solution containing a reducing agent can be prepared and, if appropriate, stored. Together, these two solutions contain all the compounds in the electrolyte composition. In this case, preferably, the second solution containing the reducing agent also contains one or more polyamines, if some of them are present. The metal ions and the reducing agent are preferably packaged separately for use in the electrodeless solution, just before contact with the substrate. The electrolyte of the present invention is preferably prepared temporarily by mixing the two solutions mentioned above.

[0152] The third objective of this invention is a 3D NAND device in which the metal used to manufacture the word lines substantially comprises an alloy of nickel and at least one element selected from boron, phosphorus and tungsten, the element being represented between 1 atomic% and 10 atomic%.

[0153] According to a specific embodiment of the 3D NAND device of the present invention, all semiconductor channels are vertical (vertical channels) and the gates of the memory cells are horizontal (horizontal gates): each channel is thus surrounded by a vertical stack of memory cells, and the control gate (also called a word line) is in the form of a horizontal line. In this vertical integration mode, the memory cells surround the channels and are in a so-called gate-around-all-around (GAA) configuration.

[0154] Various types of vertically integrated 3D NAND memory are known to those skilled in the art. Without limiting the invention to these categories, reference memory such as BiCS® (Bit-Cost Scaling®), P-BiCS® (Pipe-shape Bit-Cost Scaling®), TCAT (Trillion-Cell Array Transistor), and 3D V-NAND (vertical NAND) may be mentioned, in which information storage is achieved by means of a charge storage material (typically silicon nitride). Another type of memory system is 3D V-FG (3D Vertical Floating Gate), in which charge storage is provided by a floating gate.

[0155] In TCAT and V-NAND technologies, the control gate is deposited last (post-gate or gate replacement), which requires sacrificial nickel silicide, which is replaced by the control gate (thin metal layer), followed by metal filling. In p-BICS and 3D V-FG technologies, the metal gate is deposited first (pre-gate).

[0156] In one particular embodiment of the present invention, the 3D NAND device is a 3D V-NAND memory.

[0157] Especially in the case of 3D V-NAND, the NAND device of the present invention may include a high dielectric constant material in the gate dielectric, such as aluminum oxide instead of silicon dioxide, to optimize charge transfer.

[0158] The apparatus can be manufactured according to various methods known to those skilled in the art, wherein at least one tungsten deposition step is replaced by a nickel deposition step according to the process of the present invention described above.

[0159] The invention is illustrated by the following examples. [Example] [1] [Contains nickel] [-] [The Production of Boron Alloy Zigzag Lines]

[0160] In this example, the substrate used is a silicon sample with a side length of 4 cm × 4 cm and a thickness of 750 µm. It has a vertical cavity and a horizontal cavity. The vertical cavity has an opening of about 100 nm and a height of about 4 micrometers. The horizontal cavity has a height of 30 nm and a depth of 50 nm. All cavities are covered with an aluminum oxide (Al2O3) layer with a thickness of about 5 nm.

[0161] [a] [)] [Pretreatment of the cavity surface:] Clean the test piece according to the chemical properties of the substrate. After this cleaning step, rinse the test piece thoroughly with deionized water, immerse it in a beaker filled with deionized water, and subject it to ultrasonic treatment (40 kHz) for 2 minutes. Then remove the test piece from the beaker, rinse it thoroughly with deionized water, and dry it in an oven at 100°C for 10 minutes.

[0162] [b] [)] [Activation of cavity surfaces:] [b1] [)] [Preparation of Activation Solution:] [] In a beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 ml of anhydrous DMSO (maximum 50 ppm H2O). [b2] [)] [Activation treatment of substrate surface] [:] [] The sample prepared in step a1) was immersed in a beaker containing the activation solution prepared in step b1), and subjected to a rapid vacuum sufficient to expel any air trapped within the cavity of the structure. For this purpose, the beaker was introduced into a desiccator, which was itself connected to a vane pump, and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample was heated to 65°C for 20 minutes. The sample was removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample was then removed from the beaker and thoroughly rinsed with deionized water.

[0163] [c] [)] [Through electrodeless deposition] [NiB] [Metallic layer] [:] [c1] [)] [Pre-preparation of electrodeless solution] [:] [] In a 1-liter container and with minimal deionized water, 31.11 g of nickel sulfate hexahydrate (0.118 mol), 44.67 g of citric acid (0.232 mol), 52.26 g of N-methylaminoethanol (0.700 mol), 2.5 ppm of polyethyleneimine (PEI) (with Mn = 600 g / mol), 55 ppm of hypophosphite, and 6 ppm of dipropylenetriamine were added sequentially. The final pH was adjusted to 9.3 using N-methylaminoethanol, and the total volume was adjusted to 1 liter using deionized water. Only before the next step, add one volume of reducing solution to the previous nine volumes of solution. The latter contains 28 g / L dimethylamine borane (DMAB; 0.475 moles) and 60.00 g N-methylaminoethanol (0.798 moles). [c2] [)] [Formed on the alumina layer] [NiB] [Alloy Layer] [:] [] The nickel-boron alloy layer was deposited on the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water. The beaker was rapidly evacuated to a vacuum sufficient to remove trapped air from the cavity of the structure. For this purpose, the beaker was introduced into a desiccator, which was connected to a vane pump, and subjected to vacuum for approximately 2 minutes. After returning to ambient pressure, the sample was rapidly immersed in a pre-prepared electrodeless solution and heated to 65°C for 30 seconds to 9 minutes, depending on the desired final thickness and the size of the treated structure. A bright gray metallic coating was then observed on the sample. The sample was removed from the solution, thoroughly rinsed with deionized water, immersed in a beaker of deionized water, and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample was then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The specimens were subjected to rapid thermal annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This operation can be performed using a tube furnace or a hot plate.

[0164] [d] [)] Properties of metal deposits filling cavities After the hot annealing of the specimen obtained in step c2), it was observed that all horizontal cavities were filled with a nickel-boron alloy without material voids, and the vertical cavities were not completely filled. The pattern of the resulting alloy deposit is shown in Figure 5. [e] [)] [made] [EELS] [curve] [:] [Metal Barrier Properties] [] At the end of step c2), the sample obtained is subjected to a new thermal annealing for one minute at 800°C in a reducing atmosphere (4% hydrogen in nitrogen) to simulate the transformations it undergoes during all manufacturing steps of industrial 3D NAND memory. EELS curves (shown in Figure 17) demonstrate that the nickel-boron alloy does not diffuse into SiO2. The metal deposited according to the process of the present invention makes it possible to eliminate the step of depositing a barrier layer of several nanometers, necessitating interpolation between the dielectric and the cavity-filling metal to manufacture prior art 3D NAND memory. [f] [)] [Evaluation of wafer bending induced by metal film] [] In the context of this invention, the bending caused by the 50 nm NiB deposit annealed at 400°C for 2 hours does not interfere with the flatness of the wafer. The stress applied to the NiB layer was evaluated to be 825 MPa, which is greater than 2 GPa for a tungsten-CVD W layer of equivalent thickness. This is illustrated in Figure 16. [Example] [2] [Depositing nickel on the walls of the cavity intended to form the letter lines] [-] [Boron alloy thin film]

[0165] Example 1 is repeated, except that 55 ppm hypophosphoric acid is not added in step c1). The horizontal cavity is covered with a thin layer of NiB alloy, and a schematic diagram of the resulting substrate is shown in Figure 6. [Example] [3] [By using nickel] [-] [Boron alloy is used to create the contact between the bit line and the polycrystalline silicon channel] [] The objective of this example is to activate a substrate with a mixed structure of silicon dioxide (SiO2) and polycrystalline silicon (pSi) from a solution containing silane and palladium complexes to fill the "contact" structure between the "bit lines" and "channels" of a NAND substrate with a NiB-type alloy.

[0166] The substrate used in this example consists of a silicon wafer with 4×4 cm sides and a thickness of 750 µm, covered with a structured silicon oxide layer having through-holes (grooves) with an opening of approximately 100 nm and a height of approximately 300 nm. The bottom of the cavity is recessed and in direct contact with polycrystalline silicon (pSi). This structure simulates the contacts in a NAND device.

[0167] [Clean the surface of the cavity] [:]

[0168] The sample was immersed in solution SC1 at 70°C and ultrasonically treated (40 kHz) for 10 minutes. After this cleaning step, the sample was thoroughly rinsed with deionized water, then immersed in a beaker filled with deionized water and ultrasonically treated (40 kHz) for 2 minutes. The sample was then removed from the beaker, thoroughly rinsed with deionized water, and dried in an oven at 100°C for 10 minutes.

[0169] [Cavity Surface Activation] [:] [b1] [)] [Preparation of Activation Solution] [:] [] In a dry beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 ml of anhydrous DMSO (maximum 50 ppm H2O). [b2] [)] [Activation treatment of substrate surface] [:] [] The sample prepared in step a) was immersed in a beaker containing the activation solution prepared in step b1), and subjected to a rapid vacuum sufficient to expel any air trapped within the cavity of the structure. For this purpose, the beaker was introduced into a desiccator, which was itself connected to a vane pump, and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample was heated to 65°C for 10 minutes. The sample was removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample was then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream.

[0170] [Through electrodeless deposition] [NiB] [Metallic layer:] [c1] [)] [Pre-preparation of electrodeless solution] [:] [] In a 1-liter container and a minimal amount of deionized water, sequentially add 31.11 g nickel sulfate hexahydrate (0.118 mol), 44.67 g citric acid (0.232 mol), 52.26 g N-methylaminoethanol (0.700 mol), 2.5 ppm polyethyleneimine (PEI) (where Mn = 600 g / mol), 55 ppm hypophosphite, and 6 ppm dipropylenetriamine. Adjust the final pH to 9.3 with N-methylaminoethanol and bring the total volume to 1 liter with deionized water. Only before the next step, add one volume of reducing solution to the nine volumes of the previous solution. The latter contains 28 g / L dimethylamine borane (DMAB; 0.475 mol) and 60.00 g N-methylaminoethanol (0.798 mol). For 4 × 4 cm test pieces, 100 ml of this mixture will be required. [c2] [)] [Fill in the hybrid structure] [NiB] [Alloy Layer] [:] [] The nickel-boron alloy layer was deposited onto the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water. The beaker was rapidly evacuated to a vacuum sufficient to remove trapped air from the cavities of the structure. For this purpose, the beaker was introduced into a desiccator, which was itself connected to a vane pump, and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the sample was rapidly immersed in the electrodeless solution previously prepared in (c1) and heated to 65°C for a period of 2 to 9 minutes, depending on the desired final thickness and the size of the treated structure. The solution was subjected to 3-second pulses of 40 kHz ultrasound in purge mode every 15 seconds for 2 minutes. Ultrasound was then applied continuously for a subsequent 7 minutes. This step therefore lasted for 9 minutes. A bright gray metallic coating was subsequently observed on the sample. After being removed from the solution, the sample is thoroughly rinsed with deionized water and then immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The sample is then subjected to rapid thermal annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This process can be performed using a tube furnace or a hot plate.

[0171] [Properties of metal deposits in filling contacts] Following heat annealing of the specimens obtained at the end of step c2), it was observed that all through-holes were uniformly filled with a nickel-boron alloy. The adhesion, measured according to standard ASTM 3359, was 16 / 16. This electrodeless solution therefore functions for both creating word lines (as in Examples 1 and 2) and creating contacts beneath the bit lines. [Example] [4] [:Produces nickel] [-] [Borne Alloy Bit Line] [] The objective of this example is to activate a substrate coated with a hybrid structure of silicon dioxide (SiO2) and NiB alloy, which is derived from a solution containing silane and palladium complex to fill the bit line structure above the NiB contacts of a NAND substrate having NiB alloy, such contacts having been manufactured, for example, according to Example 3.

[0172] The substrate used in this example consists of a 4×4 cm² silicon wafer with a thickness of 750 µm, covered with a structured silicon oxide layer containing vias (grooves) with an opening of approximately 300 nm and a height of approximately 500 nm. The bottom of the cavity is recessed and in direct contact with the NiB alloy or tungsten of the "contact" portion of the NAND structure. This structure simulates the bit lines in a NAND chip.

[0173] [Pre-treatment of cavity surfaces:] The sample was subjected to a reducing plasma treatment using hydrogen gas. After this surface pretreatment step, the sample was stored in a nitrogen atmosphere until the next step.

[0174] [Cavity Surface Activation] [:]

[0175] [b1] [)] [Preparation of Activation Solution:] In a dry beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 ml of anhydrous DMSO (maximum 50 ppm H2O). [b2] [)] [Activation treatment of substrate surface] [:] [] The sample prepared in step a) is immersed in a beaker containing the activation solution prepared in step b1), and subjected to a rapid vacuum sufficient to expel any air trapped within the cavity of the structure. For this purpose, the beaker is introduced into a desiccator, which is itself connected to a vane pump, and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample is heated to 65°C for 10 minutes. The sample is removed from the solution, thoroughly rinsed with deionized water, and immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. Subsequently, the sample is removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen flow.

[0176] [c] [)] [Through electrodeless deposition] [NiB] [Metallic layer] [:] [c1] [)] [Pre-preparation of electrodeless solution] [:] [] In a 1-liter container and with minimal amounts of deionized water, 31.11 g of nickel sulfate hexahydrate (0.118 mol), 44.67 g of citric acid (0.232 mol), 52.26 g of N-methylaminoethanol (0.700 mol), and 2.5 ppm of polyethyleneimine (PEI) (where Mn = 600 g / mol) were added sequentially. The final pH was adjusted to 9.3 using N-methylaminoethanol, and the total volume was adjusted to 1 liter using deionized water. Only before the next step, add one volume of reducing solution to the previous nine volumes of solution. The latter contains 28 g / L dimethylamine borane (DMAB; 0.475 moles) and 60.00 g N-methylaminoethanol (0.798 moles). [c2] [)] [Formed on a hybrid structure] [NiB] [Alloy Layer] [:] [] The nickel-boron alloy layer was deposited onto the surface of the substrate treated in step b) by first immersing it in a beaker of deionized water. The beaker was rapidly evacuated to a vacuum sufficient to remove trapped air from the cavities of the structure. To perform this operation, the beaker was introduced into a desiccator connected to a paddle pump and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the sample was rapidly immersed in the electrodeless solution previously prepared in (c1) and heated to 65°C for a period of 2 to 9 minutes, depending on the desired final thickness and the size of the treated structure. The solution was subjected to 3-second pulses of 40 kHz ultrasound in purge mode every 15 seconds for 2 minutes. Ultrasound was then applied continuously for a subsequent 7 minutes. This step therefore lasted for 9 minutes. A bright gray metallic coating was subsequently observed on the sample. After being removed from the solution, the sample is thoroughly rinsed with deionized water and then immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The sample is then subjected to rapid thermal annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This process can be performed using a tube furnace or a hot plate.

[0177] Properties of metal deposits filling cavities After heat annealing of the specimens obtained at the end of step c2), it was observed that all through-holes were uniformly filled with a nickel-boron alloy of one thickness. The adhesion, measured according to standard ASTM 3359, was 16 / 16.

[0178] [Example] [5] [:] [Contains nickel] [-] [Generation of boron alloy and copper bit lines] The substrate is the same as in Example 4.

[0179] [Pretreatment of the cavity surface] [:] The substrate was processed in the same manner as part a) in Example 4.

[0180] [Activate cavity surface] [:] [b1] [)] [Preparation of Activation Solution] [:] [] The solution is the same as the solution prepared in Example 4b). [b2] [)] [Activation treatment of substrate surface] [:] [] The surface treatment is the same as that performed in b2) of Example 4. [Through electrodeless deposition] [NiB] [Metallic layer] [:] [] [(] [c1] [)] [Pre-preparation of electrodeless solution] [:] [] The solution is the same as the solution prepared in c1) of Example 4. [c2] [)] [Formed on a hybrid structure] [NiB] [Alloy Layer] [:] [] The surface treatment is the same as that performed in c2) of Example 4. However, by shortening the process time or adjusting the additive concentration according to the knowledge of those skilled in this technique, the process is not performed completely, so that the NiB alloy bits are not completely filled. The remaining cavities are filled with copper in the following steps. [Using copper to fill the remaining cavities via an electrodeposition process] [] [d1] [)] [Electrodeposition solution] [:] [] In this solution, the concentration of Cu²⁺ is equal to 15 g / L obtained from CuSO₄(H₂O)₅. Ethylenediamine and copper exist in a stoichiometric ratio of 2. The pH of the solution was adjusted to 7.0 by adding tetraethylammonium hydroxide. Then, 50 ppm of thiodiacetic acid was introduced. [d2] [)] [equipment] [:] [] In this example, an electrodeposition apparatus consisting of two parts is used: a cell containing the electrodeposition solution, equipped with a fluid recirculation system to control the system's hydrodynamics; and a rotating electrode equipped with a sample holder suitable for the size of the sample used (4 cm × 4 cm). The electrodeposition cell has two electrodes: Copper anode

[0181] A silicon test piece coated with the layer described in c) above constitutes a cathode. The reference element is connected to the anode. The connector allows for electrical contact between the electrodes, which are connected by wires to a voltage regulator that supplies up to 20 V or 2 A. [d3] [)] [Experimental Protocol] [:] [] [Basic Steps] [:] [] If the substrate obtained in step c) is newly fabricated, it does not undergo any specific treatment. The sample prepared in step c) is first immersed in a beaker of deionized water, depending on the situation. The beaker is then rapidly evacuated to a vacuum sufficient to remove trapped air from the cavities of the structure. To perform this operation, the beaker is introduced into a desiccator connected to a paddle pump and subjected to a vacuum for approximately 2 minutes. After returning to ambient pressure, the sample is quickly mounted into a deposition unit immersed in the solution prepared in step d1). This assembly then undergoes an electrical process with a cold inlet. [Electrical process:] [] The process is performed as follows: The cathode is biased in a pulsed current mode within a current range of 5 mA (or 2 mA / cm²) to 50 mA (or 20 mA / cm²), for example, 20 mA (or 8 mA / cm²), where the pulse duration is between 5 and 1000 ms of cathode bias, and between two cathode pulses, there is a zero bias of 5 to 1000 ms. This step is performed at 60 rpm for 10 minutes. The contact between the electrolyte and the substrate is delayed by 30 seconds before energization. The sample is removed from the solution, thoroughly rinsed with deionized water, and immersed in a beaker containing deionized water and subjected to ultrasonic treatment (40 kHz) for 30 seconds. The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen flow.

[0182] [d4] [)] [annealing] [:]

[0183] The specimens were subjected to rapid thermal annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This operation can be performed using a tube furnace or a hot plate.

[0184] [Results obtained:]

[0185] Scanning electron microscopy analysis (Mag=100 k, EHT=2 kV) revealed copper fillers without interface or porosity defects. Adhesion measured according to standard ASTM 3359 was 16 / 16.

[0186] 1: Silicon dioxide / Sacrificial material / Sacrificial layer 1a: Covering layer / Dielectric layer 1b: Dielectric Block / Dielectric Material 1c: Contact dielectric layer / component 1d: Dielectric layer / component 1e: Dielectric / Dielectric Material 2: Insulating materials / insulating layers 3: Cavity / Horizontal Cavity 4: Silicon substrate / semiconductor substrate 5: Polysilicon Channels / Semiconductor Channels 6a: Dielectric ring 6b: Dielectric coating 7: Barrier Dielectric Layer 8: Charge storage material / charge storage region / charge storage layer 9: Tunneling dielectric layer 10: Alumina layer 20: Metal deposits / deposited metal / excess metal / nickel or cobalt alloys 20a: Word line / nickel or cobalt alloy layer 20b: Deposits / Nickel or Cobalt Alloy / Metallic Layer 20c: Sediments 21: Barrier material / barrier layer 22: Material porosity 23: Word lines / metal deposits 24: Word Line 25: Word Line 30: Vertical cavity 100: Central Area 200: Surrounding Area 201: Light and Shadow Mask 202: Cavity 203: Peripheral Contact Components 204: Barrier layer 205: Peripheral tungsten contacts 206: Peripheral contact parts 301: Light Shadow Mask 302a: Cavity 302b: Cavity 303a: Peripheral contact components 303b: Contacts 304a: Barrier material / barrier layer 304b: Barrier layer 305a: Tungsten contact / peripheral tungsten contact 305b: Metal contacts / Tungsten contacts 306: Contacts 403: Bitline 404: Copper diffusion barrier material / barrier layer 405: Copper / Copper Seed Layer 406: Copper Bit Line / Copper a: Size b: Size c: Size

Claims

1. A method for manufacturing 3D NAND memory, comprising at least one metallization process selectively metallizing an inorganic oxide surface in a solvent phase, the metallization process being performed by forming a metal alloy deposit of nickel or cobalt having elements selected from boron, phosphorus, and tungsten, and the metallization process comprising: a step of activating the inorganic oxide surface with a noble metal, the activation step being followed by: a step of contacting the inorganic oxide surface with an electrodeless solution without polarization to form the metal alloy deposit, the electrodeless solution comprising: metal ions, the metal ions being nickel ions or cobalt ions; at least two reducing agents for the metal ions comprising at least one member selected from boron, phosphorus, or tungsten; a stabilizer in an amount sufficient to misalign the metal ions; a poly(ethylene ethyleneimine) having a number average molecular weight (Mn) between 500 g / mol and 700 g / mol; and an aliphatic polyamine having a molecular weight of less than 500 g / mol, wherein the aliphatic polyamine comprises diallyltriamine.

2. The method of claim 1, wherein the step of contacting the inorganic oxide surface with the electrodeless solution is performed by subjecting the inorganic oxide surface to ultrasound.

3. The method of claim 1 or 2, wherein the element selected from boron, phosphorus and tungsten accounts for a percentage of the metal alloy between 1 atomic percentage and 10 atomic percentage.

4. The method of claim 1 or 2, wherein the inorganic oxide is SiO2 or Al2O3.

5. The method of claim 1 or 2, wherein the precious metal is palladium.

6. A 3D NAND memory device comprising word lines, bit lines, polysilicon channels, contacts between the polysilicon channels and the bit lines, and peripheral contacts between the word lines and the source lines, characterized in that the memory device further comprises at least one metal alloy deposit comprising a metal of nickel or cobalt and an element selected from boron, phosphorus and tungsten, and is obtained by the method of any one of claims 1 to 5.

7. The 3D NAND memory device of claim 6, wherein the word lines comprise the at least one metal alloy deposit.

8. The 3D NAND memory device of claim 6 or 7, wherein the contacts between the polysilicon channels and the bit lines comprise the at least one metal alloy deposit.

9. A 3D NAND memory device as claimed in claim 6 or 7, wherein the equibit line comprises the at least one metal alloy deposit.

10. The 3D NAND memory device of claim 6 or 7, wherein the peripheral contacts between the word lines and the source lines comprise the at least one metal alloy deposit.

11. An electrolyte for manufacturing a 3D NAND memory device, comprising: metal ions, wherein the metal ions comprise at least one metal salt of nickel or cobalt, and the concentration of the metal ions is between 10⁻³ M and 1 M; at least two reducing agents for the metal ions, the total amount of which is between 400 mM and 550 mM; a stabilizer used in an amount sufficient to cause the metal ions to misculate; a reagent for adjusting and maintaining the pH value between 6 and 11; a poly(ethylene ethyleneimine) having a number average molecular weight (Mn) between 500 g / mol and 700 g / mol; and an aliphatic polyamine having a molecular weight of less than 500 g / mol, wherein the aliphatic polyamine comprises diallyltriamine.

12. The electrolyte of claim 11, wherein the two reducing agents are hypophosphoric acid and dimethylaminoborane.

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