Semiconductor structure, semiconductor device and method of forming the same

Abstract

A method of forming a semiconductor device includes: attaching a first local interconnect element to a first substrate using a first adhesive; forming a first rewiring structure on a first side of the first local interconnect element; and removing the first local interconnect element and the first rewiring structure from the first substrate and attaching the first rewiring structure to a second substrate. The method further includes: removing the first adhesive from the first local interconnect element and forming an interconnect structure on a second side of the first local interconnect element and a first encapsulation, wherein the second side is opposite to the first side. A first conductive feature of the interconnect structure is physically coupled and electrically coupled to a second conductive feature of the first local interconnect element.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming a semiconductor device. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integrated density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, these improvements in integrated density stem from the iterative reduction in the minimum feature size, allowing more components to be integrated into a given area. With the increasing demand for miniaturized electronic devices, there has been a need for smaller and more innovative semiconductor die packaging technologies. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the Invention

[0003] This disclosure describes a method for creating a semiconductor device, the method comprising the following steps: forming a first through-hole and a second through-hole on a first substrate; attaching a first local interconnect element to the first substrate, the first local interconnect element being disposed between the first through-hole and the second through-hole, the first local interconnect element being attached to the first substrate using a first adhesive; encapsulating the first local interconnect element, the first through-hole, and the second through-hole using a first encapsulation body; removing the top portion of the first encapsulation body and the top portion of the first local interconnect element; forming a first rewiring structure on a first side of the first local interconnect element, the first through-hole, the second through-hole, and the first encapsulation body; removing the first local interconnect element, the first encapsulation body, the first through-hole, the second through-hole, and the first rewiring structure from the first substrate and attaching the first rewiring structure to a second substrate; removing the first adhesive from the first local interconnect element. An interconnect structure is formed on the second side of the first local interconnect element, the first through hole, the second through hole, and the first encapsulation body. The second side is opposite to the first interconnect structure. The first conductive feature of the interconnect structure is physically coupled and electrically coupled to the second conductive feature of the first local interconnect element.

[0004] This disclosure describes a method for using a semiconductor device, the method comprising the following steps: Forming a first plurality of redistribution layers on a first substrate, the first plurality of redistribution layers including a first plurality of conductive pads exposed on the top surface of the first plurality of redistribution layers. Forming an adhesive on the first plurality of redistribution layers. Monomerizing the first substrate, the first plurality of redistribution layers, and the adhesive into a plurality of local interconnect elements, a first local interconnect element comprising: a monomerized portion of the first substrate; a monomerized portion of the first plurality of redistribution layers located on the monomerized portion of the first substrate; a first conductive pad and a second conductive pad of the first plurality of conductive pads extending to the top surface of the monomerized portion of the first plurality of redistribution layers; and a monomerized portion of the adhesive covering the monomerized portion of the first plurality of redistribution layers. Attaching the first local interconnect element to a second substrate. Encapsulating the first local interconnect element using a first encapsulation body. Removing the top portion of the first encapsulation body and removing the monomerized portion of the first substrate from the first local interconnect element. A first rewiring structure is formed on a first side of a first local interconnect element and on a first encapsulation. The first local interconnect element, the first encapsulation, and the first rewiring structure are removed from a second substrate, and the first rewiring structure is attached to a third substrate. Monomerized portions of the adhesive are removed to expose a first conductive pad and a second conductive pad. A second rewiring structure is formed on a second side of the first local interconnect element and on the first encapsulation, with the second side opposite to the first side. The second rewiring structure includes a third conductive pad and a fourth conductive pad, with the third conductive pad bonded to the first conductive pad and the fourth conductive pad bonded to the second conductive pad.

[0005] This disclosure describes a semiconductor structure including a first redistribution structure, local interconnect elements, and a first interconnect structure. The first redistribution structure includes a first dielectric layer and a first plurality of conductive features. Local interconnect elements are disposed on the first redistribution structure, with sidewalls of the local interconnect elements surrounded by bottom filler adhesive. The local interconnect elements include a first plurality of redistribution layers. The first plurality of redistribution layers include a second plurality of conductive features, a third plurality of conductive features, and a fourth plurality of conductive features. The second plurality of conductive features are located on a first side of the local interconnect element, the first side being in contact with the first redistribution structure. Each of the first plurality of conductive features is in-situ coupled and electrically coupled to a corresponding conductive feature among the second plurality of conductive features. The third plurality of conductive features and the fourth plurality of conductive features are located on a second side of the local interconnect element opposite to the first side. The first interconnect structure is located on the second side of the local interconnect element, and the first interconnect structure includes a fifth plurality of conductive features and a sixth plurality of conductive features. Each of the third plurality of conductive features is coupled to a corresponding conductive feature among the fifth plurality of conductive features, and each of the fourth plurality of conductive features is coupled to a corresponding conductive feature among the sixth plurality of conductive features. Simple Explanation of the Diagram

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 shows a cross-sectional view of a packaged element according to some embodiments. Figure 2 shows a detailed view of a portion of the cross-sectional view shown in Figure 1 according to some embodiments. Figure 3 shows a plan view of a packaged element according to some embodiments. Figures 4 to 11 show cross-sectional views of intermediate steps during the process of forming local interconnect elements according to some embodiments. Figures 12 to 24 and 27 to 30 show cross-sectional views of intermediate steps during the process of forming packaged elements according to some embodiments. Figure 25 shows a plan view of the layout of the packaging area on a wafer substrate according to some embodiments. Figure 26 shows a plan view of the layout of the encapsulation area on the panel substrate according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0009] The embodiments discussed herein can be described in a specific context (i.e., a packaged element comprising one or more integrated circuit dies). In some embodiments, the packaged assembly is a system-on-integrated-substrate (SoIS) package. The packaged element includes a double-sided local interconnect component embedded in a redistribution structure. The embedded double-sided local interconnect component can increase the communication bandwidth between the integrated circuit die and other bonded packages (e.g., a core substrate), which can be useful for high-performance computing. Forming the double-sided local interconnect component without adhesives (e.g., die attach film, DAF) allows for a wider reliability window. During the fabrication of packaged components, the use of adhesives (such as die-attach film (DAF)) to bond local interconnect components to a carrier substrate allows for the avoidance of solder joint attachment processes (including, for example, forming microbumps on the local interconnect components and microbump pads on the carrier substrate). This simplifies the process flow, increases throughput, and reduces crack formation caused by the subsequent removal of microbumps and microbump pads. The higher reliability and improved electrical performance resulting from lower contact resistance are at least partly attributable to the solderless connection between the embedded bilateral local interconnect components and the redistribution structure. By eliminating solder connections in the final structure, electromigration problems associated with solder joints are reduced.

[0010] The redistribution structure connects to the integrated circuit die and provides electrical connections between the integrated circuit die and the core substrate and / or between integrated circuit dies. The core substrate is additionally connected to a set of external conductive features. In this way, the integrated circuit die is electrically connected to the core substrate and ultimately electrically connected to the external conductive features through the core substrate and the redistribution structure.

[0011] According to some embodiments, redistribution structures, embedded dual-sided local interconnects, core substrates, and integrated circuit dies can be fabricated and tested separately before the completed packaged components are assembled. This can further improve component and board-level reliability.

[0012] Due to the increased communication bandwidth between integrated circuit dies provided by the dual-sided local interconnect elements, no interposer is required between the integrated circuit die and the redistribution structure. Eliminating the need for an interposer reduces wafer-package interaction issues, thus widening the reliability window. Warpage mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and redistribution structure) is reduced because the coefficient of thermal expansion (CTE) mismatch between the two package structures is reduced.

[0013] Figure 1 shows a cross-sectional view of a monolithic package element 100 according to some embodiments. Figure 2 shows a detailed view of region 1000 of the cross-sectional view shown in Figure 1 according to some embodiments. The monolithic package element 100 includes a plurality of integrated circuit dies, a rewiring structure 200 having one or more rewiring layers, a core substrate 300, external connectors 620, and other components. An integrated circuit die may include one or more dies, such as logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In some embodiments, a semiconductor device may be an integrated circuit die.

[0014] As shown in the figure, for illustrative purposes, the plurality of integrated circuit dies include one or more logic dies 512, one or more memory dies 514, and one or more input / output (I / O) dies 516 (not shown in Figure 1, but see Figure 3). The integrated circuit dies may be formed in one or more wafers, which may include different device regions that are individualized in subsequent steps. The integrated circuit dies may be packaged together with other similar or different integrated circuit dies using known manufacturing techniques.

[0015] In some embodiments, one or more of the integrated circuit dies 512, 514, and 516 may be a stacked device comprising multiple semiconductor substrates. For example, memory die 514 may be a memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In this embodiment, memory die 514 includes multiple semiconductor substrates interconnected via through-substrate vias (TSVs). Each of the semiconductor substrates may (or may not) have interconnect structures. Encapsulation 520 may surround integrated circuit dies 512, 514, and 516.

[0016] Dies 512, 514, and 516 have bonding pads 518 that are bonded to conductive connector 188. In some embodiments, bonding pads 518 are made of conductive material and may resemble conductive lines described below (see, for example, conductive line 110).

[0017] The conductive connector 188 provides an electrical connection between the redistribution structure 200 and the integrated circuit chips 512, 514, and 516. It may also include an underfill adhesive 610 to securely bond the integrated circuit chips 512, 514, and 516 to the redistribution structure 200 and provide structural support and environmental protection.

[0018] As discussed in more detail below, the redistribution structure 200 provides electrical paths and connections between integrated circuit dies 512, 514, and 516 and the core substrate 300 via conductive connectors 390. In some embodiments, the redistribution structure 200 has one or more redistribution layers, the one or more redistribution layers including: a metallization pattern including, for example, conductive lines 92 and 110 and vias 94, 106, 112, and 116; and dielectric layers 90, 108, and 114 located on the top and bottom sides of the conductive lines 92 and 110. The conductive lines 92 and 110 and the vias 94, 106, 112, and 116 are electrically coupled to the integrated circuit dies 512, 514, and 516.

[0019] As discussed in more detail below, the redistribution structure 200 includes one or more local interconnect elements 120. The local interconnect elements 120 provide electrical wiring and connections between integrated circuit dies 512, 514, and 516 and may be referred to as interconnect dies 120 or local interconnect structure 120. As shown in Figures 1 and 2, the conductive features 236 of the local interconnect elements 120 are physically coupled and electrically coupled to the vias 112 of the redistribution structure 200 in a solderless manner, which reduces electrical migration issues associated with solder joints. The local interconnect elements 120 increase the communication bandwidth between integrated circuit dies 512 to 516 while maintaining low contact resistance and high reliability. The low contact resistance and high reliability are at least partly due to the solderless connection between the embedded local interconnect elements 120 and the redistribution structure 200.

[0020] Due to the increased communication bandwidth between integrated circuit dies provided by local interconnect elements, no interposer layer is required between the integrated circuit die and the redistribution structure. By eliminating the need for an interposer layer, warpage mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and the redistribution structure) is reduced, due to a reduction in the coefficient of thermal expansion (CTE) mismatch between the two package structures.

[0021] Local interconnect element 120 is also electrically connected to core substrate 300 on its bottom side via conductive connector 390. Such dual-sided connections, such as those between integrated circuit chips 512, 514, and 516 and core substrate 300, can provide high-bandwidth communication with low resistance, which can increase signal and power integrity.

[0022] As discussed in more detail below, local interconnect element 120 may be encapsulated by encapsulation 420, also referred to as underfill 420, which may be formed of molding compound, epoxy resin, or the like, and may be applied by compression molding, transfer molding, or similar methods. Through-hole 118 may extend through encapsulation 420 adjacent to local interconnect element 120 and may be electrically coupled to conductive line 110 via via 116 extending through dielectric layer 114.

[0023] As discussed in more detail below, local interconnect element 120, via 118, and encapsulation 420 may be disposed on one or more redistribution layers, said one or more redistribution layers including: a metallized pattern including, for example, conductive lines 208 and vias 202, 204, and 212; and dielectric layers 206 and 210 located on the top and bottom sides of the conductive lines 208. The via 118 may be physically and electrically coupled to the via 204 on the bottom side. Conductive connectors 122 (e.g., metal pillars, such as copper pillars) on the bottom side of the local interconnect element 120 may be coupled to the via 202 by metal-to-metal bonding (e.g., copper-to-copper bonding). In some embodiments, the local interconnect element 120 is coupled to the via 202 and dielectric layer 206 by a hybrid bonding.

[0024] Vias 202 and 204 are electrically coupled to conductive line 208, and conductive line 208 is electrically coupled to via 212 extending to the bottom surface of dielectric layer 210. Conductive pad 214 located on the bottom side of redistribution structure 200 is electrically coupled to via 212.

[0025] The redistribution structure 200 can be electrically and mechanically bonded to the core substrate 300. The core substrate 300 may include: a central core body 310, through which a via 320 extends; and additional selective redistribution structures 340 extending on opposite sides of the central core body 310. Generally, the core substrate 300 provides structural support for component packages and provides electrical signal routing between integrated circuit packages and external connectors 620, which may be physically and electrically coupled to conductive pads 214.

[0026] Encapsulation 520 may be included between redistribution structure 200 and core substrate 300 to securely bond associated components and provide structural support and environmental protection. Encapsulation 520 may be formed of or contain organic materials such as molding compounds, molding underfill adhesives, epoxy resins, resins, or the like.

[0027] Figure 3 shows a plan view of a packaged element according to some embodiments. The embodiment shown in Figure 3 includes two logic dies 512, four memory dies 514, two I / O dies 516, and seven local interconnect elements 120. In this embodiment, the first logic die 512 is connected to the first memory die 514 via a first local interconnect element 120 (see above, Figures 1 and 2), the first logic die 512 is connected to the second memory die 514 via a second local interconnect element 120, the first logic die 512 is connected to the third memory die 514 via a third local interconnect element 120, and the first logic die 512 is connected to the fourth memory die 514 via a fourth local interconnect element 120. The second logic die 512 is connected to the first I / O die 516 via a fifth local interconnect element 120, and the second logic die 512 is connected to the second I / O die 516 via a sixth local interconnect element 120. Additionally, the first logic die 512 and the second logic die 512 are connected together via a seventh local interconnect element 120. In some embodiments, the logic dies 512 are connected to each other via a single local interconnect element 120, and other dies are connected to each other via a redistribution layer in the redistribution structure 200. Other embodiments may include more or fewer logic dies 512, memory dies 514, I / O dies 516, and local interconnect elements 120. In some embodiments, each of the integrated circuit dies is connected to each adjacent integrated circuit die via local interconnect elements.

[0028] Figures 4 through 11 illustrate the various intermediate stages of fabricating a local interconnect element (see Figure 10) according to some embodiments. For ease of illustration, the features are simplified in Figures 4 through 16.

[0029] Referring first to FIG4, a carrier substrate 102 is provided. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (e.g., a bulk semiconductor), or the like. The carrier substrate 102 may be a wafer, allowing multiple redistribution structures to be formed simultaneously on the carrier substrate 102. The carrier substrate 102 may comprise an active layer of doped or undoped silicon, or a semiconductor-on-insulator (SOI) substrate. The carrier substrate 102 may comprise: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the carrier substrate 102 may be made of ceramic materials, polymer films, magnetic materials, the like, or combinations thereof. Other substrates (e.g., multilayer substrates or gradient substrates) may also be used. The carrier substrate 102 has an active surface (e.g., the upward-facing surface in FIG4) (sometimes referred to as the front side) and a non-active surface (e.g., the downward-facing surface in FIG4) (sometimes referred to as the rear side).

[0030] In Figure 5, a dielectric layer 222 can be formed on a carrier substrate 102. The bottom surface of the dielectric layer 222 can contact the top surface of the carrier substrate 102. The dielectric layer 222 can be formed from polyimide, photo-imageable dielectric (PID), prepreg, Ajinomoto build-up film (ABF), resin coated copper (RCC), molding compound, molding film, epoxy resin, or the like, and can be applied by compression molding, transfer molding, combinations thereof, or similar molding. The dielectric layer 222 can be formed by any acceptable deposition process (e.g., spin coating, chemical vapor deposition (CVD), lamination, similar processes, or combinations thereof).

[0031] In some embodiments, dielectric layer 222 has a thickness ranging from 0.5 μm to 30 μm (e.g., 4 μm). A dielectric layer 222 with a thickness ranging from 0.5 μm to 30 μm may be useful because it can be advantageous for interconnect impedance control. A dielectric layer 222 with a thickness less than 0.5 μm may be disadvantageous because it can lead to lower reliability and a higher risk of yield loss. A dielectric layer 222 with a thickness greater than 30 μm may be disadvantageous because it can cause impedance control mismatch in the serializer / deserializer (SerDes).

[0032] In Figure 6, the dielectric layer 222 is then patterned to form an opening 224 that exposes a portion of the top surface of the carrier substrate 102. Patterning can be performed using acceptable processes, such as lithography processes that expose the dielectric layer 222 to light when it is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 222 is a photosensitive material, it can be developed after exposure.

[0033] In Figure 7, the metallization pattern includes conductive elements, such as conductive lines 226 extending along the main surface of dielectric layer 222 and conductive connectors 122 extending through dielectric layer 222 to fill opening 224. As an example of forming the metallization pattern, a seed layer extending through dielectric layer 222 is formed on dielectric layer 222 and in opening 224. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on top of the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or similar processes. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or similar processes, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive lines 226 of the metallization pattern. The patterning step forms openings through the photoresist to expose the seed layer. Next, a conductive material is formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating, electroless plating, or similar plating). The conductive material may include metals (such as copper, titanium, tungsten, aluminum, or the like). The combination of the conductive material and the portion below the seed layer forms a conductive connector 122 (e.g., a metal pillar (e.g., a copper pillar)) and conductive lines 226 of a metallized pattern. The portion of the photoresist and seed layer above which no conductive material is formed is removed. The photoresist can be removed by an acceptable ashing process or stripping process (e.g., using oxygen plasma or similar methods). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by an acceptable etching process (e.g., by wet etching or dry etching).

[0034] In some embodiments, the conductive connector 122 has a width ranging from 2 μm to 35 μm, which may be useful for providing lower interconnect resistance. A conductive connector 122 with a width less than 2 μm may be disadvantageous as it may result in higher resistance and a worse reliability window. A conductive connector 122 with a width greater than 35 μm may be disadvantageous as it may result in undesirable dense wiring.

[0035] In some embodiments, the conductive connector 122 has a height ranging from 2 μm to 30 μm, which may be useful for providing lower interconnect resistance. A conductive connector 122 with a height less than 2 μm may be disadvantageous as it may lead to yield losses due to leakage. A conductive connector 122 with a height greater than 30 μm may be disadvantageous as it may lead to a worse reliability window.

[0036] In some embodiments, the conductive line 226 has a thickness in the range of 0.5 μm to 10 μm (e.g., 2 μm). A conductive line 226 with a thickness in the range of 0.5 μm to 10 μm can be used to provide lower interconnect resistance. A conductive line 226 with a thickness less than 0.5 μm may be disadvantageous as it may lead to increased interconnect resistance. A conductive line 226 with a thickness greater than 10 μm may be disadvantageous as it may lead to yield loss due to insufficient etching.

[0037] In some embodiments, the conductive lines 226 have a spacing between adjacent conductive lines 226 in the range of 0.5 μm to 10 μm (e.g., 2 μm). Conductive lines 226 with a spacing in the range of 0.5 μm to 10 μm may be useful for improving wiring performance. Conductive lines 226 with a spacing less than 0.5 μm may be disadvantageous as it may cause yield loss due to short circuits within the redistribution layer. Conductive lines 226 with a spacing greater than 10 μm may be disadvantageous as it may result in poorer wiring density.

[0038] In some embodiments, the conductive line 226 has a width in the range of 0.5 μm to 10 μm (e.g., 2 μm). A conductive line 226 with a width in the range of 0.5 μm to 10 μm can be used to provide lower interconnect resistance. A conductive line 226 with a width less than 0.5 μm may be disadvantageous as it may lead to increased interconnect resistance. A conductive line 226 with a width greater than 10 μm may be disadvantageous as it may lead to poorer wiring density.

[0039] In Figure 8, a via 228 is formed on the conductive line 226. As an example of forming the via 228, a photoresist is formed on the structure and patterned. The photoresist can be formed by spin coating or a similar process and can be exposed to light for patterning. The patterning step forms an opening through the photoresist to expose the conductive line 226, wherein the opening in the photoresist corresponds to the via 228. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the conductive line 226. The conductive material can be formed by plating (e.g., electroplating or electroless plating, or similar plating). The conductive material may include metals (such as copper, titanium, tungsten, aluminum, or the like). The conductive material forms the via 106. The portion of the photoresist and seed layer above which no conductive material is formed is removed. The photoresist can be removed by an acceptable ashing process or stripping process (e.g., using oxygen plasma or a similar method). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, using an acceptable etching process (e.g., by wet etching or dry etching).

[0040] In some embodiments, via 228 has a width in the range of 2 μm to 55 μm (e.g., 7 μm). A via 228 with a width in the range of 2 μm to 55 μm can be used to provide lower interconnect resistance. A via 228 with a width less than 2 μm may be disadvantageous as it may lead to increased interconnect resistance. A via 228 with a width greater than 55 μm may be disadvantageous as it may lead to poorer wiring density.

[0041] In some embodiments, the via 228 has a height ranging from 0.5 μm to 30 μm (e.g., 4 μm). A via 228 with a height ranging from 0.5 μm to 30 μm can be used to improve wiring capabilities. A via 228 with a height less than 0.5 μm may be disadvantageous as it may lead to yield losses due to leakage. A via 228 with a height greater than 30 μm may be disadvantageous as it may lead to a worse reliability window.

[0042] In Figure 9, a redistribution structure 220 is fabricated by forming additional redistribution layers on dielectric layer 222 and conductive lines 226. These additional redistribution layers include dielectric layers and embedded metallized patterns, including conductive lines and vias. In some embodiments, the additional dielectric material may have the same material composition and dimensions as dielectric layer 222. In other embodiments, the redistribution structure comprises a mixed dielectric, wherein some of the additional dielectric layers may have compositions different from dielectric layer 222 and different from each other. As an example, dielectric layer 222 may comprise a polymer (e.g., polyimide) and dielectric layer 234 may comprise a molding compound or a molding film. For example, in some embodiments, alternating dielectric layers are polyimide and molding compounds.

[0043] Conductive lines and vias are arranged such that the redistribution structure 220 can subsequently be individualized into local interconnect elements (see Figures 10-11 below). In the illustrated embodiment, five redistribution layers are formed in the redistribution structure 220, but any suitable number of redistribution layers can be formed, such as two to ten. Dielectric layers, conductive lines, and vias can be formed using methods and materials similar to those used for dielectric layer 222, conductive connector 122, and conductive lines 226. Metallization patterns are formed such that vias 236 extending to the top surface of dielectric layer 234 (on the top surface of redistribution structure 220) are electrically coupled to adjacent vias 236 (also referred to as conductive connectors 236 or conductive pads 236) and conductive connectors 122 extending to the bottom side of redistribution structure 220. In some embodiments, conductive connectors 236 are conductive pads comprising metal (e.g., copper).

[0044] In some embodiments, the conductive connector 236 has a height ranging from 2 μm to 30 μm, which may be useful for improving wiring capabilities. A conductive connector 236 with a height less than 2 μm may be disadvantageous as it may lead to yield loss due to trace cracking. A conductive connector 236 with a height greater than 30 μm may be disadvantageous as it may lead to yield loss due to insufficient etching.

[0045] In some embodiments, adjacent conductive connectors 236 are spaced apart with a pitch ranging from 20 μm to 80 μm, which may be useful for improving wiring capability. Spaced apart adjacent conductive connectors 236 with a pitch less than 20 μm may be disadvantageous, as this could lead to worse reliability. Spaced apart adjacent conductive connectors 236 with a pitch greater than 80 μm may be disadvantageous, as this could lead to worse wiring density.

[0046] In Figure 10, adhesive 280 is formed on the redistribution structure 220. Adhesive 280 can then be used to bond individual local interconnect elements to a carrier substrate (see Figure 12 below). Bonding local interconnect elements to the carrier substrate using adhesive 280 avoids the formation of microbumps on the local interconnect elements and microbump pads on the carrier substrate, which is required for solder joint bonding processes. This simplifies the process flow and increases throughput. Adhesive 280 can be any suitable adhesive, epoxy resin, die bond film (DAF), or the like. In some embodiments, adhesive 280 has a thickness ranging from 5 μm to 100 μm (e.g., 25 μm).

[0047] Further, in Figure 10, a unitization process is performed by sawing along the cutting path 250. The sawing unitizes the redistribution structure 220 to form a plurality of unitized local interconnect elements 120 (see below, Figure 10).

[0048] Figure 11 illustrates a monolithic local interconnect element 120, also referred to as local interconnect element 120 or local interconnect structure 120. In the illustrated embodiment, local interconnect element 120 has five redistribution layers. In other embodiments, local interconnect element 120 may have two to ten redistribution layers. The first redistribution layer of the illustrated local interconnect element 120 (including dielectric layer 222 and conductive connector 122) is located on the top surface of the remainder of the carrier substrate 102. The conductive connector 122 extends through dielectric layer 222 to the top surface of the remainder of the carrier substrate 102 and is electrically coupled to conductive line 226. The conductive connector 122 can then be used to couple to other elements (e.g., core substrate 300 (see above, Figures 1 and 2)). The conductive line 226 is coupled to conductive line 232 in the top redistribution layer of the local interconnect element 120 via intermediate conductive features (e.g., additional vias and wires). Conductive line 232 can be coupled to via 236, which can then be used to couple integrated circuit dies 512, 514, and 516 to each other and to other components (e.g., core substrate 300 (see above, Figures 1 and 2)). The interconnection of integrated circuit dies 512, 514, and 516 with each other and with both sides of the core substrate 300 via local interconnect element 120 increases the communication bandwidth between integrated circuit dies while maintaining low contact resistance and high reliability, thus achieving high signal integrity and power integrity.

[0049] In some embodiments, the local interconnect element 120 has a horizontal width ranging from 2 mm to 50 mm and a horizontal length ranging from 3 mm to 80 mm. The thickness of the monolithized portion of the carrier substrate may range from 2 mm to 31 mm (e.g., 18 mm).

[0050] Figures 12 through 30 illustrate the various intermediate stages of fabricating a redistribution structure 200 (see Figure 20) according to some embodiments. A first package region 101A and a second package region 101B are shown, each of which is ultimately monolithized from the other package regions. For ease of illustration, the features are simplified in Figures 12 through 30.

[0051] Referring first to Figure 12, a carrier substrate 702 is provided. The carrier substrate 702 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 702 may be a wafer, allowing multiple redistribution structures to be formed simultaneously on the carrier substrate 702. The carrier substrate 702 may have a release layer (not shown) on its top surface. The release layer may be formed of a polymeric material and may be removed along with the carrier substrate 702 from an overlay structure to be formed in a subsequent step. In some embodiments, the release layer is an epoxy resin-based heat-release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer may be a UV (UV) adhesive that loses its adhesive properties when exposed to ultraviolet (UV) light. The release layer may be dispensed as a liquid and cured, and may be a laminated film laminated onto the carrier substrate 702, or the like. The top surface of the release layer can be flush and flat within the process variations.

[0052] In Figure 13, a through-hole 118 is formed on a carrier substrate 702. The through-hole 118 is also referred to as a through molding via (TMV) 118. As an example of forming the through-hole 118, a seed layer (not shown) is formed on the carrier substrate 702. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer on top of the titanium layer. The seed layer can be formed using, for example, PVD or similar processes. A photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or similar processes and can be exposed to light for patterning. The pattern of the photoresist corresponds to a via. The patterning step forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating, or similar plating). The conductive material may include metals (such as copper, titanium, tungsten, aluminum, or the like). The portion of the photoresist and seed layer above which no conductive material is formed is removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma or similar methods). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by an acceptable etching process (e.g., by wet or dry etching). The remaining portion of the seed layer and the conductive material form the via 118.

[0053] In Figure 14, local interconnect element 120 is attached to carrier substrate 702. Local interconnect element 120 can be placed on carrier substrate 702 using a pick and place process or another suitable process, and the local interconnect element 120 is bonded to a release layer (not shown) of carrier substrate 702 using adhesive 280 with, for example, a pick and place tool. Using adhesive 280 to attach local interconnect element 120 to carrier substrate 702 allows for the avoidance of solder joint bonding processes (e.g., forming microbumps on local interconnect element 120 and microbump pads on carrier substrate 102), which simplifies the process flow, increases throughput, and reduces crack formation caused by subsequent removal of microbumps and microbump pads.

[0054] In Figure 15, according to some embodiments, an encapsulation 420 is formed on and around the perforation 118 and the local interconnect element 120. The encapsulation 420 encapsulates the local interconnect element 120 and the perforation 118. In some embodiments, the encapsulation 420 may be formed from prepreg, Ajinomoto laminate (ABF), resin-coated copper (RCC), molding compound, photosensitive dielectric (PID), epoxy resin, epoxy molding compound, dispensing molding underfill, or the like, and may be applied by compression molding, transfer molding, or similar molding. The encapsulation may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulation 420 is formed on a carrier substrate 702 such that the perforation 118 and the local interconnect element 120 are buried or covered.

[0055] In Figure 16, a planarization process is performed to remove the top portion of the encapsulation 420 and the substrate 102 of the local interconnect element 120, thereby exposing the through-hole 118 and the conductive connector 122 of the local interconnect element 120. Following the planarization process, within a process variation, the topmost surface of the encapsulation 420, the topmost surface of the through-hole 118, and the topmost surface of the conductive connector 122 of the local interconnect element 120 (see above, Figure 10) are flush (e.g., flat). The planarization process can be, for example, abrasive grinding or chemical-mechanical polishing (CMP). In some embodiments, the encapsulation 420 may comprise other materials, such as silicon oxide, silicon nitride, or the like.

[0056] Local interconnect elements 120 provide electrical connections between subsequently bonded integrated circuit dies (e.g., 512, 514, and 516) and other components (e.g., core substrate 300). The embedded local interconnect elements 120 can increase the communication bandwidth between the integrated circuit dies and the core substrate 300 while maintaining low contact resistance and high reliability. In some embodiments, other components (e.g., integrated voltage regulators (IVRs), integrated passive devices (IPDs), static random access memory, the like, or combinations thereof) can also be embedded in a similar manner to the embedded local interconnect elements.

[0057] Figures 17A and 17B show a redistribution structure 270 (also referred to as interconnect structure 270 or backside redistribution structure 270) formed over the encapsulation 420, through-hole 118, and local interconnect element 120. Figure 17B shows a detailed cross-sectional view of region 1002 shown in Figure 17A. Although the backside redistribution structure 270 with six redistribution layers is shown according to the embodiment shown in Figures 17A and 17B, any suitable number of redistribution layers can be formed, for example, from one to twenty redistribution layers. The redistribution structure 270 can be used to couple the through-hole 118 and local interconnect element 120 to subsequently bonded elements (e.g., such as core substrate 300 (see above, Figures 1 and 2)).

[0058] The redistribution structure 270 may have a bottom redistribution layer 260 formed over and in contact with the encapsulation 420, the through-hole 118, and the local interconnect element 120. The bottom redistribution layer 260 includes a dielectric layer 206 and vias 202 and 204 extending through the dielectric layer 206 to couple conductive connections 122 and 118 of the local interconnect element 120, respectively. The dielectric layer 206 may be formed over the encapsulation 420, the through-hole 118, and the local interconnect element 120. In some embodiments, the dielectric layer 108 is formed from a polymer (e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like). In other embodiments, the dielectric layer 206 is formed of: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 206 can be formed by any acceptable deposition process (e.g., spin coating, CVD, lamination, similar processes, or combinations thereof).

[0059] In some embodiments, vias 202 and 204 are formed using a damascene process. In this process, photolithography is used to pattern and etch the dielectric layer 206 to form trenches corresponding to the desired pattern of the vias, for example, on the conductive connectors 122 of the through-hole 118 and the local interconnect element 120. Selective diffusion barrier layers and / or selective adhesive layers may be deposited, and conductive materials may be used to fill the trenches. Suitable materials for the barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, or other alternatives, and suitable materials for the conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In embodiments, vias 202 and 204 can be formed by depositing a seed layer of copper or a copper alloy and filling the trenches using electroplating. Chemical mechanical planarization (CMP) or similar processes can be used to remove excess conductive material from the surface of the dielectric layer 206 and planarize the surface for subsequent processing.

[0060] Referring again to Figures 17A and 17B, a redistribution layer 262 is formed on the redistribution layer 260. The redistribution layer 262 includes conductive features, such as conductive lines 208 and vias 212 embedded in the dielectric layer 210. The conductive lines 208 and vias 212 can couple vias 202 and 204 to subsequently bonded components (e.g., such as the core substrate 300 (see above, Figures 1 and 2)).

[0061] As an example of forming redistribution layer 262, a seed layer is formed over dielectric layer 206 and vias 202 and 204. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD or similar processes. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or similar processes and can be exposed to light for patterning. The pattern of the photoresist corresponds to conductive lines 208. The patterning step forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating, or similar plating). The conductive material may include metals (such as copper, titanium, tungsten, aluminum, or the like). The combination of the conductive material and the portion below the seed layer forms conductive lines 208. Remove the portion of the photoresist and seed layer above which no conductive material has been formed. The photoresist can be removed by an acceptable ashing process or stripping process (e.g., using oxygen plasma or similar methods). Once the photoresist has been removed, the exposed portion of the seed layer is removed, for example, by an acceptable etching process (e.g., by wet etching or dry etching).

[0062] Referring again to Figures 17A and 17B, a via 212 is formed on the conductive line 208 and extends from the conductive line 208. As an example of forming the via 212, a photoresist is formed on the conductive line 208 and patterned. The photoresist can be formed by spin coating or a similar process and can be exposed to light for patterning. The patterning step forms an opening through the photoresist to expose the conductive line 208, wherein the opening in the photoresist corresponds to the via 212. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the conductive line 208. The conductive material can be formed by plating (e.g., electroplating or electroless plating, or similar plating). The conductive material may include metals (such as copper, titanium, tungsten, aluminum, or the like). The conductive material forms the via 212. The photoresist is then removed. The photoresist can be removed by an acceptable ashing process or stripping process (e.g., using oxygen plasma or similar methods). In some embodiments, the via 212 has a width in the range of 2 μm to 100 μm (e.g., 30 μm).

[0063] Referring further to Figures 17A and 17B, according to some embodiments, a dielectric layer 210 is formed on and around the conductive line 208 and the via 212. After formation, the dielectric layer 210 surrounds the via 212 and the conductive line 208. The dielectric layer 210 and the metallization pattern (including the via 212 and the conductive line 208) form a redistribution layer 262. In some embodiments, the dielectric layer 210 is formed of a polymer (e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like). In other embodiments, the dielectric layer 210 is formed of: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 210 can be formed by any acceptable deposition process (e.g., spin coating, CVD, lamination, similar processes, or combinations thereof). In some other embodiments, the dielectric layer 210 can be formed from prepreg, Ajinomoto laminate (ABF), resin-coated copper (RCC), molding compound, polyimide, photosensitive dielectric (PID), epoxy resin, epoxy molding compound, or the like, and can be applied by compression molding, transfer molding, or similar molding. The dielectric material can be applied in a liquid or semi-liquid form and then subsequently cured to form the dielectric layer 210.

[0064] In some embodiments, a dielectric layer 210 is formed over a dielectric layer 206, such that the conductive lines 208 and vias 212 are buried or covered, and then a planarization process is performed on the dielectric layer 210 to expose the vias 212. Following the planarization process, within a process variation, the topmost surface of the dielectric layer 210 is flush with (e.g., planar) the topmost surface of the vias 212. The planarization process may be, for example, CMP.

[0065] Additional redistribution layers of the redistribution structure 270 can be formed on redistribution layer 262 using the same methods and materials described above for redistribution layer 262. Any of the materials described above for dielectric layer 210 can be used to form the dielectric layer of the additional redistribution layers. In some embodiments, some additional dielectric layers are formed using a polymer (e.g., polyimide) and some additional dielectric layers are formed using a molding compound. In some embodiments according to FIG. 17B, redistribution layer 270A (including redistribution layer 262) includes a dielectric layer formed using a molding compound, and redistribution layer 270B includes a dielectric layer formed using a polymer (e.g., polyimide). However, any suitable material can be used in any number of redistribution layers in any order.

[0066] Referring again to Figures 17A and 17B, conductive pads 214 are formed on the redistribution structure 270, and the conductive pads 214 are electrically coupled to vias 212. External connectors can then be formed on the conductive pads 214 to couple to external devices (e.g., core substrate 300 (see above, Figures 1 and 2)). Conductive pads can be formed using methods and materials similar to those described above for conductive lines 208.

[0067] In Figure 18, a carrier substrate debond is performed to separate (or “peel off”) the carrier substrate 702 from the adhesive 280 on the local interconnect element 120, encapsulation 420, and perforation 118. According to some embodiments, the debond involves projecting light (e.g., laser or UV light) onto a release layer (not shown) over the carrier substrate 702, causing the release layer to decompose under the heat of the light and making the carrier substrate 702 removable. The structure is then flipped and placed on another carrier substrate 802 and a release layer (not shown).

[0068] In Figure 19, planarization (e.g., grinding or chemical mechanical polishing) is performed to remove adhesive 280 (see Figure 18), thereby exposing the top surface of the conductive connector 236 of the local interconnect element 120. Exposing the top surface of the conductive connector 236 allows the conductive connector 236 to be directly coupled to and electrically coupled to the conductive features of the subsequently formed interconnect structure (see Figures 20A and 20B below). The top portion of the encapsulation 420 and the top portion of the through-hole 118 may also be removed. By eliminating solder joints in the final structure, electrical migration issues at solder joints are reduced. The increased reliability and improved electrical performance resulting from lower contact resistance are likely at least in part attributable to the solderless connection between the embedded dual-sided local interconnect elements and the redistribution structure. Using adhesive 280 to bond local interconnect components to carrier substrate 702 and then removing adhesive 280 allows for the avoidance of solder joint bonding processes (including, for example, forming microbumps on local interconnect components and forming microbump pads on carrier substrate). This simplifies the process flow, increases throughput, and reduces crack formation caused by subsequent removal of microbumps and microbump pads.

[0069] After planarization, the top surface of the conductive connector 236 may be flush with the top surface of the encapsulation 420 and the top surface of the perforation 118. After planarization to remove the adhesive 280, the encapsulation 420 may have a thickness in the range of 5 μm to 150 μm.

[0070] Figures 20A and 20B illustrate a redistribution structure 200 with an interconnect structure 284, also referred to as redistribution structure 284. Redistribution structure 284 includes redistribution layers 281, 282, and 283 formed over an encapsulation 420, vias 118, and local interconnect elements 120. Figure 20B shows a detailed cross-sectional view of region 1004 shown in Figure 20A. Although the embodiment shown in Figures 20A and 20B illustrates an interconnect structure 284 with three redistribution layers, any suitable number of redistribution layers can be formed, for example, from zero to five. The redistribution layers 281, 282, and 283 can be used to couple vias 118 and local interconnect elements 120 to subsequently bonded components (e.g., integrated circuit dies 512, 514, and 516). In an embodiment with zero redistribution layers (not shown), under-bump metallization (UBM) 264 (see below) may be formed directly above the via 118 and the conductive connector 236 and physically coupled and electrically coupled to the via 118 and the conductive connector 236.

[0071] Redundancy layer 281 includes a dielectric layer 114 and vias 112 and 116 extending through the dielectric layer 114 to couple conductive connectors 236 and through-holes 118 of local interconnect element 120, respectively. The dielectric layer 114, vias 112, and vias 116 can be formed using methods and materials similar to those used for dielectric layer 206 and vias 202 and 204 (see above, Figures 17A and 17B). In some embodiments, dielectric layer 114 comprises a polymer (e.g., polyimide). In some embodiments, dielectric layer 114 has a thickness ranging from 2 μm to 50 μm.

[0072] A redistribution layer 282 is formed on top of redistribution layer 281, and redistribution layer 282 includes dielectric layer 108 and metallization pattern, the metallization pattern including conductive lines 110 and vias 94. Conductive lines 110 may be formed on and coupled to vias 112 and 116. Conductive lines 110 and vias 94 may be formed using methods and materials similar to those used for conductive lines 208 and vias 212 (see above, Figures 17A and 17B). Dielectric layer 108 may be formed using the same materials and methods as dielectric layer 206.

[0073] A redistribution layer 283 is formed on top of redistribution layer 282, and redistribution layer 283 includes a dielectric layer 90 and a metallization pattern, the metallization pattern including conductive lines 92 and vias 106. Conductive lines 92 may be formed on and coupled to vias 94. Conductive lines 92 and vias 106 may be formed using methods and materials similar to those used for conductive lines 208 and vias 212 (see above, Figures 17A and 17B). The dielectric layer 90 may be formed using the same materials and methods as the dielectric layer 206.

[0074] Referring again to Figures 20A and 20B, an under-bump metal (UBM) 264 (sometimes referred to as pad 264) is formed for external connections to the via 106. The UBM 264 has a bump portion located on and extending along the main surface of the dielectric layer 90, and may have a via portion extending into the dielectric layer 90 to physically and electrically couple the via 106. Therefore, the UBM 264 is electrically coupled to the through-hole 118 and the local interconnect element 120. The UBM 264 may be formed of the same material as the via 106.

[0075] Referring further to Figures 20A and 20B, conductive connectors 188 are formed on the UBM 264. Conductive connectors 188 enable physical and electrical connections to dies (such as integrated circuit dies 512, 514, and 516) or another package structure. Conductive connectors 188 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. Conductive connectors 188 may comprise conductive materials (e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof). In some embodiments, conductive connectors 188 are formed by initially forming a solder layer using processes such as vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once a solder layer has been formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 188 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or similar processes. The metal pillar may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process. In some embodiments, adjacent conductive connectors are spaced apart by a pitch ranging from 20 μm to 80 μm.

[0076] In Figure 21, a carrier substrate stripping is performed to separate (or “peel”) the carrier substrate 802 from the redistribution structure 200. According to some embodiments, the stripping involves projecting light (e.g., laser or UV light) onto a release layer (not shown) over the carrier substrate 802, causing the release layer to decompose under the heat of the light and making the carrier substrate 802 removable. The structure is then flipped over and placed on another carrier 804 (e.g., a strip).

[0077] Figure 22 illustrates the core substrate 300, which is then incorporated into the redistribution structure 200 (see Figure 23 below). Utilizing the core substrate 300 has the advantage of allowing it to be manufactured in separate processes. Furthermore, because the core substrate 300 is formed in separate processes, it can be tested separately, thus allowing the use of known, high-quality core substrates. For example, in some embodiments, the core substrate 300 can be tested, validated, and / or verified individually or in batches before being incorporated into the redistribution structure 200.

[0078] The core substrate 300 may be, for example, an organic substrate, a ceramic substrate, a silicon substrate, or a similar substrate. The core substrate 300 is bonded to the redistribution structure 200 using conductive connectors 390. Bonding the core substrate 300 may include placing the core substrate 300 on the redistribution structure 200 and reflowing the conductive connectors 390 to physically and electrically couple the core substrate 300 to the redistribution structure 200.

[0079] Before being bonded to the redistribution structure 200, the core substrate 300 may be processed according to an applicable manufacturing process to form the redistribution structure in the core substrate 300. For example, the core substrate 300 includes a core body 310. The core body 310 may be formed from one or more layers of materials such as: glass fiber, resin, filler, prepreg, epoxy resin, silica filler, Ajinomoto laminate (ABF), polyimide, molding compound, other materials, and / or combinations thereof. For example, in some embodiments, two layers of material constitute the core body 310. The core body 310 may be formed from organic and / or inorganic materials. In some embodiments, the core body 310 includes one or more passive elements (not shown) embedded within it. The core body 310 may contain other materials or components. A via 320 extending through the core body 310 is formed. In some embodiments, the via 320 comprises a conductive material 320A (e.g., copper, copper alloy, or other conductor) and may include a barrier layer (not shown), a pad (not shown), a seed layer (not shown), and / or a filler material 320B. The via 320 provides a vertical electrical connection from one side of the core body 310 to the other side of the core body 310. For example, some vias 320 are coupled between a conductive feature located on one side of the core body 310 and a conductive feature located on the opposite side of the core body 310. As an example, the vias 320 can be formed using drilling, photolithography, laser processing, or other methods, and then the vias 320 can be filled or plated with a conductive material. In some embodiments, the via 320 is a hollow conductive through-hole having a center filled with an insulating material. Redistribution structures 340A and 340B are formed on the opposite sides of the core body 310. The redistribution structure 340A and redistribution structure 340B are electrically coupled through via 320 and can be used for fan-in / fan-out electrical signals.

[0080] Redundancy structures 340A and 340B each include a dielectric layer formed of ABF, prepreg, or the like, and a metallization pattern. Each corresponding metallization pattern has a line portion located on and extending along the main surface of the corresponding dielectric layer, and a via portion extending through the corresponding dielectric layer. Redundancy structures 340A and 340B each include: under-bump metallization (UBM) 330A and 330B for external connection; and solder resist 350A and 350B to protect the features of redundancy structures 340A and 340B. Redundancy structure 340A can then be attached to redundancy structure 200 via UBM 330A using conductive connector 390, as shown in Figure 23 below. Compared to that shown in Figure 22, more or fewer dielectric layers and metallization patterns can be formed in redundancy structures 340A and 340B.

[0081] The core substrate 300 may include active and passive devices (not shown), or may not have either or both active and passive devices. A wide variety of devices can be used, such as transistors, capacitors, resistors, inductors, combinations of these devices, and the like. Any suitable method can be used to form the device.

[0082] The core substrates 300A and 300B can be bonded to the redistribution structure 200 using conductive connectors 390, as shown in Figure 23 below. The conductive connectors 390 can be formed first on either the core substrates 300A and 300B, or on the conductive pads 214 of the redistribution structure 200 (see above, Figure 21), and then reflowed to complete the bonding. For example, in the embodiment shown in Figure 22, the conductive connectors 390 are formed on the UBM 330A of the bottom redistribution structure 340A with a pitch ranging from 20 μm to 500 μm. The conductive connectors 390 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse die connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, or the like. The conductive connector 390 may comprise a conductive material (e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof). The integration of this conductive connector 390 provides flexibility in the placement of semiconductor devices (e.g., integrated passive device (IPD) wafers, integrated voltage regulators (IVRs), active wafers, and other electrical components) to implement system-on-a-chip (SoC) packaged components, thus reducing fabrication complexity. This embodiment also provides greater flexibility for various other package configurations.

[0083] In some embodiments, the conductive connector 390 is formed by initially forming a solder layer using processes such as vapor deposition, electroplating, printing, solder transfer, balling, or similar processes. Once the solder layer has been structurally formed, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 390 includes a metal pillar (e.g., a copper pillar) formed by processes such as sputtering, printing, electroplating, electroless plating, CVD, or similar processes. The metal pillar may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process.

[0084] In Figure 23, core substrates 300A and 300B are bonded to the redistribution structure 200 in the first package region 101A and the second package region 101B, respectively (see above, Figure 21). In some embodiments, core substrates 300A and 300B can be placed on the redistribution structure 200 using a pick-and-place process or another suitable process and conductive connectors 390 bonded via flip-chip bonding or other suitable bonding processes. In some embodiments, conductive connectors 390 are reflowed to bond core substrates 300A and 300B to the redistribution structure 200 via conductive pads 214. Conductive connectors 390 electrically couple and / or physically couple core substrates 300A and 300B to the redistribution structure 200 and couple core substrates 300A and 300B to integrated circuit dies 512, 514, and 516 via local interconnect elements 120. Integrated circuit chips 512, 514 and 516 are connected to each other and to both sides of the core substrate 300 via local interconnect elements 120, which increases the communication bandwidth between integrated circuit chips while maintaining low contact resistance and high reliability.

[0085] The conductive connector 390 may have an epoxy flux (not shown) formed thereon before reflow soldering, and at least some of the epoxy portion of the epoxy flux is retained after the core substrates 300A and 300B are bonded to the redistribution structure 200.

[0086] In Figure 24, encapsulation is performed by forming encapsulations 520 on and around various components. After formation, the encapsulations 520 surround the core substrates 300A and 300B, including the exposed surfaces of the conductive connector 390, the metallized pattern 174, and the dielectric layer 172. The encapsulations 520 may be formed or comprised of molding compounds, epoxy resins, underfills, molding underfills, the like, or combinations thereof, and may be applied by compression molding, transfer molding, or similar processes. The encapsulations 520 may be applied in liquid or semi-liquid form and then subsequently cured. The encapsulations 520 may be formed on a frame such that the core substrates 300A and 300B are buried or covered.

[0087] Referring further to FIG24, a planarization process may be performed on the encapsulation 520 as required to expose the UBM 330 of the core substrates 300A and 300B. Following the planarization process, the topmost surface of the encapsulation 520 is flush with (e.g., flat) the topmost surface of the UBM 330. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or a similar process. In some embodiments, for example, if the UBM 330 has already been exposed, planarization may be omitted. Other processes may be used to achieve similar results. For example, a dielectric or passivation layer may be formed on the UBM 330 before forming the encapsulation 520. In this case, the dielectric or passivation layer may be patterned in a subsequent step to expose portions of the UBM 330.

[0088] As described above, the redistribution structure 200 can be larger and include multiple packaging regions, such as a first packaging region 101A and a second packaging region 101B. For example, FIG25 illustrates a redistribution structure 200 as shown in FIG20A above, having a circular wafer shape with multiple packaging regions. In the illustrated embodiment, four packaging regions 101A, 101B, 101C, and 101D are included on the wafer, thereby allowing four final package components to be fabricated on a single wafer and subsequently individualized. In other embodiments, fewer or more packaging regions may be utilized on a single wafer. Subsequent steps in the process use the redistribution structure 200 as a basis on a carrier substrate 802, upon which the fabrication flow, as further detailed below, continues. As further detailed below, the individual packaging regions are individualized by sawing along line 401 and around the outer edges of packaging regions 101A, 101B, 101C, and 101D.

[0089] Figure 26 illustrates a redistribution structure 200 manufactured using a panel-type fabrication process utilizing multiple package regions. In the illustrated embodiment, nine package regions 101A to 101I are included on the wafer, enabling the fabrication of nine final package components on a single wafer or panel. In other embodiments, fewer or more package regions may be utilized on a single wafer or panel. Subsequent steps in the process use the redistribution structure 200 as a basis on a carrier substrate 802, upon which the fabrication process, as further detailed below, continues. As further detailed below, the individual package regions are individualized by sawing along line 402 and around the periphery of package regions 101A to 101I.

[0090] In Figure 27, a monomerization process is performed by sawing along a dicing region, for example, between a first package region 101A and a second package region 101B. The sawing isolates the first package region 101A from the adjacent package region to form a plurality of monomerized package assemblies 100. As shown in Figure 24, an encapsulation 520 covers the sidewalls of the core substrate 300, thereby protecting the sidewalls of the core substrates 300A and 300B during and after monomerization.

[0091] In Figure 28, multiple integrated circuit dies (e.g., one or more logic dies 512, one or more memory dies 514, and one or more input / output (I / O) dies 516 (not shown in Figure 23, but see Figure 3)) are bonded to the redistribution structure 200. Dies 512, 514, and 516 have bonding pads 518 that bond to conductive connectors 188. In some embodiments, bonding pads 518 are made of a conductive material and may resemble the conductive lines described above (see, for example, conductive line 110). In some embodiments, dies 512, 514, and 516 may be placed on the redistribution structure 200 using a pick-and-place process or another suitable process and conductive connectors 188 bonded via flip-chip bonding or other suitable bonding processes. In some embodiments, conductive connectors 188 are reflowed to bond dies 512, 514, and 516 to the redistribution structure 200 via bonding pads 518. Dies 512, 514, and 516 can be coupled to the redistribution structure 200, such that adjacent dies 512, 514, and 516 are coupled to each other via local interconnect element 120 (see above, Figure 3). Local interconnect element 120 provides electrical wiring and connections between integrated circuit dies 512, 514, and 516 of the integrated circuit package 500 and increases the communication bandwidth between integrated circuit dies 512 to 516, while maintaining low contact resistance and high reliability.

[0092] Figure 29 illustrates the underfill 610 shown in Figure 1, which can form conductive connections 188 between integrated circuit dies 512, 514, and 516 and the redistribution structure 200. The underfill 610 reduces stress and protects joints formed by reflow of the conductive connections 188. The underfill 610 can be formed by a capillary flow process after the integrated circuit package 500 is bonded, or by a suitable deposition method. In some embodiments, a single layer of underfill 610 is formed under a plurality of adjacent devices, and further subsequent underfills (not shown) or encapsulations (not shown) can be formed under and / or around additional devices placed on top of the monolithic package element 100.

[0093] Figure 30 illustrates an external connector 620 formed on a UBM 330B on a core substrate 300. The external connector 620 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse die connection (C4) bumps, microbumps, or the like. The external connector 620 may contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the external connector 620 is formed by initially forming a resolderable material layer on the UBM 330B using processes such as vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once a resolderable material layer has been formed on the UBM 330B, resoldering can be performed to shape the material into the desired bump shape.

[0094] The embodiments offer advantages. For example, embedded dual-sided local interconnects can increase communication bandwidth between integrated circuit dies while maintaining low contact resistance and high reliability. The embedded dual-sided local interconnects can increase communication bandwidth between integrated circuit dies and other bonded packages (such as a core substrate), which can be useful for high-performance computing. During the fabrication of packaged components, using an adhesive (such as a die-attach film (DAF)) to bond the local interconnects to the carrier substrate allows for the avoidance of solder joint bonding processes (including, for example, forming microbumps on the local interconnects and microbump pads on the carrier substrate). This simplifies the process flow, increases throughput, and reduces crack formation caused by subsequent removal of microbumps and microbump pads. Solder-free connections between embedded dual-sided local interconnects and redistribution structures contribute to higher reliability and improved electrical performance, and reduce electromigration issues associated with solder joints. Due to the increased communication bandwidth between integrated circuit dies provided by the dual-sided local interconnect elements, no interposer is required between the integrated circuit die and the redistribution structure. Eliminating the need for an interposer reduces wafer-package interaction issues and widens the reliability window. This reduces the coefficient of thermal expansion (CTE) mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and redistribution structure), thus reducing warpage mismatch.

[0095] According to an embodiment, a method for forming a semiconductor device includes: forming a first through-hole and a second through-hole on a first substrate; attaching a first local interconnect element to the first substrate, the first local interconnect element being disposed between the first through-hole and the second through-hole, the first local interconnect element being attached to the first substrate using a first adhesive; encapsulating the first local interconnect element, the first through-hole, and the second through-hole using a first encapsulation body; removing the top portion of the first encapsulation body and the top portion of the first local interconnect element; and forming a first through-hole, the first through-hole, and the second through-hole on a first side of the first local interconnect element. A first rewiring structure is formed on the first encapsulation; the first local interconnect element, the first encapsulation, the first via, the second via, and the first rewiring structure are removed from the first substrate, and the first rewiring structure is attached to the second substrate; the first adhesive is removed from the first local interconnect element; and an interconnect structure is formed on a second side of the first local interconnect element, the first via, the second via, and the first encapsulation, the second side being opposite to the first side, wherein a first conductive feature of the interconnect structure is physically coupled and electrically coupled to a second conductive feature of the first local interconnect element. In an embodiment, the first adhesive has a thickness in the range of 5 μm to 100 μm. In an embodiment, removing the first adhesive includes a polishing process. In an embodiment, removing the top portion of the first local interconnect element includes removing a portion of the substrate. In an embodiment, the method further includes: attaching a first integrated circuit die to the interconnect structure and attaching a second integrated circuit die to the interconnect structure, wherein the first integrated circuit die is coupled to the second integrated circuit die through the first local interconnect element. In one embodiment, the method further includes: attaching a second local interconnect element to the first substrate using a second adhesive; encapsulating the second local interconnect element using a first encapsulator; removing the top portion of the second local interconnect element; forming a first rewiring structure on the second local interconnect element; removing the second local interconnect element from the first substrate; removing the second adhesive from the second local interconnect element; and forming the interconnect structure on the second local interconnect element, wherein a third conductive feature of the interconnect structure is physically coupled and electrically coupled to a fourth conductive feature of the second local interconnect element. In another embodiment, the method further includes: attaching a third integrated circuit die to the interconnect structure, wherein the first integrated circuit die is coupled to the third integrated circuit die through the second local interconnect element. In another embodiment, the first integrated circuit die is a logic die, the second integrated circuit die is a logic die, and the third integrated circuit die is a memory die.In one embodiment, the first integrated circuit die is a logic die. In another embodiment, the second integrated circuit die is a memory die and the third integrated circuit die is a memory die. In yet another embodiment, the second integrated circuit die is a logic die and the third integrated circuit die is an input / output die.

[0096] According to another embodiment, a method of forming a semiconductor device includes: forming a first plurality of redistribution layers on a first substrate, the first plurality of redistribution layers including a first plurality of conductive pads exposed on a top surface of the first plurality of redistribution layers; forming an adhesive over the first plurality of redistribution layers; and monomerizing the first substrate, the first plurality of redistribution layers, and the adhesive into a plurality of local interconnect elements, wherein a first local interconnect element of the plurality of local interconnect elements includes a monomerized portion of the first substrate, a monomerized portion of the first plurality of redistribution layers, a first conductive pad and a second conductive pad among the first plurality of conductive pads, and a monomerized portion of the adhesive, the monomerized portion of the first plurality of redistribution layers being located on the monomerized portion of the first substrate, the first conductive pad and the second conductive pad among the first plurality of conductive pads extending to the top surface of the monomerized portion of the first plurality of redistribution layers, and the adhesive... The monomerized portion of the first plurality of redistribution layers covers the monomerized portion of the first plurality of redistribution layers; the first local interconnect element is attached to a second substrate; the first local interconnect element is encapsulated using a first encapsulator; the top portion of the first encapsulator is removed and the monomerized portion of the first substrate is removed from the first local interconnect element; a first redistribution structure is formed on a first side of the first local interconnect element and on the first encapsulator; the first local interconnect element, the first encapsulator, and the first redistribution structure are removed from the second substrate and the first redistribution structure is attached to a third substrate; the monomerized portion of the adhesive is removed to expose the first conductive pad and the second conductive pad; and a second redistribution structure is formed on a second side of the first local interconnect element and on the first encapsulator, the second side being opposite to the first side, the second redistribution structure including a third conductive pad and a fourth conductive pad, the third conductive pad being bonded to the first conductive pad, and the fourth conductive pad being bonded to the second conductive pad. In an embodiment, the first plurality of redistribution layers comprise polyimide. In an embodiment, the first plurality of redistribution layers comprise a molded film. In an embodiment, the method further includes: attaching a first integrated circuit die to a second rewiring structure, attaching a second integrated circuit die to the second rewiring structure, and attaching a core substrate to the first rewiring structure, wherein the first integrated circuit die is electrically coupled to the second integrated circuit die through a first local interconnect element, and the core substrate is electrically coupled to the first integrated circuit die through the first local interconnect element.

[0097] According to another embodiment, a semiconductor structure includes: a first rewiring structure, the first rewiring structure including a first dielectric layer and a first plurality of conductive features; and a local interconnect element disposed on the first rewiring structure, the sidewalls of the local interconnect element being surrounded by a bottom filler adhesive, the local interconnect element including the first plurality of rewiring layers, the first plurality of rewiring layers including: a second plurality of conductive features located on a first side of the local interconnect element, the first side being in contact with the first rewiring structure in a physical manner, each of the first plurality of conductive features being physically coupled and electrically coupled to a corresponding conductive feature of the second plurality of conductive features. The local interconnect element includes a third plurality of conductive features and a fourth plurality of conductive features, the third plurality of conductive features and the fourth plurality of conductive features being located on a second side of the local interconnect element opposite to the first side; and a first interconnect structure located on the second side of the local interconnect element, the second side being opposite to the first side, the first interconnect structure including a fifth plurality of conductive features and a sixth plurality of conductive features, each of the third plurality of conductive features being coupled to a corresponding conductive feature of the fifth plurality of conductive features, and each of the fourth plurality of conductive features being coupled to a corresponding conductive feature of the sixth plurality of conductive features. In one embodiment, the semiconductor structure further includes: a first integrated circuit die, physically coupled and electrically coupled to the first interconnect structure opposite to the local interconnect element, the first integrated circuit die being electrically coupled to the fifth plurality of conductive features of the first interconnect structure; and a second integrated circuit die, physically coupled and electrically coupled to the first interconnect structure opposite to the local interconnect element, the second integrated circuit die being adjacent to the first integrated circuit die, the second integrated circuit die being electrically coupled to the sixth plurality of conductive features of the first interconnect structure. In another embodiment, the semiconductor structure further includes a semiconductor package, the semiconductor package being attached to the first rewiring structure opposite to the local interconnect element, the semiconductor package being coupled to the first integrated circuit die through the local interconnect element. In another embodiment, the semiconductor package is a core substrate. In an embodiment, the semiconductor structure further includes a plurality of vias extending through the bottom filler adhesive, the bottom surface of each of the plurality of vias being coupled to a corresponding conductive feature of the first redistribution structure, and the top surface of each of the plurality of vias being coupled to a corresponding conductive feature of the first interconnect structure.

[0098] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0099] 90, 108, 114, 206, 210, 222, 234: Dielectric layers 92, 110, 208, 226, 232: Conductive wires 94, 106, 112, 116, 202, 204, 212, 228, 320: Through holes 100: Monolithic packaged components / Packaged components 101A: First Package Area / Package Area 101B: Second Package Area / Package Area 101C, 101D, 101E, 101F, 101G, 101H, 101I: Package area 102: Carrier substrate / substrate 118: Perforation / Molded Perforation (TMV) 120: Local internal wiring element 122, 188, 390: Conductive connectors 200, 220, 340B: Rewiring Structure 214: Conductive pad 224: Opening 236: Conductive features / vias / conductive connectors / conductive pads 250: Cutting track 260: Bottom Rewiring Layer / Rewiring Layer 262, 270A, 270B, 281, 282, 283: Rewiring Layer 264: Under Bump Metal (UBM) / Pad 270: Internal wiring structure / rewiring structure / rearside rewiring structure 280: Adhesive 284: Interconnection / Rewire Structure 300, 300A, 300B: Core Base 310: Central Core / Core 320A: Conductive material 320B: Filler material 330, 330A, 330B: Under-bump metal (UBM) 340: Rewiring Structure 340A: Rewiring Structure / Bottom Rewiring Structure 350A, 350B: Solder resist 401, 402: Lines 420: Encapsulating body / bottom filler 500: Integrated Circuit Package 512: Integrated circuit chip / chip / logic chip / first logic chip / second logic chip 514: Integrated circuit die / die / memory die / first memory die / second memory die / third memory die / fourth memory die 516: Integrated circuit chip / chip / input / output (I / O) chip / first I / O chip / second I / O chip 518: Bonding pads 520: Encapsulation 610: Bottom filler glue 620: External connector 702, 802: Carrier substrate 804: Carrier 1000, 1002, 1004: District

Claims

1. A method for forming a semiconductor device, the method comprising: A first through-hole and a second through-hole are formed on a first substrate; a first partial interconnect element is attached to the first substrate, the first partial interconnect element being disposed between the first through-hole and the second through-hole, and the first partial interconnect element is attached to the first substrate using a first adhesive; the first partial interconnect element, the first through-hole, and the second through-hole are encapsulated using a first encapsulating body; the top portion of the first encapsulating body and the top portion of the first partial interconnect element are removed; a first rewiring structure is formed on a first side of the first partial interconnect element, the first through-hole, the second through-hole, and the first encapsulating body; the first partial interconnect element, the first encapsulating body, the first through-hole, the second through-hole, and the first rewiring structure are removed from the first substrate, and the first rewiring structure is attached to a second substrate; The first adhesive is removed from the first local interconnect element; and an interconnect structure is formed on the second side of the first local interconnect element, the first perforation, the second perforation and the first encapsulation, the second side being opposite to the first side, wherein a first conductive feature of the interconnect structure is physically coupled and electrically coupled to a second conductive feature of the first local interconnect element.

2. The method of forming a semiconductor device as described in claim 1, further comprising: A first integrated circuit die is attached to the interconnect structure and a second integrated circuit die is attached to the interconnect structure, wherein the first integrated circuit die is coupled to the second integrated circuit die through the first local interconnect element.

3. The method for forming a semiconductor device as described in claim 1, further comprising: The second local interconnect element is attached to the first substrate using a second adhesive. The second local interconnect element is encapsulated using the first encapsulating body; Remove the top portion of the second local interconnect element; form the first rewiring structure on the second local interconnect element; remove the second local interconnect element from the first substrate; remove the second adhesive from the second local interconnect element; and form the interconnect structure on the second local interconnect element, wherein a third conductive feature of the interconnect structure is physically coupled and electrically coupled to a fourth conductive feature of the second local interconnect element.

4. A method of forming a semiconductor device, the method comprising: A first plurality of redistribution layers are formed on a first substrate, the first plurality of redistribution layers including a first plurality of conductive pads exposed on the top surface of the first plurality of redistribution layers; an adhesive is formed on the first plurality of redistribution layers; the first substrate, the first plurality of redistribution layers, and the adhesive are monomerized into a plurality of local interconnect elements, a first local interconnect element comprising: a monomerized portion of the first substrate; a monomerized portion of the first plurality of redistribution layers located on the monomerized portion of the first substrate; a first conductive pad and a second conductive pad of the first plurality of conductive pads extending to the top surface of the monomerized portion of the first plurality of redistribution layers; and a monomerized portion of the adhesive covering the monomerized portion of the first plurality of redistribution layers; the first local interconnect element is attached to a second substrate; the first local interconnect element is encapsulated using a first encapsulation body; the top portion of the first encapsulation body is removed and the monomerized portion of the first substrate is removed from the first local interconnect element. A first rewiring structure is formed on a first side of the first local interconnect element and on the first encapsulation; the first local interconnect element, the first encapsulation, and the first rewiring structure are removed from the second substrate and the first rewiring structure is attached to a third substrate; the monomerized portion of the adhesive is removed to expose the first conductive pad and the second conductive pad; and a second rewiring structure is formed on a second side of the first local interconnect element and on the first encapsulation, the second side being opposite to the first side, the second rewiring structure including a third conductive pad and a fourth conductive pad, the third conductive pad being attached to the first conductive pad and the fourth conductive pad being attached to the second conductive pad.

5. A method of forming a semiconductor device, the method comprising: A local interconnect element is attached to a carrier substrate, wherein the local interconnect element includes a first plurality of redistribution layers, the first plurality of redistribution layers including: a first plurality of conductive features located on a first side of the local interconnect element, and a second plurality of conductive features located on a second side of the local interconnect element opposite to the first side; a molding compound is formed surrounding the sidewalls of the local interconnect element, and the formation of the molding compound further includes performing a planarization process to remove a top portion of the molding compound, and removing a first external portion of the local interconnect element; A first rewiring structure is formed on the first side of the local interconnect element, the first rewiring structure including a first dielectric layer and a third plurality of conductive features, wherein after the first rewiring structure is formed on the local interconnect element, the first side of the local interconnect element is in contact with the first rewiring structure in a physical manner, each of the first plurality of conductive features of the local interconnect element is in a physical manner coupled and electrically coupled to a corresponding conductive feature of the third plurality of conductive features of the first rewiring structure, and the molding compound is located on the back side of the first rewiring structure; and the carrier substrate is removed, and a first interconnect structure is formed on the second side of the local interconnect element, wherein forming the first interconnect structure on the second side of the local interconnect element includes removing a second external portion of the local interconnect element, wherein the second external portion is opposite to the first external portion of the local interconnect element, and the first interconnect structure includes a fourth plurality of conductive features, each of the second plurality of conductive features of the local interconnect element being coupled to a corresponding conductive feature of the fourth plurality of conductive features of the first interconnect structure.

6. A semiconductor structure, comprising: A first rewiring structure, comprising a first dielectric layer and a first plurality of conductive features; a local interconnect element disposed on the first rewiring structure, the sidewalls of the local interconnect element being surrounded by bottom filler adhesive, the local interconnect element comprising a first plurality of rewiring layers, the first plurality of rewiring layers comprising: a second plurality of conductive features located on a first side of the local interconnect element, the first side being in contact with the first rewiring structure in a physical manner, each of the first plurality of conductive features being physically coupled and electrically coupled to a corresponding conductive feature among the second plurality of conductive features; a third plurality of conductive features and a fourth plurality of conductive features located on a second side of the local interconnect element opposite to the first side; and a first interconnect structure located on a second side of the local interconnect element, the second side being opposite to the first side, the first interconnect structure comprising a fifth plurality of conductive features and a sixth plurality of conductive features, each of the third plurality of conductive features being coupled to a corresponding conductive feature among the fifth plurality of conductive features, and each of the fourth plurality of conductive features being coupled to a corresponding conductive feature among the sixth plurality of conductive features.

7. The semiconductor structure as described in claim 6, further comprising: The first integrated circuit die is physically coupled and electrically coupled to the first interconnect structure relative to the local interconnect element, and the first integrated circuit die is electrically coupled to the fifth plurality of conductive features of the first interconnect structure. And a second integrated circuit die, which is physically coupled and electrically coupled to the first interconnect structure relative to the local interconnect element, the second integrated circuit die being adjacent to the first integrated circuit die, and the second integrated circuit die being electrically coupled to the sixth plurality of conductive features of the first interconnect structure.

8. A semiconductor device, comprising: A first rewiring structure, the first rewiring structure including a first via embedded in a first dielectric layer; a local interconnect including: a second via located on a first side of the local interconnect, wherein the second via is physically coupled and electrically coupled to the first via; and a third via located on a second side opposite to the first side of the local interconnect; a molding compound surrounding the local interconnect; and a second rewiring structure including a fourth via adjacent to the second side of the local interconnect, wherein the fourth via is electrically coupled and physically coupled to the third via.

9. The semiconductor device of claim 8, wherein the first rewiring structure further comprises: The fifth via is embedded in the first dielectric layer; The second dielectric layer is adjacent to the first dielectric layer opposite to the local interconnect. A first conductive line is embedded in the second dielectric layer, wherein the first conductive line is electrically coupled and physically coupled to the first via and the fifth via; And a sixth via, embedded in the second dielectric layer, adjacent to the first conductive line opposite to the first dielectric layer.

10. A semiconductor device, comprising: The first wiring structure includes a first via embedded in a first dielectric layer. A local interconnect structure includes: a first conductive connector embedded in a second dielectric layer, wherein the first conductive connector contacts the first via, and the first dielectric layer contacts the second dielectric layer; The local interconnect structure includes a second conductive connector embedded in a third dielectric layer, the third dielectric layer being disposed on the side of the local interconnect structure opposite to the second dielectric layer; a second redistribution structure including a second via, wherein the second via contacts the second conductive connector; and a molding compound encapsulating the local interconnect structure, wherein the molding compound extends from a first side of the local interconnect structure to a second side of the local interconnect structure.

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