Semiconductor device and semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are provided. In one embodiment, the exemplary semiconductor structure includes a gate structure located on a channel region of an active region; a drain structure located on a drain region of the active region; a source structure located on a source region of the active region; a back-side source contact located below the source structure; an isolation structure located on and in contact with the source structure; a drain contact located on and electrically coupled to the drain structure; and a gate contact via located on and electrically coupled to the gate structure. The distance between the gate contact via and the drain contact is greater than the distance between the gate contact via and the isolation structure. The exemplary semiconductor structure reduces parasitic capacitance and increases the allowable leakage current range.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices having a back-side source contact. Prior Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (such as the number of interconnect devices per unit wafer area) typically increases as geometric dimensions (such as the smallest components or lines that the manufacturing process can produce) shrink. Shrinking dimensions generally facilitates increased production capacity and reduced associated costs. However, shrinking dimensions also increases the complexity of handling and manufacturing integrated circuits.

[0003] For example, drastically reducing the size of integrated circuits results in closely packed source / drain and gate structures, as well as closely packed source / drain contacts and gate-to-hole vias. The reduced space between two adjacent conductive structures (such as gate-to-hole vias and source / drain contacts) can cause leakage current, which increases power consumption and can even lead to complete circuit failure (if the leakage current is large enough). Therefore, while existing technologies generally meet the intended purpose, they cannot fully satisfy all requirements. Summary of the Invention

[0004] An exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a first source / drain structure located at a first source / drain junction; a second source / drain structure located on a back-side dielectric layer; a plurality of channel components, each extending between the first source / drain structure and the second source / drain structure; a gate structure, connecting the channel components and located on the back-side dielectric layer; a bottom dielectric layer directly located on the second source / drain structure; a first dielectric layer located on the bottom dielectric layer; and an isolation structure extending through the first dielectric layer and directly located on the first source / drain structure. The composition of the isolation structure differs from that of the bottom dielectric layer, and the first source / drain structure is separated from the first dielectric layer by the isolation structure.

[0005] Another exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a first gate structure located on a channel region of a first active region; a drain structure located on a drain region of the first active region; a source structure located on a source region of the first active region; a back-side source contact located below the source structure; an isolation structure located on and in contact with the source structure; a drain contact located on and electrically coupled to the drain structure; and a gate contact via located on and electrically coupled to the first gate structure. The distance between the gate contact via and the drain contact is greater than the distance between the gate contact via and the isolation structure.

[0006] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes: an active region located on a substrate; a gate structure located on a channel region of the active region; a first source / drain structure located on a first source / drain region of the active region and on a semiconductor plug in the substrate; a second source / drain structure located on a second source / drain region of the active region; and a first dielectric layer including a first portion directly located on the first source / drain structure and a second portion directly located on the second source / drain structure. The method also includes selectively removing a first portion of the first dielectric layer to form an isolation structure opening to expose the first source / drain structure; forming an isolation structure in the isolation structure opening, wherein the composition of the isolation structure is different from the composition of the first dielectric layer; and replacing the semiconductor plug with a back-side source / drain contact. Simple Explanation of the Diagram

[0007] Figure 1 is a flowchart of a method for forming a semiconductor device with a back-side power rail in one or more embodiments of the present invention. Figure 2 is a partial top view of an exemplary workpiece in various stages of the method of Figure 1, according to several embodiments of the present invention. Figures 3 to 16 are partial cross-sectional views along section line A-A' shown in Figure 2 of an exemplary workpiece at various manufacturing stages in the method of Figure 1, according to one or more embodiments of the present invention. Figure 17 is a partial cross-sectional view along section line B-B' shown in Figure 2, illustrating various manufacturing stages of an exemplary workpiece in the method of Figure 1, according to one or more embodiments of the present invention. Figures 18 to 25 are partial cross-sectional views along section line A-A' shown in Figure 2 of an exemplary workpiece at various manufacturing stages in the method of Figure 1, according to one or more embodiments of the present invention. Figure 26 is a partial top view of the illustrative workpiece shown in Figure 25. Figure 27 is a flowchart of a method for determining the setting of the gate contact through hole formed by the method of Figure 1 in one or more embodiments of the present invention. Figures 28 to 37 are partial cross-sectional views or top views of an exemplary workpiece in various manufacturing stages of the method in Figure 27, according to one or more embodiments of the present invention. Figures 38 and 39 are partial cross-sectional views of an exemplary workpiece at various manufacturing stages in the method of Figure 1, according to one or more embodiments of the present invention. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, the same reference numerals may be used repeatedly in various embodiments of the present invention for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, spatial relative terms such as "below," "below," "lower side," "above," "upper side," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, not just those shown in the illustration. For example, if the device in the illustration is flipped, the element below or below will become the element above or above. Elements can also be rotated 90° or other angles; therefore, directional terms are only used to describe the direction shown in the illustration.

[0011] Furthermore, when numerical values ​​or ranges are described using terms such as "about," "approximately," or similar expressions, they are intended to cover values ​​within a reasonable range, such as those inherent to the manufacturing process that are considered by those skilled in the art. For example, based on known manufacturing tolerances related to the numerical value, the numerical value or range covers a reasonable range including the number, for example, within + / - 10% of the number. For example, when the thickness of the material layer is about 5 nm and those skilled in the art know that the manufacturing tolerance for deposited material layers is 15%, the included size range is 4.25 nm to 5.75 nm. Furthermore, the same reference numerals may be used repeatedly in various embodiments of the invention for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence.

[0012] Multi-gate devices, such as finned field-effect transistors (FETs) and multi-bridge channel transistors (MCCs), are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects. FETs have raised channels with gates covering multiple sides of the channels (e.g., the top and sidewalls of fins covering semiconductor material extending from the substrate). The gate structure of a MCC can partially or completely surround the channel region to contact both sides or more of the channel region. Because the gate structure of a MCC surrounds the channel region, it can also be considered a gate-wound transistor or a fully-wound gate transistor. The channel region of a MCC can be formed from nanowires, nanosheets, or other nanostructures; therefore, it can also be considered a nanowire transistor or a nanosheet transistor. The three-dimensional structure of multi-gate devices can significantly reduce size while maintaining gate control and mitigating short-channel effects.

[0013] As mentioned above, significantly reducing the size of integrated circuits results in more densely packed transistors, which in turn leads to more densely packed mid-band fabrication structures. Mid-band fabrication typically involves creating the conductive structures (or conductive regions) from contacts to the integrated circuit device, such as creating contact-to-source / drain structures. The challenges of creating densely packed mid-band structures limit further increases in transistor density. Closely adjacent source / drain contacts and gate contact vias also increase parasitic capacitance between them, causing leakage current.

[0014] The semiconductor device and method provided in this invention can place an isolation structure on the source / drain structure instead of forming a front-side source / drain contact. An exemplary semiconductor device includes a first source / drain structure located on a back-side source / drain contact, a second source / drain structure, a gate structure located above and between the first and second source / drain structures, a bottom dielectric layer directly located on the second source / drain structure, a first dielectric layer located on the bottom dielectric layer, and an isolation structure extending through the first dielectric layer and directly located on the first source / drain structure. The composition of the isolation structure differs from that of the bottom dielectric layer, and the first source / drain structure is separated from the first dielectric layer by the isolation structure. By forming an isolation structure on the source structure instead of forming a front-side source contact, the parasitic capacitance and potential leakage current between the front-side source contact and the gate via can be substantially eliminated. Forming an isolation structure on the source structure can also increase the design flexibility of the gate contact via, thereby increasing the allowable leakage current range between the metal contacts on the front drain contact and the gate contact (such as reducing or substantially eliminating leakage current), and / or reducing the parasitic resistance associated with the gate contact via.

[0015] Various embodiments of the present invention will be described in detail with reference to the accompanying drawings. For this purpose, FIG1 is a flowchart of method 100 for forming a semiconductor device. FIG27 is a flowchart of method 300, which determines the gate contact via configuration created by the method of FIG1. ​​Methods 100 and 300 will be described below with reference to FIGS. 2 to 26 and 28 to 39. Methods 100 and 300 are merely illustrative and not intended to limit the scope of the embodiments described herein. Additional steps may be provided before, during, and / or after methods 100 and 300, and additional embodiments of the methods may replace, eliminate, or substitute some of the steps described. Not all steps are detailed herein for simplicity. Since the result of the fabrication process is the fabrication of workpiece 200 into a semiconductor device, workpiece 200 can also be considered as a semiconductor device. For the avoidance of doubt, the X, Y, and Z directions shown in FIGS. 2 to 26 and 28 to 39 are perpendicular to each other and aligned. In embodiments of the present invention, similar designations are used to indicate similar structures unless otherwise stated.

[0016] As shown in Figures 1 to 3, step 102 of method 100 involves receiving a workpiece 200. Figure 2 is a partial top view of an exemplary workpiece 200. Figure 3 is a partial cross-sectional view of an exemplary workpiece 200 along section line A-A' shown in Figure 2. As shown in Figures 2 and 3, the workpiece 200 includes a substrate 202. In one embodiment, the substrate 202 is a substrate silicon (e.g., comprising a substrate single-crystal silicon). In various embodiments, the substrate 202 may comprise other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, germanium silicon, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, indium gallium arsenide phosphide, or combinations thereof. In some other embodiments, the substrate 202 may be a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a germanium-on-insulator substrate. The semiconductor substrate on the insulating layer can be fabricated by methods such as separator embrittlement, wafer bonding, and / or other suitable methods.

[0017] As shown in Figures 2 and 3, the workpiece 200 also includes multiple fin structures 205 located on the substrate 202. The fin structures 205 can be formed by a portion of the substrate 202 and a vertically stacked 207 of interleaved semiconductor layers (such as channel layers 208 and sacrificial layers 206). In the embodiment described, the vertically stacked 207 may include multiple interleaved channel layers 208 and multiple sacrificial layers 206. Each channel layer 208 may be composed of silicon, and each sacrificial layer 206 may be composed of silicon-germanium. The channel layers 208 and sacrificial layers 206 can be epitaxially deposited on the substrate 202, and their formation methods may include molecular beam epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, and / or other suitable epitaxial growth processes. The fin structures 205 extend longitudinally along the X direction and are divided into a channel region 205C overlapping with the dummy gate stack 210 and source / drain regions 205S / D. Each channel region 205C is located along the X direction between the source / drain regions 205S / D. This embodiment employs a gate substitution process (or a post-gate fabrication process), with the dummy gate stack 210 serving as a placeholder for the functional gate structure. Other processes and configurations are also possible. Suitable deposition, photolithography, and etching processes can be used to form the dummy gate stack 210. As shown in FIG3, the dummy gate stack 210 includes a dummy dielectric layer 212, a dummy gate layer 213 located on the dummy dielectric layer 212, and a hard masking layer 214 on top of the gate located on the dummy gate layer 213. In one embodiment, the dummy dielectric layer 212 comprises silicon oxide. The dummy gate layer 213 comprises polysilicon, and the hard masking layer 214 on top of the gate comprises a silicon nitride layer 214b formed on the silicon oxide layer 214a.

[0018] As shown in Figures 2 and 3, the workpiece 200 also includes an isolation structure 204 formed around the fin structure 205 to isolate adjacent fin structures 205. In some embodiments, the isolation structure 204 is deposited in trenches defining the fin structure 205. These trenches may extend through the channel layer 208 and the sacrificial layer 206 and terminate in the substrate 202. The isolation structure 204 may also be considered as a shallow trench isolation structure. The isolation structure 204 may comprise silicon oxide, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials.

[0019] As shown in Figures 2 and 3, the workpiece 200 also includes a gate spacer 216 along the sidewall of the dummy gate stack 210. In some embodiments, the gate spacer 216 may comprise silicon carbide, silicon carbonitride, silicon nitride, silicon carbonitride, zirconium oxide, aluminum oxide, or a suitable dielectric material.

[0020] As shown in Figures 1 and 4, step 104 of method 100 recesses the source / drain regions 205S / D to form source openings 218S and drain openings 218D. The source / drain regions 205S / D of the fin structure 205 not covered by the dummy gate stack 210 and gate spacer 216 are anisotropically etched using a dry etching process or a suitable etching process. The dry etching process may employ oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, tetrachloromethane, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or bromoform), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In the embodiment shown in Figure 4, the source openings 218S and drain openings 218D may extend through the vertical stack 207 and may partially extend into the substrate 202. When forming the source opening 218S and the drain opening 218D, the gate spacer 216 may be slightly etched. The slightly etched gate spacer 216 can be regarded as the gate spacer 216'. Each gate spacer 216' includes an outwardly curved sidewall 216s, and its width (the dimension along the X direction) gradually decreases along the Z direction.

[0021] As shown in Figures 1 and 5, step 106 of method 100 forms the inner spacer structure 220. After exposing the sacrificial layer 206 in the source opening 218S and drain opening 218D, the sacrificial layer 206 can be selectively partially recessed to form the inner spacer recess (which is then filled with the inner spacer structure 220), and the exposed channel layer 208 is not etched. In one embodiment, the channel layer 208 is substantially composed of silicon, and the sacrificial layer 206 is substantially composed of silicon-germanium, and the step of selectively partially recessing the sacrificial layer can be performed using a selective isotropic etching process. After forming the inner spacer recess, an inner spacer material layer is deposited on the workpiece 200 to fill the inner spacer recess. The inner spacer material layer may comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. Next, the inner spacer material layer is etched back to remove excess inner spacer material layer on the sidewall of the channel layer 208, thereby forming the inner spacer structure 220. In some embodiments, the etch-back process in step 106 may be a dry etching process, which may be similar to the dry etching process used to form the source opening 218S and the drain opening 218D.

[0022] As shown in Figures 1, 6, and 7, step 108 of method 100 forms a semiconductor plug 228 under the source opening 218S. In some embodiments, a mask film 222 is deposited on the workpiece 200, followed by the deposition of a photoresist layer 224 on the mask film 222. In some embodiments, the mask film 222 may be a bottom anti-reflective coating. The photoresist layer 224 is patterned as an etching mask in the etching process of the patterned mask film 222. As shown in Figure 6, the patterned photoresist layer 224 and the patterned mask film 222 cover or protect the drain opening 218D and expose the source opening 218S. An etching process is then performed to extend the source opening 218S into the substrate 202 to form an extended opening 226. In some embodiments, the etching process in step 108 may be a dry etching process, and it may be similar to the dry etching process used to form the source opening 218S and the drain opening 218D. The patterned photoresist layer 224 may then be removed.

[0023] While the masking film 222 still covers the drain opening 218D, a semiconductor plug 228 can be selectively formed in the extended opening 226, and the formation method can employ molecular beam epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, and / or other suitable epitaxial growth processes. The composition of the semiconductor plug 228 differs from that of the substrate 202, allowing the substrate 202 to be selectively removed in subsequent processes. For example, when the substrate 202 is composed of silicon, the semiconductor plug 228 may contain undoped silicon germanium, boron-doped silicon, phosphorus-doped silicon, boron-doped silicon germanium, arsenic-doped silicon, or other suitable materials, thus allowing the substrate 202 to be selectively removed without substantially etching the semiconductor plug 228. In one embodiment, the substrate 202 is composed of silicon, while the semiconductor plug 228 is composed of undoped silicon germanium. After the semiconductor plug 228 is formed, the masking film 222 covering the drain opening 218D can be selectively removed using a suitable etching process.

[0024] As shown in Figures 1 and 8, in step 110 of method 100, a source structure 232S is formed in the source opening 218S, and a drain structure 232D is formed in the drain opening 218D. The source structure 232S and drain structure 232D can each be formed using epitaxial processes such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and / or other suitable processes. Therefore, the source structure 232S and drain structure 232D are coupled to the channel layer 208 in the channel region 205C of the fin structure 205. The source structure 232S and drain structure 232D can be n-type or p-type source / drain structures, depending on the conductivity type of the transistor to be formed. An exemplary n-type source / drain structure may comprise silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing n-type dopants such as phosphorus, arsenic, or antimony during the epitaxial process, or out-of-situ doped by using a junction implantation process. An exemplary p-type source / drain structure may comprise germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped by introducing p-type dopants such as boron or gallium during the epitaxial process, or out-of-situ doped by using a junction implantation process.

[0025] As shown in Figures 1 and 9, in step 112 of method 100, a contact etch stop layer 234 and a bottom interlayer dielectric layer 236 are deposited on the workpiece 200. The contact etch stop layer 234 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art, and its formation method may be atomic layer deposition, plasma-assisted chemical vapor deposition, and / or other suitable deposition or oxidation processes. As shown in Figure 9, the contact etch stop layer 234 may be compliantly deposited on the upper surface of the source structure 232S, the upper surface of the drain structure 232D, and the sidewalls of the gate spacer 216. After depositing the contact etch stop layer 234, the bottom interlayer dielectric layer 236 is deposited on the substrate 200, and its deposition method may be a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. The composition of the bottom interlayer dielectric layer 236 is different from that of the gate spacer 216', allowing the bottom interlayer dielectric layer 236 to be selectively removed in subsequent processes. The bottom interlayer dielectric layer 236 may comprise materials such as oxides of tetraethoxysilane, undoped silicate glass, or doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, or borosilicate glass), and / or other suitable dielectric materials. Planarization processes such as chemical mechanical polishing may be performed to remove excess material and expose the upper surface of the dummy gate layer 213 in the dummy gate stack 210.

[0026] As shown in Figures 1 and 10, step 114 of method 100 replaces the dummy gate stack 210 with a gate structure 210'. With the dummy gate layer 213 exposed, step 114 can remove the dummy gate stack 210. The method of removing the dummy gate stack 210 may include one or more etching processes that are selective for the materials in the dummy gate stack 210. After removing the dummy gate stack 210, the sacrificial layer 206 may be selectively removed to release the channel layer 208 as a channel component in the channel region 205C. The method of selectively removing the sacrificial layer 206 may be dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes etching with a mixture of ammonium hydroxide, hydrogen peroxide, and water.

[0027] A gate structure 210' is deposited to cover a channel assembly such as channel layer 208. Each gate structure 210' includes a gate dielectric layer 212' and a gate layer 213' on the gate dielectric layer 212'. In some embodiments, the gate dielectric layer 212' includes an interface layer on the channel assembly such as channel layer 208 and a high dielectric constant dielectric layer on the interface layer, and its formation may be performed by atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The high dielectric constant dielectric layer here can be considered as a dielectric material with a dielectric constant greater than that of silicon oxide (about 3.9). In some embodiments, the interface layer includes silicon oxide. The dielectric layer with a high dielectric constant may comprise hafnium oxide, zirconium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials.

[0028] Next, a gate layer 213' is deposited on the gate dielectric layer 212', and the deposition method can be atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable methods. The gate layer 213' may comprise a single-layer or multi-layer structure, such as a combination of metal layers, pad layers, wetting layers, adhesive layers, metal alloys, or metal silicides having a selected work function to improve device performance. For example, the gate layer 213' may comprise titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, other suitable metallic materials, or combinations thereof. Furthermore, when a semiconductor device, such as workpiece 200, includes an n-type transistor and a p-type transistor, different gate layers can be formed separately for the n-type transistor and the p-type transistor, and the gate layer can contain different work function metal layers (to provide different n-type and p-type work function metal layers).

[0029] In some embodiments, the workpiece 200 also includes a self-aligned capping layer 237 directly formed on the gate layer 213'. In some embodiments, the self-aligned capping layer 237 may be directly formed on the gate layer 213' and the gate spacer 216'. The composition of the self-aligned capping layer 237 differs from that of the bottom interlayer dielectric layer 236 to allow for selective removal of the bottom interlayer dielectric layer 236 in subsequent processes. In one embodiment, the self-aligned capping layer 237 comprises silicon nitride. In some other embodiments, the composition of the self-aligned capping layer 237 may be silicon oxycarbide, silicon carbide, silicon carbonitride, silicon nitride, silicon, hafnium silicate, silicon oxycarbide, aluminum oxide, zirconium silicate, aluminum oxynitride, zirconium oxide, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, silicon carbonitride, zirconium nitride, or a combination thereof.

[0030] As shown in Figures 1, 11, and 12, step 116 of method 100 selectively removes the contact etch stop layer 234 and the bottom interlayer dielectric layer 236 directly located on the source structure 232S to form a dielectric plug opening 244. As shown in Figure 11, the method for depositing the first interlayer dielectric layer 238 on the workpiece 200 can be chemical vapor deposition, flowable chemical vapor deposition, plasma-assisted chemical vapor deposition, or other suitable processes. In some embodiments, the composition of the first interlayer dielectric layer 238 can be similar to that of the bottom interlayer dielectric layer 236. A hard mask layer 240 can be deposited on the first interlayer dielectric layer 238, and then the hard mask layer 240 is patterned by a lithography process to form the opening 242. An exemplary lithography process includes spin coating a photoresist layer, soft baking the photoresist layer, aligning the photomask, exposure, post-exposure baking, developing the photoresist layer, rinsing, and drying (such as hard baking). As shown in Figure 12, when a patterned hard mask layer 240 is used as an etching mask, one or more etching processes can be performed on the workpiece 200 to selectively remove the first interlayer dielectric layer 238, the bottom interlayer dielectric layer 236, and the contact etch stop layer 234 exposed in the opening 242, and form a dielectric plug opening 244 to expose the source structure 232S. In some embodiments, one or more etching processes can selectively remove the first interlayer dielectric layer 238 and the bottom interlayer dielectric layer 236 to form a dielectric plug opening 244 on the contact etch stop layer 234. The contact etch stop layer 234 still protects the source structure 232S. All upper surfaces of the source structure 232S can be exposed in the dielectric plug opening 244. The etching process can selectively etch the first interlayer dielectric layer 238 and the bottom interlayer dielectric layer 236, while substantially not etching the gate spacer 216' and the self-aligned capping layer 237. After the dielectric plug opening 244 is formed, the patterned hard masking layer 240 can be removed. In some embodiments, the dielectric plug opening 244 may also expose the upper surface of the gate spacer 216'. In some embodiments, the dielectric plug opening 244 may also expose the upper surface of the self-aligning capping layer 237.

[0031] As shown in Figures 1 and 13, step 118 of method 100 forms a dielectric plug 246 in the dielectric plug opening 244. The method of forming the dielectric plug 246 may include multiple processes such as deposition and planarization processes. For example, a dielectric plug layer may be deposited on the workpiece 200 and filled into the dielectric plug opening 244; the deposition method may be atomic layer deposition, physical vapor deposition, chemical vapor deposition, or a suitable process. The dielectric plug layer may comprise silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbide, silicon carbonitride, or a combination thereof. The composition of the dielectric plug layer may differ from the composition of the self-aligned capping layer 237. The composition of the dielectric plug layer may also differ from the composition of the first interlayer dielectric layer 238 and the bottom interlayer dielectric layer 236. In one embodiment, the gate spacer 216 may comprise silicon carbonitride, the self-aligned capping layer 237 may comprise silicon nitride, the first interlayer dielectric layer 238 may comprise silicon oxide, and the dielectric plug 246 may comprise silicon carbonitride. A planarization process, such as chemical mechanical polishing, is then performed to remove excess dielectric plug on the first interlayer dielectric layer 238 and provide a flat surface. The dielectric plug 246 then directly covers all the upper surfaces of the source structure 232S. In embodiments where the contact etch stop layer 234 is not removed during the formation of the dielectric plug opening 244, the contact etch stop layer 234 will cover all the upper surfaces of the source structure 232S, and the dielectric plug 246 will cover all the upper surfaces and sidewall surfaces of the contact etch stop layer 234. Therefore, the horizontal portion of the contact etch stop layer 234 is sandwiched between the source structure 232S and the dielectric plug 246. The dielectric plug 246 extends the shape of the dielectric plug opening 244. The lower surface of the dielectric plug 246 directly contacts the upper surface of the source structure 232S. The width W1 (along the X direction) of the lower surface of the dielectric plug 246 is substantially equal to the width of the upper surface of the source structure 232S. The upper surface of the dielectric plug 246 is coplanar with the upper surface of the first interlayer dielectric layer 238 and has a width W2. In the embodiment described, the width W2 is greater than the width W1, so the dielectric plug 246 may have a funnel shape and tapered sidewalls. As described above, the dielectric plug opening 244 may also expose the upper surface of the self-aligning capping layer 237. Figure 14 shows another embodiment in which the corresponding dielectric plug 246' is formed directly on the gate spacer 216' and a portion of the self-aligning capping layer 237. Therefore, the width W2' of the upper surface of the dielectric plug 246' is greater than the width W2. It should be understood that the shape of the dielectric plug 246 is not limited to the examples shown in Figures 13 and 14. By forming a dielectric plug 246 on the source structure 232S instead of forming a front source contact, the leakage current path between the desired gate contact via and the front source contact can be substantially eliminated. Forming a dielectric plug 246 on the source structure 232S also increases the design flexibility of the gate contact via. The design flexibility of forming the gate contact via will be further explained in detail with reference to Figures 28 to 37.

[0032] As shown in Figures 1 and 15, step 120 of method 100 forms a drain contact 248 on the drain structure 232D. The method of forming the drain contact 248 may include forming a drain contact opening (for filling the drain contact 248) through a first interlayer dielectric layer 238, a bottom interlayer dielectric layer 236, and a contact etch stop layer 234 to expose at least a portion of the drain structure 232D. The method of forming the drain contact opening may include photolithography and etching processes. A silicon layer 247 is then formed in the drain contact opening. In some examples, the silicon layer 247 may comprise titanium silicon, cobalt silicon, nickel silicon, tantalum silicon, or tungsten silicon. The drain contact 248 is then formed on the silicon layer 247. The drain contact 248 may include a barrier layer (not shown) deposited on the upper surface of the workpiece 200. The barrier layer may comprise a metal or a metal nitride, such as titanium nitride, cobalt nitride, nickel, or tungsten nitride. A metal filler layer (not shown) may then be deposited on the barrier layer. The metal filler layer may comprise tungsten, ruthenium, cobalt, nickel, or copper. A chemical mechanical polishing process may then be performed to remove excess material, defining the final shape of the drain contact 248 and the dielectric plug 246 and providing a flat surface. In some embodiments, the width W2 of the dielectric plug 246 is greater than the width W3 of the upper surface of the drain contact 248. The aspect ratio of the dielectric plug 246 is less than that of the drain contact 248. In the hypothetical situation where the dielectric plug 246 is not formed to cover the source structure 232S, step 120 will result in the front source contact being located on the source structure 232S. Although the front source contact may have a similar composition to the drain contact 248, it may still be non-functional because the electronic signal is connected to the source structure 232S via the back source contact to be formed. Thus, the front source contact is a dummy source contact. In other words, forming the dielectric plug 246 avoids the need to form a source contact.

[0033] As shown in Figures 1, 16, and 17, step 122 of method 100 forms a drain contact via 251 on the drain contact 248. As shown in Figure 16, a second interlayer dielectric layer 250 is formed on the first interlayer dielectric layer 238. The material and formation method of the second interlayer dielectric layer 250 may be similar to those of the first interlayer dielectric layer 238. Figure 17 shows a cross-sectional view of the workpiece 200 along section line B-B' shown in Figure 2. The drain contact via opening (later filled with drain contact via 251) can pass through the second interlayer dielectric layer 250 to expose a portion of the upper surface of the drain contact 248. As shown in Figure 17, the drain contact via 251 is formed on the drain contact 248 and the drain contact via opening is filled. The drain contact via 251 may include a barrier layer and a metal filler layer located on the barrier layer. The materials and formation methods of the barrier layer and metal filler layer in the drain contact via 251 can be similar to those of the drain contact 248 shown in FIG. 15. A chemical mechanical polishing process is then performed to remove excess material and define the final shape of the drain contact via 251. In some embodiments, the method of this embodiment, such as method 100, does not form any front-side source contact vias. Since the electronic circuitry of the source structure 232S passes through the back-side source contact, any front-side source contact via (if formed) is a dummy source contact via without any function. In some embodiments, to comply with some prior art and reduce costs, the dummy source contact via can be formed together with the drain contact via and located on the dielectric plug 246. The formation method of the dummy source contact via can be similar to the formation method of the drain contact via 251.

[0034] As shown in Figures 1, 18, and 19, step 124 of method 100 forms a gate contact via on the gate structure 210'. As shown in Figure 18, a patterned hard mask layer 252 is formed on the second interlayer dielectric layer 250 to expose a portion of the second interlayer dielectric layer 250. A photoresist layer can be coated on the hard mask layer, and a first photolithography mask is used to pattern the photoresist layer. The patterned photoresist layer is used as an etching mask to pattern the hard mask layer, thus obtaining the patterned hard mask layer 252. Next, during the etching process of forming the gate contact via opening 253 through the second interlayer dielectric layer 250, the first interlayer dielectric layer 238, and the self-aligned capping layer 237, the patterned hard mask 252 is used as an etching mask. As shown in Figure 19, a first gate contact via 254 is formed in the gate contact via opening 253 and electrically connected to the gate layer 213'. The process and materials used to form the first gate contact via 254 can be similar to those used to form the drain contact via 251. In this example, all lower surfaces of the first gate contact via 254 are in direct contact with the gate layer 213'. In some embodiments, the first gate contact via 254 and the drain contact via 251 can be formed simultaneously. In some embodiments, the first gate contact via 254 can be formed before the drain contact via 251.

[0035] As shown in Figure 20, after forming the first gate contact via 254 and the drain contact via 251, a first interconnect structure 256 can be formed on the front side of the workpiece 200. In some embodiments, the first interconnect structure 256 may include multiple intermetallic dielectric layers, and multiple metal lines or contact vias located in each intermetallic dielectric layer. In some examples, the intermetallic dielectric layers and the bottom interlayer dielectric layer 236 may share a similar composition. The metal lines and contact vias in each intermetallic dielectric layer may be composed of metals such as aluminum, tungsten, ruthenium, or copper. Since the first interconnect structure 256 is formed on the front side of the workpiece 200, the first interconnect structure 256 can also be regarded as a front-side interconnect structure.

[0036] As shown in Figures 1 and 21, in step 126 of method 100, the workpiece 200 is flipped and planarized to expose the semiconductor plug 228. A carrier plate 258 is bonded to a first interconnect structure 256. In some embodiments, the carrier plate 258 is bonded to the workpiece 200 by fusion bonding, using an adhesive layer, or a combination thereof. In some embodiments, the carrier plate 258 may comprise a semiconductor material (such as silicon), sapphire, glass, a polymer material, or other suitable material. Once the carrier plate 258 is bonded to the first interconnect structure 256 of the workpiece 200, the workpiece 200 is flipped. The back side of the workpiece 200 is then planarized to expose the semiconductor plug 228.

[0037] As shown in Figures 1 and 22, step 128 of method 100 replaces substrate 202 with a back-side dielectric layer 260. After exposing the semiconductor plug 228, substrate 202 can be selectively removed to form a dielectric opening, and the removal method can be a selective etching process such as a selective wet etching process or a selective dry etching process. The method of selectively removing substrate 202 does not substantially damage the semiconductor plug 228. The dielectric layer 260 can be deposited on the back side of workpiece 200 by a suitable process. In some examples, the composition of dielectric layer 260 can be similar to that of the bottom interlayer dielectric layer 236. A planarization process such as chemical mechanical polishing can be performed to planarize the back side of workpiece 200 and remove excess dielectric layer 260 on semiconductor plug 228.

[0038] As shown in Figures 1, 23, and 24, step 130 of method 100 replaces the semiconductor plug 228 with a back-side source contact 268. As shown in Figure 23, a selective etching process can selectively remove the semiconductor plug 228 without substantially damaging the dielectric layer 260. The etching process stops when the source structure 232S in the back-side source contact opening 262 is exposed from the back side of the workpiece 200. The step of selectively removing the semiconductor plug 228 is a self-aligned step. In one embodiment, the selective etching process may use a mixture of ammonium hydroxide, hydrogen peroxide, and water. As shown in Figure 24, a dielectric barrier layer 264 is deposited on the workpiece 200, and then the dielectric barrier layer 264 is etched back so that it only covers the sidewall of the back-side source contact opening 262 and exposes the source structure 232S. In some embodiments, the dielectric barrier layer 264 may comprise silicon nitride or other suitable materials. A silicate layer 266 can be formed on the exposed surface of the source structure 232S to reduce the contact resistance between the source structure 232S and the desired back-side source contact 268. The silicate layer 266 may comprise nickel silicate, nickel germanide, or nickel germanide silicate. After forming the silicate layer 266, a back-side source contact 268 can be formed in the back-side source contact opening 262. The back-side source contact 268 may comprise aluminum, rhodium, ruthenium, copper, iridium, or tungsten. A planarization process, such as chemical mechanical polishing, can then be performed to remove excess material and provide a flat surface. The back-side source contact 268 can be electrically coupled to the source structure 232S by the silicate layer 266. Since the method of forming the back-side source contact 268 is self-aligned, the width of the back-side source contact 268 (along the X direction) is smaller than the width W2 of the dielectric plug 246.

[0039] As shown in Figures 1 and 25, step 132 of method 100 involves subsequent processes, such as forming a back-side power rail 270. Although not shown in Figure 25, the back-side power rail 270 can be embedded in an insulating layer. In an illustrative process, an insulating layer with a composition similar to the bottom interlayer dielectric layer 236 can be deposited on the back side of the workpiece 200, including deposition on the dielectric layer 260 and the back-side source contact 268. Power rail trenches are then patterned in the insulating layer. The back-side power rail 270 can then be formed in the power rail trenches. The composition and formation method of the back-side power rail 270 can be similar to the composition and formation method of the drain contact 248 shown in Figure 15. A chemical mechanical polishing process can be performed to remove excess material. The formation method and structure of the second interconnect structure 272 can be similar to the formation method and structure of the first interconnect structure 256. Since the second internal connection structure 272 is formed on the back side of the workpiece 200, the second internal connection structure 272 can also be regarded as a back side internal connection structure.

[0040] Figure 26 shows an exemplary top view of the workpiece 200. Since the method for forming the back-side source contact 268 is self-aligned, the back-side source contact 268 is formed below the fin structure 205. Specifically, the back-side source contact 268 is formed below the source structure 232S (not shown). As described above, the method of this embodiment does not form a conductive front-side source contact 248S. Instead, a dielectric plug 246 is formed on the source structure 232S. The width W2 of the dielectric plug 246 is greater than the width of the back-side source contact 268. A first gate contact via 254 is formed on the gate layer 213' and has a width Wg along the X direction. A drain contact via 251 is formed on the drain contact 248. In one embodiment, the centerline 254m of the first gate contact via 254 is aligned with the centerline of the gate structure 210'. The distance D1 between the centerline 254m and the centerline 246m of the dielectric plug 246 is substantially equal to the distance D2 between the centerline 254m and the centerline 248m of the drain contact 248. The first gate contact via 254 and the drain contact 248 have a distance D3 between them. Due to the method of forming the dielectric plug 246, the design flexibility of the first gate contact via 254 is increased because the probability of the first gate contact via 254 being shorted to any front source contact or a front source contact via on it is zero or negligible. Therefore, the tolerance for process errors in lithography, such as the alignment of the photomask, and / or other inaccuracies in forming the gate contact via can be increased. Furthermore, the absence of a front source contact via eliminates the parasitic capacitance between the front source contact via and the first gate contact via 254. All of the above results in better device performance, yield, and reliability.

[0041] As described above, integrated circuit technology is moving towards smaller technology nodes, and the adjacent front source / drain contacts (and / or front source / drain vias) and gate contact vias increase their parasitic capacitance, resulting in leakage current. In the method 100 described above, the dielectric plug 246 is formed directly on the source structure 232S instead of the front source contact. This helps to reduce the parasitic capacitance of the workpiece 200. Since the dielectric plug 246 is formed on the source structure 232S, the arrangement (e.g., position and shape) of the first gate contact via 254 can be adjusted to further improve device performance. For example, the position of the first gate contact via 254 affects the distance between the first gate contact via 254 and the drain contact 248 or drain contact via 251, thus affecting the parasitic capacitance and leakage current. The diameter of the first gate contact via 254 determines the contact area between the first gate contact via 254 and the gate structure 210', thus affecting the parasitic resistance. Increasing the distance between the first gate contact via 254 and the drain contact 248 or drain contact via 251 reduces the parasitic capacitance between these structures. However, it can also reduce the contact area and increase the parasitic resistance.

[0042] Different applications may have varying requirements for parasitic capacitance and resistance in semiconductor devices. For example, high-speed wireless / wired communication applications require lower parasitic capacitance because it adversely limits the high-frequency performance of RF integrated circuits in wireless / wired communication systems. In these applications, reducing parasitic capacitance is more important than reducing parasitic resistance. In applications seeking better DC characteristics, such as electrostatic discharge circuits or input / output circuits, lower parasitic resistance is needed to achieve higher current, and reducing parasitic resistance is more important than reducing parasitic capacitance. Embodiments of this invention, by forming gate contact vias with different configurations (e.g., position or size), can adjust the parasitic resistance and capacitance (and leakage current) associated with the gate contact vias to improve the performance of the semiconductor device.

[0043] Figure 27 shows a flowchart of an exemplary method 300 to confirm the configuration of the gate contact via to be formed at step 124 of method 100. The configuration parameters of the gate contact via affect the parasitic resistance, parasitic capacitance, and leakage current of the workpiece 200. By selecting different photolithography masks to form the gate contact via opening, the configuration of the gate contact via can be confirmed, thus confirming the distance between the gate contact via and the drain contact, as well as the contact area between the gate contact via and the gate structure. By changing the configuration of the gate contact via, the parasitic resistance and parasitic capacitance associated with the gate contact via can be changed according to the application of the final semiconductor device. Method 300 in Figure 27 will be explained in conjunction with Figures 28 to 37.

[0044] As shown in Figure 27, step 302 of method 300 confirms whether a back-side source contact is formed in the workpiece 200. If no back-side source contact is formed in the workpiece 200, step 304 of method 300 is performed to fabricate a front-side source contact 248S (as shown in Figure 26) on the source structure 232S of the workpiece 200, without forming a dielectric plug 246. The material and forming method of the front-side source contact 248S can be similar to the material and forming method of the drain contact 248 shown in Figure 15. In this case, the setting of the gate contact via can be similar to the first gate contact via 254 shown in Figure 18. Additional processes such as forming a front-side interconnect structure can be performed. If the workpiece 200 to be formed does not have a back-side source contact (such as a back-side source contact 268), then step 306 of method 300 is performed to perform method 100, such as forming a dielectric plug 246 and a back-side source contact 268.

[0045] As shown in Figure 27, before fabricating the semiconductor device using method 100, step 308 confirms whether a final structure of the semiconductor device with improved performance compared to workpiece 200 in Figure 25 is being fabricated. Further performance improvements will increase the additional cost of existing fabrication processes. For example, a new photolithography mask may be required to improve performance. If the benefits outweigh the costs, the semiconductor device to be fabricated is confirmed to have improved performance. If the semiconductor device to be fabricated does not require improved performance or the cost of improved performance outweighs the benefits, then step 310 of method 300 is performed to fabricate the semiconductor device using method 100, and a first mask may be used to form the gate contact via opening 253 (and the first gate contact via 254 of workpiece 200 in Figure 25).

[0046] As shown in Figure 27, if it is necessary to improve the performance of the semiconductor device to be manufactured, then steps 312a and 312b of method 300 are performed. In step 312, it is determined whether the semiconductor device to be manufactured needs to have an increased leakage current tolerance range (and / or reduced parasitic capacitance). If it is not necessary to increase the leakage current tolerance range, then method 300 jumps back to step 310. If it is necessary to increase the leakage current tolerance range, then method 300 proceeds to step 314a and uses a second photolithography mask to facilitate the formation of a second gate contact via opening. Compared with the first photolithography mask, the second photolithography mask can be intentionally offset in a stacking manner on the second gate contact via opening. The second gate contact via formed in the second gate contact via opening can have a second configuration. Figures 28 to 32 show other embodiments in which a second photolithography mask is used when forming a workpiece 200A containing a second gate contact via 254a with a second configuration.

[0047] As shown in Figure 28, workpiece 200A includes a second gate contact via 254a, a gate spacer 216a adjacent to the dielectric plug 246, and a gate spacer 216b adjacent to the drain contact 248. The second gate contact via 254a is not only directly formed on the gate structure 210', but also directly located on the gate spacer 216a. In other words, the second gate contact via 254a directly contacts a portion of the upper surface of the gate spacer 216a. The upper surface of the gate spacer 216b does not have the second gate contact via 254a. Due to intentional offset, there is a difference between the centerline of the gate structure 210' and the centerline 254m of the second gate contact via 254a. Figure 29 shows an exemplary layout of workpiece 200A. As shown in Figure 29, the second gate contact via 254a is intentionally offset a distance S towards the dielectric plug 246. The distance S can be less than 0.5 times the width Wg, ensuring that the second gate contact via 254a remains on the gate structure 210'. This prevents unintentional misalignment or other inaccuracies in the second photolithography mask during the lithography process of forming the opening of the second gate contact via. Unintentional misalignment can be less than 0.5 * width Wg, where Wg is the width of the first gate contact via 254. Due to the offset of the second gate contact via 254a, the distance D2 is greater than the distance D1. As shown in Figure 29, the distance D4 between the drain contact 248 and the second gate contact via 254a is greater than the distance D3 (indicated by dashed lines) between the drain contact 248 and the first gate contact via 254a. Increasing the distance from D3 to D4 helps reduce the parasitic capacitance between the second gate contact via 254a and the drain contact 248, and also helps increase the allowable leakage current range.

[0048] In another embodiment shown in FIG30, workpiece 200B includes a gate contact via. With a deliberate increase in stack offset, the gate contact via is formed not only directly on the gate spacer 216a, but also directly on a portion of the dielectric plug 246. FIG31 is an exemplary layout of workpiece 200A. Compared to the layout in FIG29, the distance D2 can be further increased. The parasitic capacitance between the gate contact via and the drain contact 248 in workpiece 200B is smaller than that in workpiece 200A, and the allowable leakage current range can be further increased.

[0049] The gate contact vias are filled into the corresponding gate contact via openings. Before filling the corresponding gate contact via openings, the corresponding gate contact via openings expose the upper surfaces of the gate structure 210', the gate spacer 216', and the dielectric plug 246. The method for forming the corresponding gate contact via openings may include performing an atomic layer etching process to selectively remove the self-aligned capping layer 237, exposing a portion of the upper surface of the gate structure 210' without significantly damaging the gate spacer 216' and the dielectric plug 246. The atomic layer etching process may include a deposition process. The deposition process may use a suitable gas such as hexafluorobutadiene or other suitable materials. An etching process is then performed to etch at least a portion of the self-aligned capping layer 237. This etching process may use a nitrogen-containing gas (such as nitrogen trifluoride) and other carbon- and fluorine-containing gases, or other suitable gases. The deposition and etching processes can be repeated multiple times. In the embodiments shown in Figures 28 to 31, the first gate contact via 254 is offset along the X direction. Besides being offset along the X direction, the first gate contact via 254 can also be offset along the Y direction. In the two other embodiments shown in Figures 32 and 33, the gate contact via is offset along the Y direction. As shown in Figure 32, workpiece 200C includes a gate contact via 254c. The gate contact via 254c directly contacts the bottom interlayer dielectric layer 236, the gate structure 210', and the gate spacer 216a adjacent to the active region. Compared to the gate contact via in Figure 29, the gate contact via 254c is also offset along the Y direction. As shown in Figure 33, workpiece 200D includes a gate contact via 254d. Compared to the first gate contact via 254 in Figure 26, the gate contact via 254d is also offset along the Y direction. The offset along the Y direction can be intentional or unintentional. As described above, significantly reducing the integrated circuit size results in a denser arrangement of source / drain contact vias and gate contact vias. Compared to the method of forming dummy (non-functional) front source contacts 248S and conductive dummy source vias 251S, the method of forming dielectric plugs 246 on the source structure 232S increases the process tolerance and design flexibility of the gate contact vias. It is worth noting that the offset gate contact vias reduce the contact area between the gate contact vias and the gate structure 210'. Therefore, the parasitic resistance of workpiece 200A is greater than that of workpiece 200 in FIG. 26. Another embodiment provides a workpiece with an increased leakage current tolerance and parasitic resistance similar to workpiece 200 in FIG. 26, which will be detailed with reference to FIG. 36 and 37.

[0050] As shown in Figure 27, step 312b confirms whether the fabricated semiconductor device needs to reduce parasitic resistance. If it needs to reduce parasitic resistance, step 314b of method 300 can employ a third photolithography mask to facilitate the formation of a third gate contact via opening. Compared to the first photolithography mask, the third photolithography mask can be used to form a gate contact via opening enlarged on one side. The third gate contact via formed in the third gate contact via opening can have a third configuration. Figures 34 and 35 show, in other embodiments, the use of a third photolithography mask when fabricating a workpiece 200A with a third gate contact via 254e having a third configuration.

[0051] As shown in Figure 34, workpiece 200E includes a third gate contact via 254e. The side of the first gate contact via 254 (as shown in Figures 25 and 26), adjacent to the dielectric plug 246, is enlarged to form the third gate contact via 254e. The enlarged third gate contact via 254e is formed not only directly on the gate structure 210', but also directly on the gate spacer 216a and the dielectric plug 246. In other words, the third gate contact via 254e directly contacts a portion of the upper surface of the dielectric plug 246. Figure 35 shows an exemplary layout of workpiece 200E. Due to the increased size, there is a gap between the centerline of the gate structure 210' and the centerline of the third gate contact via 254e. As shown in Figure 35, the left side of the first gate contact via 254 (adjacent to the dielectric plug 246) is enlarged to form the third gate contact via 254e. The width difference between the third gate contact via 254e and the first gate contact via 254 is less than approximately 0.5 times the gate structure spacing P. The width difference E is chosen such that the increased width of the third gate contact via 254e does not cause significant leakage current between the third gate contact via 254e and the outer gate structure 210' (e.g., one on the left side of the dielectric plug 246). In some embodiments, the width of the increased width of the third gate contact via 254e is greater than the width of the gate structure 210'. Due to the increased width, the contact area between the third gate contact via 254e and the gate structure 210' can be greater than the contact area associated with the first gate contact via 254. Therefore, compared to workpiece 200 in FIG. 27, it is advantageous to reduce the parasitic resistance associated with the gate contact vias of workpiece 200E without substantially sacrificing the allowable leakage current range.

[0052] Figure 36 shows another embodiment that increases the allowable leakage current range without significantly reducing the contact area between the gate contact via and the gate structure (e.g., without significantly increasing parasitic resistance). In this embodiment, the left side of the first gate contact via 254 is enlarged and offset toward the dielectric plug 246 to form the gate contact via 254f in the workpiece 200F. Figure 37 shows an exemplary layout of the workpiece 200F. The distance between the gate contact via 254f and the drain contact 248 increases due to the offset, thus increasing the allowable leakage current range compared to the workpiece 200 in Figure 26. Furthermore, due to the enlargement on the left side, the contact area between the gate contact via 254f and the gate structure 210' is substantially similar to the contact area in the workpiece 200 in Figure 26. Therefore, the allowable leakage current range of the workpiece 200F is increased without significantly changing the parasitic resistance.

[0053] According to embodiments of the present invention, methods 100 and 300 create gate contact vias with different configurations in different device regions. Semiconductor devices in these device regions can be fabricated according to methods 100 and 300 to meet their design requirements. For example, the workpiece 400 shown in FIG38 includes a first device region 400A and a second device region 400B. The first device region 400A and the second device region 400B can be formed on the same substrate or different substrates. In one example, the semiconductor device in the first device region 400A includes a source structure 232S, a front source contact 248S located on the source structure 232S, and a back source contact 268 located below the source structure 232S. Forming the front source contact 248S and the back source contact 268 helps to provide more flexible wiring. The semiconductor device in the second device region 400B includes a source structure 232S, a dielectric plug 246 located in the source structure 232S, and a back-side source contact 268 located below the source structure 232S. Forming the dielectric plug 246 helps increase the design flexibility of the gate contact via. Although the first gate contact via 254 in the figure is in the second device region 400B, it should be understood that other configurations of gate contact vias according to methods 100 and 300 are also feasible.

[0054] For example, the workpiece 500 shown in Figure 39 includes a first device region 500A and a second device region 500B. In one embodiment, the semiconductor device in the first device region 500A includes an offset second gate contact via 254a, which increases the allowable leakage current range of the semiconductor device. The semiconductor device in the second device region 500B includes a single-sided enlarged third gate contact via 254e, which reduces the parasitic resistance of the semiconductor device. Therefore, different regions can be used for different functions.

[0055] In the embodiments shown in Figures 1 to 39, methods 100 and 300 can form dielectric plugs on the source structure of a multi-bridge channel transistor. It should be understood that methods 100 and 300 can also be used for workpieces having dielectric plugs on a drain structure and back-side drain contacts. Embodiments of the present invention can also be used in other multi-gate devices such as finned field-effect transistors.

[0056] This invention provides numerous advantages. For example, it provides a method for forming a semiconductor device with a dielectric plug located on the source / drain structure. This increases the design flexibility of the gate contact via. Therefore, in the lithography process used to form the gate contact via, the tolerance for process errors and / or other inaccuracies in the photomask alignment can be increased. Furthermore, forming the dielectric plug also reduces parasitic capacitance because the front-side source / drain contacts have been replaced with the dielectric plug. All of these methods result in better device performance, yield, and reliability. This invention also provides a method for forming a gate contact via with intentionally offset stacking, which increases the allowable leakage current and reduces parasitic capacitance associated with the gate contact via. Stacking can refer to the alignment phenomenon between multiple components on different layers in a semiconductor device such as an integrated circuit chip. This invention also provides a method for forming a single-sided enlarged gate contact via, which increases the contact area between the gate contact via and the gate structure and reduces parasitic resistance.

[0057] This invention provides many different embodiments. Semiconductor structures and their fabrication methods are disclosed herein. One exemplary embodiment of the invention relates to a semiconductor device. The semiconductor device includes a first source / drain structure located at a first source / drain junction; a second source / drain structure located on a back-side dielectric layer; a plurality of channel components, each extending between the first source / drain structure and the second source / drain structure; a gate structure, engaging the channel components and located on the back-side dielectric layer; a bottom dielectric layer directly located on the second source / drain structure; a first dielectric layer located on the bottom dielectric layer; and an isolation structure extending through the first dielectric layer and directly located on the first source / drain structure. The composition of the isolation structure differs from that of the bottom dielectric layer, and the first source / drain structure is separated from the first dielectric layer by the isolation structure.

[0058] In some embodiments, the semiconductor device may also include a second source / drain contact extending through the first dielectric layer and the bottom dielectric layer and electrically connected to the second source / drain structure; a second dielectric layer located on the first dielectric layer; and a gate contact via extending through the second dielectric layer and the first dielectric layer and directly contacting the gate structure.

[0059] In some embodiments, the semiconductor device may also include a first gate spacer along a first sidewall of the gate structure and in direct contact with the isolation structure; and a second gate spacer along a second sidewall of the gate structure, with the second sidewall opposite to the first sidewall. The distance between the first centerline of the gate contact via and the second source / drain contact is greater than the distance between the first centerline and the isolation structure.

[0060] In some embodiments, the gate contact via may be located on and directly contact the first gate spacer. In some embodiments, the gate contact via may be located on and directly contact the isolation structure. In some embodiments, the first centerline of the gate contact via is offset from the second centerline of the gate structure, the gate structure may have a width W1, and the distance between the first centerline of the gate contact via and the second centerline of the gate structure is less than about 0.5 times the width W1.

[0061] In some embodiments, the upper surface of the isolation structure may have a first width, and the lower surface of the isolation structure may have a second width, wherein the second width is smaller than the first width. The upper surface of the isolation structure and the upper surface of the first dielectric layer may be coplanar, and the lower surface of the isolation structure may directly contact the first source / drain structure. In some embodiments, the isolation structure may include silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonate, or silicon carbonitride.

[0062] Another exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a first gate structure located on a channel region of a first active region; a drain structure located on a drain region of the first active region; a source structure located on a source region of the first active region; a back-side source contact located below the source structure; an isolation structure located on and in contact with the source structure; a drain contact located on and electrically coupled to the drain structure; and a gate contact via located on and electrically coupled to the first gate structure. The distance between the gate contact via and the drain contact is greater than the distance between the gate contact via and the isolation structure.

[0063] In some embodiments, the semiconductor device may also include a first gate spacer along a first sidewall of the first gate structure and adjacent to the source structure; and a second gate spacer along a second sidewall of the first gate structure and adjacent to the drain structure. A gate contact via may be located directly on the first gate spacer. In some embodiments, the gate contact via is located directly on the isolation structure and directly contacts the isolation structure.

[0064] In some embodiments, the semiconductor device may also include a second gate structure located on the channel region of the second active region; a second source structure located on the source region of the second active region; a front source contact located on the second source structure; and another back source contact located below the second source structure.

[0065] In some embodiments, the semiconductor device may also include a second gate structure located on the channel region of the second active region. The first gate structure and the second gate structure are separated by a first gate spacer and an isolation structure.

[0066] In some embodiments, the semiconductor device may also include a bottom dielectric layer on the drain structure; a first dielectric layer on the bottom dielectric layer; and a second dielectric layer on the first dielectric layer. An isolation structure may extend through the first dielectric layer and cover the upper surface of the source structure.

[0067] In some embodiments, the semiconductor device may also include a self-aligned capping layer located on the first gate structure. A gate contact via further extends through the self-aligned capping layer. An isolation structure may also directly contact the self-aligned capping layer. In some embodiments, the aspect ratio of the isolation structure may be smaller than that of the drain contact.

[0068] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes: an active region located on a substrate; a gate structure located on a channel region of the active region; a first source / drain structure located on a first source / drain region of the active region and on a semiconductor plug in the substrate; a second source / drain structure located on a second source / drain region of the active region; and a first dielectric layer including a first portion directly located on the first source / drain structure and a second portion directly located on the second source / drain structure. The method also includes selectively removing a first portion of the first dielectric layer to form an isolation structure opening to expose the first source / drain structure; forming an isolation structure in the isolation structure opening, wherein the composition of the isolation structure is different from the composition of the first dielectric layer; and replacing the semiconductor plug with a back-side source / drain contact.

[0069] In some embodiments, the method may also include forming a source / drain contact opening through the first dielectric layer to expose a second source / drain structure; forming a source / drain contact in the source / drain contact opening; forming a second dielectric layer on the first dielectric layer; forming a via opening through the first and second dielectric layers to expose a gate structure; and forming a contact via in the via opening and directly contacting the gate structure. The distance between the contact via and the source / drain contact is greater than the distance between the contact via and the isolation structure.

[0070] In some embodiments, the workpiece may also include a first gate spacer, laterally adjacent to the isolation structure along a first sidewall of the gate structure, and a second gate spacer, laterally adjacent to the source / drain contacts along a second sidewall of the gate structure. The via opening may also expose at least a portion of the first gate spacer, and the contact via may directly contact the first gate spacer.

[0071] In some embodiments, the through-hole opening may also expose a portion of the isolation structure, and the contact through-hole may also directly contact the isolation structure.

[0072] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0073] A-A',B-B': hatching line D1, D2, D3, D4, S: Distance P: Gate structure spacing Wg,W1,W2,W2',W3: Width 100, 300: Method 102,104,106,108,110,112,114,116,118,120,122,124, 126,128,130,132,302,304,306,308,310,312,312a,312b,314a,314b: Steps 200, 200A, 200B, 200C, 200D, 200E, 200F, 400, 500: Workpiece 202:Substrate 204: Isolation Structure 205: Fin-like structure 205C: Passage Area 205S / D: Source / Drain Region 206: Sacrifice Layer 207: Vertical stacking 208: Channel Layer 210: Virtual Gate Stacking 210': Gate structure 212: Virtual Dielectric Layer 212': Dielectric layer 213: Virtual Gate Layer 213': Gate layer 214,240: Hard mask layer 214a: Silicon oxide layer 214b: Silicon nitride layer 216, 216', 216a, 216b: Gate spacers 216s: Sidewall 218D: Drain Opening 218S: Source Opening 220: Inner spacer structure 222: Masking film 224: Photoresist layer 226,242: Opening 228: Semiconductor plug 232D: Drain structure 232S: Source structure 234: Contact Etching Stop Layer 236: Bottom interlayer dielectric layer 237: Self-aligned cap layer 238: First interlayer dielectric layer 244: Dielectric plug opening 246,246': Dielectric plug 246m, 248m, 254m: Centerline 247: Silicon layer 248: Drain contact 248S: Front-side source contact 250: Second interlayer dielectric layer 251: Drain contact through hole 251S: Virtual Source Via 252: Patterned hard mask 253: Gate contact through-hole opening 254: First gate contact through hole 254a: Second gate contact through hole 254b, 254c, 254d, 254f: Gate contact through holes 254e: Third gate contact through hole 256: First Intra-connection Structure 258: Carrier board 260: Dielectric layer 262: Backside source contact opening 264: Dielectric barrier layer 266: Silicon layer 268: Backside source contact 270: Rear power rail 272: Second Inner Connection Structure 400A, 500A: First Device Area 400B, 500B: Second Unit Area

Claims

1. A semiconductor device, comprising: A first source / drain structure is located on a first source / drain junction; a second source / drain structure is located on a back-side dielectric layer; a plurality of channel components extend between the first source / drain structure and the second source / drain structure; a gate structure is connected to the channel components and located on the back-side dielectric layer; a bottom dielectric layer is located directly on the second source / drain structure; a first dielectric layer is located on the bottom dielectric layer; and an isolation structure extends through the first dielectric layer and is located directly on the first source / drain structure, wherein the composition of the isolation structure is different from that of the bottom dielectric layer, and the first source / drain structure is separated from the first dielectric layer by the isolation structure.

2. The semiconductor device as described in claim 1, further comprising: A second source / drain contact extends through the first dielectric layer and the bottom dielectric layer and is electrically connected to the second source / drain structure; A second dielectric layer is located on the first dielectric layer; and a gate contact via extends through the second dielectric layer and the first dielectric layer and directly contacts the gate structure.

3. A semiconductor structure, comprising: A first gate structure is located on the channel region of a first active region; A drain electrode structure is located on the drain electrode region of the first active region; A source structure is located on the source region of the first active region; a back-side source contact is located below the source structure; an isolation structure is located on the source structure and contacts the source structure; a drain contact is located on the drain structure and electrically coupled to the drain structure; and a gate contact via is located on the first gate structure and electrically coupled to the first gate structure, wherein the distance between the gate contact via and the drain contact is greater than the distance between the gate contact via and the isolation structure.

4. A semiconductor structure, comprising: An active region is located on a substrate; A source / drain structure is located on the source / drain region of the active region; a gate structure is located on the channel region of the active region; a back-side source / drain contact is located below the source / drain structure and electrically coupled to the source / drain structure; an isolation structure is located on the source / drain structure; a gate spacer is located between the gate structure and the isolation structure; and a gate contact via is located on the gate structure and electrically coupled to the gate structure, wherein the gate contact via directly contacts the upper surface of the gate spacer, and wherein the upper surface of the isolation structure is higher than the upper surface of the gate spacer.

5. A method for forming a semiconductor structure, comprising: The method includes receiving a workpiece comprising: a gate structure located on a channel region protruding from a substrate; and a first source / drain structure and a second source / drain structure coupled to the channel region; forming a first dielectric structure directly located on the first source / drain structure and the second source / drain structure, wherein the upper surface of the first dielectric structure is coplanar with the upper surface of the gate structure; forming a second dielectric structure on the first dielectric structure; and forming a dielectric structure extending through the second dielectric structure and the first dielectric structure to directly contact the first source / drain structure, wherein the composition of the dielectric structure is different from the composition of the first dielectric structure and the second dielectric structure. A first source / drain contact is formed, the first source / drain contact being directly located under the first source / drain structure and electrically coupled to the first source / drain structure; and a second source / drain contact is formed to extend through the second dielectric structure and the first dielectric structure and be electrically coupled to the second source / drain structure.

6. A method for forming a semiconductor structure, comprising: A first dielectric structure is formed on a first source / drain structure in a first source / drain recess; A second dielectric structure is formed on the first dielectric structure; the first dielectric structure and the second dielectric structure are patterned to form a first opening to expose all the upper surfaces of the first source / drain structure; a dielectric structure is formed in the first opening; and a first source / drain contact is formed, wherein the first source / drain contact is directly located under the first source / drain structure.

7. A method for forming a semiconductor structure, comprising: The method involves receiving a workpiece, the workpiece comprising: an active region located on a substrate; a gate structure located on a channel region of the active region; a first source / drain structure located on the first source / drain region of the active region and on a semiconductor plug in the substrate; a second source / drain structure located on the second source / drain region of the active region; and a first dielectric layer comprising a first portion directly located on the first source / drain structure and a second portion directly located on the second source / drain structure; selectively removing the first portion of the first dielectric layer to form an isolation structure opening to expose the first source / drain structure; forming an isolation structure in the isolation structure opening, wherein the composition of the isolation structure is different from the composition of the first dielectric layer; and replacing the semiconductor plug with a back-side source / drain contact.

8. A semiconductor structure, comprising: A first source / drain structure and a second source / drain structure are located on a substrate; A dielectric structure is located on the first source / drain structure and the second source / drain structure; an isolation structure extends through the dielectric structure and is located directly on the first source / drain structure; and a source / drain contact extends through the dielectric structure to be coupled to the second source / drain structure, wherein the isolation structure in the top view has a first width, the source / drain contact has a second width, and the second width is smaller than the first width.

9. A semiconductor structure, comprising: A single source / drain structure is located on a substrate; A dielectric structure is located on the source / drain structure; a dielectric material extends through the dielectric structure and is located on the source / drain structure; and a conductive via is located below the source / drain structure, wherein the dielectric material is wider than the conductive via in the layout diagram.

10. A semiconductor structure comprising: Multiple nanostructures are located on a substrate; A gate structure is located on and covers each of the nanostructures; a source / drain structure is coupled to the nanostructures; a conductive structure is located below the source / drain structure and electrically coupled to the source / drain structure; and a gate via is perpendicularly overlapped with the gate structure and electrically coupled to the gate structure, wherein the centerline of the gate via is offset from the centerline of the gate structure.

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