Semiconductor package and method of forming same

Abstract

In one embodiment, a semiconductor package and a method of forming the same include attaching a first package assembly to a first carrier, the first package assembly comprising: an aluminum pad located near a substrate; a sacrificial pad located near the substrate, the sacrificial pad comprising a primary surface opposite to the substrate, the protrusion of the sacrificial pad extending from the primary surface; and a dielectric bonding layer located around the aforementioned aluminum pad and sacrificial pad; attaching a second carrier to the first package assembly and the first carrier, the first package assembly being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bonding layer to include a top surface coplanar with the protrusion; and etching a portion of the protrusion.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging and its forming method. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, these improvements in integration density stem from iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for ever-shrinking electronic devices grows, so does the demand for packaging technologies for smaller and more innovative semiconductor dies. One example of such a packaging system is Package-on-Package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology typically enables the production of semiconductor devices with enhanced functionality and small size on printed circuit boards (PCBs). Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor packaging method includes: attaching a first packaging assembly to a first carrier, the first packaging assembly comprising: an aluminum pad located near a substrate; a sacrificial pad located near the substrate, the sacrificial pad including a main surface opposite to the substrate, a protrusion of the sacrificial pad extending from the main surface; and a dielectric bonding layer located around the aluminum pad and the sacrificial pad; attaching a second carrier to the first packaging assembly and the first carrier, the first packaging assembly being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bonding layer to include a top surface coplanar with the protrusion; and etching a portion of the protrusion.

[0004] According to an embodiment of the present invention, a semiconductor packaging method includes: performing a circuit probe test on a first package assembly, the first package assembly including an aluminum pad and a sacrificial pad located above a substrate; the method of performing the circuit probe test includes: physically coupling a probe to the sacrificial pad; and connecting a power signal or a ground signal to the sacrificial pad, wherein after connecting the power signal or the ground signal to the sacrificial pad, the sacrificial pad includes a protrusion extending upward from a first top surface of the sacrificial pad; forming a first dielectric bonding layer over the substrate, the aluminum pad and the sacrificial pad of the first package assembly, the first dielectric bonding layer including a second top surface opposite to the substrate; planarizing the first dielectric bonding layer, the planarization exposing the protrusion of the sacrificial pad; and performing a wet etching process to remove an upper portion of the protrusion.

[0005] According to an embodiment of the present invention, a semiconductor package includes: a semiconductor substrate located above a package assembly; a silicon via extending through the entire semiconductor substrate and electrically connected to the package assembly; an interconnect structure located above the semiconductor substrate and electrically connected to an integrated circuit element on a surface of the semiconductor substrate; a first aluminum pad located above the semiconductor substrate and electrically connected to the interconnect structure, the first aluminum pad including: a top primary surface opposite to the semiconductor substrate; a first groove extending toward the semiconductor substrate; and a protrusion extending away from the semiconductor substrate; a second aluminum pad located above the semiconductor substrate and electrically connected to the silicon via; a first dielectric bonding layer located above and around the first aluminum pad and the second aluminum pad; and a passivation layer located above the first aluminum pad and in physical contact with the protrusion. Simple Explanation of the Diagram

[0006] The following detailed description, taken in conjunction with the accompanying drawings, is the best way to understand the nature of this disclosure. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1-5, 6A, 6B, 7A, 7B and 8-12 illustrate cross-sectional views of an intermediate stage in forming a semiconductor package according to some embodiments. Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first member on or above a second member may include embodiments in which the first and second members are in direct contact, and may also include embodiments in which an additional member may be formed between the first and second members such that the first and second members are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "up," and similar terms may be used herein to describe the relationship between one element or component and another element or component(s), as illustrated in the figures. In addition to the directions depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0010] This document provides a semiconductor package and a method for forming the same. According to some embodiments of this disclosure, a first package assembly is formed in a wafer, and the first package assembly includes integrated circuitry, through-silicon vias (TSVs), and aluminum pads. Some of the aluminum pads, electrically connected to the integrated circuitry, are used for circuit probe testing to identify known good dies (KGDs) within the wafer. Due to the circuit probe testing, grooves and protrusions are formed in the aluminum pads. After the aluminum pads are encapsulated in a dielectric bonding layer, the KGDs can be separated, flipped, and attached to the first wafer. One or more other package assemblies can then be attached and connected to the first package assembly, and the structure can then be flipped for subsequent processing (e.g., forming conductive connections). For example, a first carrier is removed, and the dielectric bonding layer of the first package assembly is planarized. Planarization may reach the protrusions of the aluminum pads, which may (e.g., conductive material) cause contamination of the protrusions on the dielectric bonding layer. Therefore, an etching process can be used to remove the contamination of the protrusions from the top of the dielectric bonding layer, as well as to etch away any exposed protrusions. Dielectric layers can then be formed on the dielectric bonding layers, and conductive connections can be formed through these dielectric layers for connection with other aluminum pads. Removing smudges and reducing the height of protrusions improves the reliability and yield of the semiconductor package in subsequent processing, thereby reducing manufacturing costs. Furthermore, the removed and reduced portions will improve the reliability of the completed semiconductor package during operation.

[0011] The embodiments discussed herein are examples of how the subject matter of this disclosure can be made or used, and those skilled in the art will readily understand that modifications may be made within the scope of consideration in different embodiments. In the various viewing and illustrative embodiments, reference numerals are used, for example, to designate the same elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0012] Figures 1-5, 6A-7B, and 8-12 illustrate cross-sectional and perspective views of intermediate stages in the semiconductor packaging manufacturing process, including wafer acceptance testing (WAT) and process control monitoring (PCM) processes, as well as subsequent steps in the manufacturing process to further improve efficiency and quality.

[0013] In Figure 1, the first package assembly 40 is formed, for example, in a wafer (not shown separately). According to some embodiments, the first package assembly 40 is an individual component die, which encapsulates one or more component dies, including system-on-chip (SoC) dies containing multiple integrated circuits (or component dies) integrated into a system. The component dies in the first package assembly 40 may be or may include the following dies: logic dies, memory dies, input / output dies, integrated passive devices (IPDs), etc., or combinations thereof. For example, the logic component dies in the first package assembly 40 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory chips in the first packaging component 40 may include Static Random Access Memory (SRAM) chips, Dynamic Random Access Memory (DRAM) chips, etc. The component chips in the first packaging component 40 may include a semiconductor substrate and interconnect structures.

[0014] According to some embodiments, the first package assembly 40 may include a substrate 41, which includes a semiconductor substrate 42 (e.g., a silicon substrate), integrated circuit elements (not shown separately) on the front surface of the semiconductor substrate 42, and a multilayer dielectric layer 44 formed on the semiconductor substrate 42 and the integrated circuit elements. The integrated circuit elements may include active elements, passive elements, etc. The substrate 41 of the first package assembly 40 also includes through-silicon vias (TSVs) 46 and interconnect structures 48. In some embodiments, the interconnect structure 48 may include sealing rings, such as sealing rings around conductive elements embedded in the multilayer dielectric layer 44. For example, the outer periphery of these conductive elements may be electrically separable from the rest of the interconnect structure 48 and the integrated circuit elements. The TSV 46 may extend partially through the semiconductor substrate 42 and partially through the multilayer dielectric layer 44.

[0015] Interconnection structure 48 is located above the front side of semiconductor substrate 42 and embedded in multilayer dielectric layers 44. Interconnection structure 48 includes metal lines and vias that are electrically connected to integrated circuit devices. As shown, interconnection structure 48 includes multiple metal line levels, wherein one or more metal lines 48U can be coupled to corresponding TSVs 46.

[0016] Metal pads 50 / 52, comprising aluminum pad 50 and sacrificial pad 52, are located above substrate 41 (e.g., on multilayer dielectric layer 44) and electrically connected to the upper metalline 48U of interconnect structure 48 through conductive via 54. Aluminum pad 50 will facilitate external electrical connection during operation of the first package assembly 40, and sacrificial pad 52 will provide external electrical connection during circuit probe testing of the first package assembly (see FIG. 2). Aluminum pad 50 and sacrificial pad 52 may have the same composition, such as containing aluminum, aluminum-copper alloy (e.g., containing up to 1% copper by volume), or any suitable material. Aluminum pad 50 and sacrificial pad 52 may each have a height H1 on substrate 41, ranging from 1.2 micrometers (μm) to 3.0 micrometers. Dielectric layer 56 may be coated on metal pads 50 / 52 for protection, such as against oxidation. For example, dielectric layer 56 may be an anti-reflective coating (ARC) and may contain oxides or nitrides, such as silicon oxynitride (SiON), silicon carbide (SiC), or any suitable material.

[0017] In some embodiments, aluminum pad 50 and sacrificial pad 52 (e.g., metal pads 50 / 52) are formed simultaneously on substrate 41. For example, a sacrificial material (not shown) may be formed on substrate 41 first. An opening is formed in the sacrificial material by initially applying a photoresist to the top surface of the sacrificial material and patterning it using photolithography. The patterned photoresist is then used as an etching mask to etch the opening in the sacrificial material and expose portions of substrate 41 (e.g., conductive vias 54). To form the opening, the sacrificial material can be etched using a suitable process, such as dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. In other embodiments, the sacrificial material itself is a photoresist, and an energy source (e.g., ultraviolet light) is irradiated through a photomask to alter the chemical properties (e.g., solubility) of the energy-impacted sacrificial material regions. To form the opening, these regions of the sacrificial material can be etched using a suitable process, such as an isotropic wet etching process.

[0018] The openings within the sacrificial material are filled with a conductive material to form pads 50 / 52. In one embodiment, the conductive material may comprise a seed layer and a flat metal (not shown separately). The seed layer may cover the exposed top surface of the substrate 41 and may comprise, for example, a copper layer. The seed layer may be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), depending on the desired material. The flat metal may be deposited on the seed layer using electroplating processes such as electroplating or electroless plating. The flat metal may comprise aluminum, aluminum-copper alloys, etc. In some embodiments, the sacrificial material and pads 50 / 52 may be planarized, for example, using chemical mechanical polishing (CMP) or grinding processes. The photoresist, sacrificial material, and portions of the seed layer not formed with conductive material are removed. The photoresist and / or sacrificial material may be removed by one or more acceptable ashing or stripping processes, such as using oxygen plasma. Subsequently, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process. The remainder of the conductive material (e.g., seed layer and flat metal) forms pad 50 / 52.

[0019] Although only one aluminum pad 50 and one sacrificial pad 52 are shown, it should be understood that each first package assembly 40 includes multiple metal pads 50 / 52 of each type. Some aluminum pads 50 may be connected to the TSV 46 via upper metal lines 48U. Some aluminum pads 50 may be connected to integrated circuit elements on the surface of the semiconductor substrate 42 via interconnect structures 48. Furthermore, some sacrificial pads 52 may be connected to corresponding aluminum pads 50, which are connected to integrated circuit elements via upper metal lines 48U of interconnect structures 48.

[0020] In Figure 2, a first wafer acceptance test (WAT) is performed on the first package assembly 40, such as a circuit probe test, to determine whether the first package assembly 40 is a known good die (KGD). The first package assembly 40 can be tested using one or more probes 62. The probes 62 are physically and electrically coupled to the sacrificial pads 52 via, for example, resolderable test connectors. Although not specifically stated, multiple probes 62 (e.g., two probes 62) can be coupled to corresponding sacrificial pads 52 (e.g., two sacrificial pads 52). Only wafers of the first package assembly 40 with KGD will proceed to the next processing and packaging, while wafers of the first package assembly 40 that fail the circuit probe test will not proceed to the next processing and packaging. This test may include providing power, ground, and signal voltages to the sacrificial pads 52 to test the functionality of various components of the first package assembly 40 (e.g., integrated circuit elements 48 and interconnect structures 48 therein). In some embodiments, circuit probe testing may include testing for known open or short circuits, which may be anticipated based on the design of the integrated circuitry within the first package assembly 40. In some embodiments, after testing is complete, probe 62 is removed, and any excess resolderable material on the sacrificial pad 52 may be removed by processes such as etching, chemical mechanical polishing (CMP), or grinding.

[0021] As described above, some of the sacrificial pads of sacrificial pad 52, after being tested by circuit probes, can be electrically connected to integrated circuit elements located on the semiconductor substrate 42 via interconnect structure 48. The upper metal lines 48U of the interconnect structure can electrically connect some of the aluminum pads of aluminum pad 50 to these sacrificial pads of sacrificial pad 52. Therefore, these sacrificial pads of sacrificial pad 52 are electrically connected to integrated circuit elements for circuit probe testing, and these aluminum pads of aluminum pad 50 are also electrically connected to integrated circuit elements to fulfill the functional purpose of the semiconductor package.

[0022] As shown in the figure, circuit probe testing may cause deformation of the sacrificial pad 52, for example, forming probe marks in the sacrificial pad 52. For example, probe marks may include grooves 52R (e.g., caused by physical contact with probe 62) and corresponding protrusions 52P in the sacrificial pad 52 (e.g., caused by material displacement of the sacrificial pad 52 due to physical contact with probe 62). Thus, the depth D1 of the groove 52R can reach 1.1 micrometers. Furthermore, the protrusion 52P represents a vertical displacement of the material of the sacrificial pad 52 to a height H2 above the top main surface of the sacrificial pad 52, which can reach a maximum of 1.2 micrometers but is less than the height H1. Additionally, circuit probe testing may cause the dielectric layer 56 located in the grooves 52R and protrusions 52P of the sacrificial pad 52 to be displaced or removed, while the dielectric layer 56 remains on other portions of the sacrificial pad 52 and the aluminum pad 50.

[0023] In Figure 3, a dielectric bonding layer 58 is formed on the aluminum pad 50 and sacrificial pad 52 of the first package assembly 40. The dielectric bonding layer 58 can be a single homogeneous layer or a composite layer of two or more layers, comprising, for example, oxides and / or nitrides, such as silicon oxide (SiO₂), silicon oxynitride (SiON), silicon nitride (SiN), or any suitable material. The dielectric bonding layer 58 can be formed using spin coating, flowable chemical vapor deposition (FCVD), or the like. The dielectric bonding layer 58 forms a top surface having a protrusion 52P that is higher than the sacrificial pad 52. According to some embodiments, after the dielectric bonding layer 58 is formed, the individual first package assemblies 40 are separated from the wafer using any suitable sawing process so that the KGDs of the first package assemblies 40 undergo subsequent processing and packaging as described below.

[0024] In Figure 4, the separated first package assembly 40 is bonded to the first carrier 20 via an oxide-oxide bonding process, such as fusion. Although only one first package assembly 40 is shown, multiple first package assemblies 40 (e.g., KGDs) may be bonded to the first carrier 20. These multiple first package assemblies 40 may be physically separate individual package assemblies, and the bonding process is die-to-wafer bonding. In embodiments not shown, where the first package assembly 40 is not initially separated, the first package assembly 40 may be within an uncuttered wafer, and the bonding process is wafer-to-wafer bonding.

[0025] The first carrier 20 includes a base carrier 22 and one or more dielectric bonding layers 24. In some embodiments, the base carrier 22 may be a wafer and may be formed of the same material as the semiconductor substrate 42 in the overlying first packaging assembly 40, thereby reducing warpage caused by mismatch in coefficients of thermal expansion (CTE) during subsequent packaging processes. For example, the base carrier 22 may be formed of silicon or a silicon-containing material, or other materials such as laminates, ceramics, glass, silicate glass, etc., may be used. According to some embodiments, the entire base carrier 22 is formed of a homogeneous material and does not contain any other material different from the homogeneous material therein. For example, the entire base carrier 22 may be formed of silicon (doped or undoped) and does not contain any metal regions, dielectric regions, etc.

[0026] Before attaching the first encapsulation component 40 to the first carrier 20, a dielectric bonding layer 24 is deposited on the substrate carrier 22. The dielectric bonding layer 24 may comprise oxide-based materials (or silicon oxide-based materials) such as silicon oxide (SiO), phospholipid glass (PSG), borosilicate glass (BSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), nitride-based materials such as silicon nitride (SiN), and oxynitride-based materials such as silicon oxynitride (SiON). It may also be formed from other materials, such as silicon carbide (SiOC), silicon carbonitride (SiCN), etc., or contain the aforementioned other materials. The dielectric bonding layer 24 may be formed using spin coating, FCVD, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or combinations thereof. For example, in some embodiments, the dielectric bonding layer 24 may be a bottom layer containing oxides (e.g., close to the substrate carrier 22), one or more intermediate layers containing nitrides and / or oxide oxynitrides, and an top layer containing oxide oxynitrides (e.g., with a lower nitrogen-to-oxygen ratio compared to the intermediate layers) (e.g., far from the substrate carrier 22). Although not specifically described, alignment marks may be formed in the dielectric bonding layer 24 (e.g., the topmost layer) using any suitable method.

[0027] According to some embodiments, bonding the first encapsulation assembly 40 to the first carrier 20 includes pretreating the dielectric bonding layers 24 and 58 in a process gas containing oxygen (O2) and / or nitrogen (N2), performing a pre-bonding process to connect the dielectric bonding layers 24 and 58 together, and performing an annealing process after the pre-bonding process. According to some embodiments, in the pre-bonding process, the first encapsulation assembly 40 contacts the first carrier 20, and pressure is applied to press the first encapsulation assembly 40 against the first carrier 20. The pre-bonding process can be performed at room temperature (in the range of 20°C to 25°C) or at higher temperatures.

[0028] Following the pre-bonding process, an annealing process is performed. A chemical bond, such as a silicon-oxygen-silicon (Si-O-Si) bond, can be formed between dielectric bonding layers 24 and 58, allowing them to bond together with high bonding strength. According to some embodiments, the annealing process is performed at a temperature range of 200°C to 400°C. The annealing time may be between 30 and 60 minutes.

[0029] In Figure 5, after the first encapsulation assembly 40 is attached to the first carrier 20, a liner 30 and a gap filler 32 are formed on the first encapsulation assembly 40 and the first carrier 20 to encapsulate the first encapsulation assembly 40. The liner 30 may be a conformal layer extending along the top surface and sidewalls of the first encapsulation assembly 40 and along the top surface of the dielectric bonding layer 24. The liner 30 may also be referred to as a moisture barrier, and in some embodiments, the liner 30 serves as an etch stop layer in subsequent steps. The liner 30 may be formed of a dielectric material that has good adhesion to the sidewalls of the first encapsulation assembly 40. For example, the liner 30 may be formed of an extra-low-k (ELK) material, comprising, for example, silicon nitrides and / or oxides such as silicon oxide. The deposition of the liner 30 may include conformal deposition processes such as ALD, CVD, or any suitable process. The gap filler 32 may be formed of molding compounds, epoxy resins, resins, and / or the like. For example, the gap filler material 32 may contain, for example, silicon nitride nitride and / or, for example, silicon oxide oxide, and may be formed using spin coating, FCVD, PECVD, LPCVD, ALD or any suitable process deposition.

[0030] Then, a planarization process, such as CMP and / or mechanical polishing, is performed to remove portions of the liner 30 and spacer filler 32 from above the back surface of the first package assembly 40 (the top surface as illustrated). The planarization process can continue to thin portions of the semiconductor substrate 42 until the TSV 46 is exposed. After the planarization process, the semiconductor substrate 42 may be coplanar with the top surface of the liner 30 and spacer filler 32 (within the range of process variations).

[0031] In Figures 6A and 6B, a dielectric bonding layer 34 and bonding pads 35 are formed over the back side of the first package assembly 40 (e.g., the back surface of the semiconductor substrate 42). In some embodiments, the dielectric bonding layer 34 may initially be deposited using any suitable method, such as ALD, CVD, etc. The dielectric bonding layer 34 is then patterned to form openings that are filled with a conductive material to form the bonding pads 35, similar to how the bonding pads 35 are formed as described above for the metal pads 50 / 52.

[0032] Figure 6B illustrates an embodiment in which a dielectric bonding layer 34 and bonding pads 35 are formed over a semiconductor substrate 42 and a TSV 46 prior to the formation of the liner 30 and the gap filler material 32. In some such embodiments, the dielectric bonding layer 34 and bonding pads 35 may be formed before the first package assembly 40 is separated and attached to the first carrier 20 (see Figure 4). Thus, the dielectric bonding layer 34 and bonding pads 35 can be considered part of the first package assembly 40. After the liner 30 and gap filler material 32 are formed, a planarization process, such as a CMP process and / or a mechanical polishing process, is performed to remove portions of the liner 30 and gap filler material 32 from the back surface of the first package assembly 40. The planarization process may continue until the bonding pads 35 and the dielectric bonding layer 34 are exposed. As shown, after the planarization process, the liner 30 and gap filler material 32 may be coplanar with the dielectric bonding layer 34 and bonding pads 35 (within the range of process variations).

[0033] In Figures 7A-7B, the second encapsulation component 70 is connected to the first encapsulation component 40. Figure 7A illustrates the connection with the structure illustrated in Figure 6A, and Figure 7B illustrates the connection with the structure illustrated in Figure 6B. It is worth noting that the following figures illustrate the subsequent processing steps performed on the structure of Figure 7A; however, those skilled in the art will understand how these subsequent processing steps will also apply to the structure of Figure 7B.

[0034] The second package assembly 70 may include a second package assembly 70A having integrated circuitry and a second package assembly 70B serving as a dummy package assembly. For example, the second package assembly 70A may be attached via a hybrid bonding process, and the second package assembly 70B may be attached via an oxide-oxide bonding process (e.g., fusion bonding). Although only one of the second package assemblies 70A and one of the second package assemblies 70B is schematically illustrated, multiple second package assemblies 70A and / or multiple second package assemblies 70B may be attached to the first package assembly 40. The multiple second package assemblies 70A / B may be physically separate individual package assemblies (e.g., separated from their respective wafers).

[0035] According to some embodiments, the second package component 70A may be the same as, similar to, or different from the first package component 40. For example, the second package component 70A may be an individual component die, which encapsulates one or more component dies, such as a system-on-a-chip (SoC) die containing multiple integrated circuits (or component dies) integrated into a system. The component dies in the second package component 70A may be or may include the following types of dies: logic dies, memory dies, input / output dies, integrated passive components (IPDs), or combinations thereof. For example, the logic component dies in the second package component 70A may be central processing unit (CPU) dies, graphics processing unit (GPU) dies, mobile application dies, microcontroller unit (MCU) dies, baseband (BB) dies, application processor (AP) dies, etc. The memory dies in the second package component 70A may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, etc. The component dies in the second package component 70A may include a semiconductor substrate and interconnect structures.

[0036] According to some embodiments not specifically described, the second package assembly 70A may include features similar to those described in the first package assembly 40 above. For example, the second package assembly 70A may include a semiconductor substrate, integrated circuit elements, and multiple dielectric layers formed on the semiconductor substrate and the integrated circuit elements. The aforementioned integrated circuit elements may include active elements, passive elements, etc. The second package assembly 70A may also include a dielectric bonding layer 76, wherein bonding pads 77 are embedded within the dielectric bonding layer 76.

[0037] According to some embodiments, the second package component 70B may be a dummy package component, which does not contribute to the integrated circuit function and / or is electrically isolated from the first package component 40 and the second package component 70A. The second package component 70A may provide structural support for the semiconductor package and heat dissipation from the first package component 40 and / or the second package component 70A during the operation of the semiconductor package.

[0038] Referring again to Figures 7A-7B, in some embodiments, a dielectric bonding layer 36 and a bonding pad 37 may be formed over the dielectric bonding layer 34 and the bonding pad 35 before the second package assembly 70A / B is attached to the first package assembly 40. The dielectric bonding layer 36 and the bonding pad 37 may be formed in a manner similar to that described above for the dielectric bonding layer 34 and the bonding pad 35.

[0039] The bonding of the second package assembly 70A to the first package assembly 40 can be achieved via hybrid bonding, wherein both metal-to-metal direct bonding (bonding between bonding pads 37 and 77 or between bonding pads 37 and 35, if bonding pad 37 is formed on the second package assembly 70A prior to bonding) and dielectric-to-dielectric bonding (e.g., silicon-oxygen-silicon bonding between surface dielectric bonding layers 36 and 76 or bonding between dielectric bonding layers 36 and 34, if dielectric bonding layer 36 is formed on the second package assembly 70A prior to bonding) are formed. Furthermore, one or more second package assemblies 70A can be bonded to the same first package assembly 40. Multiple second package assemblies 70A bonded to the same first package assembly 40 can be identical or different from each other.

[0040] According to some embodiments, dielectric bonding layer 76 is bonded to dielectric bonding layer 36 via dielectric-to-dielectric bonding without the use of any adhesive material (e.g., die attachment film). Similarly, bonding pad 77 is bonded to pad 37 via metal-to-metal bonding without the use of any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. In the pre-bonding process, a small pressure is applied to press the second package assembly 70A against the first package assembly 40. Pre-bonding is performed at a low temperature, such as room temperature, for example, in the temperature range of 15°C to 30°C, and after pre-bonding, dielectric bonding layer 76 and dielectric bonding layer 36 are bonded to each other. The bond strength is then increased in a subsequent annealing step, wherein dielectric bonding layer 76 and dielectric bonding layer 36 are annealed at a high temperature, for example, in the temperature range of 100°C to 450°C. After annealing, a bond is formed between dielectric bonding layer 76 and dielectric bonding layer 36, for example, by fusion. For example, the aforementioned bonding can be a covalent bonding between the materials of dielectric bonding layer 76 and dielectric bonding layer 36. Bonding pads 77 and 37 are connected to each other in a one-to-one correspondence. Bonding pads 77 and 37 can be made into physical contact after pre-bonding, or they can be expanded during annealing to achieve physical contact. Furthermore, during the annealing process, the materials of bonding pads 77 (e.g., copper) and bonding pads 37 (e.g., copper) are mixed together, thus also forming a metal-to-metal bonding. Therefore, the bonding obtained between the second package assembly 70A and the first package assembly 40 is a hybrid bonding, which includes both dielectric-to-dielectric bonding and metal-to-metal bonding.

[0041] The bonding of the second package assembly 70B to the first package assembly 40 can be performed before, after, or at various points on the second package assembly 70A. The bonding of the second package assembly 70B is achieved via oxide-oxide bonding, wherein a dielectric-to-dielectric bonding is formed (e.g., a silicon-oxygen-silicon bonding between surface dielectric bonding layers 36 and 78). Furthermore, one or more second package assemblies 70B can be bonded to the same first package assembly 40. Multiple second package assemblies 70B bonded to the same first package assembly 40 can be identical or different from each other.

[0042] After the second encapsulation assembly 70A / B is attached to the first encapsulation assembly 40, a liner 80 and a gap filler material 82 are formed above and between the second encapsulation assembly 70A / B to encapsulate the second encapsulation assembly 70A / B. The liner 80 may be a conformal layer extending along the top surface and sidewalls of the second encapsulation assembly 70 and along the top surface of the dielectric bonding layer 36, and may serve as a moisture barrier. The liner 80 may be formed of a dielectric material having good adhesion to the sidewalls of the second encapsulation assembly 70. For example, the liner 80 may be formed of an ultra-low k (ELK) material, comprising, for example, silicon nitrides and / or oxides such as silicon oxide. The deposition of the liner 80 may include conformal deposition processes such as ALD, CVD, or any suitable process. The gap filler material 82 may be formed of molding compounds, epoxy resins, resins, and / or the like. For example, the gap filler material 82 may comprise nitrides such as silicon nitrides and / or oxides such as silicon oxide. For example, the liner 80 and the gap filler 82 can be formed in a manner similar to that described above for the formation of the liner 30 and the gap filler 32.

[0043] The liner 80 and the gap filler 82 can be planarized to become flush with the top surface of the second package assembly 70. For example, a thinning process such as CMP, polishing, etching, or a combination thereof can be used.

[0044] In Figure 8, the second carrier 90 is bonded to the second package assembly 70 via an oxide-oxide bonding process (e.g., fusion bonding). The second carrier 90 includes a base carrier 92 and one or more dielectric bonding layers 94. The base carrier 92 may be a wafer and may be formed of the same material as, for example, the base carrier 22 in the first carrier 20, thereby reducing warpage caused by mismatch in coefficient of thermal expansion (CTE) during subsequent packaging processes. According to some embodiments, the base carrier 92 may be formed of silicon or a silicon-containing material, or other materials such as laminates, ceramics, glass, silicate glass, etc., may be used. According to some embodiments, the entire base carrier 92 is formed of a homogeneous material and does not contain any other material different from the homogeneous material therein. For example, the entire base carrier 92 may be formed of silicon (doped or undoped) and does not contain any metal regions, dielectric regions, etc.

[0045] Before attaching the second carrier 90 to the second package assembly 70, one or more dielectric bonding layers 94 are deposited on the base carrier 92, and one or more dielectric bonding layers 86 are deposited on the second package assembly 70. The dielectric bonding layers 86 and 94 may be formed in a manner similar to that described above with respect to any dielectric bonding layers 24 / 34 / 36 / 76.

[0046] According to some embodiments, bonding the second carrier 90 to the second encapsulation assembly 70 includes pretreating the dielectric bonding layers 86 and 94 in a process gas containing oxygen (O2) and / or nitrogen (N2), performing a pre-bonding process to bond the dielectric bonding layers 86 and 94 together, and performing an annealing process after the pre-bonding process. According to some embodiments, in the pre-bonding process, the second carrier 90 contacts the dielectric bonding layer 86, and pressure is applied to press the second carrier 90 against the second encapsulation assembly 70. Pre-bonding can be performed at room temperature (in the range of 20°C to 25°C) or at higher temperatures.

[0047] Following pre-bonding, an annealing process is performed. A chemical bond, such as a silicon-oxygen-silicon bond, can be formed between dielectric bonding layers 86 and 94, allowing them to bond together with high bonding strength. According to some embodiments, the annealing process is performed at a temperature range of 200°C to 400°C. The annealing duration may be between 30 and 60 minutes.

[0048] In Figure 9, the structure can be flipped over to remove the first carrier 20 and expose the dielectric bonding layer 58. The first carrier 20 can be removed using any suitable method (e.g., a planarization process). The planarization process can continue until the dielectric bonding layer 58 is coplanar with the gap filler material 32 and the liner 30 (within a range of process variations). The aforementioned planarization process can be a CMP process, a polishing process, or a combination thereof. According to some embodiments, the planarization process can form a contaminated area 95 because the upper portion of the protrusion 52P is contaminated above and / or along the upper surface of the dielectric bonding layer 58. As further illustrated, after the planarization process, the new top surface of the protrusion 52P can be flush with the dielectric bonding layer 58, the gap filler material 32, and the liner 30.

[0049] In Figure 10, a wet etching process is performed to remove the smudged area 95 that was previously the upper part of the protrusion 52P. The wet etching process can be performed using an etchant with high selectivity for the material of the etch sacrificial pad 52 (e.g., aluminum and / or aluminum-copper alloys), while the materials of the dielectric bonding layer 58, the gap filler 32, and the liner 30 remain substantially unetched and intact. For example, the etching process can be an isotropic wet etching process containing etchants such as HF, H₂SO₄ / H₂O₂, H₂O, and combinations thereof. The wet etching process can be performed at standard temperature and pressure for durations ranging from 15 seconds to 3 minutes. In addition to removing the smudged area 95, the wet etching process can also remove a new upper portion of the protrusion 52P, thereby forming a groove 96 from the top surface of the dielectric bonding layer 58, wherein the groove 96 is located directly above the protrusion 52P of the sacrificial pad 52.

[0050] As described above, the sacrificial pad 52 has a top primary surface with a height H1 above the substrate 41, and the sacrificial pad 52 may have a groove 52R formed during circuit probe testing (see FIG. 2), the depth of which is measured from the top primary surface of the sacrificial pad 52, D1. However, due to the steps of planarizing the dielectric bonding layer 58 and the protrusion 52P (see FIG. 9), followed by a wet etching process performed on the protrusion 52P and the smeared area 95, the protrusion 52P may now have a height H3 above the top primary surface of the sacrificial pad 52. For example, the height H3 is smaller than the previous height H2 (and the height H1 of the sacrificial pad 52), for example, in the range of 0.2 micrometers to 1.1 micrometers. In some embodiments, the height H3 of the protrusion 52P after etching may be in the range of 6.6% to 91% of the height H1 of the protrusion 52P before etching.

[0051] As further explained, the uppermost surface of the protrusion 52P can be located at a depth D2 below the top surface of the dielectric bonding layer 58. In contrast, the top primary surface of the sacrificial pad 52 can be located at a depth D3 below the top surface of the dielectric bonding layer 58. For example, the depth D2 of the protrusion 52P below the top surface of the dielectric bonding layer 58 can range from 0.1 micrometers to 1.0 micrometers. Furthermore, the depth D3 of the top surface of the sacrificial pad 52 below the top surface of the dielectric bonding layer 58 can range from 0.4 micrometers to 1.2 micrometers.

[0052] In Figure 11, a passivation layer 102 and a dielectric layer 104 are formed over the aluminum pad 50 and the sacrificial pad 52 (e.g., metal pads 50 / 52). Furthermore, an opening 106 is formed through the passivation layer 102, the dielectric layer 104, the dielectric bonding layer 58, and the dielectric layer 56 to expose the aluminum pad 50. The passivation layer 102 can be a single layer or multiple layers and is conformally deposited as, for example, an oxide of silicon oxide, a nitride of silicon nitride, silicon oxynitride, or a combination thereof. For example, a lower layer of silicon oxide (not shown separately) can be deposited initially on the dielectric bonding layer 58 and fill the entire groove 96. An upper layer of silicon nitride (also not shown separately) can then be deposited over the lower layer of silicon oxide. Any suitable method can be used to deposit, for example, by CVD, ALD, a combination of the foregoing, or any suitable method, a single layer or multiple layers containing the passivation layer 102. After the previous removal of the smudged area 95, a passivation layer 102 is formed on the dielectric bonding layer 58, resulting in higher efficiency and fewer defects. The improved deposition strengthens the bond between the passivation layer 102 and the dielectric bonding layer 58, thereby reducing the risk of delamination in subsequent processing steps.

[0053] The passivation layer 102 can be formed with an average thickness ranging from 2.0 micrometers to 3.5 micrometers. In some embodiments, the passivation layer 102 (e.g., conformal deposition) can have a top surface containing a groove 102R, located directly above the protrusion 52P of the sacrificial pad 52 (e.g., directly above the location of the groove 96 formed in FIG. 10). As a result, the depth D4 of the groove 102R on the top surface of the passivation layer may be less than the depth D2 (e.g., depth D4 is shallower than depth D2), for example, in the range of 100 nanometers (nm) to 900 nanometers. In other embodiments, the top surface of the passivation layer 102 can be as close as other portions elsewhere to the portion directly above 102R.

[0054] The passivation layer 102 can then be patterned to form an opening 106 through the passivation layer 102 and through the dielectric bonding layer 58. For example, a photoresist can be applied to and patterned on the top surface of the passivation layer 102. The patterned photoresist is then used as an etching mask to etch portions of the passivation layer 102 to form the opening 106 and expose the dielectric layer 56. The passivation layer 102 can be etched via a suitable process, such as dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. In some embodiments, the etchant can be selected such that the passivation layer 102 and / or the dielectric bonding layer 58 have higher etch selectivity than the dielectric layer 56, so that the dielectric layer 56 serves as an etch stop layer during the etching process.

[0055] The dielectric layer 104 can be formed from polymeric materials such as polyimide, polybenzoxazole (PBO), or any suitable material. The dielectric layer 104 can be conformally deposited using, for example, spin coating, FCVD, PECVD, LPCVD, ALD, or combinations thereof. As shown, the dielectric layer 104 can be formed on the top surface and along the exposed sidewalls of the passivation layer 102 and along the exposed sidewalls of the dielectric bonding layer 58 within the opening 106. Thus, the dielectric layer 104 partially fills the opening 106 and extends completely through it. The top surface of the dielectric layer 104 can be substantially flat, located directly above the groove 102R (if present) of the passivation layer 102 and directly above the protrusion 52P of the sacrificial pad 52.

[0056] The dielectric layer 104 can then be patterned to reform the opening 106. For example, a photoresist can be applied to the top surface of the dielectric layer 104 and patterned. The patterned photoresist is then used as an etching mask to etch the dielectric layer 104 and dielectric layer 56 (if still present in the opening 106) to reform the opening 106 and expose the aluminum pad 50. The dielectric layer 104 can be etched via a suitable process, such as dry etching (e.g., RIE or NBE, etc.), wet etching, etc. In embodiments where the dielectric layer 56 is used as an etch stop layer in the previous patterning process, the dielectric layer 56 can be etched in the same etch process or in a subsequent etch process to expose the aluminum pad 50. Although a selected etchant is used to etch the dielectric layers 56 and 104, the patterning process can be performed similarly to that described above for the patterning process.

[0057] In Figure 12, under-bump metallurgies (UBMs) 110 and conductive connectors 124 are formed over dielectric layer 104 and passivation layer 102, and the UBMs 110 and conductive connectors 124 pass through dielectric layer 104 and passivation layer 102 to electrically connect to aluminum pad 50. As an example of forming UBMs 110, a seed layer (not shown separately) is formed on the exposed surfaces of aluminum pad 50 and dielectric layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer, the composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The aforementioned seed layer can be formed using processes such as PVD. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be patterned by exposing it to light. The pattern of the photoresist corresponds to UBMs 110. An opening is patterned through the photoresist to expose the seed layer. A conductive material is then formed in the opening of the photoresist and the exposed portion of the seed layer. The conductive material can be formed via electroplating, such as electroplating or electroless plating. The conductive material can contain metals such as copper, titanium, tungsten, aluminum, etc. Next, the photoresist and the portion of the seed layer without conductive material are removed. The photoresist can be removed via an acceptable ashing or stripping process, such as using an oxygen plasma process. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, via an acceptable etching process. The remaining portion of the seed layer and conductive material forms UBMs 110.

[0058] Then, conductive connectors 124 are formed on UBMs 110. The conductive connectors 124 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connectors 124 can contain conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connectors 124 are initially formed by forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of solder is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 124 includes a metal pillar (such as a copper pillar) formed via sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The aforementioned metal cap layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed via an electroplating process.

[0059] Although not specifically stated, semiconductor packages can undergo a second wafer acceptance test (WAT) process or multiple WAT processes. The second WAT process may involve subjecting the semiconductor package to extreme conditions (e.g., high temperature, humidity, and / or pressure) while testing the functionality of the integrated circuitry within. For example, a highly accelerated temperature and humidity stress test (HAST) allows for accelerated testing of durability and reliability under extreme environmental conditions.

[0060] The advantages of the disclosed embodiments can be achieved, for example, during the second WAT process. In particular, removing the smudged areas 95 and / or reducing the protrusions 52P before forming the UBMs 110 and conductive connectors 124 improves the performance of the integrated circuit by minimizing or preventing unwanted short circuits and parasitic capacitances. The stronger bond between the passivation layer 102 and the dielectric bonding layer 58 (e.g., due to the removal of the smudged areas 95) can also improve the performance and reliability of the semiconductor package during the second WAT process and its operation.

[0061] Although not specifically described, the semiconductor package can be separated by sawing the second carrier 90, the dielectric layer 104, and the layers in between. Separation can be performed before, after, or between the second WAT process. Further advantages of the disclosed embodiments can be achieved, for example, during the separation of the semiconductor package. Specifically, the bonding between the passivation layer 102 and the dielectric bonding layer 58 is stronger due to the removal of the smudged area 95, which would otherwise be inserted between the layers. As a result, delamination of the passivation layer 102 from the dielectric bonding layer 58 is prevented or reduced during the separation of the semiconductor package. In fact, delamination is similarly prevented or reduced during any other processing steps that might tend to cause partial or complete warping of the semiconductor package.

[0062] In one embodiment, a method includes attaching a first package assembly to a first carrier, the first package assembly comprising: an aluminum pad located near a substrate; a sacrificial pad located near the substrate, the sacrificial pad comprising a main surface opposite to the substrate, a protrusion of the sacrificial pad extending from the main surface; and a dielectric bonding layer located around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package assembly and the first carrier, the first package assembly being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bonding layer to include a top surface coplanar with the protrusion; and etching a portion of the protrusion. In another embodiment, the method further comprises, prior to attachment to the first package assembly: performing a circuit probe test on the first package assembly, the circuit probe test comprising forming the protrusion of the sacrificial pad; and forming a dielectric bonding layer on the protrusion of the sacrificial pad. In another embodiment, performing the circuit probe test further comprises: electrically connecting a power signal to the sacrificial pad; and forming a first groove in the main surface of the sacrificial pad. In another embodiment, the method further comprises, prior to attachment to a second carrier, co-bonding the second package assembly to the first package assembly. In another embodiment, the method further includes performing an oxide-oxide bonding between the dummy package assembly and the first package assembly before attaching it to the second carrier. In another embodiment, after etching this portion of the protrusion, the protrusion is recessed below the top surface of the aforementioned dielectric bonding layer. In another embodiment, the method further includes forming a passivation layer on the aforementioned dielectric bonding layer, wherein a portion of the passivation layer is located directly above the protrusion containing the second recess. In another embodiment, the method further includes: forming a dielectric layer over the passivation layer; and forming an opening through the dielectric layer, the passivation layer, and the dielectric bonding layer to expose the aluminum pad.

[0063] In one embodiment, a method includes circuit probe testing of a first package assembly, the first package assembly including an aluminum pad and a sacrificial pad located on a substrate. The method of circuit probe testing includes: physically coupling a probe to the sacrificial pad; and connecting a power or ground signal to the sacrificial pad, wherein after connecting the power or ground signal to the sacrificial pad, the sacrificial pad includes a protrusion extending upward from a first top surface of the sacrificial pad; forming a first dielectric bonding layer over the substrate, the aluminum pad, and the sacrificial pad of the first package assembly, the first dielectric bonding layer including a second top surface opposite the substrate; planarizing the first dielectric bonding layer to expose the protrusion of the sacrificial pad; and performing a wet etching process to remove the upper portion of the protrusion. In another embodiment, the substrate of the first package assembly includes: an interconnect structure electrically connected to the sacrificial pad; a silicon via electrically connected to the aluminum pad; and a semiconductor substrate, the aforementioned silicon vias extending through the semiconductor substrate. In another embodiment, the method further includes: attaching a second top surface of the first dielectric bonding layer to a first carrier; thinning the semiconductor substrate to expose the silicon via; and forming a second dielectric bonding layer and a bonding pad adjacent to the first package assembly, electrically interlocking the silicon via between the bonding pad and the aluminum pad. In another embodiment, the method further includes using the second dielectric bonding layer and the bonding pad to co-bond the second package assembly to the first package assembly. In another embodiment, after a power or ground signal is connected to the sacrificial pad, the sacrificial pad includes a groove extending downward from the first top surface of the sacrificial pad. In another embodiment, the sacrificial pad comprises aluminum, and wherein performing a wet etching process includes etching aluminum onto the material of the first dielectric bonding layer using a highly selective etchant.

[0064] In one embodiment, the semiconductor package includes: a semiconductor substrate located above a package assembly; a silicon via extending through the entire semiconductor substrate and electrically connected to the package assembly; an interconnect structure located above the semiconductor substrate and electrically connected to integrated circuit elements on the semiconductor substrate; a first aluminum pad located above the semiconductor substrate and electrically connected to the interconnect structure, the first aluminum pad including: a top major surface opposite the semiconductor substrate; a first groove extending toward the semiconductor substrate; and a protrusion extending away from the semiconductor substrate; a second aluminum pad located above the semiconductor substrate and electrically connected to the silicon via; a first dielectric bonding layer located above and around the first and second aluminum pads; and a passivation layer located above the first aluminum pad and in physical contact with the protrusion. In another embodiment, the semiconductor package further includes a third aluminum pad located above the semiconductor substrate and electrically connected to the first aluminum pad and the interconnect structure. In another embodiment, the semiconductor package further includes under-bump metal located above and in physical contact with the second aluminum pad. In another embodiment, the aforementioned semiconductor package further includes: a first bonding layer disposed along the bottom surface of a semiconductor substrate; a first bonding pad embedded in the first bonding layer; a second bonding layer disposed along the upper surface of the package assembly; and a second bonding pad embedded in the second bonding layer, the second bonding pad being in solid contact with the first bonding pad. In another embodiment, the height of the protrusion above the top major surface is less than the height of the top major surface from the bottom major surface. In another embodiment, the passivation layer includes a second groove located directly above the protrusion.

[0065] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other programs and structures to implement the same purposes as the embodiments introduced herein and / or to achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0066] 20: The First Carrier 22: Base carrier 24: Dielectric bonding layer 30: Lining 32: Gap filling material 34: Dielectric bonding layer 35: Joint pad 36: Dielectric bonding layer 37: Joint pad 40: First encapsulation component 41:Substrate 42: Semiconductor substrate 44: Multilayer dielectric layer 46: Through-Silicone Via (TSV) 48: Interconnection Structure 48U: Top metal wire 50: Metal pad / Aluminum pad 52: Metal Pad / Sacrificial Pad 52P: Protrusion 52R: Groove 54: Conductive via 56: Dielectric layer 58: Dielectric bonding layer 62: Probe 70: Second encapsulation component 70A: Second package component (containing integrated circuitry) 70B: Second encapsulation component (dummy encapsulation component) 76: Dielectric bonding layer 77: Joint Pad 78: Dielectric bonding layer 80: Lining 82: Gap filling material 86: Dielectric bonding layer 90: Second carrier 92: Base Carrier 94: Dielectric bonding layer 95: Stained Area 96: Groove 102: Passivation layer 102R: Groove 104: Dielectric layer 110: Under-bump metal (UBMs) 124: Conductive connector H1~H3: Height D1~D4: Depth

Claims

1. A semiconductor packaging method comprising: attaching a first packaging assembly to a first carrier, the first packaging assembly comprising: an aluminum pad located near a substrate; a sacrificial pad located near the substrate, the sacrificial pad including a primary surface opposite to the substrate, a protrusion of the sacrificial pad extending from the primary surface; and a dielectric bonding layer located around the aluminum pad and the sacrificial pad; attaching a second carrier to the first packaging assembly and the first carrier, the first packaging assembly being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bonding layer to include a top surface coplanar with the protrusion; and etching a portion of the protrusion.

2. The method of claim 1 further includes, prior to attachment to the first package assembly: performing a circuit probe test on the first package assembly, the circuit probe test including forming the protrusion of the sacrificial pad; and forming the dielectric bonding layer over the protrusion of the sacrificial pad.

3. The method of claim 1 further includes, prior to attachment to the second carrier, co-attaching a second encapsulation component with the first encapsulation component.

4. A semiconductor packaging method includes: performing a circuit probe test on a first package assembly, the first package assembly including an aluminum pad and a sacrificial pad located above a substrate, the method of performing the circuit probe test including: physically coupling a probe to the sacrificial pad; and connecting a power signal or a ground signal to the sacrificial pad, wherein after connecting the power signal or the ground signal to the sacrificial pad, the sacrificial pad includes a protrusion extending upward from a first top surface of the sacrificial pad; forming a first dielectric bonding layer over the substrate, the aluminum pad and the sacrificial pad of the first package assembly, the first dielectric bonding layer including a second top surface opposite the substrate; planarizing the first dielectric bonding layer, the planarization exposing the protrusion of the sacrificial pad; and performing a wet etching process to remove an upper portion of the protrusion.

5. The method of claim 4, wherein the substrate of the first packaging assembly comprises: an interconnect structure electrically connected to the sacrificial pad; a silicon via electrically connected to the aluminum pad; and a semiconductor substrate, wherein a portion of the silicon via extends through the semiconductor substrate.

6. A semiconductor packaging method includes: forming an integrated circuit over a semiconductor substrate; forming a first metal pad and a second metal pad over the integrated circuit; forming a groove and a protrusion in the first metal pad; depositing a first dielectric bonding layer over the first metal pad and the second metal pad; fusing the first dielectric bonding layer to a carrier; forming a second dielectric bonding layer and a bonding pad over the semiconductor substrate; attaching an integrated circuit die to the second dielectric bonding layer and the bonding pad; removing the carrier; planarizing the first dielectric bonding layer and the protrusion; performing an etching process after planarizing the first dielectric bonding layer and the protrusion; forming a passivation layer over the first dielectric bonding layer after performing the etching process; and forming an under-bump metal that passes through the passivation layer and is electrically connected to the second metal pad.

7. A semiconductor package includes: a package assembly; a semiconductor substrate; an interconnect structure located above the semiconductor substrate and electrically connected to an integrated circuit arrangement on a surface of the semiconductor substrate; a first aluminum pad located above the semiconductor substrate and electrically connected to the interconnect structure, the first aluminum pad including: a top primary surface opposite to the semiconductor substrate; a first recess extending in the top primary surface toward the semiconductor substrate; and a protrusion extending from the top primary surface away from the semiconductor substrate; a second aluminum pad located above the semiconductor substrate and electrically connected to the interconnect structure; and a first dielectric bonding layer located above and around the first and second aluminum pads, wherein the semiconductor substrate is located between the package assembly and the first aluminum pad.

8. The semiconductor package of claim 7 further includes a silicon via that extends through the semiconductor substrate and is electrically connected to the interconnect structure.

9. A semiconductor device comprising: a package assembly; an interconnect structure located above a semiconductor substrate; a first metal pad located above and electrically connected to the interconnect structure, the first metal pad including a first top major surface opposite to the semiconductor substrate, the first top major surface being flat; and a second metal pad located above and electrically connected to the interconnect structure, the second metal pad including: a second top major surface opposite to the semiconductor substrate; a first recess in the second top major surface; and a protrusion extending from the second top major surface; and a dielectric layer located above and around the lateral edges of the first metal pad and the second metal pad, wherein the semiconductor substrate is located between the package assembly and the first metal pad.

10. A semiconductor device comprising: a packaging assembly; a semiconductor substrate; an integrated circuit located on a surface of the semiconductor substrate; a first metal pad located above and electrically connected to the integrated circuit, the first metal pad having a first top surface that is flat and facing away from the integrated circuit; a second metal pad located above and electrically connected to the integrated circuit, the second metal pad having a second top surface that is non-flat and includes a protrusion, the second top surface facing away from the integrated circuit; a first dielectric layer located around the first metal pad and the second metal pad, the first dielectric layer being located above the first top surface and the second top surface; and a second dielectric layer located above the first dielectric layer and in solid contact with the protrusion, wherein the semiconductor substrate is located between the packaging assembly and the first metal pad.

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