A duty-cycle corrector circuit

Abstract

This document provides a duty cycle corrector circuit that generates a clock signal having a given duty cycle (e.g., 50 percent) or substantially a given duty cycle. The duty cycle (DC) corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit adjusts the delay between two local clock signals until the phase difference between the aforementioned local clock signals is equal to or substantially equal to zero. The DCC circuit adjusts the duty cycle of the local clock signals until the aforementioned duty cycle error is equal to or substantially equal to zero. When the duty cycle of the local clock signal is equal to or substantially equal to 50 percent, the aforementioned duty cycle error is equal to or substantially equal to zero.

Description

Technical Field

[0001] This invention relates to a duty cycle corrector circuit. Prior Technology

[0002] The number of high-speed circuits and systems produced in industry is constantly increasing. Generally, the duty cycle of the clock signal in a high-speed circuit should be 50%. However, due to variations in process, voltage, and temperature (PVT), the duty cycle of the clock signal is often higher or lower than 50%. In some cases, even if the duty cycle of the clock source is 50%, the actual duty cycle may deviate significantly from 50%.

[0003] Furthermore, determining and applying corrections for cycle time errors can be challenging. For example, traditional analog cycle time corrector circuits use analog integrators to detect cycle time errors. However, analog integrators are only suitable for low-speed applications. Digital cycle time corrector circuits typically use two delay lines to correct accuracy. Using two delay lines requires complex circuitry and results in relatively high power consumption. For example, comparator circuits can be used to compare the signal levels of the two delay lines. Comparator circuits are typically complex (e.g., containing many transistors) and consume a significant amount of area on the die. Summary of the Invention

[0004] According to an embodiment of the present invention, a duty cycle corrector circuit includes: a delay-locked loop circuit; and a duty cycle correction circuit, which can be connected to the delay-locked loop circuit, wherein: the duty cycle correction circuit includes: a duty adjustment circuit, which can be used to receive a clock input signal and output a delayed first signal, the duty adjustment circuit being further used to adjust a duty cycle of the delayed first signal according to a received duty control signal; a pulse generator circuit, which can be connected to the duty adjustment circuit, the pulse generator circuit being used to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal; and a duty correction circuit, which can be connected to the pulse generator circuit, the duty correction circuit being used to receive the first pulse signal from the pulse generator circuit. The circuit includes: a second pulse signal, and outputs a working control signal received by the working adjustment circuit based on the signal levels of the first and second pulse signals, and uses this signal to adjust the working period of the delayed first signal; and a delay-locked loop circuit including: a phase detector circuit for receiving the delayed first signal and the delayed second signal and detecting a phase difference between the delayed first signal and the delayed second signal; an inverter circuit for receiving the delayed first signal and outputting a second signal; and a variable delay circuit for connecting between the phase detector circuit and the inverter circuit, the variable delay circuit being used to adjust a delay of the second signal to generate the delayed second signal, the adjustment of the delay of the second signal being an adjustment of a delay between the delayed first signal and the delayed second signal.

[0005] According to an embodiment of the present invention, an electronic device having a duty cycle includes: a duty cycle corrector circuit, comprising: a delay-locked loop circuit; and a duty cycle correction circuit, which can be connected to the delay-locked loop circuit, wherein: the duty cycle correction circuit includes: a duty adjustment circuit, which can be used to receive a clock input signal and output a delayed first signal, the duty adjustment circuit being further used to adjust a duty cycle of the delayed first signal according to a received duty control signal; a pulse generator circuit, which can be connected to the duty adjustment circuit, the pulse generator circuit being used to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal; and a duty correction circuit, which can be connected to the pulse generator circuit, the duty correction circuit being used to receive from the pulse generator circuit The first pulse signal and the second pulse signal, and based on the signal levels of the first and second pulse signals, output the working control signal received via the working adjustment circuit to adjust the working period of the delayed first signal; and the delay-locked loop circuit includes: a phase detector circuit, which can be used to receive the delayed first signal and the delayed second signal, and detect a phase difference between the delayed first signal and the delayed second signal; an inverter circuit, which can be used to receive the delayed first signal and output a second signal; and a variable delay circuit, which can be connected between the phase detector circuit and the inverter circuit, the variable delay circuit can be used to adjust a delay of the second signal to generate the delayed second signal, the adjustment of the delay of the second signal is to adjust a delay between the delayed first signal and the delayed second signal.

[0006] According to an embodiment of the present invention, a method for a duty cycle corrector circuit includes: receiving a clock input signal; generating a delayed clock input signal as a delayed first signal; inverting the delayed first signal to generate a second signal; adjusting a delay of the second signal to generate a delayed second signal, wherein the delay is adjusted to reduce a phase difference between the delayed first signal and the delayed second signal, and the delay is adjusted until the phase difference is equal to or substantially equal to a first given value; and adjusting a first duty cycle of the delayed first signal and a second duty cycle of the delayed second signal until the first and second duty cycles are equal to or substantially equal to a second given value. Simple Explanation of the Diagram

[0007] The following detailed description, taken in conjunction with the accompanying drawings, is the best way to understand the nature of this disclosure. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 illustrates a block diagram of a high-speed circuit according to some embodiments;

[0009] Figure 2 illustrates a first example block diagram of a duty cycle corrector circuit according to some embodiments;

[0010] Figure 3 illustrates an example first timing diagram of the duty cycle corrector circuit shown in Figure 2 according to some embodiments;

[0011] Figure 4 illustrates an example second timing diagram of the duty cycle corrector circuit shown in Figure 2 according to some embodiments;

[0012] Figure 5 illustrates a schematic diagram of an example operating control circuit suitable for the duty cycle corrector circuit shown in Figure 2, according to some embodiments;

[0013] Figure 6A illustrates a first example schematic diagram of a duty cycle corrector circuit suitable for a duty cycle corrector circuit shown in Figure 2, according to some embodiments;

[0014] Figure 6B illustrates, according to some embodiments, an example waveform of an INP signal with a duty cycle less than a given value, and an example waveform of an INP signal with an adjusted duty cycle substantially equal to the given value;

[0015] Figure 7 illustrates a second example block diagram of a duty cycle corrector circuit according to some embodiments;

[0016] Figure 8 illustrates a second example schematic diagram of a duty cycle corrector circuit suitable for a duty cycle corrector circuit as shown in Figure 7, according to some embodiments;

[0017] Figure 9 illustrates an example first timing diagram of the duty cycle corrector circuit shown in Figure 7 according to some embodiments;

[0018] Figure 10 illustrates an example second timing diagram of the duty cycle corrector circuit shown in Figure 7 according to some embodiments;

[0019] Figure 11 illustrates a third example schematic diagram of a DA circuit suitable for a DC corrector circuit as shown in Figure 7, according to some embodiments;

[0020] Figure 12 illustrates a fourth example schematic diagram of a DA circuit suitable for a DC corrector circuit as shown in Figure 7, according to some embodiments;

[0021] Figure 13 illustrates an example pulse generator circuit schematic diagram applicable to the duty cycle corrector circuit shown in Figures 2 and 7 according to some embodiments;

[0022] Figure 14 illustrates a method flowchart of the operating duty cycle corrector circuit shown in Figure 2 according to some embodiments; and

[0023] Figure 15 illustrates a method flowchart of operating the duty cycle corrector circuit shown in Figure 7 according to some embodiments. Implementation

[0024] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first member on or above a second member may include embodiments in which the first and second members are in direct contact, and may also include embodiments in which an additional member may be formed between the first and second members such that the first and second members are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] The embodiments disclosed herein provide a duty cycle (DC) corrector circuit that generates a duty cycle that satisfies a given duty cycle clock signal. In one embodiment, the given duty cycle is 50 percent or substantially 50 percent of the duty cycle. The DC corrector circuit utilizes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is used to adjust the delay between two local clock signals, a delayed clock input (INP) signal and a delayed inverted clock (INN_d) signal, until the phase difference between the local clock signals equals a given phase difference. In one embodiment, the given phase difference is zero or substantially zero. In one embodiment, the DLL circuit ultimately aligns the rising edges of the local clock signals with each other. The DCC circuit is used to adjust the duty cycles of the delayed clock_in signal and the delayed inverted clock_in signal until the duty cycle error is zero (or substantially zero). The DLL and DCC circuits generate clock output signals with a duty cycle of 50 percent or substantially 50 percent.

[0026] Embodiments of DC calibrator circuits can be used in both low-speed and high-speed circuits and systems. DC calibrator circuits can operate on input signals over a wide frequency range and / or can accommodate a wide range of duty cycle errors. Additionally or alternatively, embodiments of DC calibrator circuits are less complex than conventional duty cycle calibrator circuits and use less area on the die. For example, exemplary embodiments of DC calibrator circuits are constructed using fewer transistors than conventional duty cycle calibrator circuits. In some cases, DC calibrator circuits consume less power than conventional duty cycle calibrator circuits.

[0027] Figure 1 illustrates a block diagram of a high-speed circuit according to some embodiments. The high-speed circuit 100 can be any suitable type of high-speed circuit, including a processing device, a memory input / output interface, and a high-frequency data converter. Example processing devices include, but are not limited to, a central processing unit, a microprocessor, and a digital signal processor. The high-speed circuit 100 typically includes multiple circuits, including a DC corrector circuit 102. In a non-limiting, non-exclusive example, the DC corrector circuit 102 is implemented in circuit 104. Circuit 104 can be any suitable circuit. Example circuits include, but are not limited to, error correction (deskew) circuitry, a memory input / output interface, and / or data converter circuitry.

[0028] Figure 2 illustrates a first example block diagram of a DC corrector circuit according to some embodiments. The DC corrector circuit 200 includes a DLL circuit 202 and a DCC circuit 204. The DLL circuit 202 includes a phase detector (PD) circuit 206, a charge pump (CP) circuit 208 available for connection to the output of the PD circuit 206, a low-pass filter (LPF) circuit 210 available for connection to the output of the CP circuit 208, a variable delay circuit 212 available for connection to the output of the LPF circuit 210, and an inverter circuit 214 available for connection to the input of the variable delay circuit 212. Any suitable PD circuit, CP circuit, LPF circuit, and variable delay circuit can be used for the PD circuit 206, CP circuit 208, LPF circuit 210, and variable delay circuit 212, respectively.

[0029] In the illustrated embodiment, PD circuit 206 can be used to detect a phase difference between the INP signal received on signal line 216 and the INN_d signal received on signal line 218. The INP signal is a delayed version of the clock_in (CLK_IN) signal, and the INN_d signal is an inverted delayed version of the INP signal. In one embodiment, PD circuit 206 can be used to detect the phase difference between the rising edges of the INP signal and the INN_d signal.

[0030] PD circuit 206 outputs corresponding rising / falling signals on signal lines 220 and 222. These rising / falling signals drive CP circuit 208. LPF circuit 210 performs a low-pass filter (LPF) on the CP signal output on signal line 224 to generate a delay control signal (DELAY_ctrl) on signal line 226. The DELAY_ctrl signal is used to adjust the delay of variable delay circuit 212 to reduce the delay between INP and INN_d signals. In one embodiment, the DELAY_ctrl signal is used to adjust the delay of the INN_d signal (e.g., adjusting the delay input signal of the INN signal, input to variable delay circuit 212). The negative feedback operation of PD circuit 206 aligns the INN_d signal with the INP signal.

[0031] DC corrector circuit 204 includes a duty adjustment (DA) circuit 228, which can be connected to a pulse generator (PG) circuit 230. DA circuit 228 receives the CLK_IN signal on signal line 232. An INP signal is output from DA circuit 228 on signal line 234. The INP signal is input as a first input signal to PG circuit 230 on signal line 236. The INP signal is also input to inverting circuit 214, which outputs an inverted INP signal (INN signal) on signal line 238. The INP signal is input to variable delay circuit 212. Variable delay circuit 212 delays the INP signal to output the INN_d signal on signal line 240.

[0032] Duty control (DC) circuit 242 can be connected between the output of PG circuit 230 and the input of DA circuit 228. Based on the signal levels of the INP and INN_d signals, PG circuit 230 generates a PULSE_n signal on signal line 244 and a PULSE_p signal on signal line 246. In one embodiment, PG circuit 230 generates PULSE_n and PULSE_p signals when the INP and INN_d signals are aligned (e.g., the phase difference between the INP and INN_d signals is zero or substantially zero).

[0033] The PULSE_n and PULSE_p signals are received by DC circuit 242, which generates the DUTY_ctrl signal on signal line 248. The DUTY_ctrl signal is received by DA circuit 228, and based on the signal level of the DUTY_ctrl signal, the pulse widths of the INP and INN_d signals are increased or decreased according to the aforementioned signal level until the pulse widths are equal to (or substantially equal to) 50%. When the pulse widths of the INP and INN_d signals are equal to or close to 50%, the pulse widths of the PULSE_p and PULSE_n signals are zero, and the operating period of the clock_out (CLK_OUT) signal output on signal line 250 is equal to or substantially equal to 50%.

[0034] Figure 3 illustrates an example first timing diagram of the duty cycle (DC) corrector circuit shown in Figure 2 according to some embodiments. In the illustrated timing diagram, initially the duty cycle of the INP signal is 40%, the duty cycle of the INN_d signal is 60%, and the duty cycle error is 20%. When the duty cycle of the INN_d signal is greater than the duty cycle of the INP signal, the duty cycle of the INP signal increases until it reaches 50% (or substantially 50%), and the duty cycle of the INN_d signal decreases until it reaches 50% (or substantially 50%). At time t0, the INP, INN, and INN_d signals are in phase, as shown in region 300. Therefore, the DLL circuit (e.g., DLL circuit 202 in Figure 2) has already corrected for any phase difference between the rising edges of the INP and INN_d signals.

[0035] At time t1, the falling edge 302 in the INP signal triggers a transition or the rising edge 304 in the PULSE_p signal (e.g., the start of pulse 306). At time t2, the falling edge 308 in the INN_d signal triggers the falling edge 310 in the PULSE_p signal (the end of pulse 306). Thus, the timing of the falling edge 302 in the INP signal and the falling edge 308 in the INN_d signal controls the pulse width 311 of pulse 306.

[0036] At time t1, the rising edge 304 of pulse 306 triggers a decrease ΔV1 in the signal level of the DUTY_ctrl signal. The pulse width 311 of pulse 306 controls the duration of ΔV1 in the signal level of the DUTY_ctrl signal (see Figure 5). Furthermore, the decrease of ΔV1 in the DUTY_ctrl signal increases the duty cycle of the INP signal and decreases the duty cycle of the INN_d signal (see Figure 6A).

[0037] In one embodiment, the timing of each rising edge of a subsequent transition in the INP signal is adjusted to repeatedly increase the duty cycle of the INP signal until the duty cycles of the INP and INN_d signals are fifty percent, or substantially fifty percent. This adjustment causes the rising edge of the next transition in the INP signal (e.g., 312) to occur earlier or faster than the previous rising edge (e.g., 314), while the timing of the falling edge of the next transition in the INP signal (e.g., 316) remains substantially the same as the timing of the previous falling edge (e.g., 302), thus increasing the duty cycle of the INP signal. Therefore, the pulse width 318 will be greater than the previous pulse width 320. For example, if the duty cycle of the INP signal increases to forty-two percent, the duty cycle of the INN_d signal will decrease to fifty-eight percent. Based on the aforementioned increase in the duty cycle of the INP signal and the decrease in the duty cycle of the INN_d signal, the duty cycle error will be reduced to sixteen percent.

[0038] At time t3, the INP, INN, and INN_d signals remain in the same phase, as shown in region 322. At time t4, the falling edge 316 of the INP signal triggers the rising edge 324 of the PULSE_p signal (e.g., the start of pulse 326). At time t5, the falling edge 328 of the INN_d signal triggers the falling edge 330 of the PULSE_p signal (e.g., the end of pulse 326).

[0039] At time t4, the rising edge 324 of pulse 326 triggers another decrease ΔV2 in the signal level of the DUTY_ctrl signal. The pulse width 332 of pulse 326 controls the duration of ΔV2 in the signal level of the DUTY_ctrl signal (see Figure 5). The decrease in ΔV2 in the DUTY_ctrl signal increases the duty cycle of the INP signal and decreases the duty cycle of the INN_d signal (see Figure 6A).

[0040] Similarly, in one embodiment, the rising edge of the next transition in the INP signal occurs faster than the rising edge 312 of the previous transition, while the timing of the falling edge of the next transition in the INP signal remains substantially the same as the timing of the falling edge 316. This increases the duty cycle of the INP signal. For example, if the duty cycle of the INP signal increases to 45%, the duty cycle of the INN_d signal will decrease to 55%. Based on the aforementioned increase in the duty cycle of the INP signal and decrease in the duty cycle of the INN_d signal, the duty cycle error will be reduced to 10%.

[0041] The process of increasing the duty cycle of the INP signal and decreasing the duty cycle of the INN_d signal will be repeated until the duty cycle of the INP signal is fifty percent or substantially fifty percent, and the duty cycle of the INN_d signal is fifty percent or substantially fifty percent. When the duty cycles of both the INP and INN_d signals are fifty percent (or substantially fifty percent), the duty cycle error is zero (or substantially zero).

[0042] Figure 4 illustrates an example second timing diagram of the duty cycle corrector circuit shown in Figure 2 according to some embodiments. In the illustrated timing diagram, initially the duty cycle of the INP signal is 60%, the duty cycle of the INN_d signal is 40%, and the duty cycle error is 20%. When the duty cycle of the INN_d signal is less than the duty cycle of the INP signal, the duty cycle of the INP signal decreases until it reaches 50%, or substantially 50%, and the duty cycle of the INP signal increases until it reaches 50%, or substantially 50%. At time t0, the INP, INN, and INN_d signals are in phase, as shown in region 400. Therefore, the DLL circuit (e.g., DLL circuit 202 in Figure 2) has already corrected for any phase difference between the rising edges of the INP and INN_d signals.

[0043] At time t1, the falling edge 402 in the INN_d signal triggers the rising edge 404 in the PULSE_n signal (e.g., the start of pulse 406). At time t2, the falling edge 408 in the INP signal triggers the falling edge 410 in the PULSE_n signal (e.g., the end of pulse 406). Thus, the timing of the falling edge 402 in the INN_d signal and the falling edge 408 in the INP signal controls the pulse width 411 of pulse 406.

[0044] At time t1, the rising edge 404 of pulse 406 triggers an increase ΔV1 in the signal level of the DUTY_ctrl signal. The pulse width 411 of pulse 406 controls the duration of ΔV1 in the signal level of the DUTY_ctrl signal (see Figure 5). Furthermore, the increase of ΔV1 in the DUTY_ctrl signal reduces the duty cycle of the INP signal and increases the duty cycle of the INN_d signal (see Figure 6A).

[0045] In one embodiment, the timing of each falling edge of a subsequent transition in the INP signal is adjusted to repeatedly reduce the duty cycle of the INP signal until the duty cycles of the INP and INN_d signals are fifty percent, or substantially fifty percent. This adjustment causes the falling edge of the next transition in the INP signal (e.g., 412) to occur earlier or faster than the previous falling edge (e.g., 408), while the timing of the rising edge 414 of the next transition in the INP signal remains substantially the same as the previous rising edge 416, thus reducing the duty cycle of the INP signal. Therefore, the pulse width 418 will be smaller than the previous pulse width 420. For example, if the duty cycle of the INP signal is reduced to fifty-eight percent, the duty cycle of the INN_d signal will increase to forty-two percent. Based on the aforementioned reduction in the duty cycle of the INP signal and the increase in the duty cycle of the INN_d signal, the duty cycle error will be reduced to sixteen percent.

[0046] At time t3, the INP, INN, and INN_d signals remain in the same phase, as shown in region 422. At time t4, the falling edge 424 in the INN_d signal triggers another rising edge 426 in the PULSE_n signal (e.g., the start of pulse 428). At time t5, the falling edge 412 in the INP signal triggers the falling edge 430 in the PULSE_n signal (e.g., the end of pulse 428).

[0047] At time t4, the rising edge 426 of pulse 428 triggers another increase ΔV2 in the signal level of the DUTY_ctrl signal. The pulse width 432 of pulse 428 controls the duration of ΔV2 in the signal level of the DUTY_ctrl signal (see Figure 5). The increase of ΔV2 in the DUTY_ctrl signal reduces the duty cycle of the INP signal and increases the duty cycle of the INN_d signal.

[0048] Similarly, in one embodiment, the falling edge of the next transition in the INP signal occurs faster than the previous falling edge 412, while the timing of the rising edge of the next transition in the INP signal remains substantially the same as the timing of the previous rising edge 414. This reduces the duty cycle of the INP signal. For example, if the duty cycle of the INP signal is reduced to 55%, the duty cycle of the INN_d signal will increase to 45%. Based on the aforementioned increase in the duty cycle of the INN_d signal and the reduction in the duty cycle of the INP signal, the duty cycle error will be reduced to 10%.

[0049] The process of decreasing the duty cycle of the INP signal and increasing the duty cycle of the INN_d signal will be repeated until the duty cycle of the INP signal is fifty percent or substantially fifty percent, and the duty cycle of the INN signal is fifty percent or substantially fifty percent. When the duty cycles of both the INP and INN_d signals are fifty percent (or substantially fifty percent), the duty cycle error is zero (or substantially zero).

[0050] Figure 5 illustrates an example operational control circuit schematic for a duty cycle corrector circuit as shown in Figure 2, according to some embodiments. A first terminal 502 of charge pump circuit 500 can be connected to voltage source 504 (e.g., VDD), and a second terminal 506 of charge pump circuit 500 can be connected to node 508. A first terminal 510 of another charge pump circuit 512 can be connected to node 508, and a second terminal 514 of charge pump circuit 512 can be connected to reference voltage source 516 (e.g., VSS or ground). A low-pass filter (LPF) circuit 518 can be connected to node 508.

[0051] The charge pump circuit 500 includes one or more charging circuits, and the charge pump circuit 512 includes one or more discharging circuits. Essentially, the DC circuit 242 acts as a switch, which operates based on the signal levels of the PULSE_n and PULSE_p signals to charge or discharge the LPF circuit 518 and generate a DUTY_ctrl signal on signal line 520. The DC circuit 242 receives the PULSE_n signal on signal line 522 and the PULSE_p signal on signal line 524. When the PULSE_n signal is valid (e.g., when the signal level is high), current flows from the voltage source 504 to the LPF circuit 518 to charge it. Depending on the charging of the LPF circuit 518, the signal level of the DUTY_ctrl signal on signal line 520 increases (e.g., ΔVn, where n is a number equal to or greater than 1). As described above, when the signal level of the DUTY_ctrl signal increases, the duty cycle of the INP signal decreases while the duty cycle of the INN_d signal increases.

[0052] Conversely, when the PULSE_p signal is active (e.g., when the signal level is high), current flows from the LPF circuit 518 to the reference voltage source 516 to discharge the LPF circuit 518. Based on the discharge of the LPF circuit 518, the signal level of the control voltage signal DUTY_ctrl decreases (e.g., ΔVn, where n is a number equal to or greater than 1). As described above, when the signal level of the DUTY_ctrl signal decreases, the duty cycle of the INP signal increases while the duty cycle of the INN_d signal decreases.

[0053] Figure 6A illustrates a first example schematic diagram of a duty cycle (DC) corrector circuit suitable for a duty cycle (DC) corrector circuit as shown in Figure 2, according to some embodiments. The example DA circuit 228 includes four transistors connected in series. A first terminal 602 of transistor 600 can be connected to a voltage source 604, and a second terminal 606 of transistor 600 can be connected to node 608. A first terminal 610 of transistor 612 can be connected to node 608, and a second terminal 614 of transistor 612 can be connected to node 616. A first terminal 618 of transistor 620 can be connected to node 616, and a second terminal 622 of transistor 620 can be connected to node 624. A first terminal 626 of transistor 628 can be connected to node 624, and a second terminal 630 of transistor 628 can be connected to a reference voltage 632. In the illustrated embodiment, transistors 600 and 612 are p-type transistors (e.g., PMOS transistors), and transistors 620 and 628 are n-type transistors (e.g., NMOS transistors), but other embodiments are not limited to this implementation. For example, transistors 600 and 612 may be n-type transistors, and transistors 620 and 628 may be p-type transistors.

[0054] The DUTY_ctrl signal, generated by the DC circuit 242, is received by the gates of transistor 600 on signal line 634 and transistor 628 on signal line 636. The CLK_IN signal is received by the gates of transistors 612 and 620 on signal line 232. The INP signal is output from the DA circuit 228 on signal line 234. The DA circuit 228 is used to change the timing of the rising edge of the INP signal, thereby adjusting the duty cycle of the INP signal. When the signal level of the DUTY_ctrl signal decreases and the signal level of the CLK_IN signal is low, transistors 600 and 612 are turned on so that the rising edge of the next INP signal occurs faster than the previous rising edge. In this way, the duty cycle of the INP signal increases (see the timing diagram in Figure 3). When the signal level of the DUTY_ctrl signal increases and the signal level of the CLK_IN signal is at a high level, transistors 620 and 628 are turned on, so that the falling edge of the next INP signal occurs faster than the previous falling edge. In this way, the duty cycle of the INP signal is reduced (see the timing diagram in Figure 4).

[0055] Figure 6B illustrates, according to some embodiments, example waveforms of INP signals with a duty cycle less than a given value, and example waveforms of INP signals with an adjusted duty cycle substantially equal to the given value. Figure 6B illustrates an embodiment of increasing the duty cycle of the INP signal. The dashed waveform represents an INP signal with a duty cycle less than 50 percent of the given value, and the solid waveform represents an INP signal with an adjusted duty cycle of 50 percent (or substantially 50 percent).

[0056] As described above, when the signal level of the DUTY_ctrl signal decreases and the signal level of the CLK_IN signal is low, the duty cycle of the INP signal increases. Transistors 600 and 612 are turned on so that the rising edge of the next INP signal occurs faster than the previous rising edge. In the embodiment illustrated in Figure 6A, when the DUTY_ctrl signal decreases, the on-resistance (Ron) of the p-type transistor 600 decreases, and the Ron of the n-type transistor 628 increases, thus increasing the duty cycle of the INP signal. When the duty cycle of the INP signal is fifty percent or substantially fifty percent, the Ron of the p-type transistor 600 is equal to (or substantially equal to) the Ron of the n-type transistor 628.

[0057] Alternatively, when the duty cycle of the INP signal is to be reduced (not shown in Figure 6B), the signal level of the DUTY_ctrl signal is increased and the signal level of the CLK_IN signal is high. Transistors 620 and 628 are turned on so that the falling edge of the next INP signal occurs faster than the previous falling edge. In the embodiment illustrated in Figure 6A, when the DUTY_ctrl signal increases, the Ron of the p-type transistor 600 increases while the Ron of the n-type transistor 628 decreases, thus reducing the duty cycle of the INP signal.

[0058] Figure 7 illustrates a second example block diagram of a duty cycle corrector circuit according to some embodiments. The DC corrector circuit 700 is similar to the DC corrector circuit 200 shown in Figure 2, except for the DCC circuit 702. Specifically, the DCC circuit 702 includes a different DC circuit 704, a different DA circuit 706, and a latch detector (LD) circuit 708. In the illustrated embodiment, the DC circuit 704 is an up / down (UP / DN) counter circuit. Any suitable type of UP / DN counter circuit can be used here.

[0059] DC circuit 704 (e.g., UP / DN counter circuit) counts the PULSE_p and PULSE_n pulses to adjust the DUTY_ctrl signal (e.g., UP / DN code signal) on signal line 248. The DUTY_ctrl signal is received by DA circuit 706. When DC circuit 704 is an UP / DN counter circuit, the DUTY_ctrl signal is the UP / DN code representing the UP count and DN count. As described in more detail with reference to Figure 8, one or more transistors are turned on and off according to the PULSE_p and PULSE_n counts represented by the DUTY_ctrl signal.

[0060] The LD circuit 708 receives the DUTY_ctrl signal (e.g., the current UP and DN counts) on signal line 710. When the DUTY_ctrl signal changes (e.g., the count changes within a given number of cycles), the LD circuit 708 outputs a lock-out signal on signal line 712. The aforementioned lock-out signal indicates that the duty cycle of the INP and INN_d signals is not (or substantially not) a given value, for example, fifty percent (or substantially fifty percent).

[0061] When the DUTY_ctrl signal maintains a constant value for a given time period (e.g., the count does not change within a given number of cycles), the CLK_out signal has a duty cycle of fifty percent (or substantially fifty percent). When the count does not change within a given number of cycles, the LD circuit 708 outputs a "lock" signal, indicating that the duty cycles of the INP and INN_d signals are at (or substantially at) a given value, where in the illustrated embodiment it is fifty percent (or substantially fifty percent). The lock signal indicates that the duty cycle error is zero (or substantially zero). The lock signal locks the DCC circuit 702, which causes the value of the DUTY_ctrl signal to remain constant (e.g., the value of the UP / DN code remains constant).

[0062] Figure 8 illustrates a second example schematic diagram of a duty cycle (DC) corrector circuit suitable for a duty cycle (DC) corrector circuit as shown in Figure 7, according to some embodiments. The DA circuit 706 includes a transistor block 800 that can be connected between a voltage source 802 (e.g., VDD) and a node 804. The transistor block 800 includes one or more transistors 806 connected in parallel, wherein a first terminal 808 of each transistor can be connected to the voltage source 802, and a second terminal 810 can be connected to the node 804.

[0063] A first terminal 812 of transistor 814 can be connected to node 804, and a second terminal 816 of transistor 814 can be connected to node 818. A first terminal 820 of transistor 822 can be connected to node 818, and a second terminal 824 of transistor 822 can be connected to node 826. A transistor block 828 can be connected between node 826 and a reference voltage source 830 (e.g., ground). Transistor block 828 includes one or more transistors 832 connected in parallel, wherein a first terminal 834 of each transistor 832 can be connected to node 826, and a second terminal 836 of each transistor 832 can be connected to the reference voltage source 830.

[0064] In the illustrated embodiment, transistors 806 and 814 are p-type transistors, and transistors 822 and 832 are n-type transistors. When the PULSE_n signal is active, the DN code decreases while the UP code increases. When the CLK_IN signal level is low, transistors 822 and transistor block 828 are off, while transistors 814 and one or more transistors 806 in transistor block 800 are on. The transistors 806 in transistor block 800 are turned on gradually (e.g., as the UP code increases). Thus, when the UP code is 1, the UP[0] signal is active to turn on one transistor 806. When the UP code is 2, the UP[0] and UP[1] signals are active to turn on two transistors 806, and so on. In this way, the duty cycle of the INP signal increases.

[0065] When the PULSE_p signal is active, the DN code increments while the UP code decrements. When the CLK_IN signal level is high, transistor 814 and transistor block 800 are off, while one or more transistors 832 in transistor 822 and transistor block 828 are on. The transistors 832 in transistor block 828 are turned on gradually (e.g., as the DN code increments). Thus, when the DN code is 1, the DN[0] signal is active to turn on one transistor 832. When the DN code is 2, the DN[0] and DN[1] signals are active to turn on two transistors 832, and so on. In this way, the duty cycle of the INP signal is reduced. In other embodiments, transistors 806 and 814 may be n-type transistors, and transistors 822 and 832 may be p-type transistors.

[0066] Figure 9 illustrates an example first timing diagram of the duty cycle corrector circuit shown in Figure 7 according to some embodiments. In the illustrated timing diagram, the duty cycle of the INP signal is initially 40 percent, while the duty cycle of the INN_d signal is 60 percent. As described above, when the duty cycle of the INN_d signal is greater than the duty cycle of the INP signal, the duty cycle of the INP signal increases until it reaches 50 percent (or substantially 50 percent), and the duty cycle of the INN_d signal decreases until it reaches 50 percent (or substantially 50 percent). At time t0, the INP, INN, and INN_d signals are in phase, as shown in region 900. Therefore, the DLL circuit (e.g., DLL circuit 202 in Figure 2) has already corrected for any phase difference between the rising edges of the INP and INN_d signals.

[0067] At time t0, both the DN code and the UP code are zero. At time t1, the falling edge 902 in the INP signal triggers the rising edge 904 in the PULSE_p signal (e.g., the start of pulse 906). According to pulse 906, the DN code increases by one to a positive one, and the UP code decreases by one to a negative one. The increase in the DN code and the decrease in the UP code cause the rising edge 908 of the next transition in the INP signal to occur faster than the rising edge 910 of the previous transition. For example, in the embodiment shown in FIG8, transistor 814 and transistor block 800 are turned off, while transistor 822 and transistor 832 associated with the DN[0] input in transistor block 828 are turned on to adjust the timing of the rising edge of the INP signal.

[0068] At time t2, the INP, INN, and INN_d signals remain in the same phase, as shown in region 912. At time t3, the falling edge 914 in the INP signal triggers the rising edge 916 in the PULSE_p signal (e.g., the start of pulse 918). According to pulse 918, the DN code increases by one to a positive two, while the UP code decreases by one to a negative two. The increase in the DN code and the decrease in the UP code cause the rising edge of the next transition in the INP signal to occur faster than the rising edge 908 of the transition. For example, in the embodiment shown in FIG8, transistor 814 and transistor block 800 are turned off, while transistor 822 and transistor 832 associated with the DN[0] and DN[1] inputs in transistor 828 are turned on to adjust the timing of the rising edge of the INP signal.

[0069] Figure 10 illustrates an example second timing diagram of the duty cycle corrector circuit shown in Figure 7 according to some embodiments. In the illustrated timing diagram, the duty cycle of the INP signal is initially 60 percent, and the duty cycle of the INN_d signal is 40 percent. As described above, when the duty cycle of the INN_d signal is less than the duty cycle of the INP signal, the duty cycle of the INP signal will decrease until the duty cycle of the INP signal is 50 percent (or substantially 50 percent), and the duty cycle of the INN_d signal will increase until the duty cycle of the INN_d signal is 50 percent (or substantially 50 percent). At time t0, the INP signal, the INN signal, and the INN_d signal are in phase, as shown in region 1000. Therefore, the DLL circuit (e.g., DLL circuit 202 in Figure 2) has already corrected for any phase difference between the rising edges of the INP and INN_d signals.

[0070] At time t0, both the DN code and the UP code are zero. At time t1, the falling edge 1002 in the INN_d signal triggers the rising edge 1004 in the PULSE_n signal (e.g., the start of pulse 1006). According to pulse 1006, the DN code decreases by one to negative one, and the UP code increases by one to positive one. The increase in the UP code and the decrease in the DN code cause the falling edge 1008 of the next transition in the INP signal to occur faster than the falling edge 1010 of the previous transition. For example, in the embodiment shown in FIG8, transistor 822 and transistor block 828 are turned off, while transistor 814 and transistor 806 associated with the UP[0] input in transistor block 800 are turned on to adjust the timing of the falling edge of the INP signal.

[0071] At time t2, the INP, INN, and INN_d signals remain in the same phase, as shown in region 1012. At time t3, the falling edge 1014 in the INN_d signal triggers the rising edge 1016 in the PULSE_n signal (e.g., the start of pulse 1018). According to pulse 1018, the UP code increases by one to a positive two, and the DN code decreases by one to a negative two. The increase in the UP code and the decrease in the DN code cause the falling edge of the next transition in the INP signal to occur faster than the falling edge 1008. For example, in the embodiment shown in FIG8, transistor 822 and transistor block 828 are turned off, while transistor 814 and transistor 806 associated with the UP[0] and UP[1] inputs in transistor block 800 are turned on to adjust the timing of the falling edge of the INP signal.

[0072] Figure 11 illustrates a third example schematic diagram of a DA circuit suitable for a DC corrector circuit shown in Figure 7, according to some embodiments. The DA circuit 706 is implemented using only p-type transistor control during the duty cycle of the INP signal. The DA circuit 706 includes a transistor block 800 that can be connected between a voltage source 802 (e.g., VDD) and node 804. The transistor block 800 includes one or more transistors 806 connected in parallel, wherein a first terminal 808 of each transistor can be connected to a reference voltage source 830, and a second terminal 810 can be connected to node 804.

[0073] Transistor 814 has a first terminal 812 that can be connected to node 804, and a second terminal 816 that can be connected to node 818. Transistor 822 has a first terminal 820 that can be connected to node 818, and a second terminal 824 that can be connected to node 826. Transistor 1100 can be connected between node 826 and a reference voltage source 830 (e.g., ground). Transistor 1100 has a first terminal 1102 that can be connected to node 826, and a second terminal 1104 that can be connected to the reference voltage source 830. The gate 1106 of transistor 1100 is connected to the voltage source VDD. Therefore, transistor 1100 operates in the off region and acts as an open switch (e.g., is turned off).

[0074] In the illustrated embodiment, transistors 806 and 814 are p-type transistors, and transistors 822 and 1100 are n-type transistors. The UP code increments when the PULSE_n signal is active. When the CLK_IN signal level is low, transistors 822 and 1100 are off, while transistors 814 and one or more transistors 806 in transistor block 800 are active. The transistors 806 in transistor block 800 are activated sequentially (e.g., as the UP code increments). Therefore, when the UP code is 1, the UP[0] signal is active to activate one transistor 806. When the UP code is 2, the UP[0] and UP[1] signals are active to activate two transistors 806, and so on. In this way, the duty cycle of the INP signal increases.

[0075] When the PULSE_p signal is valid, the UP code will decrease. When the CLK_IN signal level is high, transistor 814 and transistor block 800 will be turned off, while transistor 822 will be turned on. Since transistor 1100 operates in the cutoff region, the duty cycle of the INP signal will not change.

[0076] Figure 12 illustrates a fourth example schematic diagram of a DA circuit suitable for a DC corrector circuit shown in Figure 7, according to some embodiments. The DA circuit 706 is implemented using n-type transistor control only during the duty cycle of the INP signal. The DA circuit 706 includes a transistor 1200 that can be connected between a voltage source 802 and a node 804. A first terminal 1202 of the transistor 1200 can be connected to the voltage source 802, and a second terminal 1204 can be connected to the node 804. The gate 1206 of the transistor 1200 is grounded. Therefore, the transistor 1200 operates in the cutoff region and acts as an on switch (e.g., is turned off).

[0077] A first terminal 812 of transistor 814 can be connected to node 804, and a second terminal 816 of transistor 814 can be connected to node 818. A first terminal 820 of transistor 822 can be connected to node 818, and a second terminal 824 of transistor 822 can be connected to node 826. A transistor block 828 can be connected between node 826 and a reference voltage source 830 (e.g., ground). Transistor block 828 includes one or more transistors 832 connected in parallel, wherein a first terminal 834 of each transistor 832 can be connected to node 826, and a second terminal 836 of each transistor 832 can be connected to the reference voltage source 830.

[0078] In the illustrated embodiment, transistors 1200 and 814 are p-type transistors, and transistors 822 and each of 832 are n-type transistors. The DN code increments when the PULSE_p signal is active. When the CLK_IN signal level is high, transistor 814 is off, while transistors 822 and transistor block 828 are on. Transistors 832 in transistor block 828 are gradually turned on (e.g., as the DN code increments). Thus, when the DN code is 1, the DN[0] signal is active to turn on one transistor 832. When the DN code is 2, the DN[0] and DN[1] signals are active to turn on both transistors 832, and so on. In this way, the duty cycle of the INP signal is reduced.

[0079] When the PULSE_n signal is valid and the CLK_IN signal level is low, transistor 814 will be turned on and transistor 822 and transistor block 828 will be turned off. Since transistor 1200 operates in the cutoff region, the duty cycle of the INP signal will not change.

[0080] Figure 13 illustrates a schematic diagram of an example pulse generator (PG) circuit suitable for a duty cycle corrector circuit as shown in Figures 2 and 7, according to some embodiments. The INN_d signal is input as a first input signal to the NAND gate 1300 on signal line 240, and the INN_d signal is also input to the inverter circuit 1302 on signal line 1304. The inverted INN_d signal is output from the inverter circuit 1302 on signal line 1306 and input as a first input signal to the NAND gate 1308. The INP signal is input as a second input signal to the NAND gate 1308 on signal line 236, and the INP signal is input to the inverter circuit 1310 on signal line 1312. The inverted INP signal is output from the inverter circuit 1310 on signal line 1314 and input as a second input signal to the NAND gate 1300.

[0081] When the signal level of the INN_d signal is high and the signal level of the INP signal is low, a pulse is generated in the PULSE_n signal and the signal level of the PULSE_p signal is low. When the signal level of the INN_d signal is low and the signal level of the INP signal is high, a pulse is generated in the PULSE_p signal and the signal level of the PULSE_n signal is low. When both the signal levels of the INN_d and INP signals are high or both are low, the signal levels of the PULSE_p and PULSE_n signals are low. In other embodiments, the PG circuit 230 can be configured differently.

[0082] Figure 14 illustrates a method flowchart of the operation of the duty cycle corrector circuit shown in Figure 2 according to some embodiments. In one embodiment, in block 1400, the phase difference between the INP and INN_d signals is reduced to a given value (or substantially reduced to a given value). In one embodiment, the given value is zero. In block 1402, the duty cycle of the INP and INN_d signals is adjusted to a given value, or substantially a given value (e.g., fifty percent, or substantially fifty percent), such that the error in the duty cycle is zero or substantially zero.

[0083] Block 1400 begins at block 1404, where the phase difference between the delayed first signal (INP signal) and the delayed second signal (INN_d signal) is determined. In block 1406, it is determined whether the phase difference is equal to or substantially equal to a given value (e.g., zero). When it is determined that the phase difference is greater than the given value, the method flow continues to block 1408, where the delay of the delayed second signal is adjusted, and the method returns to block 1404. In the example embodiment of FIG2, the delay of the variable delay circuit 212 is adjusted to adjust the delay of the INN_d signal and reduce the phase difference.

[0084] When it is determined in block 1406 that the phase difference is equal to or substantially equal to a given value, the method flow proceeds to block 1410, where the delay value of the variable delay circuit (e.g., variable delay circuit 212 in FIG. 2) is locked (e.g., the DLL circuit is locked). The method flow then proceeds to block 1402. Block 1402 begins with block 1412, where the duty cycle error between the delayed first signal (INP signal) and the delayed second signal (INN_d signal) is determined. In block 1414, it is determined whether the duty cycle error is equal to or substantially equal to a given value (e.g., zero). When it is determined that the duty cycle error is greater than the given value, the method flow continues to block 1416, where the duty cycles of the delayed first signal and the delayed second signal are adjusted to reduce the duty cycle error, and the method returns to block 1412. In one embodiment, the duty cycle of the delayed first signal (INP signal) is adjusted, thereby adjusting the duty cycle of the delayed second signal (INN_d signal). In the example embodiment shown in Figure 2, the duty cycle of the INP signal is adjusted by the DA circuit 228 until the duty cycles of the delayed first and delayed second signals are equal to or substantially equal to fifty percent. In the illustrated embodiment, block 1402 is a correction loop in the background operation. Therefore, when it is determined in block 1414 that the duty cycle error is equal to or substantially equal to a given value (e.g., zero or substantially zero), the method returns to block 1412.

[0085] Figure 15 illustrates a method flowchart for operating the duty cycle corrector circuit shown in Figure 7 according to some embodiments. This method comprises the numerous blocks shown in Figure 14. For simplicity, these blocks will not be described in detail.

[0086] In one embodiment, in block 1400, the phase difference between the delayed first signal (INP signal) and the delayed second signal (INN_d signal) is reduced to a given value (or substantially a given value). For example, in block 1400, the phase difference is reduced to zero, or substantially zero. In block 1500, the duty cycles of the delayed first signal (INP signal) and the delayed second signal (INN_d signal) are adjusted to a given value, or substantially adjusted to a given value (e.g., fifty percent or substantially fifty percent).

[0087] Block 1500 begins at block 1412, where the cycle error between the delayed first signal (INP signal) and the delayed second signal (INN_d signal) is determined. In block 1414, it is determined whether the cycle error is equal to or substantially equal to a given value (e.g., zero). When it is determined that the cycle error is greater than the given value, the method flow continues to block 1416, where the cycles of the delayed first and delayed second signals are adjusted to reduce the cycle error, and the method returns to block 1412. In one embodiment, the cycle of the delayed first signal (INP signal) is adjusted, thereby adjusting the cycle of the second delayed signal (INN_d signal). When it is determined in block 1414 that the cycle error is equal to or substantially equal to the given value, a lock signal is generated in block 1502. The aforementioned lock signal locks the DCC circuit 702, which keeps the value of the DUTY_ctrl signal constant. Since the DC circuit 704 in Figure 7 outputs a digital code signal, the aforementioned output has a fixed duty cycle. Therefore, the process ends after the lock signal is generated.

[0088] The embodiments disclosed herein are described using block diagrams and / or operational illustrations of reference methods and systems. However, these embodiments are not limited to the operational flowcharts shown in Figures 14 and 15. In other embodiments, the operations illustrated in the blocks of Figures 14 and 15 may occur in a different order. For example, depending on the functions / actions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or sometimes these blocks may be executed in reverse order.

[0089] In one configuration, the duty cycle (DC) corrector circuit includes a delay-locked loop (DLL) circuit and a duty cycle correction (DCC) circuit that can be connected to the DLL circuit. The DCC circuit includes a duty adjustment (DA) circuit, a pulse generator circuit that can be connected to the DA circuit, and a duty correction (DC) circuit that can be connected to the PG circuit. The DA circuit receives a clock input signal and outputs a delayed first signal. The DA circuit can also adjust the duty cycle of the delayed first signal based on a received duty control signal. The PG circuit receives the delayed first signal and a delayed second signal, and outputs a first pulse signal and a second pulse signal. The DC circuit receives the first and second pulse signals from the PG circuit and outputs a duty control signal based on the signal levels of the first and second pulse signals. This duty control signal is received by the DA circuit and used to adjust the duty cycle of the delayed first signal. The DLL circuit includes a phase detector (PD) circuit, an inverter circuit, and a variable delay circuit that can be connected between the PD circuit and the inverter circuit. The PD circuit receives the delayed first signal and the delayed second signal and detects the phase difference between the delayed first signal and the second signal. An inverter circuit is used to receive a delayed first signal and output a second signal. A variable delay circuit can be used to adjust the delay of the second signal to produce a delayed second signal. The aforementioned adjustment of the delay of the second signal adjusts the delay between the delayed first signal and the delayed second signal.

[0090] In another embodiment, an electronic device includes a duty cycle (DC) corrector circuit. In a non-limiting, non-exclusive example, the DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty cycle correction (DCC) circuit that can be connected to the DLL circuit. The DCCC circuit includes a duty adjustment (DA) circuit, a pulse generator circuit that can be connected to the DA circuit, and a duty correction (DC) circuit that can be connected to the PG circuit. The DA circuit receives a clock_in signal and outputs a delayed first signal. The DA circuit can also adjust the duty cycle of the delayed first signal according to a received duty control signal. The PG circuit receives the delayed first signal and a delayed second signal and outputs a first pulse signal and a second pulse signal. The DC circuit receives the first pulse signal and the second pulse signal from the PG circuit and outputs a duty control signal according to the signal levels of the first pulse signal and the second pulse signal, the duty control signal being received by the DA circuit and used to adjust the duty cycle of the delayed first signal. The DLL circuit includes a phase detector (PD) circuit, an inverter circuit, and a variable delay circuit that can be connected between the PD circuit and the inverter circuit. The PD circuit receives a delayed first signal and a delayed second signal, and detects the phase difference between the delayed first and second signals. The inverter circuit receives the delayed first signal and outputs the delayed second signal. The variable delay circuit adjusts the delay of the second signal to produce the delayed second signal. The aforementioned adjustment of the second signal's delay adjusts the delay between the delayed first and delayed second signals.

[0091] In another embodiment, a method includes receiving a clock input (clock_in) signal and generating a delayed clock_in signal. The delayed clock_in signal is a delayed first signal. The delayed first signal is inverted to generate a second signal. The second signal is delayed to generate a delayed second signal. The phase difference between the delayed first signal and the delayed second signal is adjusted to reduce the phase difference until the phase difference is equal to or substantially equal to a first given value. In one embodiment, the first given value is zero. The method further includes adjusting a first duty cycle of the delayed first signal and a second duty cycle of the delayed second signal until the first and second duty cycles are equal to or substantially equal to a second given value (e.g., fifty percent). A delay-locked loop circuit is used to reduce the phase difference, and a duty cycle correction circuit is used to adjust the first and second duty cycles.

[0092] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other programs and structures to implement the same purposes as the embodiments introduced herein and / or to achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0093] 100: High-speed circuit 102: Duty Cycle (DC) Corrector Circuit 104: Circuit 200: DC calibrator circuit 202: Delay-Locked Loop (DLL) Circuit 204: DCC (Digital Cycle Correction) Circuit 206: Phase Detector (PD) Circuit 208: Charge Pump (CP) Circuit 210: Low-pass filter (LPF) circuit 212: Variable Delay Circuit 214: Inverter Circuit 216: Signal line (INP signal) 218: Signal line (INN_d signal) 220: Signal line 222: Signal line (CLK_IN signal) 224: Signal line 226: Signal line (DELAY_ctrl signal) 228: Operating Adjustment (DA) Circuit 230: Pulse Generator (PG) Circuit 232: Signal line (CLK_IN signal) 234: Signal line (INP signal) 236: Signal line (INP signal) 238: Signal line (INN signal) 240: Signal line (INN_d signal) 242: Operation control (DC) circuit 244: Signal line (PULSE_n signal) 246: Signal line (PULSE_p signal) 248: Signal line (DUTY_ctrl signal) 250: Signal line (CLK_OUT signal) 300: Area 302: Descent Edge 304: Rising Edge 306: Pulse 308: Descent Edge 310: Descent Edge 311: Pulse Width 312: Rising Edge 314: Rising Edge 316: Descent Edge 318: Pulse Width 320: Pulse width 322: Area 324: Rising Edge 326: Pulse 328: Descent Edge 330: Descent Edge 332: Pulse Width 400: Area 402: Descent Edge 404: Rising Edge 406: Pulse 408: Descent Edge 410: Descent Edge 411: Pulse Width 412: Descent Edge 414: Rising Edge 416: Rising Edge 418: Pulse Width 420: Pulse Width 422: Area 424: Descent Edge 426: Rising Edge 428: Pulse 430: Descent Edge 432: Pulse Width 500: Charge pump circuit 502: First terminal 504: Voltage Source 506: Second terminal 508: Node 510: First terminal 512: Charge Pump Circuit 514: Second terminal 516: Reference voltage source 518: Low-pass filter (LPF) circuit 520: Signal line (DUTY_ctrl signal) 522: Signal line (PULSE_n signal) 524: Signal line (PULSE_p signal) 600: Transistor 602: First terminal 604: Voltage Source 606: Second terminal 608: Node 610: First terminal 612: Transistor 614: Second terminal 616: Node 618: First terminal 620: Transistor 622: Second terminal 624: Node 626: First terminal 628: Transistor 630: Second terminal 632: Reference Voltage 634: Signal line (DUTY_ctrl signal) 636: Signal line (DUTY_ctrl signal) 700: DC calibrator circuit 702: DCC Circuit 704: DC Circuit 706: DA Circuit 710: Signal line 712: Signal line 800: Transistor Block 802: Voltage Source 804: Node 806: Transistor 808: First terminal 810: Second terminal 812: First terminal 814: Transistor 816: Second terminal 818: Node 820: First terminal 822: Transistor 824: Second terminal 826: Node 828: Transistor Block 830: Reference Voltage Source 832: Transistor 834: First terminal 836: Second terminal 900: Area 902: Descent Edge 904: Rising Edge 906: Pulse 908: Rising Edge 910: Rising Edge 912: Area 914: Descent Edge 916: Rising Edge 918: Pulse 1000: Area 1002: Descent Edge 1004: Rising Edge 1006: Pulse 1008: Descent Edge 1010: Descent Edge 1012: Area 1014: Descent Edge 1016: Rising Edge 1018: Pulse 1100: Transistor 1102: First terminal 1104: Second terminal 1106: Gate (TIE TO VDD signal) 1200: Transistor 1202: First terminal 1204: Second terminal 1206: Gate (TIE TO GND signal) 1300: Reverse and gate 1302: Inverter Circuit 1304: Signal line (INN_d signal) 1306: Signal line (inverted INN_d signal) 1308: Reverse and gate 1310: Inverting circuit 1312: Signal line (INP signal) 1314: Signal line (inverted INP signal) 1400: Process Block 1402: Process Block 1404: Process Block 1406: Process Block 1408: Process Block 1410: Process Block 1412: Process Block 1414: Process Block 1416: Process Block 1500: Process Block 1502: Process Block ΔV1: Signal level ΔV2: Signal level t0-t5: Time points UP[0]-UP[2]: Signal DN[0]-DN[2]: signal

Claims

1. A duty cycle corrector circuit, comprising: a delay-locked loop circuit; and a duty cycle correction circuit, which can be connected to the delay-locked loop circuit, wherein: The duty cycle correction circuit includes: a duty adjustment circuit for receiving a clock input signal and outputting a delayed first signal, the duty adjustment circuit further being configured to adjust a duty cycle of the delayed first signal according to a received duty control signal; a pulse generator circuit for connection to the duty adjustment circuit, the pulse generator circuit for receiving the delayed first signal and a delayed second signal and outputting a first pulse signal and a second pulse signal; and a duty correction circuit for connection to the pulse generator circuit, the duty correction circuit for receiving the first pulse signal and the second pulse signal from the pulse generator circuit, and outputting the duty control signal received via the duty adjustment circuit according to the signal levels of the first and second pulse signals, for adjusting the duty cycle of the delayed first signal; and the delay lock-in loop circuit includes: a phase detector circuit for receiving the delayed first signal and the delayed second signal and detecting a phase difference between the delayed first and delayed second signals; An inverter circuit is used to receive the delayed first signal and output a second signal; and a variable delay circuit is used to connect between the phase detector circuit and the inverter circuit, the variable delay circuit being used to adjust a delay of the second signal to generate the delayed second signal, the adjustment of the delay of the second signal being an adjustment of a delay between the delayed first signal and the delayed second signal.

2. The duty cycle corrector circuit of claim 1, wherein the delay-locked loop circuit comprises: a charge pump circuit that can be connected to the phase detector circuit; and a low-pass filter circuit that can be connected to the charge pump circuit and can be used to output a delay control signal for adjusting the delay of the second signal, wherein the variable delay circuit can be connected to the low-pass filter circuit to receive the delay control signal.

3. An electronic device having a duty cycle, comprising: a duty cycle corrector circuit, including: a delay-locked loop circuit; and a duty cycle correction circuit, which can be connected to the delay-locked loop circuit, wherein: The duty cycle correction circuit includes: a duty adjustment circuit for receiving a clock input signal and outputting a delayed first signal, the duty adjustment circuit further being configured to adjust a duty cycle of the delayed first signal according to a received duty control signal; a pulse generator circuit for connection to the duty adjustment circuit, the pulse generator circuit for receiving the delayed first signal and a delayed second signal and outputting a first pulse signal and a second pulse signal; and a duty correction circuit for connection to the pulse generator circuit, the duty correction circuit for receiving the first pulse signal and the second pulse signal from the pulse generator circuit, and outputting the duty control signal received via the duty adjustment circuit according to the signal levels of the first and second pulse signals, for adjusting the duty cycle of the delayed first signal; and the delay lock-in loop circuit includes: a phase detector circuit for receiving the delayed first signal and the delayed second signal, and detecting a phase difference between the delayed first and delayed second signals; An inverter circuit is provided, which can be used to receive the delayed first signal and output a second signal; and a variable delay circuit is provided, which can be connected between the phase detector circuit and the inverter circuit, the variable delay circuit being used to adjust a delay of the second signal to generate the delayed second signal, the adjustment of the delay of the second signal being an adjustment of a delay between the delayed first signal and the delayed second signal.

4. A method for a duty cycle corrector circuit, comprising: receiving a clock input signal; generating a delayed clock input signal as a delayed first signal; inverting the delayed first signal to generate a second signal; adjusting a delay of the second signal to generate a delayed second signal, wherein the delay is adjusted to reduce a phase difference between the delayed first signal and the delayed second signal, and the delay is adjusted until the phase difference is equal to or substantially equal to a first given value; receiving the delayed first signal and the delayed second signal and outputting a first pulse signal and a second pulse signal; and adjusting a first duty cycle of the delayed first signal and a second duty cycle of the delayed second signal according to the signal levels of the first pulse signal and the second pulse signal, until the first and second duty cycles are equal to or substantially equal to a second given value.

5. A duty cycle corrector circuit, comprising: A delayed-locked loop circuit; The circuit includes a duty cycle correction circuit connected to the delay-locked loop circuit, wherein the duty cycle correction circuit comprises: a duty adjustment circuit operable to receive a clock input signal and output a delayed first signal, the duty adjustment circuit being further operable to adjust a duty cycle of the delayed first signal based on the reception of a duty control signal; a pulse generation circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal; and a duty correction circuit operable to receive the first pulse signal and the second pulse signal from the pulse generation circuit, the duty correction circuit being operable to receive the first pulse signal and the second pulse signal from the pulse generation circuit, and output a duty control signal received by the duty adjustment circuit and used to adjust the duty cycle of the delayed first signal based on the signal levels of the first pulse signal and the second pulse signal.

6. A method for a duty cycle corrector circuit, comprising: Receives a clock input signal; A delayed clock input signal is generated as a first delayed signal; The delayed first signal is inverted to generate a second signal; a first clock signal and a second clock signal are generated based on the delayed first signal and the delayed second signal; a working control signal is generated based on the signal levels of the first clock signal and the second clock signal; and a first working cycle of the delayed first signal is adjusted based on the working control signal.

7. A method for a duty cycle corrector circuit, comprising: Receives a clock input signal; A delayed clock input signal is generated as a first delayed signal; The delayed first signal is inverted to generate a second signal; a phase difference between the delayed first signal and the delayed second signal is detected; a delay of the second signal is adjusted based on the phase difference; the delayed first signal and the delayed second signal are received and a first pulse signal and a second pulse signal are output; and a working control signal is output to a working adjustment circuit according to the signal level of the first pulse signal and the second pulse signal, the working control signal being used to adjust a working cycle of the delayed first signal.

8. A duty cycle corrector circuit, comprising: A delay-locked loop circuit includes: a phase detector circuit operable to: receive a delayed first signal and a delayed second signal; detect a phase difference between the delayed first signal and the delayed second signal; and generate a delay control signal; a variable delay circuit operablely connected to the phase detector circuit, wherein the variable delay circuit is operable to adjust a delay of the second signal based on the delay control signal to generate the delayed second signal; and a duty cycle correction circuit connected to the delay-locked loop circuit, wherein the duty cycle correction circuit is operable to output a duty control signal to adjust a duty cycle of the delayed first signal based on the level between a first pulse signal and a second pulse signal output from the received delayed first signal and the delayed second signal.

9. A duty cycle corrector circuit, comprising: A delay-locked loop circuit; a duty cycle correction circuit connected to the delay-locked loop circuit, wherein the duty cycle correction circuit is operable to: receive a clock input signal; generate a delayed clock input signal as a delayed first signal; invert the delayed first signal to generate a second signal; generate a first clock signal and a second clock signal based on the delayed first signal and the delayed second signal; generate a duty control signal based on the signal levels of the first clock signal and the second clock signal; and adjust a first duty cycle of the delayed first signal based on the duty control signal.

10. A method for a duty cycle corrector circuit, comprising: Receives a clock input signal; A delayed clock input signal is generated as a first delayed signal; The delayed first signal is inverted to generate a second signal; a phase difference between the delayed first signal and the delayed second signal is detected; the phase difference between the delayed first signal and the delayed second signal is reduced until the phase difference equals a first given value; the delayed first signal and the delayed second signal are received and a first pulse signal and a second pulse signal are output; and according to the signal levels of the first pulse signal and the second pulse signal, a working control signal is output to a working adjustment circuit, the working control signal being used to adjust a working cycle of the delayed first signal.

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