Process for fabricating a semiconductor structure comprising a working layer made of silicon carbide with improved electrical properties

Abstract

This invention relates to a method for fabricating a semiconductor structure, comprising the following steps: a) providing a single-crystal silicon carbide donor substrate and a silicon carbide carrier substrate; b) preparing a working layer to be transferred, comprising: - implanting a light element on the front side of the donor substrate to form a damaged profile, the damaged profile being particularly measurable by Laserford backscattering spectroscopy, the profile having a primary peak defining a deep defect of a buried fragile plane and a secondary peak defining a defect of a damaged surface layer; - through chemical... The donor substrate is etched and / or chemically mechanically polished to remove the damaged surface layer, forming a new front side of the donor substrate. The embedded weak plane and the new front side of the donor substrate define the working layer to be transferred, with a thickness between 50 nm and 1400 nm. c) The donor substrate and the carrier substrate are bonded on one side of the front side by molecular adhesion to form an assembly bonded along the bonding interface. d) Separation is performed along the embedded weak plane to transfer the working layer to the carrier substrate to form a semiconductor structure.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor materials for microelectronic devices. More particularly, it relates to a method for fabricating a semiconductor structure comprising a single-crystal silicon carbide working layer, which is transferred to a silicon carbide carrier substrate via a bonding interface. When vertical conductivity is required, this method can improve the electrical properties of the working layer and, consequently, the electrical properties of the semiconductor structure. [Previous Technology]

[0002] A common practice in forming semiconductor structures is to transfer a thin, high-crystal-quality semiconductor working layer onto a semiconductor carrier substrate that advantageously has lower crystal quality. A well-known thin-layer transfer solution is the Smart Cut® method, which is based on implanting lightweight elements and bonding them at the bonding interface via molecular adhesion. The lightweight elements are typically selected from hydrogen or helium ions, or combinations of both. Direct bonding via molecular adhesion can be achieved at ambient temperature or a specific temperature, under atmospheric or controlled pressure, particularly in a vacuum, by applying pressure to the substrate after the surfaces to be bonded are in close contact, or simply by the localized triggering of a bonding wave when the surfaces are arranged face-to-face. Various direct bonding methods can also be distinguished by pre-treating the surfaces to be bonded before bonding. Dry or wet chemical cleaning, surface activation via plasma or atomic bombardment (e.g., SAB (Surface Activated Bonding), ADB (Atomic Diffusion Bonding)), mechanical or chemimechanical smoothing of the surface, or the effective deposition of an additional layer to promote bonding can all be applied to the substrate to be bonded.

[0003] After the working layer is transferred to the carrier substrate, it is also common practice to subject the semiconductor structure to high-temperature or even extremely high-temperature annealing to restore the structure and electrical properties of the working layer and bonding interface. It is also well known practice to perform thermal smoothing or chemical mechanical polishing-based smoothing to obtain low surface roughness on the free surface of the transferred working layer intended to accommodate microelectronic components.

[0004] Especially in the field of power electronics, excellent conductivity of the active layer is desirable. Furthermore, it is advantageous to form a semiconductor structure with good conductivity between the active layer and the carrier substrate, thereby allowing the fabrication of vertical components.

[0005] For example, in a semiconductor structure comprising a single-crystal silicon carbide active layer and a lower-quality (single-crystal or polycrystalline) silicon carbide carrier substrate, the electrical characteristics of the active layer are expected to follow Ohm's law, and the resistivity of the active layer is defined by its doping degree. For compatibility with vertical devices, vertical conductivity, i.e., including conduction through the bonding interface, is expected to be operable: that is, the resistivity of the bonding interface is as low as possible, preferably less than 1 mohm·cm², or even less than 0.1 mohm·cm², and it has ohmic I(V) characteristics (current as a function of voltage).

[0006] The working layer made of single-crystal silicon carbide is transferred to a carrier substrate also made of single-crystal silicon carbide through an intermediate metal layer. The semiconductor structure is then subjected to final restorative annealing using the Smart Cut® method, which is performed in a temperature range of 1300°C-1700°C. This is insufficient to obtain the electrical characteristics mentioned above. As can be clearly seen in Figure 4(a), the I(V) curve, which represents the electrical characteristics of the working layer and the vertical conductivity (across the bonding interface) of the semiconductor structure, does not meet the target of ohmic behavior.

[0007] Of course, annealing at higher temperatures, typically above 1800°C, can partially improve the electrical properties of the working layer and semiconductor structure, but such a process is particularly cumbersome and more likely to cause other types of undesirable crystal defects, especially step bunching, which requires additional steps to protect the surface to prevent the occurrence of these defects, or additional steps to treat the surface afterward to eliminate these defects. [Summary of the Invention]

[0008] The present invention aims to overcome all or some of the aforementioned defects. In particular, the present invention relates to a method for fabricating a semiconductor structure in which the working layer is made of single-crystal silicon carbide and transferred to a silicon carbide carrier substrate via a bonding interface, the working layer possessing excellent electrical properties. The method according to the present invention further improves the vertical conductivity of the semiconductor structure, while providing simple implementation steps.

[0009] This invention relates to a method for fabricating a semiconductor structure, comprising the following steps: a) providing a single-crystal silicon carbide donor substrate and a silicon carbide carrier substrate; b) preparing a working layer to be transferred, comprising: - implanting a light element on the front side of the donor substrate to form a damaged profile, the damaged profile being particularly measurable by Laserford backscattering spectroscopy, the profile having a primary peak defining a depth defect of a buried fragile plane and a secondary peak defining a defect of a damaged surface layer; - removing the damaged surface layer by chemical etching and / or chemical mechanical polishing of the front side of the donor substrate to form a new front side of the donor substrate, the buried fragile plane and the new front side of the donor substrate together defining the working layer to be transferred, the thickness of which is between 50 nm and 1400 nm; c) bonding the donor substrate and the carrier substrate to one side of the front side by molecular adhesion to form an assembly bonded along the bonding interface; d) Separation is performed along the embedded vulnerable plane, allowing the working layer to transfer to the carrier substrate to form a semiconductor structure.

[0010] According to other advantageous and non-limiting features of the invention, individually or in any technically feasible combination: the removal in step b) results in a peel between 5 nm and 200 nm, preferably between 30 nm and 50 nm; the carrier substrate is made of a single crystal or polycrystalline material; the light element is hydrogen ions implanted at an energy between 30 keV and 210 keV, and at a dose between 1 × 10¹⁶ / cm² and 5 × 10¹⁷ / cm²; the fabrication method includes a final finishing step e) of the semiconductor structure produced in step d), step e) involving heat treatment at a temperature between 1300°C and 1700°C; step e) includes a chemical mechanical smoothing treatment of the free surface of the working layer; Step c) includes forming at least one additional layer on the front side of a donor substrate and / or on the front side of a carrier substrate prior to bonding via molecular adhesion; and the bonded assembly obtained after bonding via molecular adhesion includes an additional layer located between the donor substrate and the carrier substrate, the layer being adjacent to or containing the bonding interface; the at least one additional layer includes a material selected from silicon, tungsten, carbon, and titanium; the method further includes the step of fabricating at least one high-voltage microelectronic device on a semiconductor structure.

[0011] The present invention also relates to a high-voltage microelectronic device fabricated on a semiconductor structure obtained by the above-described fabrication method.

Implementation Method

[0015] This invention relates to a method for fabricating a semiconductor structure 100, the semiconductor structure 100 including a working layer 10 (FIG. 1) made of single-crystal silicon carbide (SiC) transferred onto a carrier substrate 2. The carrier substrate 2 may be formed of single-crystal or polycrystalline silicon carbide.

[0016] The fabrication method first includes step a) providing a donor substrate 1 made of single-crystal silicon carbide and a carrier substrate 2 made of single-crystal or polycrystalline silicon carbide (Fig. 2a). These two initial substrates 1 and 2 are preferably in the form of wafers with diameters of 100 mm, 150 mm or 200 mm (in a plane (x, y)), and the thickness (along the z-axis) is typically between 300 and 800 micrometers. They each have front sides 1a, 2a and back sides 1b, 2b. The surface roughness of the front sides 1a and 2a is advantageously selected to be less than 1 nm RMS, and the surface roughness is measured by atomic force microscopy (AFM) in a 20 micrometer × 20 micrometer scan.

[0017] The donor substrate 1 may, for example, be 4H or 6H polytype and have n-type or p-type doping. Later in this method, the working layer 10 of the semiconductor structure 100 will be separated from the donor substrate 1: therefore, the donor substrate must have the mechanical, electrical and crystallographic properties required for the target application.

[0018] According to a particular embodiment, the donor substrate 1 includes an initial substrate on which a donor layer has been formed by epitaxy. An epitaxial growth step is performed such that the donor layer has a lower crystal defect density than the initial substrate. Since the working layer 10 is separated from the donor layer in this case, the initial substrate does not need to have the same high quality level as the donor layer.

[0019] The carrier substrate 2 must meet the specifications regarding mechanical strength, as well as the potential specifications regarding the vertical conductivity electrical characteristics that allow for good operation of vertical power elements fabricated on and in the final semiconductor structure 100.

[0020] Then, the fabrication method includes step b), which involves preparing the working layer 10 to be transferred. This step first involves implanting a light element into the donor substrate 1 (or donor layer, if present) on the front side 1a to form an implantation profile of the light element and a damaged profile 11 (FIG. 2b). The two profiles are almost overlapping, the first corresponding to the concentration of the implanted element at its depth, and the other corresponding to the defects generated in the lattice of the donor substrate 1 SiC material when the element diffuses in.

[0021] The damaged profile 11 can be specifically measured by Rasherford backscattering spectroscopy (or RBS). RBS is well known to be used to determine the structure and composition of a material by analyzing the backscattering of a high-energy ion beam bombarding the material. In this case, defect regions present in the SiC lattice implanted in the donor substrate 1 can be revealed.

[0022] Curve A in Figure 3 corresponds to the RBS measurement of donor substrate 1 before implantation of light elements: the RBS profile is flat (except for a very narrow peak detected on the front side 1a, which appears on all measured samples and is therefore indistinguishable).

[0023] Curve B in Figure 3 corresponds to the RBS measurement of the donor substrate 1 after the implantation of the light element. The damage profile 11 has a primary peak 12a that defines the depth defect of the embedded weak plane 12 (which is essentially superimposed on the peak of the implanted light element concentration). The damage profile 11 also has a secondary peak 13a that defines the defect of the damaged surface layer 13.

[0024] The preferred implanted light elements are hydrogen, helium, or a combination of both. Referring to the Smart Cut® method mentioned in the introduction, these light elements will form microcavities distributed in a thin layer at and / or near the main peak 12a. This thin layer is parallel to the front side 1a of the donor substrate 1, i.e., parallel to the plane (x, y) in the figure. For simplicity, this thin layer is referred to as the embedded vulnerable plane 12.

[0025] The implantation energy of the light element is selected to achieve a specific depth in the donor substrate 1. Typically, the implantation energy of hydrogen ions is between 30 keV and 210 keV, and the dose is between 1×10¹⁶ / cm² and 5×10¹⁷ / cm², to form a buried vulnerable plane 12 at a depth between 100 nm and 1500 nm.

[0026] The secondary peak 13a visible in Figure 3 extends from the front side 1a of the donor substrate 1 to a variable depth between 10 nm and 100 nm, mainly depending on the implantation conditions (energy, dose, temperature, etc.). This damaged surface layer 13 may specifically include local crystal defects other than the implanted light element, extended defects (dislocations, etc.), or unintentionally introduced material. The surface roughness of the donor substrate 1 is not affected on the front side 1a after implantation and remains substantially similar to the initial roughness, typically less than 1 nm RMS.

[0027] After the ion implantation of light elements, step b) of preparing the working layer 10 includes removing the damaged surface layer 13 by chemical etching and / or by chemical mechanical polishing of the front side 1a of the donor substrate 1 (Fig. 2b').

[0028] Chemical etching is advantageously dry etching, such as reactive ion etching based on O2 / SF6 / Ar / F gases. Chemical mechanical polishing can be performed using polishing solutions (slurries) with alumina or diamond-based nanoabrasives and conventional methods of preparation of polyurethane or thermoplastic foam types.

[0029] Regardless of the technique used, the removal performed in step b) results in the stripping of SiC between 5 nm and 200 nm, preferably between 20 nm and 100 nm, and more preferably between 30 nm and 50 nm. After this material is stripped, a new front side 1a' of the donor substrate 1 is formed.

[0030] The objective is to remove the entire damaged surface layer 13 while maintaining good uniformity of the working layer 10 to be transferred: specifically, the working layer 10 is defined by the stripped-off embedded vulnerable plane 12 and the front side 1a' of the donor substrate 1. The thickness target for the working layer 10 is a non-uniformity of less than + / - 20%. The working layer 10 to be transferred typically has a thickness between 50 nm and 1400 nm.

[0031] Then, the manufacturing method includes step c), which includes bonding the donor substrate 1 on the front side 1a' and the carrier substrate 2 on the front side 2a by means of molecular adhesion to form an assembly 50 bonded along the bonding interface 51 (FIG. 2c).

[0032] As is well known, direct bonding via molecular adhesion does not require adhesive materials because the bonding is established at the atomic scale between the bonding surfaces. Several types of bonding via molecular adhesion exist, which differ significantly in terms of temperature, pressure, atmospheric conditions, or treatment before bringing the surfaces into contact. Notable examples include bonding systems at room temperature, with or without prior plasma activation of the surfaces to be bonded, atomic diffusion bonding (ADB), surface activated bonding (SAB), etc.

[0033] The bonding step c) may include routine procedures such as chemical cleaning (e.g., RCA cleaning) and surface activation (e.g., by oxygen or nitrogen plasma) or other surface treatments (e.g., brushing) before bringing the surfaces to be bonded into contact, which may promote the quality of the bonding interface 51 (low defect density, high adhesion energy).

[0034] According to the first embodiment, the front side 1a' of the donor substrate 1 and the front side 2a of the carrier substrate 2 are directly joined, as shown in FIG2c.

[0035] According to the second embodiment, step c) includes forming at least one additional layer (not shown) on the front side 1a' of the donor substrate 1 and / or the front side 2a of the carrier substrate 2 prior to bonding via molecular adhesion. This "at least one additional layer" may include materials such as silicon, tungsten, carbon, or titanium, which are advantageously selected to promote vertical conductivity in the final semiconductor structure 100. This intermediate layer can further promote bonding via molecular adhesion, particularly by eliminating residual roughness or surface defects present on the surfaces to be bonded. It can be conventionally planarized or smoothed to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, thereby promoting bonding; it can also be pretreated, for example, as mentioned above (cleaning, activation, etc.). The thickness of the additional layer is preferably selected between 0.5 nm and 50 nm.

[0036] The manufacturing method according to the present invention ultimately includes step d) separating along the buried vulnerable plane 12, so that the working layer 10 is transferred to the carrier substrate 2 to form a semiconductor structure 100 (FIG. 2d).

[0037] Separation along the embedded vulnerable plane 12 is typically achieved by heat treatment at a temperature between 800°C and 1200°C. Such heat treatment causes cavities and microcracks to develop in the embedded vulnerable plane 12, and they are pressurized by light elements in gaseous form until the cracks propagate along the vulnerable plane 12. Alternatively or commonly, mechanical stress may be applied to the bonded assembly 50, and particularly to the embedded vulnerable plane 12, to propagate or facilitate the mechanical propagation of cracks, thereby leading to separation. The result of this separation is a semiconductor structure 100, which on one hand includes a carrier substrate 2 and a single-crystal silicon carbide transfer working layer 3, and on the other hand includes the remainder 1” of the donor substrate. The doping degree and type of the working layer 10 are defined by selecting the characteristics of the donor substrate 1, or may subsequently be adjusted by known techniques for doping semiconductor layers.

[0038] The free surface 10a of the working layer 10 is typically rough after separation: for example, its roughness is between 5 nm and 100 nm RMS (AFM, 20 μm × 20 μm scan). Cleaning and / or smoothing steps can be applied to restore a good surface finish (typically, the roughness on a 20 μm × 20 μm AFM scan is less than a few angstroms RMS).

[0039] The fabrication method according to the invention advantageously includes a final finishing step e). Applied to the semiconductor structure 100 produced in step d), step e) may include chemical mechanical smoothing (CMP) of the free surface 10a of the working layer 10. A stripping process between 50 nm and 300 nm effectively restores the surface finish of the layer 10.

[0040] Step e) may also include heat treatment at a temperature between 1300°C and 1700°C. Such heat treatment is applied to remove residual light elements from the working layer 10 and to promote the rearrangement of the lattice of the working layer 10.

[0041] As mentioned above, if the final heat treatment is maintained at a temperature below 1800°C, it is difficult to obtain the good electrical properties of the working layer 10, which is typically transferred by implanting light elements. In the example of FIG4(a), the semiconductor structure not according to the invention is formed from a working layer made of single-crystal SiC (typical resistivity of about 20 mohm·cm) and transferred to a carrier substrate (typical resistivity of about 50 mohm·cm) via an additional metal layer; the implantation conditions in the donor substrate are as follows: 130 keV, 6*10¹⁶ H / cm², and a finishing heat treatment at 1700°C for 1 hour. It can be seen that the I(V) behavior of this structure is not ohmic.

[0042] In the method according to the invention, the heat treatment can be performed at a temperature less than or equal to 1700°C, or even at a temperature between 1400°C and 1500°C. In fact, perfect ohmic behavior of the bonding interface 51 of the working layer 10 and the semiconductor structure 100 made according to the invention is observed on the I(V) curve in FIG4(b). The semiconductor structure is formed by a working layer 10 made of single-crystal SiC (typical resistivity of about 20 mohm·cm) and transferred to a carrier substrate 2 (typical resistivity of about 20 mohm·cm) via an additional metal layer (a stack compared to the structure according to the prior art, see FIG4(a) above); the implantation in the donor substrate 1 (step b) occurs under conditions of 130 keV, 6*10¹⁶ H / cm², and the removal of the damaged surface layer 13 (step b)) is performed by peeling off 50 nm CMP and the heat treatment of step e) at 1700°C for 1 hour.

[0043] It should be noted that annealing up to 1900°C can obviously be performed, but these very high temperatures are not necessary for restoring the electrical quality of the thin layer 10 in the method according to the invention.

[0044] The applicant has determined that removing the damaged surface layer 13 (which is produced during ion implantation in step b of preparing the working layer 10 to be transferred from the donor substrate 1) is crucial for obtaining excellent electrical properties for the thin film 10 and the semiconductor structure 100 as a whole after transfer, while maintaining a reasonable final finishing heat treatment temperature.

[0045] If the damaged surface layer 13 is not removed during step b) of the method according to the invention, it results in residual defects 13' in the thin layer of the final semiconductor structure, as shown in FIG5(a): the residual defects 13' are still present in the heat treatment at high temperatures of up to 1700°C or even up to 1900°C, as observed in the transmission electron microscope (TEM) image. It can also be seen in FIG5(b) that the SSRM measurement (scanning diffusion resistance microscopy, a technique for measuring resistance by scanning the tip of an atomic force microscope) shows that the region with higher resistivity near the bonding interface 51 of the semiconductor structure is associated with the region of residual defects 13'. When the damaged surface layer 13 is not removed before bonding, the residual defects 13' present in the working layer 10 near the bonding interface 51 are the cause of the non-ohmic electrical behavior of the semiconductor structure, as shown in FIG4(a).

[0046] The manufacturing method according to the present invention can ensure the high quality of the working layer 10 in the final semiconductor structure 100 and its ohmic electrical characteristics by removing the damaged surface layer 13 caused by the implantation of light elements in the donor substrate 1.

[0047] The present invention also relates to one (or more) high-voltage microelectronic components, such as Schottky diodes, MOSFETs, etc., which can be fabricated on and / or within the semiconductor structure 100 produced by the aforementioned method. Because the semiconductor structure 100 is perfectly compatible with microelectronics technology and circuitry, conventional component fabrication steps can be implemented.

[0048] Of course, the present invention is not limited to the embodiments and examples described above. Modified embodiments may be added without departing from the scope of the present invention as defined by the claims. [Simplified Explanation of the Diagram]

[0012] Other features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings: FIG1 shows a semiconductor structure produced by the fabrication method according to the present invention; FIG2a, 2b, 2b', 2c, 2d and 2e show the steps of the fabrication method according to the present invention; FIG3 shows Laserford backscattering spectroscopy (RBS) measurements of the untreated donor substrate and the donor substrate with light element implantation in step d) of the fabrication method according to the present invention; FIG4 shows the current as a function of applied voltage I(V) curve, which is measured by two electrodes disposed on the semiconductor structure, the current path passing through the bonding interface of the structure: FIG4(a) shows a prior art semiconductor structure and FIG4(b) shows a semiconductor structure according to the present invention; FIG5(a) shows a transmission electron microscope (TEM) image of the final semiconductor structure not according to the present invention, and FIG5(b) shows an image of the final semiconductor structure not according to the present invention obtained by SSRM resistance measurement.

[0013] The same component symbols in the figures can be used for the same type of components. These figures are schematic diagrams and are not drawn to scale for readability. In particular, the layer thickness along the z-axis is not proportional to the lateral dimensions along the x and y axes, and the relative thickness of layers relative to each other is not considered in the schematic diagrams.

[0014] Various possibilities (variations and embodiments described and / or detailed in the following description) must be understood as not mutually exclusive and can be combined with each other.

Claims

1. A method for fabricating a semiconductor structure (100), comprising the steps of: a) providing a donor substrate (1) made of single-crystal silicon carbide and a carrier substrate (2) made of silicon carbide; b) preparing a working layer (10) to be transferred, comprising: Light elements are implanted on the front side (1a) of the donor substrate (1) to form a damaged profile (11) measured by Lasser backscattering spectroscopy. The damaged profile has a major peak (12a) of a deep defect that defines a buried weak plane (12) and a secondary peak (13a) of the defect that defines a damaged surface layer (13). The damaged surface layer (13) is removed by chemical etching and / or chemical mechanical polishing of the front side (1a) of the donor substrate (1) to form a new front side (1a') of the donor substrate (1). The buried weak plane (12) and the new front side (1a') of the donor substrate (1) together define the working layer (10) to be transferred, with a thickness between 50 nm and 1400 nm. The donor substrate (1) and the carrier substrate (2) are bonded to the new front side (1a') by molecular adhesion to form an assembly (50) bonded along a bonding interface (51); d) Separation is performed along the buried vulnerable plane (12) so that the working layer (10) is transferred to the carrier substrate (2) to form the semiconductor structure (100), wherein the ohmic electrical properties of the working layer (10) and the bonding interface (51) of the semiconductor structure are ensured when a final finishing heat treatment at a temperature less than or equal to 1700°C is applied to the semiconductor structure (100).

2. The method of request 1, wherein the removal in step b) results in a stripping between 5 nm and 200 nm.

3. The method of claim 1 or 2, wherein the material of the carrier substrate (2) is monocrystalline or polycrystalline.

4. The method of claim 1, wherein the light element is a hydrogen ion implanted with an energy between 30 keV and 210 keV and a dose between 1×10¹⁶ / cm² and 5×10¹⁷ / cm².

5. The method of claim 1, comprising a final finishing step e) of the semiconductor structure (100) produced by step d), the step e) involving a heat treatment at a temperature between 1300°C and 1700°C.

6. The method of claim 5, wherein step e) includes a chemical-mechanical smoothing treatment of one of the free surfaces (10a) of the working layer (10).

7. As in request item 1, where: Step c) includes forming at least one additional layer on the front side (1a) of the donor substrate (1) and / or on the front side (2a) of the carrier substrate (2) before bonding by molecular adhesion; and the assembly (50) obtained after bonding by molecular adhesion includes the additional layer located between the donor substrate (1) and the carrier substrate (2), the additional layer being adjacent to or including the bonding interface (51).

8. The method of claim 7, wherein the at least one additional layer comprises a material selected from silicon, tungsten, carbon, and titanium.

9. The method of claim 1, further comprising a plurality of steps of fabricating at least one high-voltage microelectronic element on the semiconductor structure (100).

10. The method of claim 1, wherein the removal in step b) results in a stripping between 30 nm and 50 nm.

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