Memory array and memory system

Abstract

This case discloses a memory array. In one embodiment, the memory array includes a set of resistive storage circuits, including a subset of first resistive storage circuits connected in parallel between a first region line and a second region line. The first and second region lines may extend along a first direction. In one embodiment, for each resistive storage circuit of the subset of first resistive storage circuits, current injected at a first common entry point of the first region line flows out through a first common exit point of the second region line, such that each resistive storage circuit of the subset of first resistive storage circuits may have the same or substantially equal resistive load.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The development of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices has led to an increased demand for memory devices. Generally speaking, memory devices can be classified as volatile memory devices and non-volatile memory devices. Volatile memory devices can store data while power is provided, but the stored data may be lost once power is off. Unlike volatile memory devices, non-volatile memory devices can retain data even after the power is turned off, but may be slower than volatile memory devices. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of the invention. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to digits and / or letters may be repeated in one embodiment of the invention. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0007] According to some embodiments, the memory system includes metal tracks with balanced resistive loads. In one embodiment, the memory system includes a set of resistive storage circuits connected in parallel between a first metal track and a second metal track. The first metal track may be a first region line, and the second metal track may be a second region line. The first metal track may be a first global line, and the second metal track may be a second global line. Region lines may be metal tracks that can connect subsets of resistive storage circuits, wherein global lines may be metal tracks that can connect two or more region lines. Region lines may be region bit lines or region select lines extending along a first direction, wherein global lines may be global bit lines or global select lines extending along a second direction.

[0008] Advantageously, the resistive storage circuit assembly can have a balanced resistive load. For each resistive storage circuit in the resistive storage circuit assembly, current can be injected at a common entry point of the first metal rail and flow out through a common exit point of the second metal rail. In one configuration, i) the sum of the length of the first portion of the first metal rail from the common entry point to the first point connecting the first resistive storage circuit and ii) the sum of the length of the second portion of the second metal rail from the common exit point to the second point connecting the first resistive storage circuit is equal to i) the sum of the length of the third portion of the first metal rail from the common entry point to the third point connecting the second resistive storage circuit and ii) the sum of the length of the fourth portion of the second metal rail from the common exit point to the fourth point connecting the second resistive storage circuit. The first metal rail and the second metal rail can comprise the same material. Therefore, the resistive storage circuit assembly can have metal rails with the same resistive load. By having the resistive storage circuit assembly have the same or balanced resistive load, data can be reliably stored or retrieved by the resistive storage circuit assembly.

[0009] Figure 1 is a schematic diagram of a memory system 100 according to one embodiment. In some embodiments, the memory system 100 is implemented as an integrated circuit. In some embodiments, the memory system 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits 125 (or memory cells 125) configured in a two-dimensional or three-dimensional array. Each storage circuit 125 may be connected to a corresponding gate line GL and a corresponding bit line BL. Each gate line GL may include any conductive material. The memory controller 105 may write data to or read data from the memory array 120 according to electrical signals transmitted via the gate line GL and the bit line BL. In other embodiments, the memory system 100 includes more, fewer, or different components than those shown in Figure 1.

[0010] The memory array 120 is a hardware component for storing data. In one embodiment, the memory array 120 is embodied as a semiconductor memory device. The memory array 120 includes a plurality of storage circuits or a plurality of storage circuits 125. In some embodiments, the memory array 120 includes gate lines GL0, GL1, ..., GLJ, each extending in a first direction, and bit lines BL0, BL1, ..., BLK, each extending in a second direction. The gate lines GL and bit lines BL may be conductive metal or conductive rails. Each gate line GL may include a word line and a control line. In one embodiment, each storage circuit 125 is connected to a corresponding gate line GL and a corresponding bit line BL, and can operate according to the voltage or current via the corresponding gate line GL and the corresponding bit line BL. In one embodiment, each storage circuit 125 may be a non-volatile storage circuit. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0011] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line controller 112, a gate line controller 114, and a timing controller 110. In one configuration, the gate line controller 114 is a circuit that provides voltage or current through one or more gate lines GL of the memory array 120. In one configuration, the bit line controller 112 is a circuit that provides voltage or current through one or more bit lines BL of the memory array 120 and senses voltage or current from the memory array 120 through one or more bit lines BL or one or more select lines. In one configuration, the timing controller 110 is a circuit that provides control signals or clock signals to the gate line controller 114 and the bit line controller 112 to synchronize the operation of the bit line controller 112 and the gate line controller 114. Bit line controller 112 can be connected to the bit line BL and select line of memory array 120, while gate line controller 114 can be connected to the gate line GL of memory array 120. In one example, to write data to storage circuit 125, gate line controller 114 applies voltage or current to storage circuit 125 via gate line GL connected to storage circuit 125, while bit line controller 112 applies voltage or current corresponding to the data to be stored to storage circuit 125 via bit line BL connected to storage circuit 125. In one example, to read data from storage circuit 125, gate line controller 114 applies voltage or current to storage circuit 125 via gate line GL connected to storage circuit 125, while bit line controller 112 senses voltage or current corresponding to the data stored by storage circuit 125 via select line or bit line connected to storage circuit 125. In some embodiments, memory controller 105 includes more, fewer, or different components compared to that shown in Figure 1.

[0012] Figure 2 shows a schematic diagram of a three-dimensional memory array 210A, ..., 210N according to one embodiment. In some embodiments, the memory array 120 includes memory arrays 210A, ..., 210N. Each memory array 210 includes a plurality of storage circuits 125 configured in a three-dimensional array. In some embodiments, each memory array 210 may include the same number of storage circuits 125. In some embodiments, two or more memory arrays 210 may include different numbers of storage circuits 125. In one configuration, memory arrays 210A, ..., 210N are stacked along the Z direction. Each memory array 210 may have a bit line BL on one side of the memory array 210 and a select line SL on the other side of the memory array 210. In some embodiments, two adjacent memory arrays 210 may share the select line SL. In some embodiments, two adjacent memory arrays 210 may share the bit line BL. For example, memory arrays 210N-1 and 210N share or are electrically coupled to a set of select lines SL. For example, memory arrays 210N-2 and 210N-1 share or are electrically coupled to a set of bit lines BL. By sharing the select line SL and / or bit lines BL, the number of drivers in the memory controller 105 used to apply signals via the select line SL and / or bit lines BL can be reduced to achieve area efficiency. In some embodiments, memory array 120 includes additional memory arrays that may have separate select lines SL and / or bit lines BL compared to those shown in Figure 2.

[0013] Figure 3 shows a schematic diagram of a portion of a three-dimensional memory array 210 including metal tracks with balanced resistive loads according to one embodiment. In Figure 3, the memory array 210 includes a first set of resistive storage circuits and a second set of resistive storage circuits. In one configuration, the first set of resistive storage circuits includes a subset of storage circuits 310

[00] , ..., 310

[03] , which are electrically coupled to a global bit line BL[0] and a global select line SL[0] extending along the Y direction. In one configuration, the second set of resistive storage circuits includes a subset of resistive storage circuits 310

[10] , ..., 310

[13] , which are electrically coupled to a global bit line BL[1] and a global select line SL[1] extending along the Y direction. Each subset of resistive storage circuits 310 may include F resistive storage circuits 380 (e.g., storage circuits 125) arranged along the Z direction. Each set of resistive storage circuits may include more subsets of resistive storage circuits 310 along the Y direction than shown in Figure 3. The memory array 210 may include more sets of resistive storage circuits than shown in Figure 3, which are stacked along the X direction. By configuring the storage circuits 380 as shown in Figure 3, the storage density of the memory array 210 can be increased.

[0014] In one configuration, each subset 310 of resistor storage circuits includes F resistor storage circuits 380 arranged along the Z direction. Each resistor storage circuit 380 may include a switch SM coupled between the region select line LSL and the region bit line LBL, and one or more resistor cells M. Each switch SM may be embodied as a transistor (e.g., MOSFET, GAAFET, FinFET, etc.). Each switch SM may be an N-type transistor or a P-type transistor. Each resistor cell M may be embodied as a resistive random access memory (RAM) component, a phase-change RAM (PCM) component, a magnetoresistive RAM (MRAM) component, or any resistor storage component. Each switch SM may include a first electrode (e.g., a source electrode) coupled to the region select line LSL, a second electrode (e.g., a drain electrode) coupled to the first electrode of the resistor cell M, and a third electrode (e.g., a gate electrode) coupled to the corresponding word line WL[X][Z]. The character lines WL[X][Z] may extend along the X direction to connect the gate electrodes of corresponding switches SM in different sets to the memory controller (e.g., gate line controller 114). In one state, the switch SM is enabled in response to a high voltage (e.g., logic "1") applied to the character lines WL[X][Z] to electrically couple the area selection line LSL to the resistor cell M. In another state, the switch SM is disabled in response to a low voltage (e.g., logic "0") applied to the character lines WL[X][Z] to electrically decouple the area selection line LSL from the resistor cell M. Depending on the voltage applied to the resistor cell M or the current applied via the resistor cell M, each resistor cell M may have a resistance corresponding to the programmed data.

[0015] In one configuration, a subset 310 of the resistor storage circuit 380 is connected in parallel between the region selection line LSL and the region bit line LBL. The region selection line LSL may be connected to the metal track of the first port (e.g., the first electrode of the switch SM) of the resistor storage circuit subset 310. The region bit line LBL may be connected to the metal track of the second port (e.g., the second electrode of the resistor unit M) of the resistor storage circuit subset 310. The region selection line LSL may extend along the Z direction and connect to a corresponding point of the global selection line SL extending along the Y direction. Similarly, the region bit line LBL may extend along the Z direction and connect to a corresponding point of the global bit line BL extending along the Y direction.

[0016] In some embodiments, the global bit line BL[X] is connected to the corresponding switch SB[X]. Region bit lines LBL[X0], ..., LBL[X3] can be electrically coupled to memory controller 105 (e.g., bit line controller 112) via the global bit line BL[X] and the switch SB[X]. Each switch SB[X] can be embodied as a transistor (e.g., MOSFET, GAAFET, FinFET, etc.). Each switch SB[X] can be an N-type transistor or a P-type transistor. Each switch SB[X] may include a first electrode (e.g., source electrode) connected to the global bit line BL[X], a second electrode (e.g., drain electrode) connected to memory controller 105 (e.g., bit line controller 112) via a metal rail, and a third electrode (e.g., gate electrode) connected to the corresponding switch control line SBL. The switch control line SBL can be a metal rail extending in the X direction to connect memory controller 105 (e.g., gate line controller 114) to the gate electrode of switch SB. Based on the voltage or signal applied via the switch control line SBL, one or more switches SB connected to the switch control line SBL can be enabled or disabled. For example, in response to a voltage corresponding to logic state "1" provided via the switch control line SBL[X], switch SB[X] can be enabled to electrically couple memory controller 105 (e.g., bit line controller 112) to global bit line BL[X]. For example, in response to a voltage corresponding to logic state "0" provided via the switch control line SBL[X], switch SB[X] can be disabled to electrically decouple memory controller 105 (e.g., bit line controller 112) from global bit line BL[X].

[0017] In some embodiments, the global select line SL[X] is connected to the corresponding switch SS[X]. Region select lines LSL[X0], ..., LSL[X3] can be electrically coupled to memory controller 105 (e.g., bit line controller 112) via the global select line SL[X] and the switch SS[X]. Each switch SS can be embodied as a transistor (e.g., MOSFET, GAAFET, FinFET, etc.). Each switch SS[X] can be an N-type transistor or a P-type transistor. Each switch SS[X] may include a first electrode (e.g., drain electrode) connected to the global select line SL[X], a second electrode (e.g., source electrode) connected to memory controller 105 (e.g., bit line controller 112) via a metal rail, and a third electrode (e.g., gate electrode) connected to the corresponding switch control line SSL. The switch control line SSL can be a metal rail extending in the X direction to connect memory controller 105 (e.g., gate line controller 114) to the gate electrode of the switch SS. Based on the voltage or signal applied via the switch control line SSL, one or more switches SS connected to the switch control line SSL can be enabled or disabled. For example, in response to a voltage corresponding to logic state "1" provided via the switch control line SSL[X], switch SS[X] can be enabled to electrically couple memory controller 105 (e.g., bit line controller 112) to global select line SL[X]. For example, in response to a voltage corresponding to logic state "0" provided via the switch control line SSL[X], switch SS[X] can be disabled to electrically decouple memory controller 105 (e.g., bit line controller 112) from global select line SL[X].

[0018] In one configuration, switches SB and SS can be operated or configured according to voltage or signal from memory controller 105 (e.g., gate line controller 114) to selectively electrically couple the resistor storage circuit set to the corresponding global lines BL and SL. For example, during a first time period, switches SB[0] and SS[0] can be enabled simultaneously while switches SB[1] and SS[1] are disabled to operate or configure the storage unit set 310

[00] , ..., 310

[03] . For example, during a second time period, switches SB[1] and SS[1] can be enabled simultaneously while switches SB[0] and SS[0] are disabled to operate or configure the storage unit set 310

[10] , ..., 310

[13] .

[0019] In some embodiments, memory array 210 includes either switch SB or SS, but may lack the other of switch SB or SS. For example, memory array 210 includes switch SB as shown in Figure 3, wherein switch SS is omitted, and global select lines SL[0], SL[1] are connected to memory controller 105 (e.g., bit line controller 112) via metal rails. For example, memory array 210 includes switch SS as shown in Figure 3, wherein switch SB is omitted, and global bit lines BL[0], BL[1] are connected to memory controller 105 (e.g., bit line controller 112) via metal rails. Switch SS or SB can be used or operated to selectively electrically couple a corresponding resistive storage circuit set to or decouple it from the corresponding global line.

[0020] In one state, the resistor storage circuit set 310

[00] , ..., 310

[13] has a resistive load that is the same as or substantially equivalent to that of the metal rail. In one state, switch SB[X] is connected to the common entry point PB[X] of the global bit line BL[X]. In one state, switch SS[X] is connected to the common exit point PS[X] ​​of the global selection line SL[X]. The regional bit line LBL can be connected to the corresponding point of the global bit line BL, and the regional selection line LSL can be connected to the corresponding point of the global selection line SL. For each resistor storage circuit subset 310, current can be injected at the common entry point PB[X] of the global bit line BL[X] and flow out through the common exit point PS[X] ​​of the global selection line SL[X]. In one state, the sum of i) the length of the first portion of the global bit line BL[X] from the common entry point PB[X] to the first point connecting the first resistor storage circuit subset 310[XY] and ii) the length of the second portion of the global selection line SL[X] from the common exit point PS[X] ​​to the second point connecting the first resistor storage circuit subset 310[XY] is equal to the sum of i) the length of the third portion of the global bit line BL[X] from the common entry point PB[X] to the third point connecting the second resistor storage circuit subset 310[XY+1] and ii) the length of the fourth portion of the global selection line SL[X] from the common exit point PS[X] ​​to the fourth point connecting the second resistor storage circuit subset 310[XY+1]. The global bit line BL and the global selection line SL may comprise the same material. Therefore, the resistor storage circuit subsets 310[X0], ..., 310[X3] may have metal tracks with the same resistive load. By having the global bit line BL and the global select line SL have the same or balanced resistive load, data can be reliably stored or retrieved using a resistive storage circuit assembly.

[0021] Figure 4A shows a schematic diagram of a resistive storage circuit subset 310A comprising a region bit line LBL and a region select line LSL with balanced resistive loads according to one embodiment. In one example, the resistive storage circuit subset 310A has metal tracks with the same or substantially equivalent resistive loads. The storage circuit subset 310A may be connected in parallel between the region select line LSL and the region bit line LBL. Each resistive storage circuit may be connected to a corresponding point on the region bit line LBL and a corresponding point on the region select line LSL.

[0022] For each resistive storage circuit of the storage circuit subset 310A, current can be injected at the common entry point PLB of the region bit line LBL and flow out through the common exit point PSB of the region selection line LSL. For example, the current can flow along path 450 through the common entry point PLB, the first resistive storage circuit 380[0], and the common exit point PSB. For example, the current can flow along path 410 through the common entry point PLB, the second resistive storage circuit 380[F-1], and the common exit point PSB. The memory controller can sense the current through path 450 during a first time period to determine the data stored by the resistive storage circuit 380[0], and sense the current through path 410 during a second time period to determine the data stored by the resistive storage circuit 380[F-1]. In one configuration, i) the length of the first portion of the region bit line LBL from the common entry point PLB to the first point connected to the first resistor storage circuit 380[0] and ii) the length of the second portion of the region selection line LSL from the common exit point PSB to the second point connected to the first resistor storage circuit 380[0] are equal to i) the length of the third portion of the region bit line LBL from the common entry point PLB to the third point connected to the second resistor storage circuit 380[F-1] and ii) the length of the fourth portion of the region selection line LSL from the common exit point PSB to the fourth point connected to the second resistor storage circuit 380[F-1]. The region bit line LBL and the region selection line LSL may comprise the same material. Therefore, the resistor storage circuit subset 310A may have metal tracks with the same resistive load. By having the region bit line LBL and the region selection line LSL have the same or balanced resistive load, data can be reliably stored or retrieved by the resistor storage circuit subset 310A.

[0023] Figure 4B shows a schematic diagram of a subset 310B of resistive storage circuits including a region bit line LBL and a region select line LSL with balanced resistive loads according to one embodiment. The subset 310B is similar to the subset 310A of Figure 4A, except that it includes resistive storage circuits 380[0]', ..., 380[F-1]' each having two or more resistive units M. The two or more resistive units M may be connected in series between the region bit line LBL and the region select line LSL. By implementing two or more resistive units M for each resistive storage circuit 380', multi-level data can be stored in each resistive storage circuit 380' to increase storage density.

[0024] Figure 5A shows a schematic diagram of a first switch SB connected to a region bit line LBL and a second switch SS connected to a region selection line LSL of a storage circuit subset 310 according to one embodiment. As described above with respect to Figure 3, a memory controller 105 (e.g., bit line controller 112) may be electrically coupled to the resistive storage circuit subset 310 via switches SB and SS. Switch SB may be embodied as an N-type transistor or a P-type transistor, and switch SS may be embodied as an N-type transistor or a P-type transistor. The memory controller 105 (e.g., gate line controller 114) may simultaneously enable or disable switches SS and SB to configure or operate one or more resistive storage circuits 380 in the resistive storage circuit subset 310.

[0025] In some embodiments, the resistor storage circuit subset 310 is connected to one of switches SB and SS, while the other switch SB and SS is omitted. For example, in Figure 5B, switch SB is connected to the area bit line LBL without switch SS. For example, in Figure 5C, switch SS is connected to the area selection line LSL without switch SB. In one case, each switch may have parasitic resistance, which can lead to reduced operating speed or increased power consumption. As shown in Figures 5B or 5C, by omitting one of switches SB and SS, parasitic resistance can be reduced to improve operating speed or power efficiency.

[0026] Figure 6 shows a schematic diagram of a portion of a three-dimensional array comprising a plurality of switches SB

[00] , ..., SB

[03] , SB

[10] , ..., SB

[13] connected to global bit lines BL[0], BL[1], according to one embodiment. In one embodiment, memory array 210' is similar to memory array 210 in Figure 3 except that memory array 210' includes switches SB

[00] , ..., SB

[03] connected to global bit lines BL[0] and switches SB

[10] , ..., SB

[13] connected to global bit lines BL[1], without switches SS[0], SS[1]. Therefore, for the sake of brevity, detailed descriptions of its repeated portions are omitted herein. In some embodiments, memory array 210' includes switches SB

[00] , ..., SB

[03] connected to global select line SL[0] and switches SB

[10] , ..., SB

[13] connected to global select line SL[1]. Switches SB

[00] , ..., SB

[03] can be simultaneously enabled or disabled based on signals or pulses from memory controller 105 (e.g., gate line controller 114). Similarly, switches SB

[10] , ..., SB

[13] can be simultaneously enabled or disabled based on signals or pulses from memory controller 105 (e.g., gate line controller 114). In one approach, during a first time period, switches SB

[00] , ..., SB

[03] are enabled, while switches SB

[10] , ..., SB

[13] are disabled. In another approach, during a second time period, switches SB

[10] , ..., SB

[13] are enabled, while switches SB

[00] , ..., SB

[03] are disabled. In one configuration, the switches can be configured in parallel to the global line, thereby reducing the parasitic resistance caused by the switches due to the parallel configuration. Furthermore, the resistive load at the global line can be distributed at different points on the global line to allow for more reliable operation of the resistive storage circuitry.

[0027] Figure 7 shows a flowchart of a method 700 for configuring or operating a set of storage circuits (e.g., storage circuit 125) according to some embodiments. Method 700 may be performed by memory controller 105 of Figure 1. In some embodiments, method 700 is performed by other entities. In some embodiments, method 700 includes more, fewer, or different operations than those shown in Figure 7.

[0028] In operation 710, the memory controller 105 selects a subset 310 of memory cells from the set of memory cells. Each memory cell may be a resistive storage circuit. Each resistive storage circuit may include one or more resistive cells. Each resistive cell may be embodied as a resistive random access memory (RAM) component, a phase-change RAM (PCM) component, a magnetoresistive RAM (MRAM) component, or any resistive storage component. In one configuration, the subset of memory cells is connected in parallel between the region bit line LBL and the region select line LSL. The region bit line LBL may extend along a first direction (e.g., the Z direction), and the region select line LSL may extend along a first direction (e.g., the Z direction).

[0029] In operation 720, memory controller 105 selects memory cells of a selected subset. In operation 730, memory controller 105 configures the selected memory cells based on the current through the common point of the selected subset. In one method, to write data to a selected memory cell, memory controller 105 may apply a write voltage to a word line connected to the selected memory cell and another write voltage to the global bit line BL and region bit line LBL electrically coupled to the selected memory cell. Memory controller 105 may apply a ground voltage to the global select line SL and region select line LSL electrically coupled to the selected memory cell. In one method, to read data stored in a selected memory cell, memory controller 105 may apply a read voltage to a word line connected to the selected memory cell and another read voltage to the global bit line BL and region bit line LBL electrically coupled to the selected memory cell. The memory controller 105 can apply a ground voltage to the global select line SL and the local select line LSL, which are electrically coupled to the selected memory cell. In response to the applied read voltage, the memory controller 105 can sense the current passing through the selected memory cell, for example, through the global bit line BL and the local bit line LBL. Based on the sensed current, the memory controller 105 can determine the data stored in the selected memory cell.

[0030] In one method, current is injected via a common entry point of the region bit line LBL and flows out via a common exit point of the region select line LSL. Each storage circuit can be connected to a corresponding point of the region bit line LBL and a corresponding point of the region select line LSL. For a memory cell of the memory cell subset 310, current can be injected at the common entry point PLB of the region bit line LBL and flows out via the common exit point PSB of the region select line LSL. For example, the current can flow along path 450 through the common entry point PLB, the first resistive storage circuit 380[0], and the common exit point PSB. For example, the current can flow along path 410 through the common entry point PLB, the second resistive storage circuit 380[F-1], and the common exit point PSB. In one state, the sum of i) the length of the first portion of the region bit line LBL from the common entry point PLB to the first point connected to the first resistive storage circuit 380[0] and ii) the length of the second portion of the region selection line LSL from the common exit point PSB to the second point connected to the first resistive storage circuit 380[0] is equal to the sum of i) the length of the third portion of the region bit line LBL from the common entry point PLB to the third point connected to the second resistive storage circuit 380[F-1] and ii) the length of the fourth portion of the region selection line LSL from the common exit point PSB to the fourth point connected to the second resistive storage circuit 380[F-1]. The region bit line LBL and the region selection line LSL may comprise the same material. Therefore, a subset 310 of memory cells may have the same resistive load. By ensuring that the current injected into the common entry point PLB flows out through the common exit point PSB of the memory cell for any memory cell in the subset of memory cells, the subset of memory cells may have metal tracks with the same or balanced resistive loads. Balanced resistive loads allow for reliable operation or configuration of subsets of memory cells.

[0031] In operation 740, the memory controller 105 determines whether there are additional memory units in the selected subset to be configured. Additional memory units can be positioned above the selected memory units along the Z-direction. If additional memory units exist in the selected subset, the memory controller 105 can proceed to operation 720 and select subsequent memory units in the subset. If no additional memory units exist in the selected subset, the memory controller 105 can proceed to operation 750.

[0032] In operation 750, the memory controller 105 determines whether there is an additional subset of memory cells to be configured. The additional subset of memory cells may be disposed on top of the set of memory cells along the Y direction. If an additional subset exists, the memory controller 105 may proceed to operation 710 and select a subsequent subset of memory cells. In some embodiments, the memory controller 105 may select another set of memory cells and may proceed to operation 710 for that other set of memory cells. The other set of memory cells may be stacked or disposed on top of the set of memory cells along the X direction. If no additional set of memory cells exists, the memory controller 105 may terminate in operation 760.

[0033] Referring now to Figure 8, an example block diagram of a computing system 800 according to some embodiments of the present invention is shown. The computing system 800 can be used by a circuit or layout designer for integrated circuit design. As used herein, "circuit" refers to the interconnection of electrical components, such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices used to implement the desired functionality. The computing system 800 includes a host device 805 associated with a memory device 810. The host device 805 can be used to receive input from one or more input devices 815 and provide output to one or more output devices 820. The host device 805 can be used to communicate with the memory device 810, the input device 815, and the output device 820 through appropriate interfaces 825A, 825B, and 825C, respectively. The computing system 800 can be implemented in a variety of computing devices, such as computers (e.g., desktop computers, laptop computers, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and / or layout design using the main device 805.

[0034] Input device 815 may include any of a variety of input technologies, such as a keyboard, pen, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input port, one or more buttons, dial pad, joystick, and any other input peripheral device associated with main device 805 that allows external sources, such as users (e.g., circuit or layout designers), to input information (e.g., data) into the main device and send instructions to the main device. Similarly, output device 820 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, light-emitting diode, headphones, video device, and any other output peripheral device for autonomous device 805 to receive information (e.g., data). The "data" input into main device 805 and / or output by autonomous device may include any of a variety of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing by computing system 800.

[0035] The main device 805 includes one or more processing units / processors or associated with them, such as central processing unit (CPU) cores 830A-830N. CPU cores 830A-830N may be implemented as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other type of processing unit. Each of the CPU cores 830A-830N can be used to execute instructions for running one or more applications of the main device 805. In some embodiments, the instructions and data for running one or more applications may be stored in memory device 810. The main device 805 is also used to store the results of running one or more applications in memory device 810. Therefore, the main device 805 can request memory device 810 to perform various operations. For example, host device 805 may request memory device 810 to read data, write data, update or delete data, and / or perform management or other operations. One such application that host device 805 may run is standard cell application 835. Standard cell application 835 may be part of a computer-aided design or electronic design automation software suite that a user of host device 805 can use to use, generate, or modify standard cells of a circuit. In some embodiments, instructions for executing or running standard cell application 835 may be stored in memory device 810. Standard cell application 835 may be executed by one or more CPU cores 830A-830N using instructions associated with the standard cell application from memory device 810. In one instance, standard cell application 835 allows a user to assist in integrated circuit design using pre-generated schematics and / or layout designs of memory system 100 or a portion thereof. After the layout design of the integrated circuit is completed, for example, multiples of the integrated circuit including memory system 100 or a portion thereof can be manufactured by the manufacturing facility according to the layout design.

[0036] Referring again to Figure 8, the memory device 810 includes a memory controller 840 for reading data from or writing data to the memory array 845. The memory array 845 may include various volatile and / or non-volatile memory. For example, in some embodiments, the memory array 845 may include anti-flash memory cores. In other embodiments, the memory array 845 may include anti-flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores suitable for use in a memory array. The memories within the memory array 845 can be controlled individually and independently by the memory controller 840. In other words, the memory controller 840 can be used to communicate individually and independently with each memory within the memory array 845. By communicating with the memory array 845, the memory controller 840 can be used to read data from or write data to the memory array in response to instructions received from the autonomous device 805. Although shown as part of the memory device 810, in some embodiments, the memory controller 840 may be part of the host device 805 or another component of the computing system 800 and associated with the memory device. The memory controller 840 may be implemented as logic circuitry in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller 840 can be used to retrieve instructions associated with the standard cell application 835 stored in the memory array 845 of the memory device 810 upon receiving a request from the host device 805.

[0037] It should be understood that only some components of the computing system 800 are shown and described in Figure 8. However, the computing system 800 may include other components, such as various batteries and power supplies, network interfaces, routers, switches, external memory systems, controllers, etc. In general, the computing system 800 may include any of a variety of hardware, software, and / or firmware components that are necessary or deemed necessary in performing the functions described herein. Similarly, the main device 805, the input device 815, the output device 820, and the memory device 810 including the memory controller 840 and the memory array 845 may include other hardware, software, and / or firmware components that are deemed necessary or required in performing the functions described herein.

[0038] One aspect of this specification relates to a memory array. In some embodiments, the memory array includes a set of resistive storage circuits, the set of resistive storage circuits including a first subset of resistive storage circuits and a second subset of resistive storage circuits. In some embodiments, the first subset of resistive storage circuits is connected in parallel between a first region line and a second region line. In some embodiments, the first region line and the second region line extend along a first direction. In some embodiments, the second subset of resistive storage circuits is connected in parallel between a third region line and a fourth region line. In some embodiments, the third region line and the fourth region line extend along a first direction. In some embodiments, the first region line and the third region line are electrically coupled to a first global line extending along a second direction.

[0039] One aspect of this specification relates to a memory system. In some embodiments, the memory system includes a memory array and a controller. In some embodiments, the memory array includes a set of resistive storage circuits, the set of resistive storage circuits including a subset of first resistive storage circuits connected in parallel between a first region line and a second region line. In some embodiments, the first region line and the second region line extend along a first direction. In some embodiments, the controller is coupled to the memory array. In some embodiments, the memory controller is configured to apply a voltage to the first region line for each resistive storage circuit of the first resistive storage circuit subset. In some embodiments, the memory controller is configured to read data stored by each resistive storage circuit of the first resistive storage circuit subset in response to a voltage-sensing current for each resistive storage circuit of the first resistive storage circuit subset. In some embodiments, current injected at a first common entry point of the first region line for each resistive storage circuit of the first resistive storage circuit subset flows out via a first common exit point of the second region line.

[0040] One aspect of this specification relates to a method of operating a memory system. In some embodiments, the method includes applying a voltage to a first common entry point of a first metal track by a controller during a first time period. In some embodiments, a first set of resistive storage circuits is connected in parallel between the first metal track and a second metal track. In some embodiments, the method includes sensing a first current from a first resistive storage circuit of the first set of resistive storage circuits in response to a voltage via a first common exit point of the second metal track by a controller during the first time period. In some embodiments, the method includes determining, by a controller, first data stored by the first resistive storage circuit of the first set of resistive storage circuits based on the first current during the first time period. In some embodiments, the method includes applying a voltage to the first common entry point of the first metal track by a controller during a second time period. In some embodiments, the method includes sensing, by a controller, a second current from a second resistive storage circuit of the first set of resistive storage circuits in response to a voltage via a first common exit point of the second metal track during the second time period. In some embodiments, the method includes determining, by a controller, second data stored by the second resistive storage circuit of the first set of resistive storage circuits based on the second current during the second time period.

[0041] The foregoing summarizes the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this invention. Those skilled in the art should understand that one embodiment of this invention can be easily used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this invention, and that such equivalent constructions can be modified, replaced, and substituted in various ways herein without departing from the spirit and scope of one embodiment of this invention. [Simplified Explanation of the Diagram]

[0004] An embodiment of this invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standards, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic diagram of a memory system according to an embodiment. Figure 2 is a schematic diagram showing a three-dimensional memory array according to an embodiment. Figure 3 is a schematic diagram showing a portion of a three-dimensional memory array including metal tracks with balanced resistive loads according to an embodiment. Figure 4A is a schematic diagram showing a subset of resistive storage circuitry with balanced resistive loads on region lines according to an embodiment. Figure 4B is a schematic diagram showing a subset of resistive storage circuitry with balanced resistive loads on region lines according to an embodiment. Figure 5A is a schematic diagram showing a first switch connected to a region bit line and a second switch connected to a region selection line of the resistive storage circuitry subset according to an embodiment. Figure 5B is a schematic diagram showing a switch connected to a region bit line of the resistive storage circuitry subset according to an embodiment. Figure 5C is a schematic diagram showing a switch connected to a region selection line of the resistive storage circuitry subset according to an embodiment. Figure 6 shows a schematic diagram of a portion of a three-dimensional memory array including multiple switches connected to a global line according to one embodiment. Figure 7 shows a flowchart of a method for operating a group of resistive storage circuits according to some embodiments. Figure 8 is an example block diagram of a computing system according to some embodiments.

Claims

1. A memory array comprising: a set of resistive storage circuits, including: A first subset of resistor storage circuits is connected in parallel between a first region line and a second region line, wherein the first and second region lines extend along a first direction; and a second subset of resistor storage circuits is connected in parallel between a third and a fourth region line, wherein the third and fourth region lines extend along the first direction; wherein the first and third region lines are electrically coupled to a first global line extending along a second direction; the first subset of resistor storage circuits includes a first switch and a first resistor storage component; the resistor storage circuits further include a second switch and a second resistor storage component; the gate electrode of each of the first and second switches is coupled to a word line; a first terminal of the first switch is coupled to a first terminal of the first resistor storage component; a second terminal of the first resistor storage component is coupled to the first region line; the first region line is directly coupled to the first global line; and a first terminal of the second switch is coupled to a first terminal of the second resistor storage component. A second end of the second resistive storage component is coupled to a fifth region line, and the fifth region line is directly coupled to a second global line that is different from the first global line.

2. A memory system comprising: a memory array including a set of resistive storage circuits, the set of resistive storage circuits including a subset of first resistive storage circuits connected in parallel between a first region line and a second region line, wherein the first region line and the second region line extend along a first direction; and a controller coupled to the memory array, wherein the controller is configured to: apply a voltage to the first region line for each resistive storage circuit of the subset of first resistive storage circuits, and, in response to the voltage-sensing current, read data stored by each resistive storage circuit of the subset of first resistive storage circuits, wherein the current injected at a first common entry point of the first region line for each resistive storage circuit of the subset of first resistive storage circuits flows out through a first common exit point of the second region line, the subset of first resistive storage circuits including a first switch and a first resistive storage component, the set of resistive storage circuits further including a second switch and a second resistive storage component, the gate electrode of each of the first switch and the second switch being coupled to a word line. A first end of the first switch is coupled to a first end of the first resistance storage component, a second end of the first resistance storage component is coupled to the first region line, the first region line is directly coupled to a first global line, a first end of the second switch is coupled to a first end of the second resistance storage component, a second end of the second resistance storage component is coupled to a third region line, and the third region line is directly coupled to a second global line different from the first global line.

3. The memory system of claim 2, wherein during a first time period, the controller applies a voltage to the first common entry point of the first metal track, wherein a set of first resistive storage circuits is connected in parallel between the first metal track and the second metal track; during the first time period, the controller senses a first current from the first resistive storage circuits of the first resistive storage circuit set in response to the voltage via the first common exit point of the second metal track; during the first time period, the controller determines, based on the first current, first data stored by the first resistive storage circuits of the first resistive storage circuit set; during a second time period, the controller applies the voltage to the first common entry point of the first metal track; during the second time period, the controller senses a second current from the second resistive storage circuits of the first resistive storage circuit set in response to the voltage via the first common exit point of the second metal track; and during the second time period, the controller determines, based on the second current, second data stored by the second resistive storage circuits of the first resistive storage circuit set, wherein the first resistive storage circuit set is a subset of the first resistive storage circuits. The first metal track is the first region line, and the second metal track is the second region line.

4. The memory system of claim 2, wherein the controller is configured to: during a first time period, apply a voltage to a first resistive storage circuit of a first resistive storage circuit assembly through a first common entry point of a first metal track, the first metal track being coupled to a first terminal of the first resistive storage circuit assembly; during the first time period, sense a first current from the first resistive storage circuit assembly through a first common exit point of a second metal track, the second metal track being coupled to a second terminal of the first resistive storage circuit assembly opposite to the first terminal; determine first data stored by the first resistive storage circuit of the first resistive storage circuit assembly based on the first current; during a second time period, apply the voltage to the first common entry point of the first metal track; during the second time period, in response to the voltage, sense a second current from a second resistive storage circuit of the first resistive storage circuit assembly through the first common exit point of the second metal track; during the second time period, determine second data stored by the controller by means of the second current of the second resistive storage circuit assembly. The first set of resistor storage circuits is a subset of the first resistor storage circuits, the first metal track is the first region line, and the second metal track is the second region line.

5. The memory system as claimed in claim 2, further comprising: a first metal track; a second metal track; and a first set of resistive storage circuits connected in parallel between the first metal track and the second metal track, wherein the controller is configured to: apply a voltage to a first common entry point of the first metal track during a first time period; during the first time period, in response to the voltage, sense a first current from a first resistive storage circuit of the first set of resistive storage circuits through the first common exit point of the second metal track; determine first data stored by the first resistive storage circuit of the first set of resistive storage circuits based on the first current; apply the voltage to the first common entry point during a second time period; during the second time period, in response to the voltage, sense a second current from a second resistive storage circuit of the first set of resistive storage circuits through the first common exit point; determine second data stored by the second resistive storage circuit of the first set of resistive storage circuits based on the second current, wherein the first set of resistive storage circuits is a subset of the first resistive storage circuits. The first metal track is the first region line, and the second metal track is the second region line.

6. A memory array comprising: a first global line connected to a plurality of first region lines, each of the first region lines being connected at a first end to a plurality of first resistive units, a second end of each of the first resistive units being coupled to a plurality of first transistors, the first transistors being configured to selectively connect the first resistive units to a plurality of second region lines; a second global line connected to a plurality of third region lines, each of the third region lines being connected at a first end to a plurality of second resistive units, a second end of each of the second resistive units being coupled to a plurality of second transistors, the second transistors being configured to selectively connect the second resistive units to a plurality of fourth region lines; a fifth region line coupling a gate of a first transistor of the first transistors to a gate of a second transistor of the second transistors; a first resistive storage component; and a second resistive storage component. The fifth region line is a word line. A first end of the first transistor is coupled to a first end of the first resistive storage component. A second end of the first resistive storage component is coupled to a sixth region line. The sixth region line is directly coupled to the first global line. A first end of the second transistor is coupled to a first end of the second resistive storage component. A second end of the second resistive storage component is coupled to a seventh region line. The seventh region line is directly coupled to a second global line that is different from the first global line.

7. A memory system comprising: a memory array including a set of resistive storage circuits; and a controller coupled to the memory array, wherein the controller is configured to: apply a voltage to one of a plurality of first region lines for each of the plurality of resistive storage circuits, and sense a current in one of a plurality of second region lines for the resistive storage circuits, and read stored data in response to the voltage, wherein... For each of the resistor storage circuits in a subset of resistor storage circuits: the current is injected through a first common exit point of the second region lines and at a first common entry point of the first region lines; and a resistor unit has a first terminal and a second terminal, the first terminal being coupled to a first region line of the first region lines and the second terminal being coupled to a switch; and the switch being coupled to a second region line of the second region lines, wherein the resistor storage circuit set includes a first switch and a first resistor storage component, the resistor storage circuit set further includes a second switch and a second resistor storage component, the gate electrode of each of the first switch and the second switch is coupled to a word line, a first terminal of the first switch is coupled to a first terminal of the first resistor storage component, a second terminal of the first resistor storage component is coupled to the first region line, the first region line is directly coupled to a first global line, and a first terminal of the second switch is coupled to a first terminal of the second resistor storage component. A second end of the second resistive storage component is coupled to a third region line, and the third region line is directly coupled to a second global line that is different from the first global line.

8. A memory array comprising: a controller for storing data in a set of resistor cells, the set of resistor cells including a plurality of first resistor cells and a plurality of second resistor cells; a first bit line connected to a plurality of second bit lines, each of the second bit lines being connected to the first resistor cells, the first resistor cells being coupled to a plurality of first switches for connecting the first resistor cells to one of a plurality of first select lines; a third bit line connected to a plurality of fourth bit lines, each of the fourth bit lines being connected at a first end to the second resistor cells, a second end of each of the second resistor cells being coupled to one of a plurality of second switches for selectively connecting the second resistor cells to a plurality of second select lines; a wire coupling an input of a first switch of the first switches to an input of a second switch of the second switches; a first resistor storage component; and a second resistor storage component. The gate electrode of each of the first switch and the second switch is coupled to a word line. A first end of the first switch is coupled to a first end of the first resistance storage component. A second end of the first resistance storage component is coupled to a first region line. The first region line is directly coupled to the first word line. A first end of the second switch is coupled to a first end of the second resistance storage component. A second end of the second resistance storage component is coupled to a second region line. The second region line is directly coupled to a third word line that is different from the first word line.

9. A memory system comprising: a plurality of resistive storage circuits arranged in a plurality of columns, a plurality of rows, and a plurality of layers; and a controller coupled to the resistive storage circuits via: a separate word line coupled to each of the plurality of columns; and a separate bit line coupled to each of the plurality of rows and shared by the layers, wherein... For each of these resistor storage circuits, the path resistance from a first power supply voltage of the bit line to a common exit point is the same. The resistor storage circuits include a first switch, a first resistor storage component, a second switch, and a second resistor storage component. The gate electrode of each of the first switch and the second switch is coupled to the word line. A first terminal of the first switch is coupled to a first terminal of the first resistor storage component. A second terminal of the first resistor storage component is coupled to a first region line. The first region line is directly coupled to a first global line. A first terminal of the second switch is coupled to a first terminal of the second resistor storage component. A second terminal of the second resistor storage component is coupled to a second region line. The second region line is directly coupled to a second global line different from the first global line.

10. The memory system of claim 9, further comprising: a plurality of first one-time programmable memory cells stacked on top of each other in a first direction, each of the first one-time programmable memory cells comprising: a first conductive terminal electrically coupled to the first power supply voltage via a first wire extending in the first direction; a second conductive terminal electrically coupled to a second power supply voltage via a second wire extending in the first direction; and a control terminal, which, upon receiving a programmed voltage, electrically couples the first conductive terminal to the second conductive terminal, wherein... For each of the stacked first one-time programmable memory cells, the signal path from the first power supply voltage to the second power supply voltage is the same.

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