High-electron mobility transistor and method for fabricating the same

Abstract

A high electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode, and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate, the drain electrode is disposed on one side of the gate electrode, and the source electrode is disposed on the other side of the gate electrode. The first field plate is electrically connected to the source electrode and extends from the source electrode to the drain electrode, wherein the overlap region between the first field plate and the gate electrode is smaller than the overlap region between the gate electrode and the active region.

Description

High electron mobility transistors and their fabrication methods This invention relates to the field of semiconductor devices, and more particularly to a high-electron mobility transistor (HEMT) and a method for fabricating the same. HEMT is a transistor that uses a two-dimensional electron gas (2DEG) as a carrier channel. Compared with using doped regions as carrier channels, HEMT has high electron mobility and high frequency transmission capability, and can be used in high power devices. However, when applied to high-power devices, high drain bias can lead to premature failure of the HEMT or the formation of defects on the gate electrode surface during switching, affecting dynamic on-resistance. Therefore, for conventional HEMTs, it is still necessary to improve their structure to overcome the shortcomings and deficiencies of the prior art. One objective of this invention is to provide an HEMT and a method for manufacturing the same, in order to solve the aforementioned problems. According to one embodiment of the present invention, a HEMT is provided, comprising a substrate, a gate electrode, a drain electrode, a source electrode, and a first field plate. The substrate includes an active region, the gate electrode is disposed on the substrate, the drain electrode is disposed on one side of the gate electrode, and the source electrode is disposed on the other side of the gate electrode. The first field plate is electrically connected to the source electrode and extends from the source electrode toward the drain electrode, wherein the overlap region between the first field plate and the gate electrode is smaller than the overlap region between the gate electrode and the active region. According to another embodiment of the present invention, a method for fabricating a HEMT is provided, comprising the following steps: providing a substrate; forming a gate electrode on the substrate; forming a drain electrode on one side of the gate electrode; forming a source electrode on the other side of the gate electrode; and forming a first field plate, wherein the substrate includes an active region, and the first field plate is electrically connected to the source electrode and extends from the source electrode toward the drain electrode. An overlap region between the first field plate and the gate electrode is smaller than an overlap region between the gate electrode and the active region. Compared to prior art, this invention, by incorporating a first field plate, helps reduce the impact of high drain bias on HEMTs, thereby improving shortcomings such as premature HEMT failure, gate electrode surface defects, and reduced dynamic on-resistance. Furthermore, by minimizing the overlap between the first field plate and the gate electrode compared to the overlap between the gate electrode and the active region, this invention reduces the parasitic capacitance between them, thereby decreasing the HEMT's switching time and facilitating its application as a switch. The foregoing description and other technical contents, features, and effects of this invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The directional terms used in the following embodiments, such as up, down, left, right, front, back, bottom, and top, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention. Furthermore, in the following embodiments, the same or similar elements will be represented by the same or similar reference numerals. The following description of "the first feature is formed on or above the second feature" can refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature" so that the first feature and the second feature are not in direct contact. The present invention uses terms such as first and second to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another element, or the order of manufacturing methods. Please refer to Figure 1, which is a cross-sectional schematic diagram of an HEMT 100 according to an embodiment of the present invention. The HEMT 100 includes at least a substrate 110, a gate electrode 122, a drain electrode 124, a source electrode 126, and a first field plate 128. The gate electrode 122 is disposed on the substrate 110, the drain electrode 124 is disposed on one side of the gate electrode 122, and the source electrode 126 is disposed on the other side of the gate electrode 122. The first field plate 128 is electrically connected to the source electrode 126 and extends from the source electrode 126 toward the drain electrode 124. By providing the first field plate 128, it is beneficial to reduce the impact of high drain bias on the HEMT 100, thereby improving defects such as premature failure of the HEMT 100, surface defects of the gate electrode 122, and impact on dynamic on-resistance. HEMT 100 may further include a channel layer 112, a barrier layer 114, and a passivation layer 116. The channel layer 112 is disposed on the substrate 110. The source electrode 126 and the channel layer 112 can form an ohmic contact, and the drain electrode 124 and the channel layer 112 can form an ohmic contact. The barrier layer 114 is disposed on the channel layer 112, and the passivation layer 116 is disposed between the gate electrode 122 and the first field plate 128. A two-dimensional electron gas 138 can be generated at the interface between the channel layer 112 and the barrier layer 114. HEMT 100 may further include a gate cap layer 120, which is disposed on the barrier layer 114, and the gate electrode 122 is disposed on the gate cap layer 120. By disposing of the gate cap layer 120, two-dimensional electron gas 138 is prevented from being generated in the corresponding channel layer 112 below, thus partially blocking the two-dimensional electron gas 138. In this embodiment, the passivation layer 116 is exemplified as a double-layer structure, comprising a first passivation layer 116A and a second passivation layer 116B. The first passivation layer 116A is disposed on the barrier layer 114 and surrounds the gate cap layer 120, and the second passivation layer 116B is disposed on the first passivation layer 116A and covers the gate electrode 122, and the second passivation layer 116B is disposed between the gate electrode 122 and the first field plate 128. The first passivation layer 116A and the second passivation layer 116B can be formed sequentially in different steps and may contain the same or different components. However, the present invention is not limited thereto; for example, in other embodiments, the passivation layer 116 may be a single-layer structure. HEMT 100 may further include a dielectric layer 130, two contact plugs 132 and 134, and a second field plate 136. The dielectric layer 130 is disposed on the first field plate 128, and the two contact plugs 132 and 134 are disposed within the dielectric layer 130 and electrically connected to the drain electrode 124 and the source electrode 126, respectively. The second field plate 136 is electrically connected to the source electrode 126 and extends from the source electrode 126 towards the drain electrode 124. By providing the second field plate 136, the impact of high drain bias on HEMT 100 can be further reduced. The substrate 110 may be, but is not limited to, a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. The channel layer 112 may comprise one or more III-V semiconductor layers, the composition of which may be, but is not limited to, GaN, AlGaN, InGaN, or InAlGaN. Furthermore, the channel layer 112 may comprise one or more doped III-V semiconductor layers, such as p-type III-V semiconductor layers. For p-type III-V semiconductor layers, the dopant may be, but is not limited to, C, Fe, Mg, or Zn. In this embodiment, the channel layer 112 is a GaN layer. The barrier layer 114 may comprise one or more III-V semiconductor layers, and its composition differs from that of the III-V semiconductor in the channel layer 112. For example, the barrier layer 114 may comprise AlN, AlyGa(1-y)N, or a combination thereof, where 0 < y < 1. Due to the discontinuous bandgap between the channel layer 112 and the barrier layer 114, by stacking the channel layer 112 and the barrier layer 114, electrons are concentrated at the heterojunction between the channel layer 112 and the barrier layer 114 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas 138. In this embodiment, the barrier layer 114 is an AlGaN layer. The gate cap layer 120 may comprise one or more doped III-V semiconductor layers, and the composition of the gate cap layer 120 may differ from that of the barrier layer 114. For example, the gate cap layer 120 may be a P-type III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant may be, but is not limited to, C, Fe, Mg, or Zn. In this embodiment, the gate cap layer 120 is a P-type GaN layer. Gate electrode 122, drain electrode 124, source electrode 126, first field plate 128, second field plate 136, contact plugs 132 and 134 can be single-layer or multi-layer structures, and their composition can include low-resistance semiconductors such as polycrystalline silicon, metals or alloys. The metals can include, but are not limited to, Al, Cu, W, Au, Pt and Ti. The composition of the first passivation layer 116A and the second passivation layer 116B may include, but is not limited to, silicon dioxide, and the composition of the dielectric layer 130 may include, but is not limited to, tetraethoxysilane (TEOS). Please refer to Figure 2, which is a top view of HEMT 100 in Figure 1. To clearly show the relationship between the first field plate 128 and the gate electrode 122, drain electrode 124, and source electrode 126, the dielectric layer 130, contact plugs 132 and 134, and the second field plate 136 are omitted in Figure 2. The overlapping area A1 of the first field plate 128 and the gate electrode 122 is represented by dots, and the overlapping area A2 of the gate electrode 122 and the active region 111 is represented by diagonal lines. As shown in Figure 2, the substrate 110 includes an active region 111, and the overlapping area A1 of the first field plate 128 and the gate electrode 122 is the same as the overlapping area A2 of the gate electrode 122 and the active region 111. Please refer to Figure 3, which is a top view of HEMT 100a according to another embodiment of the present invention. The main difference between HEMT 100a and HEMT 100 is that the shape of the first field plate 128a is different from that of the first field plate 128. In detail, the gate electrode 122 defines a gate length direction D1. The first field plate 128a includes a first extension E1, a second extension E2, and at least one connecting portion E3. The first extension E1 extends parallel to the gate length direction D1, the second extension E2 extends parallel to the gate length direction D1, and the connecting portion E3 is connected and disposed between the first extension E1 and the second extension E2. Here, it is taken as an example that the first extension E1, the second extension E2, and the connecting portion E3 are all located within the active region 111, and the connecting portion E3 extends perpendicular to the gate length direction D1, that is, the extension directions of the first extension E1 and the second extension E2 are perpendicular to the extension direction of the connecting portion E3. Therefore, based on a top-down view, the first field plate 128a comprises an H-shape. The overlap region A1 between the first field plate 128a and the gate electrode 122 is smaller than the overlap region A2 between the gate electrode 122 and the active region 111. Compared with the HEMT 100 in Figure 2, although the HEMT 100 in Figure 2 can reduce the impact of high drain bias on the HEMT 100 by setting the first field plate 128, the overlap between the first field plate 128 and the gate electrode 122 may cause parasitic capacitance to be generated between the first field plate 128 and the gate electrode 122. It is known that the larger the parasitic capacitance, the more detrimental it is to the switching speed of the HEMT 100, and thus the less favorable it is for the application of the HEMT 100 as a switch. The HEMT 100a in Figure 3 reduces the overlap area A1 between the first field plate 128a and the gate electrode 122. This reduces the impact of high drain bias on the HEMT 100a and the parasitic capacitance between the first field plate 128a and the gate electrode 122, thereby reducing the switching time of the HEMT 100a and making it more suitable for use as a switch. Please refer to Figure 4, which is a top view of HEMT 100b according to another embodiment of the present invention. The main difference between HEMT 100b and HEMT 100a is that the shape of the first field plate 128b is different from that of the first field plate 128a. Specifically, the gate electrode 122 defines a gate length direction D1. The first field plate 128b includes a first extension E1, a second extension E2, and at least one connecting portion E3. The first extension E1 extends parallel to the gate length direction D1, the second extension E2 extends parallel to the gate length direction D1, and the connecting portion E3 is disposed between the first extension E1 and the second extension E2. Here, an example is taken where at least a portion of the first extension E1 and the second extension E2 are located within the active region 111, while the connecting portion E3 is located outside the active region 111 and extends perpendicular to the gate length direction D1. That is, the extension directions of the first extension E1 and the second extension E2 are perpendicular to the extension direction of the connecting portion E3. Therefore, based on a top-down view, the first plate 128b contains a U-shape. The first field plate 128b is offset from and does not overlap with the gate electrode 122, while the gate electrode 122 has an overlap area A2 with the active region 111. In other words, in this embodiment, the overlap area between the first field plate 128b and the gate electrode 122 is smaller than the overlap area A2 between the gate electrode 122 and the active region 111. Compared with the HEMT 100a in Figure 3, the first field plate 128b and the gate electrode 122 in the HEMT 100b in Figure 4 are completely offset, meaning that the overlap area between the first field plate 128b and the gate electrode 122 is 0, which is smaller than the overlap area A2 between the gate electrode 122 and the active region 111. This is more conducive to avoiding parasitic capacitance between the first field plate 128b and the gate electrode 122. Please refer to Figure 5, which is a top view of HEMT 100c according to another embodiment of the present invention. The main difference between HEMT 100c and HEMT 100a is that the shape of the first field plate 128c is different from that of the first field plate 128a. Specifically, compared with the first field plate 128a, the first field plate 128c includes two connecting portions E3. By increasing the number of connecting portions E3, the resistance value from the first extension E1 to the second extension E2 can be reduced. In this embodiment, the overlapping areas of the two connecting portions E3 and the gate electrode 122 are the first overlapping area A11 and the second overlapping area A12, respectively. The overlapping area A1 of the first field plate 128c and the gate electrode 122 is the sum of the first overlapping area A11 and the second overlapping area A12. As shown in Figure 5, the overlapping area A1 of the first field plate 128c and the gate electrode 122 is smaller than the overlapping area A2 of the gate electrode 122 and the active region 111. From a top-down view, the first field plate 128c comprises two H-shapes or U-shapes. Further details regarding the HEMT 100c can be found in the relevant documentation for the HEMT 100a, and will not be repeated here. In other embodiments, the layout pattern of the first field plate can be adjusted according to actual needs. For example, the number of connecting parts and the extension direction of the connecting parts can be adjusted, so that the first field plate can include shapes such as inverted U-shape, mouth shape, E-shape, or K-shape depending on a top view angle. In other words, as long as the overlap area between the first field plate and the gate electrode is greater than or equal to 0 and less than the overlap area between the gate electrode and the active region, it falls within the scope of protection of this invention. Please refer to Figure 6, which is a flowchart of a method 500 for fabricating a HEMT according to another embodiment of the present invention, including steps 510, 516, 520, 522 and 524. Step 510 is to provide a substrate. Step 516 is to form a gate electrode on the substrate. Step 520 is to form a drain electrode on one side of the gate electrode. Step 522 is to form a source electrode on the other side of the gate electrode. Step 524 is to form a first field plate, wherein the substrate includes an active region, the first field plate is electrically connected to the source electrode and extends from the source electrode to the drain electrode, and the overlap area between the first field plate and the gate electrode is smaller than the overlap area between the gate electrode and the active region. Method 500 may further include steps 512, 514, 518, 526 and 528, wherein step 512 is forming a channel layer on the substrate, step 514 is forming a barrier layer on the channel layer, step 518 is forming a passivation layer, wherein the passivation layer is disposed between the gate electrode and the first field plate, step 526 is forming a dielectric layer on the first field plate, and step 528 is forming a second field plate on the dielectric layer. Please refer to Figures 7, 8, and 9, which are schematic diagrams illustrating the steps of the HEMT fabrication method 500 shown in Figure 6. Figures 7, 8, and 9 illustrate how to fabricate an HEMT 100 using method 500. In Figure 7, firstly, a substrate 110 is provided (corresponding to step 510). Next, a channel layer 112 is formed on the substrate 110 (corresponding to step 512), a barrier layer 114 is formed on the channel layer 112 (corresponding to step 514), and a gate electrode 122 is formed on the barrier layer 114 (corresponding to step 516). In this embodiment, before forming the gate electrode 122, a gate capping layer 120 can be formed on the barrier layer 114, and then a first passivation layer 116A can be formed to cover the gate capping layer 120 and the barrier layer 114. After that, the first passivation layer 116A is patterned to form a hole H1, and then the hole H1 is filled with the material of the gate electrode 122 and covered with the first passivation layer 116A. After that, the material of the gate electrode 122 is patterned to form the gate electrode 122, and then a second passivation layer 116B is formed to cover the gate electrode 122 and the first passivation layer 116A (corresponding to step 518). Next, as shown in Figure 8, holes H2 and H3 are formed and filled with low-resistance semiconductor, metal or alloy materials. Then, the low-resistance semiconductor, metal or alloy materials are patterned to form the drain electrode 124, the source electrode 126 and the first field plate 128 (corresponding to steps 520, 522 and 524). Next, as shown in Figure 9, a dielectric layer 130 is formed on the first field plate 128 (corresponding to step 526). The dielectric layer 130 simultaneously covers the drain electrode 124 and the source electrode 126. Then, holes 132a and 134a are formed, and low-resistivity semiconductor, metal or alloy material is used to fill the holes 132a and 134a and cover them with the dielectric layer 130. Then, the low-resistivity semiconductor, metal or alloy material is patterned to form contact plugs 132 and 134 and the second field plate 136 (corresponding to step 528), thus obtaining the HEMT 100 as shown in Figures 1 and 2. The stacked layers on the substrate 110, such as the channel layer 112, the barrier layer 114, and the gate cap layer 120, can be formed by any suitable method, such as, but not limited to, molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and atomic layer deposition (ALD). The methods for forming the pores H1, H2, H3, 132a, and 134a, and for patterning them, are well known in the art and will not be described further here. The method for fabricating HEMT 100a, HEMT 100b, and HEMT 100c in Figures 3 to 5 is similar to the method for fabricating HEMT 100 in Figures 1 and 2. The only difference is that in Figure 8, when patterning low-resistivity semiconductor, metal, or alloy materials to form the drain electrode 124, source electrode 126, and first field plate 128 (corresponding to steps 520, 522, and 524), the pattern of the mask is changed so that the shapes of the first field plates 128a, 128b, and 128c are different from those of the first field plate 128. In other words, HEMT 100a, HEMT 100b, and HEMT 100c in Figures 3 to 5 do not require additional processing compared to HEMT 100 in Figures 1 and 2, thus making the parasitic capacitance between the gate electrode 122 and the first field plate 128a, 128b, or 128c smaller than the parasitic capacitance between the gate electrode 122 and the first field plate 128. Please refer to Figure 10, which is a diagram showing the relationship between capacitance and gate voltage according to Embodiments 1 and 2 of the present invention. The capacitance includes the capacitance between the gate electrode and the source electrode, and the capacitance between the gate electrode and the drain electrode. Embodiment 1 is the HEMT 100 according to Figures 1 and 2, and Embodiment 2 is the HEMT 100a according to Figure 3. As shown in Figure 10, by making the overlap region A1 between the first field plate 128a and the gate electrode 122 smaller than the overlap region A2 between the gate electrode 122 and the active region 111, parasitic capacitance can be effectively reduced, thus giving the HEMT 100a superior performance. Compared to prior art, this invention, by incorporating a first field plate, helps reduce the impact of high drain bias on HEMTs, thereby improving shortcomings such as premature HEMT failure, gate electrode surface defects, and reduced dynamic on-resistance. Furthermore, by minimizing the overlap between the first field plate and the gate electrode compared to the overlap between the gate electrode and the active region, this invention reduces the parasitic capacitance between them, thereby lowering the HEMT switching time and facilitating its application as a switch. The above description is merely a preferred embodiment of this invention; all equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. 100, 100a, 100b, 100c: HEMT 110: Substrate 111: Active Region 112: Channel Layer 114: Barrier Layer 116: Passivation Layer 116A: First Passivation Layer 116B: Second Passivation Layer 120: Gate Cap Layer 122: Gate Electrode 124: Drain Electrode 126: Source Electrode 128, 128a, 128b, 128c: First Field Plate 130: Dielectric Layer 132, 134: Contact Plug 136: Second Field Plate 138: Two-Dimensional Electron Gas A1, A2: Overlapping Region A11: First Overlapping Region A12: Second Overlapping Region D1: Gate Length Direction E1: First Extension E2: Second Extension E3: Connector H1, H2, H3, 132a, 134a: Hole 500: Method for Fabricating HEMT 510, 512, 514, 516, 518, 520, 522, 524, 526, 528: Steps Figure 1 is a cross-sectional view of a HEMT according to one embodiment of the present invention. Figure 2 is a top view of the HEMT in Figure 1. Figure 3 is a top view of a HEMT according to another embodiment of the present invention. Figure 4 is a top view of a HEMT according to yet another embodiment of the present invention. Figure 5 is a top view of a HEMT according to still another embodiment of the present invention. Figure 6 is a flowchart of a method for manufacturing a HEMT according to another embodiment of the present invention. Figures 7, 8, and 9 are schematic diagrams illustrating the steps of the method for manufacturing the HEMT in Figure 6. Figure 10 is a graph showing the relationship between capacitance and gate voltage according to embodiments 1 and 2 of the present invention. 100:HEMT 110: Base 112: Channel Layer 114: Barrier Layer 116: Passivation layer 116A: First passivation layer 116B: Second passivation layer 120: Gate cap layer 122: Gate electrode 124: Drain electrode 126: Source electrode 128: First game board 130: Dielectric layer 132, 134: Contact plugs 136: Second game board 138: Two-dimensional electronic gas

Claims

1. A high electron mobility transistor, comprising: a substrate including an active region; a gate electrode disposed on the substrate; a drain electrode disposed on one side of the gate electrode; a source electrode disposed on the other side of the gate electrode; and a first field plate electrically connected to the source electrode and extending from the source electrode toward the drain electrode, wherein the first field plate is integrally connected to the source electrode and is made of the same material, and an overlap region between the first field plate and the gate electrode is smaller than an overlap region between the gate electrode and the active region.

2. The high electron mobility transistor as described in claim 1, wherein the gate electrode defines a gate length direction, and the first field plate includes: a first extension extending parallel to the gate length direction; a second extension extending parallel to the gate length direction; and at least one connecting portion connected between the first extension and the second extension.

3. The high electron mobility transistor as described in claim 2, wherein the at least one connection is located within the active region.

4. The high electron mobility transistor as described in claim 3, wherein the first field plate comprises an H-shape.

5. The high electron mobility transistor as described in claim 2, wherein the at least one connection is located outside the active region.

6. The high electron mobility transistor as described in claim 5, wherein the first field plate comprises a U-shape.

7. The high electron mobility transistor as described in claim 1, further comprising: a dielectric layer disposed on the first field plate.

8. The high electron mobility transistor as described in claim 7 further comprises: a second field plate disposed on the dielectric layer, wherein the second field plate is electrically connected to the source electrode and extends from the source electrode toward the drain electrode.

9. The high electron mobility transistor as described in claim 1, further comprising: a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; and a passivation layer disposed between the gate electrode and the first field plate.

10. The high electron mobility transistor as described in claim 9, wherein the source electrode and the channel layer form an ohmic contact.

11. A method for fabricating a high electron mobility transistor, comprising: providing a substrate; forming a gate electrode on the substrate; forming a drain electrode on one side of the gate electrode; forming a source electrode on the other side of the gate electrode; and forming a first field plate, wherein the substrate includes an active region, the first field plate is electrically connected to the source electrode and extends from the source electrode toward the drain electrode, the first field plate is integrally connected to the source electrode and is made of the same material, and an overlap region between the first field plate and the gate electrode is smaller than an overlap region between the gate electrode and the active region.

12. The method as described in claim 11, wherein the gate electrode defines a gate length direction, and the first field plate includes: a first extension extending parallel to the gate length direction; a second extension extending parallel to the gate length direction; and at least one connecting portion connected between the first extension and the second extension.

13. The method as described in claim 12, wherein the at least one connecting portion is located within the active region.

14. The method as described in claim 13, wherein the first field plate comprises an H-shape.

15. The method as described in claim 12, wherein the at least one connecting portion is located outside the active region.

16. The method as described in claim 15, wherein the first field plate comprises a U-shape.

17. The method as described in claim 11 further comprises: forming a dielectric layer on the first field plate.

18. The method as described in claim 17 further comprises: forming a second field plate on the dielectric layer, wherein the second field plate is electrically connected to the source electrode and extends from the source electrode toward the drain electrode.

19. The method as described in claim 11 further comprises: forming a channel layer on the substrate; forming a barrier layer on the channel layer; and forming a passivation layer, wherein the passivation layer is disposed between the gate electrode and the first field plate.

20. The method as described in claim 19, wherein the source electrode and the channel layer form an ohmic contact.

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