Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a first intermetallic dielectric layer on a substrate, then forming a first groove and a second groove in the first intermetallic dielectric layer, forming a lower electrode in the first groove and the second groove, forming a ferroelectric layer on the lower electrode, and finally forming an upper electrode on the ferroelectric layer to form a ferroelectric random access memory.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing ferroelectric random access memory. [Previous Technology]

[0002] To improve memory arrays, field-effect transistors with ferroelectric gates (FeFETs) have recently become a focus of research. Generally, ferroelectric materials are dielectric crystals that exhibit spontaneous polarization, similar to ferromagnetic materials that exhibit spontaneous magnetization. When a suitable external electric field is applied to a ferroelectric material, the polarization direction can be reoriented. The basic idea is to use the spontaneous polarization direction in ferroelectric memory to store digital bits. In FeFETs, the effect utilized is the possibility of adjusting the polarization state of the ferroelectric material based on a suitable electric field applied to it, where the ferroelectric material is typically a gate oxide. Since the polarization state of the ferroelectric material is maintained (unless it is exposed to a high reverse electric field or high temperature in terms of polarization state), it is possible to "program" a capacitor formed from the ferroelectric material so that the induced polarization state reflects the information unit. Therefore, the induced polarization state is maintained even after the corresponding "programmed" device is removed from the power supply. In this way, FeFET enables the implementation of non-volatile electrically switchable data storage devices.

[0003] Based on ferroelectric materials, it is possible to provide non-volatile memory devices, especially random access memory devices with an architecture similar to DRAM devices, but the difference lies in using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. For example, the 1T-1C memory cell design in ferroelectric random access memory (FeRAM) is architecturally similar to the memory cells of widely used DRAM in that both cell types include a capacitor and a transistor. In DRAM cell capacitors, a linear dielectric is used, while in FeRAM cell capacitors, the dielectric structure includes a ferroelectric material. Other types of FeRAM are implemented as 1T memory cells, which consist of a single FeFET using a ferroelectric dielectric instead of the gate dielectric of a conventional MOSFET. Generally, the current-voltage characteristics between the source and drain of the FeFET depend on the polarization of the ferroelectric dielectric, that is, the FeFET is in an on or off state depending on the orientation of the polarization state of the ferroelectric dielectric. Writing to a FeFET is achieved by applying a write voltage relative to the source and then to the gate, while reading out the 1T-FeRAM is done by measuring the current after applying voltage to the source and drain. It is important to note that reading out the 1T-FeRAM is non-destructive.

[0004] One of the methods to optimize ferroelectric field-effect transistors and ferroelectric random access memory is to make their size smaller and smaller. However, as the size decreases, the overall capacitance of ferroelectric random access memory also decreases and the cost increases. Therefore, how to maintain product yield and improve existing processes is a major challenge for the industry. [Summary of the Invention]

[0005] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly involves first forming a first intermetallic dielectric layer on a substrate, then forming a first groove and a second groove in the first intermetallic dielectric layer, forming a lower electrode in the first groove and the second groove, forming a ferroelectric layer on the lower electrode, and then forming an upper electrode on the ferroelectric layer to form a ferroelectric random access memory.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes an intermetallic dielectric layer disposed on a substrate and a ferroelectric random access memory disposed on the intermetallic dielectric layer. The ferroelectric random access memory further includes a first groove and a second groove disposed in the intermetallic dielectric layer, a lower electrode disposed in the first groove and the second groove, a ferroelectric layer disposed on the lower electrode, and an upper electrode disposed on the ferroelectric layer.

Implementation Method

[0008] Please refer to Figures 1 to 3, which are schematic diagrams of a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in Figure 1, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composites, silicon carbide, gallium arsenide, etc. The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as interlayer dielectrics (ILDs) covering it. More specifically, the substrate 12 may include planar or non-planar (such as fin structure transistors) MOS transistor elements 14, wherein the MOS transistor 14 may include a gate dielectric layer 16, a gate electrode (e.g., a metal gate) 18, a source / drain region 20, sidewalls, an epitaxial layer, and a contact hole etch stop layer, etc. An interlayer dielectric layer 22 may be disposed on the substrate 12 and cover the MOS transistor 14, and the interlayer dielectric layer 22 may have a plurality of contact plugs 24 electrically connecting the gate electrode 18 and / or the source / drain region 20 of the MOS transistor 14. Since the related processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0009] Then, at least one metal interconnect structure is formed on the interlayer dielectric layer 22 to electrically connect the aforementioned contact plug 24. The metal interconnect structure may include an intermetallic dielectric layer 26 disposed on the interlayer dielectric layer 22, at least one metal interconnect 28 embedded in the intermetallic dielectric layer 26, an intermetallic dielectric layer 30 disposed on the intermetallic dielectric layer 26, at least one metal interconnect 32 such as a contact hole conductor embedded in the intermetallic dielectric layer 30, an intermetallic dielectric layer 34 disposed on the intermetallic dielectric layer 30, and at least one metal interconnect 36 embedded in the intermetallic dielectric layer 34. The metal interconnect 28 formed by the trench conductor may be referred to as the first layer of metal interconnect, and the metal interconnect 36 formed by the trench conductor may be referred to as the second layer of metal interconnect.

[0010] In this embodiment, each metal interconnect 28, 32, 36 can be embedded in the inter-metal dielectric layers 26, 30, 34 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 28, 32, 36 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., and preferably does not include tungsten (W), but is not limited thereto. Since single damascene or dual damascene processes are well known in the art, they will not be described in detail here. Furthermore, in this example, the metal layers in the metal interconnects 28, 32, and 36 preferably contain copper, and the intermetallic dielectric layers 26, 30, and 34 may contain silicon oxide such as tetraethyl orthosilicate (TES) or ultra-low dielectric constant dielectric layers, such as porous dielectric materials such as, but not limited to, silicon carbide (SiOC) or silicon hydrogen carbide (SiOCH).

[0011] Then, a stop layer 42 and an intermetallic dielectric layer 44 are formed on the intermetallic dielectric layer 34. A photolithography and etching process is then performed to remove part of the intermetallic dielectric layer 44 to form at least two grooves, such as grooves 46 and 48, within the intermetallic dielectric layer 44. Next, a lower electrode 50 is sequentially formed within grooves 46 and 48, but not completely filling each groove. A ferroelectric layer 52 is formed on the lower electrode 50, and then an upper electrode 54 is formed on the ferroelectric layer 52, filling the grooves 46 and 48. Subsequently, an annealing process, such as a rapid thermal annealing (RTA) process, can be selectively performed to perform a phase change on the ferroelectric layer 52. In this embodiment, the annealing temperature is preferably equal to or less than 400 degrees Celsius, and the annealing time is preferably between 25 and 35 seconds, or preferably about 30 seconds.

[0012] As shown in Figure 2, a pattern transfer process is then performed to pattern the upper electrode 54 and the ferroelectric layer 52. For example, a patterned mask (not shown) can be formed first, such as patterning photoresist on the upper electrode 54. Then, using the patterned mask as a mask, a portion of the upper electrode 54 and a portion of the ferroelectric layer 52 are removed by etching, but preferably no lower electrode 50 is removed, so that the sidewalls of the remaining upper electrode 54 are flush with the sidewalls of the remaining ferroelectric layer 52, and the unetched lower electrode 50 still completely covers the surface of the intermetallic dielectric layer 44. In this stage, the unpatterned lower electrode 50 and the patterned ferroelectric layer 52, together with the upper electrode 54, preferably constitute a ferroelectric random access memory 56.

[0013] In this embodiment, the lower electrode 50 and the upper electrode 54 preferably comprise conductive materials such as, but not limited to, titanium nitride. The ferroelectric layer 52 preferably comprises hafnium zirconate dioxide (HfZrO2), but according to other embodiments of the present invention, it may also comprise a material selected from the group consisting of: lead zirconate titanate (PbZrTiO3, PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O3, PLZT), strontium bismuth tantalite (SrBiTa2O9, SBT), bismuth lanthanum titanate ((BiLa)4Ti3O12, BLT), and barium strontium titanate (BaSrTiO3, BST).

[0014] In this embodiment, the thickness of the lower electrode 50 is approximately 5-15 nanometers or more preferably about 10 angstroms, the thickness of the ferroelectric layer 52 is approximately 5-15 nanometers or more preferably about 10 angstroms, and the thickness of the upper electrode 54 is approximately 30-40 nanometers or more preferably about 35 angstroms. The intermetallic dielectric layer 44 preferably comprises silicon oxide, such as tetraethyl orthosilicate (TES), or an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon hydrogen carbide (SiOCH).

[0015] Then, as shown in Figure 3, another photolithography and etching process can be selectively performed to remove part of the lower electrode 50, thereby defining the area occupied by the bottom of the ferroelectric random access memory 56 and preventing the lower electrode 50 from extending to the entire stop layer 42. Then, a hard mask 58 is formed on the ferroelectric random access memory 56, an intermetallic dielectric layer 60 is formed on the hard mask 58, at least one metal interconnect 62, such as a contact hole conductor, is formed and embedded in the intermetallic dielectric layer 60 and electrically connects the lower electrode 50 and the upper electrode 54 of the ferroelectric random access memory 56, an intermetallic dielectric layer 64 is formed on the intermetallic dielectric layer 60, and then a metal interconnect 66, such as a trench conductor, is formed in the intermetallic dielectric layer 64 and electrically connects to the lower metal interconnect 62. As in the aforementioned embodiments, each metal interconnect 62, 66 can be embedded in the intermetallic dielectric layers 60, 64 and electrically connected to each other according to a single damascene process or a dual damascene process. Furthermore, in this example, the metal interconnects 62 and 66 preferably contain copper, and the intermetallic dielectric layers 60 and 64 preferably contain silicon oxide, such as tetraethyl orthosilicate (TES), or ultra-low dielectric constant dielectric layers, such as porous dielectric materials, such as, but not limited to, silicon carbide (SiOC) or silicon hydrogen carbide (SiOCH). This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0016] Please refer to Figure 3 again, which discloses a schematic diagram of the structure of a semiconductor device according to one embodiment of the present invention. As shown in Figure 3, the semiconductor device mainly includes an intermetallic dielectric layer 44 disposed on a substrate 12 and a ferroelectric random access memory 56 disposed on the intermetallic dielectric layer 44. The ferroelectric random access memory 56 includes at least two grooves, such as grooves 46 and 48, disposed in the intermetallic dielectric layer 44, a lower electrode 50 disposed in grooves 46 and 48, a ferroelectric layer 52 disposed on the lower electrode 50, and an upper electrode 54 disposed on the ferroelectric layer 52.

[0017] Furthermore, the ferroelectric random access memory 56 includes a hard mask 58 disposed on the ferroelectric random access memory 56, an intermetallic dielectric layer 60 disposed on the hard mask 56, and metal interconnects 62 and 66 disposed within the intermetallic dielectric layers 60 and 64, respectively connecting the lower electrode 50 and the upper electrode 54. Preferably, the metal interconnect 62 on the left side contacts the lower electrode 50, while the metal interconnect 62 on the right side contacts the upper electrode 54. It should be noted that in this embodiment, the bottom of the ferroelectric random access memory 56 disposed within the two recesses 46 and 48 preferably does not contact the lower metal interconnect 36, and the lower electrode 50 and upper electrode 54 of the ferroelectric random access memory 56 are respectively connected to external components via the upper metal interconnect 62.

[0018] In summary, the present invention preferably discloses an improved ferroelectric random access memory (RAM) structure, which mainly involves first forming at least two or more grooves in the intermetallic dielectric layer, and then filling the grooves with components such as the lower electrode, the ferroelectric layer, and the upper electrode, and forming the ferroelectric RAM using a patterning process. According to the preferred embodiment of the present invention, the ferroelectric RAM prepared using the above process can significantly increase the capacitance value of the entire component, improve the power distribution network (PDN), and reduce the spike noise of the resonant circuit (LC circuit). The above description is only a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figures 1 to 3 are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming a first intermetallic dielectric layer on a substrate; forming a first groove and a second groove within the first intermetallic dielectric layer; forming a lower electrode within the first groove and the second groove, wherein the lower electrode completely covers a top surface of the first intermetallic dielectric layer; forming a ferroelectric layer on the lower electrode; and forming an upper electrode on the ferroelectric layer to form a ferroelectric random access memory, wherein a boundary of the lower electrode is aligned with a boundary of the ferroelectric layer and a boundary of the upper electrode in a lateral direction.

2. The method as described in claim 1 further comprises: patterning the upper electrode and the ferroelectric layer; forming a hard mask on the ferroelectric random access memory; forming a second intermetallic dielectric layer on the hard mask; and forming a first metal interconnect and a second metal interconnect within the second intermetallic dielectric layer.

3. The method as described in claim 2 further includes forming the hard mask on the lower electrode and the upper electrode.

4. The method as described in claim 2, wherein the first metal interconnect contacts the upper electrode.

5. The method as described in claim 2, wherein the second metal interconnect contacts the lower electrode.

6. The method as described in claim 2, wherein the upper electrode sidewall is flush with the ferroelectric layer sidewall.

7. A semiconductor device, characterized in that it comprises: an intermetallic dielectric layer disposed on a substrate; a ferroelectric random access memory (RAM) disposed on the intermetallic dielectric layer, wherein the ferroelectric RAM comprises: a first groove and a second groove disposed within the intermetallic dielectric layer; a lower electrode disposed within the first groove and the second groove, wherein the lower electrode completely covers a top surface of the intermetallic dielectric layer; a ferroelectric layer disposed on the lower electrode; and an upper electrode disposed on the ferroelectric layer, wherein a boundary of the lower electrode is aligned with a boundary of the ferroelectric layer and a boundary of the upper electrode in a lateral direction.

8. The semiconductor device as described in claim 7 further comprises: a hard mask disposed on the ferroelectric random access memory; a second intermetallic dielectric layer disposed on the hard mask; and a first metal interconnect and a second metal interconnect disposed within the second intermetallic dielectric layer.

9. The semiconductor device as described in claim 8, wherein the hard mask is disposed on the lower electrode and the upper electrode.

10. The semiconductor element as described in claim 8, wherein the first metal interconnect contacts the upper electrode.

11. The semiconductor element as described in claim 8, wherein the second metal interconnect contacts the lower electrode.

12. The semiconductor device as described in claim 7, wherein the upper electrode sidewall is flush with the ferroelectric layer sidewall.

Images