Tiled display device

Abstract

A video wall display device may include: a first panel containing a first display element layer, a second panel containing a second display element layer, and a shared layer containing a color conversion unit. The shared layer may include a first portion and a second portion. The first portion may overlap with the first panel in a plan view. The second portion may overlap with the second panel in a plan view. The color conversion unit may change the wavelength of light provided from the first panel and the second panel.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2021 - 0109077, filed on August 18, 2021, the entire content of which is incorporated herein by reference.

[0003] Various embodiments of the present disclosure relate to a tiled display device. Prior Art

[0004] In recent years, as people's interest in information display has been continuously increasing, the research and development of display devices have also been continuously carried out. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to a tiled display device, in which external visibility is improved and process productivity is improved.

[0006] The present disclosure is not limited to the above - mentioned purposes, and other purposes not mentioned herein will be clearly understood by those of ordinary skill in the art to which the present invention pertains through the following description.

[0007] Embodiments of the present disclosure may provide a tiled display device, which includes a first panel including a first display element layer, a second panel including a second display element layer, and a shared layer including a color conversion unit. The shared layer may include a first part and a second part. The first part may overlap the first panel in a plan view. The second part may overlap the second panel in a plan view. The color conversion unit may change the wavelength of light provided from the first panel and the second panel.

[0008] In one embodiment, the first panel and the second panel may form a lower panel of the tiled display device, and the shared layer may form an upper panel of the tiled display device.

[0009] In one embodiment, the first panel and the second panel may be disposed on the same layer, the first panel and the second panel may be separated from each other, and a bonding area may be disposed between the first panel and the second panel.

[0010] In one embodiment, the bonding area may overlap the shared layer in a plan view.

[0011] In one embodiment, the color conversion unit may include a first color unit that provides light of a first color, a second color unit that provides light of a second color, and a third color unit that provides light of a third color. The first color unit, the second color unit, and the third color unit may overlap the first panel and the second panel in a plan view.

[0012] In one embodiment, the tiled display device may further include a first sub-pixel region that emits light of a first color and overlaps the first color unit in a plan view, a second sub-pixel region that emits light of a second color and overlaps the second color unit in a plan view, and a third sub-pixel region that emits light of a third color and overlaps the third color unit in a plan view.

[0013] In one embodiment, the shared layer may further include a first color filter that overlaps the first sub-pixel region in a plan view, a second color filter that overlaps the second sub-pixel region in a plan view, and a third color filter that overlaps the third sub-pixel region in a plan view.

[0014] In one embodiment, the first display element layer includes a first light-emitting element, and the second display element layer includes a second light-emitting element. The tiled display device may further include an emission region in which the first light-emitting element and the second light-emitting element are disposed, and the emission region may be defined by components included in the first display element layer and the second display element layer.

[0015] In one embodiment, each of the first display element layer and the second display element layer may include a barrier wall that protrudes in the display direction of the tiled display device, and the barrier wall may have a shape surrounding the emission region.

[0016] In one embodiment, the emission region may include a first emission region that overlaps the first sub-pixel region in a plan view, a second emission region that overlaps the second sub-pixel region in a plan view, and a third emission region that overlaps the third sub-pixel region in a plan view.

[0017] In one embodiment, the first color unit may be arranged not to be aligned with the first emission region in a plan view, the second color unit may be arranged not to be aligned with the second emission region in a plan view, and the third color unit may be arranged not to be aligned with the third emission region in a plan view.

[0018] In one embodiment, at least a portion of the first color portion may overlap with the first emission region in a plan view, and other portions of the first color portion may not overlap with the first emission region in the plan view.

[0019] In one embodiment, a first portion of the first panel and the shared layer may form a first display device, and a second portion of the second panel and the shared layer may form a second display device. In the first display device and the second display device, a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region may be adjacent to each other and may be separated from each other by a first separation distance. A first adjacent sub-pixel region of the first display device and a second adjacent sub-pixel region of the second display device may be separated from each other by a second separation distance. The first adjacent sub-pixel region may be the region closest to the second display device among the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region provided in the first display device. The second adjacent sub-pixel region may be the region closest to the first display device among the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region provided in the second display device, and the first separation distance may be equal to the second separation distance.

[0020] In one embodiment, in the first display device and the second display device, a first emission region, a second emission region, and a third emission region may be adjacent to each other and may be separated from each other by a first emission separation distance. A first adjacent emission region of the first display device and a second adjacent emission region of the second display device may be separated from each other by a second emission separation distance. The first adjacent emission region may be the region closest to the second display device among the first emission region, the second emission region, and the third emission region provided in the first display device. The second adjacent emission region may be the region closest to the first display device among the first emission region, the second emission region, and the third emission region provided in the second display device. The first emission separation distance may be different from the second emission separation distance.

[0021] In one embodiment, the second emission separation distance may be greater than the second separation distance.

[0022] In one embodiment, when viewed from the outside, light of a first color may be observed in the first sub-pixel region, light of a second color may be observed in the second sub-pixel region, and light of a third color may be observed in the third sub-pixel region.

[0023] In one embodiment, the first panel and the second panel may be disposed on the same layer, the first panel and the second panel may be separated from each other, a bonding region may be disposed between the first panel and the second panel, and the thickness of the bonding region may be less than the second separation distance.

[0024] In one embodiment, the first color portion may include first quantum dots that convert light of a third color into light of the first color, and the second color portion may include second quantum dots that convert light of the third color into light of the second color.

[0025] In one embodiment, each of the first light-emitting element and the second light-emitting element may emit light of a third color.

[0026] In one embodiment, the color of the light provided by the first adjacent sub-pixel region may be different from the color of the light provided by the second adjacent sub-pixel region.

[0027] In one embodiment, the first light-emitting element and the second light-emitting element may be an organic light-emitting diode or a light-emitting diode having a size ranging from the nanoscale to the microscale.

[0028] One embodiment of the present disclosure provides a tiled display device, including: a first display device including a first substrate, a first display element layer disposed on the first substrate, and a first upper layer disposed on the first display element layer; and a second display device including a second substrate, a second display element layer disposed on the second substrate, and a second upper layer disposed on the second display element layer. The first upper layer and the second upper layer may be integral with each other, and each of the first upper layer and the second upper layer may include: a first color portion including first quantum dots, and a second color portion including second quantum dots.

[0029] An embodiment of the present disclosure provides a tiled display device, which includes a first sub-pixel region that emits light of a first color, a second sub-pixel region that emits light of a second color, and a third sub-pixel region that emits light of a third color. The tiled display device includes: a first panel, including a first substrate and a first display element layer disposed on the first substrate, and including a first light-emitting element that emits light of the third color; a second panel, including a second substrate and a second display element layer disposed on the second substrate, and including a second light-emitting element that emits light of the third color; and a shared layer, including a first region that overlaps with the first panel in a plan view and a second region that overlaps with the second panel in a plan view. The first sub-pixel region, the second sub-pixel region, and the third sub-pixel region may be defined by the shared layer.

[0030] The present disclosure is not limited to the above embodiments, and those of ordinary skill in the art to which the present invention pertains will clearly understand other embodiments not mentioned herein through the specification and the accompanying drawings. Brief Description of the Drawings

[0031] By referring to the accompanying drawings to describe its embodiments in detail, additional understandings of the embodiments according to the present disclosure will become clearer, wherein: FIG. 1 is a plan schematic diagram of a tiled display device according to an embodiment of the present disclosure. FIG. 2 is a perspective schematic diagram of a tiled display device according to an embodiment of the present disclosure. FIG. 3 is a block schematic diagram of a tiled display device according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram of an equivalent circuit of a pixel circuit included in a pixel according to an embodiment of the present disclosure. FIG. 5 is a plan schematic diagram of a pixel according to a first embodiment of the present disclosure. FIG. 6 is a cross-sectional schematic diagram taken along line II-II' of FIG. 5. FIG. 7 is a cross-sectional schematic diagram of a pixel according to a second embodiment of the present disclosure. FIG. 8 is a cross-sectional schematic diagram of a pixel including a shared layer, and it is a cross-sectional view taken along line I-I' of FIG. 1. FIGS. 9 to 11 are enlarged schematic diagrams of region EA1 of FIG. 1. Embodiments

[0032] Since the embodiments described herein are for clearly conveying the spirit of this disclosure to those of ordinary skill in the art to which the present invention pertains, this disclosure is not limited by the embodiments. It should be understood that various changes and modifications can be made to this disclosure without departing from the spirit and scope of this disclosure.

[0033] As used herein, the terms “about” or “approximately” include the stated value and represent an acceptable range of deviation from the specific value determined by those of ordinary skill in the art to which the present invention pertains, taking into account the relevant measurements and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0034] It can be understood that the terms “connect”, “connected to”, and “coupled to” can include physical and / or electrical connections or couplings, and vice versa.

[0035] The phrase “at least one of” is intended to include the meaning of “at least one selected from the group of”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0036] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as understood by those of ordinary skill in the art to which the present invention pertains. It can be further understood that, unless otherwise clearly defined herein, terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of this disclosure, and should not be idealized or interpreted too formally unless clearly defined herein.

[0037] The accompanying drawings are intended for the purpose of facilitating the illustration of specific embodiments and can be exaggerated as needed to assist in understanding this disclosure. This disclosure is not limited to the embodiments shown in the drawings.

[0038] When it is determined that the detailed description of the prior art related to this disclosure may make the content of this disclosure unclear, the detailed description thereof may be omitted.

[0039] Various embodiments of this disclosure relate to a tiled display device. Hereinafter, the tiled display device according to an embodiment will be described with reference to the accompanying drawings.

[0040] FIG. 1 is a plan schematic view of a tiled display device according to an embodiment of this disclosure.

[0041] The tiled display device TDD can be configured to provide visual information to a user. The tiled display device TDD can provide (or emit) light in the display direction (e.g., the third direction DR3) of the tiled display device TDD.

[0042] The tiled display device TDD can be provided by combining display devices DD. According to an embodiment, the tiled display device TDD can display a large screen by combining display devices DD, and thus can be applied to fields that require a wide display surface, such as the surface of an outdoor advertising billboard.

[0043] The display devices DD included in the tiled display device TDD can include a first display device DD1 to a fourth display device DD4. According to one embodiment, the tiled display device TDD can include four display devices DD. However, the number of display devices DD forming (or constituting) the tiled display device TDD is not limited to a specific example. Hereinafter, for convenience of description, an embodiment including four display devices DD1, DD2, DD3, and DD4 will be described.

[0044] The tiled display device TDD can include pixels PXL, a display area DA, a non-display area NDA, and a bonding area BA.

[0045] Light can be output in the display area DA. The pixels PXL can be disposed in the display area DA. The display area DA can be formed on the top surface of the tiled display device TDD. However, this disclosure is not limited thereto. The display area DA can be formed on the side surface and / or the rear surface of the tiled display device TDD. Here, an embodiment in which the display area DA is formed on the top surface of the tiled display device TDD will be described.

[0046] Pixels PXL can be set in the display area DA. The pixel PXL can include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3. The first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 can output light of different colors respectively. For example, light of a first color can be output from the first sub-pixel SPXL1, light of a second color can be output from the second sub-pixel SPXL2, and light of a third color can be output from the third sub-pixel SPXL3.

[0047] Each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 can include a light-emitting element LD (see FIG. 4). The light-emitting element LD is configured to emit light.

[0048] Light may not be output in the non-display area NDA. The non-display area NDA is an area other than the display area DA and the bonding area BA, and pixels PXL may not be set in the non-display area NDA.

[0049] According to one embodiment, the non-display area NDA may have a shape surrounding a part of the display area DA. However, the present disclosure is not limited to the above example. For example, the non-display area NDA may be selectively provided within the display area DA.

[0050] The bonding area BA may represent an area between the first panel PNL1 to the fourth panel PNL4 (see FIG. 2) respectively included in the tiled display device TDD in the display devices DD1, DD2, DD3, DD4. According to one embodiment, at least a part of the bonding area BA may be provided between the first panel PNL1 and the second panel PNL2. For example, the bonding area BA may include a first bonding area provided between the first panel PNL1 and the second panel PNL2, a second bonding area provided between the first panel PNL1 and the third panel PNL3, a third bonding area provided between the second panel PNL2 and the fourth panel PNL4, and a fourth bonding area provided between the third panel PNL3 and the fourth panel PNL4.

[0051] According to one embodiment, the bonding area BA may overlap with the shared layer 100 (see FIG. 2) in a plan view. For example, at least a part of the shared layer 100 may be provided in the bonding area BA.

[0052] According to one embodiment, the tiled display device TDD may include a shared layer 100 disposed to span the first display device DD1 to the fourth display device DD4. The shared layer 100 may overlap the first panel PNL1 to the fourth panel PNL4 in a plan view. The shared layer 100 may overlap the bonding area BA in a plan view.

[0053] Hereinafter, with reference to FIGS. 2 and 3, the description of the tiled display device TDD according to one embodiment will focus on the shared layer 100.

[0054] FIG. 2 is a perspective schematic view of a tiled display device according to an embodiment of the present disclosure. FIG. 3 is a block diagram of a tiled display device according to an embodiment of the present disclosure.

[0055] With reference to FIGS. 2 and 3, the tiled display device TDD may include a first panel PNL1, a second panel PNL2, a third panel PNL3, a fourth panel PNL4, and a shared layer 100. Here, the first panel PNL1 to the fourth panel PNL4 may be disposed as a lower structure of the tiled display device TDD, and the shared layer 100 may be disposed as an upper structure of the tiled display device TDD.

[0056] The first display device DD1 may include the first panel PNL1 and at least a portion of the shared layer 100. For example, the first display device DD1 may include the first panel PNL1 and a first shared layer (or a first upper layer). The first shared layer is a part of the shared layer 100 and may overlap the first panel PNL1. The first panel PNL1 may overlap a first region (e.g., a first portion) of the shared layer 100 in a plan view.

[0057] The second display device DD2 may include the second panel PNL2 and at least a portion of the shared layer 100. For example, the second display device DD2 may include the second panel PNL2 and a second shared layer (or a second upper layer). The second shared layer is a part of the shared layer 100 and may overlap the second panel PNL2. The second panel PNL2 may overlap a second region (e.g., a second portion) of the shared layer 100 in a plan view.

[0058] The third display device DD3 may include a third panel PNL3 and at least a portion of the shared layer 100. For example, the third display device DD3 may include a third panel PNL3 and a third shared layer (or a third upper layer). The third shared layer is a part of the shared layer 100 and may overlap with the third panel PNL3. The third panel PNL3 may overlap with a third region (e.g., a third portion) of the shared layer 100 in a plan view.

[0059] The fourth display device DD4 may include a fourth panel PNL4 and at least a portion of the shared layer 100. For example, the fourth display device DD4 may include a fourth panel PNL4 and a fourth shared layer (or a fourth upper layer). The fourth shared layer is a part of the shared layer 100 and may overlap with the fourth panel PNL4. The fourth panel PNL4 may overlap with a fourth region (e.g., a fourth portion) of the shared layer 100 in a plan view.

[0060] According to one embodiment, the first to fourth shared layers may be integrated with each other.

[0061] The first panel PNL1 may be connected to at least a portion of the shared layer 100. For example, the upper surface of the first panel PNL1 and the lower surface of the shared layer 100 may be connected through an adhesive element. The adhesive element may include an adhesive material, but the present disclosure is not limited to a specific example. Similarly, each of the second panel PNL2 to the fourth panel PNL4 may be connected to a portion of the shared layer 100.

[0062] The first panel PNL1 is a part of the first display device DD1 and may represent the lower panel of the first display device DD1. Similarly, the second panel PNL2 to the fourth panel PNL4 are parts of the second display device DD2 to the fourth display device DD4, respectively, and may represent the lower panels of the second display device DD2 to the fourth display device DD4.

[0063] According to one embodiment, the first panel PNL1 to the fourth panel PNL4 may be separated from each other. For example, as described above, the first panel PNL1 may be separated from the second panel PNL2, the third panel PNL3, and the fourth panel PNL4, and the bonding region BA is interposed therebetween. According to one embodiment, adjacent panels (e.g., the first panel PNL1 and the second panel PNL2) may be connected in the bonding region BA.

[0064] According to one embodiment, the first panel PNL1, the second panel PNL2, the third panel PNL3, and the fourth panel PNL4 may be placed on the same layer.

[0065] The first panel PNL1 may include a first substrate SUB1, a first pixel circuit portion PCL1, and a first display element portion DPL1. The first substrate SUB1, the first pixel circuit portion PCL1, and the first display element portion DPL1 may be successively stacked in the thickness direction (e.g., the third direction DR3) of the first substrate SUB1. Similarly, the second panel PNL2 to the fourth panel PNL4 may respectively include second substrates SUB2 to fourth substrates SUB4, second pixel circuit portions PCL2 to fourth pixel circuit portions PCL4, and second display element portions DPL2 to fourth display element portions DPL4, which are successively stacked in the third direction DR3.

[0066] The first panel PNL1 to the fourth panel PNL4 may emit light. For example, the first display element portions DPL1 to the fourth display element portions DPL4 respectively included in the first panel PNL1 to the fourth panel PNL4 may include light-emitting elements LD configured to emit light.

[0067] For example, the first display element portion DPL1 may include a first light-emitting element, the second display element portion DPL2 may include a second light-emitting element, the third display element portion DPL3 may include a third light-emitting element, and the fourth display element portion DPL4 may include a fourth light-emitting element.

[0068] According to one embodiment, a "display element part" may be referred to as a "display element layer". For example, the first display element portion DPL1 may be a first display element layer, the second display element portion DPL2 may be a second display element layer, the third display element portion DPL3 may be a third display element layer, and the fourth display element portion DPL4 may be a fourth display element layer.

[0069] The first panel PNL1 may overlap with the shared layer 100 in a plan view. According to one embodiment, when viewed in a plan view, the first panel PNL1 may overlap with a color conversion portion CCL (see FIG. 8) and / or a color filter portion CFL (see FIG. 8) included in the shared layer 100. Similarly, each of the second panel PNL2 to the fourth panel PNL4 may overlap with the shared layer 100 in a plan view. This will be described in detail with reference to FIG. 8 below.

[0070] The first panel PNL1 and the second panel PNL2 to the fourth panel PNL4 can be formed through different processes. For example, the first panel PNL1 can be manufactured through an individual process and coupled (or connected) to the second panel PNL2 to the fourth panel PNL4.

[0071] The first display device DD1 can include the first panel PNL1 and at least a part of the shared layer 100. For example, the first display device DD1 can include the first panel PNL1 and the first shared layer. The first shared layer is a part of the shared layer 100 and can represent the part overlapping with the first panel PNL1.

[0072] Hereinafter, the display device DD included in the tiled display device TDD according to an embodiment will be described in detail. However, for convenience of description, the first display device DD1 in the display device DD will be described. According to an embodiment, the technical features described with reference to the first display device DD1 can be applied to the second display device DD2 to the fourth display device DD4.

[0073] According to an embodiment, the structures shown in FIGS. 4 to 7 can represent the first panel PNL1 of the first display device DD1.

[0074] First, the pixel circuit PXC of the pixel PXL included in the first display device DD1 according to an embodiment will be described with reference to FIG. 4. FIG. 4 is a schematic diagram of an equivalent circuit of the pixel circuit included in the pixel according to an embodiment of the present disclosure.

[0075] Referring to FIG. 4, the pixel PXL can include a light-emitting element LD and a pixel circuit PXC.

[0076] The light-emitting element LD can be electrically connected between the first power supply line VDD and the second power supply line VSS. The first end (e.g., P-type semiconductor) of the light-emitting element LD can be electrically connected to the first power supply line VDD via the first electrode ELT1 and the pixel circuit PXC, and the second end (e.g., N-type semiconductor) of the light-emitting element LD can be electrically connected to the second power supply line VSS via the second electrode ELT2.

[0077] In one embodiment, the light-emitting element LD can emit light having a luminance corresponding to the driving current supplied thereto through the pixel circuit PXC.

[0078] In one embodiment, two or more light-emitting elements LD may be provided in a pixel PXL, and may be electrically connected to each other through various connection structures between a first power line VDD and a second power line VSS. For example, the light-emitting elements LD may be electrically connected to each other in only a parallel or only a series manner. As another example, the light-emitting elements LD may be electrically connected in a series-parallel hybrid structure.

[0079] The first power line VDD and the second power line VSS may have different potentials to cause the light-emitting element LD to emit light. The first power line VDD and the second power line VSS may have a potential difference that causes light to be emitted during the light-emitting period of the pixel PXL. For example, the first power line VDD may be set to have a potential higher than that of the second power line VSS.

[0080] The pixel circuit PXC may electrically connect the first power line VDD to the light-emitting element LD. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0081] According to one embodiment, a first electrode of the first transistor T1 may be electrically connected to the first power line VDD, and a second electrode thereof may be electrically connected to a first electrode (e.g., an anode) of the light-emitting element LD. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 may control the current flowing through the light-emitting element LD in response to the voltage applied thereto through the first node N1.

[0082] According to one embodiment, a first electrode of the second transistor T2 may be electrically connected to the data line DL, and a second electrode thereof may be electrically connected to the first node N1. A gate electrode of the second transistor T2 may be electrically connected to the scan line SL. When a scan signal is supplied from the scan line SL, the second transistor T2 may be turned on. In this case, the data signal provided from the data line DL may be transmitted to the first node N1.

[0083] According to one embodiment, a first electrode of the third transistor T3 may be electrically connected to the sense line SENL, and a second electrode thereof may be electrically connected to a second node N2. A gate electrode of the third transistor T3 may be electrically connected to the sense signal line SEL. When the third transistor T3 is turned on in response to the sense signal supplied from the sense signal line SEL, a reference voltage may be provided to the second node N2 through the sense line SENL.

[0084] According to one embodiment, a reference voltage can be used to set or initialize the voltage of an electrode (e.g., the source of the first transistor T1) of the first transistor T1 electrically connected to the light-emitting element LD to a constant value. For example, the reference voltage can be set to be less than or equal to the voltage of the second power supply line VSS.

[0085] According to one embodiment, when the third transistor T3 is turned on in response to a sensing signal provided from the sensing signal line SEL, a sensing current can be transmitted to the sensing line SENL.

[0086] In one embodiment, the sensing current can be used to calculate the change in the mobility and threshold voltage of the first transistor T1.

[0087] The storage capacitor Cst can be electrically connected between the first node N1 (or the gate electrode of the first transistor T1) and the second node N2 (or the second electrode of the first transistor T1). The storage capacitor Cst can store information about the voltage difference between the first node N1 and the second node N2.

[0088] The structure of the pixel circuit PXC is not limited to the structure shown in FIG. 4, and can be implemented in various structures. FIG. 4 shows the first transistor T1 to the third transistor T3 as N-type transistors. However, the present disclosure is not limited thereto. According to one embodiment, the first transistor T1 to the third transistor T3 can be formed of P-type transistors.

[0089] Hereinafter, the structure of the pixel PXL according to one embodiment will be described with reference to FIGS. 5 to 7. Contents that may be repeated with the above will be briefly described or omitted.

[0090] In one embodiment, the pixel PXL can include a light-emitting element LD. For example, the light-emitting element LD can be a light-emitting diode or an organic light-emitting diode (OLED) having a size in the range of nanoscale to micron scale.

[0091] First, an embodiment in which the light-emitting element LD is a light-emitting diode having a size in the range of nanoscale to micron scale will be described with reference to FIGS. 5 and 6, which is the pixel PXL according to the first embodiment.

[0092] FIG. 5 is a plan view of a pixel according to a first embodiment of the present disclosure. The pixel PXL shown in FIG. 5 may be at least one of a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0093] Referring to FIG. 5, the pixel PXL may include a first electrode ELT1, a second electrode ELT2, a first connection electrode CNL1, a second connection electrode CNL2, a first contact CNT1, a second contact CNT2, a light-emitting element LD, a first contact electrode CNE1, and a second contact electrode CNE2.

[0094] The light-emitting element LD may be disposed and arranged. For example, the light-emitting element LD may be arranged in a parallel structure in the second direction DR2. However, the arrangement structure of the light-emitting element LD is not limited thereto.

[0095] In one embodiment, the light-emitting element LD may be provided as a rod-shaped element extending in one direction. The light-emitting element LD may have a first end EP1 and a second end EP2. The first semiconductor layer 11 may be adjacent to the first end EP1 of the light-emitting element LD. The second semiconductor layer 13 may be adjacent to the second end EP2 of the light-emitting element LD.

[0096] In one embodiment, the light-emitting element LD may be a light-emitting element manufactured as a columnar shape by an etching method or a similar method. In this specification, the term "columnar shape" includes rod-like shapes and bar-like shapes such as cylindrical and prismatic shapes (e.g., having an aspect ratio greater than 1) extending in the longitudinal direction, and the cross-sectional shape thereof is not limited to a specific shape. For example, the length of the light-emitting element LD may be greater than its diameter (or the width of its cross-section). However, the shape of the light-emitting element LD is not limited to the above examples.

[0097] In one embodiment, the light-emitting element LD may have dimensions corresponding to the range from the nanoscale to the microscale.

[0098] In one embodiment, the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13.

[0099] The first semiconductor layer 11 may be a first-conductive semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer containing at least one semiconductor material among indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and doped with a first-conductive dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material forming the first semiconductor layer 11 is not limited thereto.

[0100] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. For example, when the active layer 12 has a multi-quantum well structure, the active layer 12 may be formed by periodically repeating a barrier layer, a strain-enhanced layer, and a well layer as a single unit. The lattice constant of the strain-enhanced layer may be smaller than that of the barrier layer, so that the strain applied to the well layer, such as compressive strain, can be further enhanced. However, the structure of the active layer 12 is not limited to the above embodiments.

[0101] In one embodiment, the active layer 12 may emit light having a wavelength of about 400 nm to about 900 nm. For example, the active layer 12 may include a material such as aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). However, the material thereof is not limited to the above examples.

[0102] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a different type from the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a P-type semiconductor layer. For example, the second semiconductor layer 13 may include a P-type semiconductor layer containing at least one semiconductor material among indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and doped with a second-conductive dopant such as magnesium (Mg). However, the material forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0103] If a voltage equal to or greater than the threshold voltage is applied to opposite ends of the light-emitting element LD, the light-emitting element LD will emit light through the recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled according to the above principle, the light-emitting element LD can be used as a light source for various light-emitting devices.

[0104] In one embodiment, the light-emitting element LD may further include an element insulating layer. The element insulating layer may be disposed on the outer surface of the light-emitting element LD to stabilize the electrical connection.

[0105] For example, the element insulating layer may include an inorganic material. For example, the element insulating layer may be formed as a single-layer or multi-layer structure including at least one insulating material selected from at least one of silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum oxide (AlO x), and titanium oxide (TiO x).

[0106] The structure of the light-emitting element LD is not limited to the above examples and may further include additional components. For example, the light-emitting element LD may further include a phosphor layer, an active layer, an electrode layer, and the like.

[0107] The light-emitting element LD may be disposed between electrodes configured to serve as alignment electrodes. For example, the light-emitting element LD may be arranged between a first electrode ELT1 and a second electrode ELT2 in a plan view. The light-emitting element LD may be disposed on the first electrode ELT1 and the second electrode ELT2. At least a part of the light-emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2 in a plan view.

[0108] The light-emitting element LD may be electrically connected to the first electrode ELT1 through a first contact electrode CNE1.

[0109] According to one embodiment, the second end EP2 of the light-emitting element LD may be electrically connected to the first contact electrode CNE1. Therefore, the second semiconductor layer 13 of the light-emitting element LD may be electrically connected to the first electrode ELT1 and the first contact electrode CNE1.

[0110] The light-emitting element LD may be electrically connected to the second electrode ELT2 through a second contact electrode CNE2.

[0111] According to one embodiment, the first end EP1 of the light-emitting element LD may be electrically connected to the second contact electrode CNE2. Therefore, the first semiconductor layer 11 of the light-emitting element LD may be electrically connected to the second electrode ELT2 and the second contact electrode CNE2.

[0112] The first electrode ELT1 may extend in the second direction DR2. The first electrode ELT1 may be separated from the second electrode ELT2 in the first direction DR1. The first electrode ELT1 may be electrically connected to the first connection electrode CNL1. The first direction DR1 may intersect (or may not be parallel to) the second direction DR2.

[0113] The first connection electrode CNL1 may be electrically connected to a bridging pattern BRP (see Figure 6) included in the first pixel circuit portion PCL1 through the first contact CNT1. The first connection electrode CNL1 and the first electrode ELT1 may be disposed on the same layer and integrally formed (or formed as one) with each other.

[0114] The second electrode ELT2 may extend in the second direction DR2. The second electrode ELT2 may be separated from the first electrode ELT1 in the first direction DR1. The second electrode ELT2 may be electrically connected to the second connection electrode CNL2.

[0115] The second connection electrode CNL2 may be electrically connected to a power line PL (see Figure 6) included in the first pixel circuit portion PCL1 through the second contact CNT2. The second connection electrode CNL2 and the second electrode ELT2 may be disposed on the same layer and integrally formed with each other.

[0116] The first contact electrode CNE1 may be disposed on the first electrode ELT1 to be electrically connected to the first electrode ELT1. The first contact electrode CNE1 may electrically connect the first electrode ELT1 to the light-emitting element LD.

[0117] The second contact electrode CNE2 may be disposed on the second electrode ELT2 to be electrically connected to the second electrode ELT2. The second contact electrode CNE2 may electrically connect the second electrode ELT2 to the light-emitting element LD.

[0118] Figure 6 is a schematic cross-sectional view of a pixel PXL according to an embodiment. Figure 6 is a cross-sectional view taken along line II-II' of Figure 5. Hereinafter, for convenience of explanation, the first transistor T1 among the first transistor T1 to the third transistor T3 will be mainly described.

[0119] Referring to Figure 6, the pixel PXL may include a first substrate SUB1, a first pixel circuit portion PCL1, and a first display element portion DPL1.

[0120] The first substrate SUB1 can provide an area where a first pixel circuit portion PCL1 and a first display element portion DPL1 are provided. The first substrate SUB1 can form a base element of the pixel PXL. The first substrate SUB1 can be a rigid or flexible substrate or film, but the present disclosure is not limited to specific examples.

[0121] The first pixel circuit portion PCL1 can be provided on the first substrate SUB1. The first pixel circuit portion PCL1 can include a buffer layer BFL, a first transistor T1, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a bridging pattern BRP, a power line PL, a passivation layer PSV, a first contact portion CNT1, and a second contact portion CNT2.

[0122] The buffer layer BFL can be provided on the first substrate SUB1. The buffer layer BFL can prevent impurities diffusing from the outside. The buffer layer BFL can include at least one of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxy), and aluminum oxide (AlOx).

[0123] The first transistor T1 can be a thin film transistor. According to one embodiment, the first transistor T1 can be a driving transistor.

[0124] The first transistor T1 can be electrically connected to the light emitting element LD. The first transistor T1 can be electrically connected to the bridging pattern BRP.

[0125] The first transistor T1 includes an active layer ACT, a first transistor electrode TE1, a second transistor electrode TE2, and a gate electrode GE.

[0126] The active layer ACT can represent a semiconductor layer. The semiconductor layer (active layer ACT) can be provided on the buffer layer BFL. The active layer ACT can include at least one of polysilicon, low-temperature polycrystalline silicon (LTPS), amorphous silicon, and oxide semiconductors.

[0127] The active layer ACT may include a first contact region in contact with the first transistor electrode TE1 and a second contact region in contact with the second transistor electrode TE2. Each of the first contact region and the second contact region may be a doped semiconductor pattern. The region between the first contact region and the second contact region may be a channel region. The channel region may be an intrinsic semiconductor pattern without doping impurities.

[0128] The gate electrode GE may be disposed on the gate insulating layer GI. The position of the gate electrode GE may correspond to the position of the channel region of the active layer ACT. For example, the gate electrode GE may be disposed on the channel region of the active layer ACT, and the gate insulating layer GI is interposed therebetween.

[0129] The gate insulating layer GI may be disposed on the active layer ACT. The gate insulating layer GI may include an inorganic material. For example, the gate insulating layer GI may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0130] The first interlayer insulating layer ILD1 may be located on the gate electrode GE. Similar to the gate insulating layer GI, the first interlayer insulating layer ILD1 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0131] The first transistor electrode TE1 and the second transistor electrode TE2 may be located on the first interlayer insulating layer ILD1. The first transistor electrode TE1 may pass through the gate insulating layer GI and the first interlayer insulating layer ILD1 to contact the first contact region of the active layer ACT, and the second transistor electrode TE2 may pass through the gate insulating layer GI and the first interlayer insulating layer ILD1 to contact the second contact region of the active layer ACT. For example, the first transistor electrode TE1 may be a drain electrode, and the second transistor electrode TE2 may be a source electrode. However, the present disclosure is not limited thereto.

[0132] The second interlayer insulating layer ILD2 may be located on the first transistor electrode TE1 and the second transistor electrode TE2. Similar to the first interlayer insulating layer ILD1 and the gate insulating layer GI, the second interlayer insulating layer ILD2 may include an inorganic material. The above inorganic material may include the materials forming the first interlayer insulating layer ILD1 and the gate insulating layer GI, such as at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0133] The bridging pattern BRP can be disposed on the second interlayer insulating layer ILD2. The bridging pattern BRP can be electrically connected to the first transistor electrode TE1 through a contact hole passing through the second interlayer insulating layer ILD2. The bridging pattern BRP can be electrically connected to the first electrode ELT1 through the first contact CNT1 formed in the passivation layer PSV.

[0134] The power line PL can be disposed on the second interlayer insulating layer ILD2. The power line PL can be electrically connected to the second electrode ELT2 through the second contact CNT2 formed in the passivation layer PSV.

[0135] The passivation layer PSV can be located on the second interlayer insulating layer ILD2. The passivation layer PSV can cover the bridging pattern BRP and the power line PL. The passivation layer PSV can be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the passivation layer PSV can include the first contact CNT1 electrically connected to a region of the bridging pattern BRP and the second contact CNT2 electrically connected to a region of the power line PL.

[0136] The first display element portion DPL1 can be disposed on the first pixel circuit portion PCL1. The first display element portion DPL1 can include a first insulating pattern INP1, a second insulating pattern INP2, a first electrode ELT1, a second electrode ELT2, a first insulating layer INS1, a light-emitting element LD, a second insulating layer INS2, a first contact electrode CNE1, a second contact electrode CNE2, and a third insulating layer INS3.

[0137] The first insulating pattern INP1 and the second insulating pattern INP2 can be disposed on the passivation layer PSV. Each of the first insulating pattern INP1 and the second insulating pattern INP2 can have a shape protruding in the thickness direction of the first substrate SUB1.

[0138] The first electrode ELT1 and the second electrode ELT2 can be disposed on the passivation layer PSV. According to an embodiment, at least a part of the first electrode ELT1 can be disposed on the first insulating pattern INP1, and at least a part of the second electrode ELT2 can be disposed on the second insulating pattern INP2 to serve as a reflective partition wall.

[0139] The first electrode ELT1 can be electrically connected to the bridging pattern BRP through the first contact CNT1. The second electrode ELT2 can be electrically connected to the power line PL through the second contact CNT2.

[0140] The first electrode ELT1 can be electrically connected to the light-emitting element LD. The first electrode ELT1 can be electrically connected to the first contact electrode CNE1 through a contact hole formed in the first insulating layer INS1. The first electrode ELT1 can apply an anode signal to the light-emitting element LD.

[0141] The second electrode ELT2 can be electrically connected to the light-emitting element LD. The second electrode ELT2 can be electrically connected to the second contact electrode CNE2 through a contact hole formed in the first insulating layer INS1. The second electrode ELT2 can apply a cathode signal (e.g., a ground signal) to the light-emitting element LD.

[0142] Each of the first electrode ELT1 and the second electrode ELT2 can include a conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 can include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and their alloys. However, the present disclosure is not limited to the above examples.

[0143] The first insulating layer INS1 can be disposed on the passivation layer PSV. The first insulating layer INS1 can cover the first electrode ELT1 and the second electrode ELT2. The first insulating layer INS1 can stabilize the connection between the electrode components and reduce external influences. The first insulating layer INS1 can include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0144] The light-emitting element LD can be disposed on the first insulating layer INS1. The light-emitting element LD can emit light in response to electrical signals provided from the first contact electrode CNE1 and the second contact electrode CNE2.

[0145] The second insulating layer INS2 can be disposed on the light-emitting element LD. The second insulating layer INS2 can cover the active layer 12 of the light-emitting element LD. For example, the second insulating layer INS2 can include at least one of an organic material and an inorganic material.

[0146] According to one embodiment, at least a portion of the second insulating layer INS2 may be located on the lower surface of the light-emitting element LD. In this case, the second insulating layer INS2 may fill at least a portion of the groove formed on the lower surface of the light-emitting element LD.

[0147] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first insulating layer INS1. The first contact electrode CNE1 may electrically connect the first electrode ELT1 to the light-emitting element LD, while the second contact electrode CNE2 may electrically connect the second electrode ELT2 to the light-emitting element LD.

[0148] The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a conductive material. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include a transparent conductive material, which includes indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). However, the present disclosure is not limited thereto.

[0149] The layout relationship of elements such as the light-emitting element LD and the electrodes is not limited to the example described above with reference to FIG. 6, and the layout relationship according to various modifications can be realized.

[0150] In one embodiment, although not shown in the drawings, the first display element portion DPL1 may further include a planarization layer and / or an additional insulating layer, which are disposed on the first contact electrode CNE1 and the second contact electrode CNE2.

[0151] An embodiment in which the light-emitting element LD of the pixel PXL according to the second embodiment is an organic light-emitting diode will be described with reference to FIG. 7. FIG. 7 is a cross-sectional schematic view of a pixel according to the second embodiment of the present disclosure.

[0152] Referring to FIG. 7, the pixel PXL according to the second embodiment is different from the pixel PXL according to the first embodiment (see FIGS. 5 and 6) at least in that its light-emitting element LD is an organic light-emitting diode.

[0153] Referring to FIG. 7, the light-emitting element LD may be implemented as an organic light-emitting diode. According to one embodiment, the light-emitting element LD may be an organic light-emitting diode.

[0154] According to one embodiment, the light-emitting element LD may be disposed in a region defined by the pixel definition layer PDL. A first surface of the light-emitting element LD may be electrically connected to the first electrode ELT1, and a second surface of the light-emitting element LD may be electrically connected to the second electrode ELT2.

[0155] The first electrode ELT1 may be the anode of the light-emitting element LD, and the second electrode ELT2 may be the common electrode (or cathode) of the light-emitting element LD.

[0156] In one embodiment, the light-emitting element LD may have a multilayer thin film structure including a light generation layer. The light-emitting element LD may include a hole injection layer into which holes are injected; a hole transport layer, which has desirable hole transport performance and suppresses the movement of electrons that do not recombine with holes in the light generation layer, thereby increasing the chance of recombination between holes and electrons; a light generation layer, which emits light through the recombination between the injected electrons and holes; a hole blocking layer, which suppresses the movement of holes that do not recombine with electrons in the light-emitting layer; an electron transport layer, which is arranged to smoothly transport electrons to the light generation layer; and an electron injection layer into which electrons are injected. The light-emitting element LD may emit light in response to an electrical signal provided from the first electrode ELT1 and the second electrode ELT2.

[0157] In one embodiment, the first display element unit DPL1 may include a pixel definition layer PDL and a thin film encapsulation layer TFE.

[0158] The pixel definition layer PDL may define the positions where the light-emitting elements LD implemented as organic light-emitting diodes are arranged. The pixel definition layer PDL may include an organic material. For example, the pixel definition layer PDL may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin, but the present disclosure is not limited thereto.

[0159] The thin film encapsulation layer TFE may be disposed on the second electrode ELT2. The thin film encapsulation layer TFE may eliminate the steps caused by the light-emitting element LD and the pixel definition layer PDL. The thin film encapsulation layer TFE may include an insulating layer configured to cover the light-emitting element LD. For example, the thin film encapsulation layer TFE may have a structure formed by alternately stacking an inorganic layer and an organic layer.

[0160] Hereinafter, a pixel PXL according to an embodiment will be described with reference to FIG. 8 in combination with the shared layer 100. As shown in FIG. 8, for convenience of explanation, the first pixel circuit portion PCL1 and the first display element portion DPL1 are briefly shown. In FIG. 8, the region overlapping with the first panel PNL1 is shown as a part of the shared layer 100.

[0161] FIG. 8 is a schematic cross-sectional view of a pixel including a shared layer, and it is a cross-sectional view taken along line I-I' of FIG. 1.

[0162] Referring to FIG. 8, the first display element portion DPL1 may include a barrier rib BNK. The barrier rib BNK may protrude in the thickness direction of the first substrate SUB1 (the display direction of the tiled display device TDD or the display direction of the first display device DD1, for example, the third direction DR3).

[0163] According to an embodiment, the emission region EMA and the non-emission region NEA may be defined by components included in the first display element portion DPL1.

[0164] In one embodiment, the emission region EMA may represent a region where a light-emitting element LD is provided to emit light. The emission region EMA may represent a region where light is emitted from the first panel PNL1. The non-emission region NEA may be a region other than the emission region EMA, and may represent a region where light is not emitted from the first panel PNL1.

[0165] In one embodiment, the barrier rib BNK may define the emission region EMA of the pixel PXL. The barrier rib BNK may have a shape surrounding the emission region EMA. The light-emitting element LD may be provided in the region surrounded by the barrier rib BNK. According to an embodiment, the barrier rib BNK may include an organic material or an inorganic material, but the present disclosure is not limited thereto. According to an embodiment, the non-emission region NEA may overlap with the barrier rib BNK in a plan view.

[0166] According to an embodiment, the emission region EMA may include a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3. The first emission region EMA1 may represent the emission region EMA of the first sub-pixel SPXL1. The second emission region EMA2 may represent the emission region EMA of the second sub-pixel SPXL2. The third emission region EMA3 may represent the emission region EMA of the third sub-pixel SPXL3.

[0167] For example, in a planar view, the first emission region EMA1 may overlap with the first sub-pixel region SPXA1, the second emission region EMA2 may overlap with the second sub-pixel region SPXA2, and the third emission region EMA3 may overlap with the third sub-pixel region SPXA3.

[0168] The shared layer 100 may be disposed on the first panel PNL1. As described above, the first panel PNL1 and the shared layer 100 may be electrically connected to each other in a certain way.

[0169] According to an embodiment, the shared layer 100 may be disposed on the first panel PNL1. As described above, the shared layer 100 may be disposed to span from the first panel PNL1 to the fourth panel PNL4. Referring to FIG. 8, the detailed structure of the shared layer 100 will be described.

[0170] The shared layer 100 may be disposed to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0171] The shared layer 100 may include a color conversion section CCL, an optical layer OPL, a color filter section CFL, and an upper film layer UFL.

[0172] According to an embodiment, the light-emitting elements LD respectively disposed in the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may emit light of the same color. For example, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include light-emitting elements LD that emit light of a third color (e.g., blue light). Each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may be provided with a color conversion section CCL to display a full-color image.

[0173] The color conversion section CCL may be a layer included in the shared layer 100 and may be configured to change the wavelength of at least a part of the light provided from the first display element section DPL1.

[0174] The color conversion section CCL may be disposed on the first display element section DPL1. The color conversion section CCL may be disposed on the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0175] Although not shown in FIG. 8, the color conversion unit CCL may be arranged to span the second panel PNL2, the third panel PNL3, and the fourth panel PNL4. For example, another area of the color conversion unit CCL may overlap at least one of the second display element unit DPL2, the third display element unit DPL3, and the fourth display element unit DPL4 in a plan view.

[0176] The color conversion unit CCL may include a first cover layer CAP1, a light blocking layer LBL, a first color unit 1200, a second color unit 1400, a third color unit 1600, and a second cover layer CAP2. According to one embodiment, the first color unit 1200 may be referred to as the first emission layer, the second color unit 1400 may be referred to as the second emission layer, and the third color unit 1600 may be referred to as the third emission layer.

[0177] The first cover layer CAP1 may be disposed on the first display element unit DPL1 to seal (or cover) the components disposed between the barrier ribs BNK. The first cover layer CAP1 may be disposed between the first display element unit DPL1 and the optical layer OPL. The first cover layer CAP1 may be arranged to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The first cover layer CAP1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the first display element unit DPL1.

[0178] In one embodiment, the first cover layer CAP1 may be formed as a single-layer or multi-layer structure including silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum oxide (AlO x), and titanium oxide (TiO x). However, the present disclosure is not limited thereto.

[0179] The first color unit 1200 may provide light of a first color. The first color unit 1200 may be a component included in the first sub-pixel SPXL1 and allowing light of the first color to be provided in the first sub-pixel area SPXA1. When viewed from the outside, light of the first color may be observed in the first sub-pixel area SPXA1.

[0180] According to one embodiment, the first sub-pixel area SPXA1 to the third sub-pixel area SPXA3 may be defined by the shared layer 100 (or components included in the shared layer 100).

[0181] According to one embodiment, the first sub-pixel region SPXA1 may represent a region that emits light of a first color. The first sub-pixel region SPXA1 may represent a region where the light of the first color emitted from the first sub-pixel SPXL1 is provided to the outside. In a plan view, the first sub-pixel region SPXA1 may overlap with the first color portion 1200.

[0182] The second color portion 1400 may provide light of a second color. The second color portion 1400 may be a component that is included in the second sub-pixel SPXL2 and allows the light of the second color to be provided in the second sub-pixel region SPXA2. When viewed from the outside, the light of the second color can be observed in the second sub-pixel region SPXA2.

[0183] According to one embodiment, the second sub-pixel region SPXA2 may represent a region that emits light of a second color. The second sub-pixel region SPXA2 may represent a region where the light of the second color emitted from the second sub-pixel SPXL2 is provided to the outside. In a plan view, the second sub-pixel region SPXA2 may overlap with the second color portion 1400.

[0184] The third color portion 1600 may provide light of a third color. The third color portion 1600 may be a component that is included in the third sub-pixel SPXL3 and allows the light of the third color to be provided in the third sub-pixel region SPXA3. When viewed from the outside, the light of the third color can be observed in the third sub-pixel region SPXA3.

[0185] According to one embodiment, the third sub-pixel region SPXA3 may represent a region that emits light of a third color. The third sub-pixel region SPXA3 may represent a region where the light of the third color emitted from the third sub-pixel SPXL3 is provided to the outside. In a plan view, the third sub-pixel region SPXA3 may overlap with the third color portion 1600.

[0186] When viewed in a plan view, the position of the first color portion 1200 may be set to be misaligned with the first emission region EMA1. When viewed in a plan view, the first color portion 1200 may overlap with the first emission region EMA1. According to one embodiment, a part of the first color portion 1200 may overlap with the first emission region EMA1, while another part of the first color portion 1200 may not overlap with the first emission region EMA1.

[0187] When viewed in a plan view, the position of the second color portion 1400 may be set to be misaligned with the second emission region EMA2. When viewed in a plan view, the second color portion 1400 may overlap with the second emission region EMA2. According to one embodiment, a part of the second color portion 1400 may overlap with the second emission region EMA2, while another part of the second color portion 1400 may not overlap with the second emission region EMA2.

[0188] When viewed in a plan view, the position of the third color portion 1600 may be set to be misaligned with the third emission region EMA3. When viewed in a plan view, the third color portion 1600 may overlap with the third emission region EMA3. According to one embodiment, a part of the third color portion 1600 may overlap with the third emission region EMA3, while another part of the third color portion 1600 may not overlap with the third emission region EMA3.

[0189] According to one embodiment, the first color portion 1200 may include first color conversion particles configured to convert light of a third color provided from a light emitting element LD of the first display element portion DPL1 (or a light emitting element LD included in the first sub-pixel SPXL1) into light of a first color. For example, in a case where the light emitting element LD is a blue light emitting element configured to emit blue light and the first sub-pixel SPXL1 is a red pixel, the first color portion 1200 may include first quantum dots that convert blue light emitted from the blue light emitting element into red light.

[0190] For example, the first color portion 1200 may include first quantum dots dispersed in a matrix material such as a base resin. The first quantum dots may absorb blue light and change the wavelength of the light according to energy transitions to emit red light.

[0191] According to one embodiment, the second color portion 1400 may include second color conversion particles configured to convert light of a third color provided from a light emitting element LD of the first display element portion DPL1 (or a light emitting element LD included in the second sub-pixel SPXL2) into light of a second color. For example, in a case where the light emitting element LD is a blue light emitting element configured to emit blue light and the second sub-pixel SPXL2 is a green pixel, the second color portion 1400 may include second quantum dots that convert blue light emitted from the blue light emitting element into green light.

[0192] For example, the second color portion 1400 may include second quantum dots dispersed in a matrix material such as a base resin. The second quantum dots may absorb blue light and change the wavelength of the light according to the energy transition to emit green light.

[0193] Each of the first quantum dots and the second quantum dots may be in the form of nanoparticles, nanotubes, nanowires, nanofibers, and planar nanoparticles having a spherical, conical, multi-armed shape, or cubic shape, but the present disclosure is not limited thereto. The shape of each of the first quantum dots and the second quantum dots may be changed in various ways.

[0194] According to an embodiment, the third color portion 1600 may be provided to effectively use the light of the third color emitted from the light-emitting element LD of the first display element portion DPL1 (or the light-emitting element LD included in the third sub-pixel SPXL3). For example, when the light-emitting element LD is a blue light-emitting element configured to emit blue light and the third sub-pixel SPXL3 is a blue pixel, the third color portion 1600 may include at least one type of light-scattering particles to effectively utilize the light emitted from the light-emitting element LD.

[0195] For example, the third color portion 1600 may include light-scattering particles dispersed in a matrix material such as a base resin. For example, the third color portion 1600 may include light-scattering particles such as silicon dioxide, but the material forming the light-scattering particles is not limited thereto.

[0196] The light-scattering particles do not have to be provided only in the region corresponding to the third sub-pixel SPXL3. For example, the light-scattering particles may be selectively provided in the first color portion 1200 and the second color portion 1400.

[0197] According to an embodiment, the pixel PXL may further include a light-scattering layer provided below the color conversion portion CCL. The light-scattering layer may include light-scattering particles configured to scatter light. The light-scattering layer may be provided to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The light-scattering layer may concentrate the light at a specific position to prevent color unevenness. Since the color conversion portion CCL is provided, the reliability of realizing colors can be improved.

[0198] The light-blocking layer LBL can be disposed on the first display element portion DPL1. The light-blocking layer LBL can be disposed between the first cover layer CAP1 and the second cover layer CAP2. The light-blocking layer LBL can be disposed to surround the first color portion 1200, the second color portion 1400, and the third color portion 1600 at the boundaries between the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0199] According to one embodiment, the light-blocking layer LBL can define a first sub-pixel region SPXA1, a second sub-pixel region SPXA2, and a third sub-pixel region SPXA3.

[0200] For example, the regions where the light-blocking layer LBL is not provided can be at least one of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3. Light can substantially not be emitted from the regions where the light-blocking layer LBL is provided.

[0201] According to one embodiment, the light-blocking layer LBL can be disposed to be misaligned with the emission region EMA. For example, a part of the light-blocking layer LBL can overlap with the emission region EMA in a plan view, while another part of the light-blocking layer LBL can not overlap with the emission region EMA in the plan view. For example, a part of the light-blocking layer LBL can overlap with the barrier wall BNK, while another part of the light-blocking layer LBL can not overlap with the barrier wall BNK.

[0202] According to one embodiment, the light-blocking layer LBL can be formed of an organic material including at least one of graphite, carbon black, black pigment, and black dye, or formed of a metal material including chromium (Cr). However, any material can be used as long as it can block the transmission of light and absorb light.

[0203] The second cover layer CAP2 can seal (or cover) the first color portion 1200, the second color portion 1400, and the third color portion 1600. The second cover layer CAP2 can be disposed between the optical layer OPL and the first cover layer CAP1. The second cover layer CAP2 can be disposed on the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The second cover layer CAP2 can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the first color portion 1200, the second color portion 1400, and the third color portion 1600.

[0204] In one embodiment, the second cover layer CAP2 may be formed as a single-layer or multi-layer structure including silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum oxide (AlO x), and titanium oxide (TiO x). However, the present disclosure is not limited thereto.

[0205] The optical layer OPL may be a layer for improving optical efficiency. The optical layer OPL may be disposed on the color conversion unit CCL. The optical layer OPL may include a low refractive index layer LRL and a third cover layer CAP3.

[0206] The low refractive index layer LRL may be disposed between the second cover layer CAP2 and the third cover layer CAP3. The low refractive index layer LRL may be disposed between the color conversion unit CCL and the color filter unit CFL. The low refractive index layer LRL may be disposed to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0207] The low refractive index layer LRL may reuse the light provided from the color conversion unit CCL through total reflection, thereby improving optical efficiency. To this end, the refractive index of the low refractive index layer LRL may be relatively lower than the refractive index of the color conversion unit CCL.

[0208] According to one embodiment, the low refractive index layer LRL may include a base resin and hollow particles dispersed in the base resin. The hollow particles may include hollow silica particles. As another example, the hollow particles may be pores formed through a porogen, but the present disclosure is not limited thereto. In addition, the low refractive index layer LRL may include at least one of zinc oxide (ZnO) particles, titanium dioxide (TiO 2) particles, and nanosilicate particles, but the present disclosure is not limited thereto.

[0209] The third cover layer CAP3 may be disposed on the low refractive index layer LRL. The third cover layer CAP3 may be disposed between the color filter unit CFL and the low refractive index layer LRL. The third cover layer CAP3 may be disposed on the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The third cover layer CAP3 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive index layer LRL.

[0210] In one embodiment, the third cover layer CAP3 may be formed as a single-layer or multi-layer structure including silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum oxide (AlO x), and titanium oxide (TiO x). However, the present disclosure is not limited thereto.

[0211] The color filter unit CFL may be disposed on the third cover layer CAP3. The color filter unit CFL may be disposed to straddle the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The color filter unit CFL may include color filters CF1, CF2, CF3, a planarization layer PLA, and an overcoat layer OC.

[0212] According to one embodiment, the color filters CF1, CF2, CF3 may be disposed on the third cover layer CAP3. In a plan view, the color filters CF1, CF2, CF3 may overlap with the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3, respectively. For example, the first color filter CF1 may overlap with the first sub-pixel region SPXA1, the second color filter CF2 may overlap with the second sub-pixel region SPXA2, and the third color filter CF3 may overlap with the third sub-pixel region SPXA3.

[0213] According to one embodiment, the first color filter CF1 may transmit light of the first color, but may not transmit light of the second color and the third color. For example, the first color filter CF1 may include a colorant for the first color.

[0214] According to one embodiment, the second color filter CF2 may transmit light of the second color, but may not transmit light of the first color and the third color. For example, the second color filter CF2 may include a colorant for the second color.

[0215] According to one embodiment, the third color filter CF3 may transmit light of the third color, but may not transmit light of the first color and the second color. For example, the third color filter CF3 may include a colorant for the third color.

[0216] According to an embodiment, a planarization layer PLA may be disposed on color filters CF1, CF2, and CF3. The planarization layer PLA may cover the color filters CF1, CF2, and CF3. The planarization layer PLA may eliminate steps caused by the color filters CF1, CF2, and CF3. The planarization layer PLA may be disposed on a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0217] For example, the planarization layer PLA may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfides resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto. The planarization layer PLA may include various types of inorganic materials, including silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum nitride (AlN x), aluminum oxide (AlO x), zirconium oxide (ZrO x), hafnium oxide (HfO x), or titanium oxide (TiO x).

[0218] A protective layer OC may be disposed on the planarization layer PLA. The protective layer OC may be disposed between an upper film layer UFL and a color filter portion CFL. The protective layer OC may be disposed to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The protective layer OC may cover a lower member including the color filter portion CFL. The protective layer OC may prevent moisture or air from penetrating into the lower member. The protective layer OC may protect the lower member from being affected by foreign substances such as dust.

[0219] In one embodiment, the protective layer OC may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfides resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto. The protective layer OC may include various types of inorganic materials, including silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), aluminum nitride (AlN x), aluminum oxide (AlO x), zirconium oxide (ZrO x), hafnium oxide (HfO x), or titanium oxide (TiO x).

[0220] The upper film layer UFL can be disposed on the color filter portion CFL. The upper film layer UFL can be disposed outside the first display device DD1 to reduce the external influence on the first display device DD1. The upper film layer UFL can be disposed to span the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0221] In some embodiments, the upper film layer UFL can include a transparent film. For example, the transparent thin film can be at least one of a polyethylene terephthalate (PET) film, a low-reflection film, a polarizing film, and a film with controllable light transmittance, but the present disclosure is not limited thereto.

[0222] According to one embodiment, the upper film layer UFL can include an anti-reflective (AR) coating for reducing the reflectance of light incident from the outside. The anti-reflective coating can represent an arrangement in which a material having an anti-reflective function is applied to the surface of a specific structure. The applied material can have a low reflectance. For example, the material for the anti-reflective coating can include at least one of silicon oxide (SiO x), zirconium oxide (ZrO x), aluminum oxide (Al xO y), and titanium oxide (TiO x). However, the present disclosure is not limited thereto, and various materials can be used.

[0223] Hereinafter, the reason for improving the visibility of the tiled display device TDD according to one embodiment will be described with reference to FIGS. 9 to 11.

[0224] FIGS. 9 to 11 are enlarged schematic views of the region EA1 of FIG. 1. For ease of explanation, in FIGS. 9 to 11, the first display device DD1 and the second display device DD2 adjacent to each other in the display device DD included in the tiled display device TDD will be mainly described. The technical features and the connection relationship of each of the first display device DD1 and the second display device DD2 can be applied to the third display device DD3 and the fourth display device DD4.

[0225] FIGS. 9 to 11 show a region of a part of each of the first display device DD1 and the second display device DD2.

[0226] FIG. 9 shows a specific first sub-pixel region SPXA1, a second sub-pixel region SPXA2, and a third sub-pixel region SPXA3 in a plan view.

[0227] Figure 10 shows, in a plan view, a specific first emission area EMA1, a second emission area EMA2, and a third emission area EMA3.

[0228] Figure 11 shows a state where Figures 9 and 10 are overlapped to represent the positional relationship between a first sub-pixel area SPXA1, a second sub-pixel area SPXA2, and a third sub-pixel area SPXA3 and the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0229] First, referring to Figure 9, the first sub-pixel area SPXA1, the second sub-pixel area SPXA2, and the third sub-pixel area SPXA3 can be arranged in a pattern. For example, Figure 9 shows an embodiment in which the first sub-pixel area SPXA1, the second sub-pixel area SPXA2, and the third sub-pixel area SPXA3 are arranged in a first direction DR1, but the present disclosure is not limited thereto.

[0230] According to one embodiment, the first sub-pixel area SPXA1, the second sub-pixel area SPXA2, and the third sub-pixel area SPXA3 adjacent to each other in the first display device DD1 can be separated from each other by a first separation distance 220. The first sub-pixel area SPXA1, the second sub-pixel area SPXA2, and the third sub-pixel area SPXA3 adjacent to each other in the second display device DD2 can be separated from each other by a first separation distance 220.

[0231] For example, in the display device DD, the first sub-pixel area SPXA1, the second sub-pixel area SPXA2, and the third sub-pixel area SPXA3 can be separated from each other by a first separation distance 220 in a second direction DR2. In the first display device DD1, the first sub-pixel area SPXA1 and the second sub-pixel area SPXA2 can be separated from each other by a first separation distance 220. In the first display device DD1, the second sub-pixel area SPXA2 and the third sub-pixel area SPXA3 can be separated from each other by a first separation distance 220. In the second display device DD2, the first sub-pixel area SPXA1 and the second sub-pixel area SPXA2 can be separated from each other by a first separation distance 220. In the second display device DD2, the second sub-pixel area SPXA2 and the third sub-pixel area SPXA3 can be separated from each other by a first separation distance 220.

[0232] In one embodiment, the first adjacent sub-pixel region 2200 may be separated from the second adjacent sub-pixel region 2400 by a second separation distance 240. For example, the first adjacent sub-pixel region 2200 may be separated from the second adjacent sub-pixel region 2400 by the second separation distance 240 in the second direction DR2.

[0233] The first adjacent sub-pixel region 2200 may represent the sub-pixel region closest to the adjacent second display device DD2 among the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 provided in the first display device DD1. The second adjacent sub-pixel region 2400 may represent the sub-pixel region closest to the adjacent first display device DD1 among the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 provided in the second display device DD2.

[0234] In one embodiment, the color represented by the first adjacent sub-pixel region 2200 and the color represented by the second adjacent sub-pixel region 2400 may be different from each other.

[0235] In one embodiment, the first adjacent sub-pixel region 2200 and the second adjacent sub-pixel region 2400 may be separated from each other, and a bonding region BA may be interposed therebetween. The thickness of the bonding region BA (e.g., the separation distance between the first panel PNL1 of the first display device DD1 and the second panel PNL2 of the second display device DD2) may be less than the second separation distance 240. However, the present disclosure is not limited thereto.

[0236] In one embodiment, the bonding region BA may be arranged to be misaligned with the region that defines the second separation distance 240 between the first adjacent sub-pixel region 2200 and the second adjacent sub-pixel region 2400.

[0237] Referring to FIG. 10, the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 may be arranged in a pattern. For example, FIG. 10 shows an embodiment in which the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 are arranged in the first direction DR1, but the present disclosure is not limited thereto.

[0238] According to one embodiment, a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3 adjacent to each other in a first display device DD1 may be separated from each other by a first emission separation distance 320. A first emission region EMA1, a second emission region EMA2, and a third emission region EMA3 adjacent to each other in a second display device DD2 may be separated from each other by a first emission separation distance 320.

[0239] For example, in a display device DD, a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3 may be separated from each other by a first emission separation distance 320 in a second direction DR2.

[0240] In the first display device DD1, the first emission region EMA1 and the second emission region EMA2 may be separated from each other by a first emission separation distance 320. In the first display device DD1, the second emission region EMA2 and the third emission region EMA3 may be separated from each other by a first emission separation distance 320. In the second display device DD2, the first emission region EMA1 and the second emission region EMA2 may be separated from each other by a first emission separation distance 320. In the second display device DD2, the second emission region EMA2 and the third emission region EMA3 may be separated from each other by a first emission separation distance 320.

[0241] In one embodiment, a first adjacent emission region 3200 may be separated from a second adjacent emission region 3400 by a second emission separation distance 340. For example, the first adjacent emission region 3200 may be separated from the second adjacent emission region 3400 by a second emission separation distance 340 in a second direction DR2.

[0242] The first adjacent emission region 3200 may represent the emission region among the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 provided in the first display device DD1 that is closest to the adjacent second display device DD2. The second adjacent emission region 3400 may represent the emission region among the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 provided in the second display device DD2 that is closest to the adjacent first display device DD1.

[0243] According to one embodiment, the thickness of the bonding region BA can be less than the second emission separation distance 340. For example, in a plan view, the bonding region BA can overlap with the region that defines the second emission separation distance 340 between the first adjacent emission region 3200 and the second adjacent emission region 3400.

[0244] According to one embodiment, the first emission separation distance 320 and the second emission separation distance 340 can be different from each other. For example, the first emission separation distance 320 can be less than the second emission separation distance 340.

[0245] According to one embodiment, the second emission separation distance 340 can be greater than the second separation distance 240.

[0246] To manufacture the tiled display device TDD, the first display device DD1 and the second display device DD2 can be manufactured separately and connected to each other. In the first display device DD1, the emission regions EMA can be manufactured to be separated from each other by the first emission separation distance 320. In the second display device DD2, the emission regions EMA can be manufactured to be separated from each other by the first emission separation distance 320. When the first display device DD1 and the second display device DD2 are connected to each other, the first adjacent emission region 3200 and the second adjacent emission region 3400 can be separated from each other by the second emission separation distance 340, and the second emission separation distance 340 is different from the first emission separation distance 320.

[0247] Experimentally, since the first emission separation distance 320 and the second emission separation distance 340 are different from each other, the bonding region BA can be visually recognized from the outside. In this case, the visibility of the tiled display device TDD may be impaired.

[0248] However, according to one embodiment, a shared layer 100 forming (or configuring) the upper panel of the tiled display device TDD can be provided, thereby improving external visibility.

[0249] More specifically, referring to FIG. 11, the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 defined by the components included in the shared layer 100 can be arranged in a pattern regardless of the structure of the respective components of the first panel PNL1 and the second panel PNL2.

[0250] In addition, the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 defined by components included in the shared layer 100 may be arranged in a pattern and have a different layout structure from the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 defined by components forming the lower panel. Referring to FIG. 11, according to one embodiment, it can be seen that the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 are set not to be aligned with each other with the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3.

[0251] For example, the separation distances between the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 in the first display device DD1, the separation distances between the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 in the second display device DD2, and the separation distances of the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 in a region where the first display device DD1 and the second display device DD2 are adjacent to each other may be substantially the same as each other.

[0252] In this case, even when the separation distances between the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 defined by components (e.g., components of the first panel PNL1 and the second panel PNL2) forming the lower panel of the tiled display device TDD are partially non-uniform, the external visibility is not impaired.

[0253] According to one embodiment, the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 may be respectively larger than the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3.

[0254] For example, in a plan view, at least a part of the first sub-pixel region SPXA1 may protrude without overlapping with the first emission region EMA1. The first emission region EMA1 may be arranged to be included in the first sub-pixel region SPXA1 in the plan view. In the plan view, at least a part of the second sub-pixel region SPXA2 may protrude without overlapping with the second emission region EMA2. The second emission region EMA2 may be arranged to be included in the second sub-pixel region SPXA2 in the plan view. In the plan view, at least a part of the third sub-pixel region SPXA3 may protrude without overlapping with the third emission region EMA3. The third emission region EMA3 may be arranged to be included in the third sub-pixel region SPXA3 in the plan view.

[0255] However, the present disclosure is not limited to the above examples. For example, the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 may be equal to or smaller than the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3.

[0256] According to one embodiment, since the color conversion unit CCL and the color filter unit CFL are provided in the shared layer 100, external visibility can be improved. As described above with reference to FIG. 8, the color conversion unit CCL and the color filter unit CFL provided across the display device DD may be provided in the shared layer 100. Specifically, the color conversion unit CCL may include a first color unit 1200 configured to emit light of a first color, a second color unit 1400 configured to emit light of a second color, and a third color unit 1600 configured to emit light of a third color. In this case, when viewed from the outside, the first sub-pixel SPXL1 that emits light of the first color, the second sub-pixel SPXL2 that emits light of the second color, and the third sub-pixel SPXL3 that emits light of the third color may be defined by the structure of the color conversion unit CCL included in the shared layer 100. In other words, even when the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 are partially and unevenly arranged in the lower panel (especially near the bonding region BA), it may not be visually recognized from the outside.

[0257] In addition, since the color conversion unit CCL and the color filter unit CFL can be formed through a photo process, a photolithography process, or a printing process, which can be performed on a large area, the process productivity can be improved.

[0258] In addition, according to an embodiment, the bonding region BA can be regarded as a separation region or gap between adjacent first sub-pixel regions SPXA1, second sub-pixel regions SPXA2, and third sub-pixel regions SPXA3, and thus external visibility problems in the bonding region BA that may occur in the related art can be solved.

[0259] The above description is only an illustration of the technical idea of the present disclosure, and those of ordinary skill in the art to which the present invention pertains can make various changes and modifications to the present disclosure without departing from the scope of the present disclosure. Therefore, the above embodiments can be implemented alone or in combination.

[0260] Therefore, since the embodiments are illustrative rather than restrictive, it should be understood that the technical spirit of the present disclosure is not limited to specific embodiments. All technical ideas within the equivalent scope should be understood to be included within the scope of the present disclosure.

[0261] According to an embodiment, a tiled display device can be provided, in which external visibility is improved and process productivity is improved.

[0262] The present disclosure is not limited to the above effects, and those of ordinary skill in the art to which the present invention pertains will clearly understand other effects not mentioned herein through the description and the accompanying drawings.

[0263] 11: First semiconductor layer 12: Active layer 13: Second semiconductor layer 100: Shared layer 220: First separation distance 240: Second separation distance 320: First emission separation distance 340: Second emission separation distance 1200: First color section 1400: Second color section 1600: Third color section 2200: First adjacent sub-pixel region 2400: Second adjacent sub-pixel region 3200: First adjacent emission region 3400: Second adjacent emission region ACT: Active layer BA: Bonding region BFL: Buffer layer BNK: Retaining wall BRP: Bridging pattern CAP1: First covering layer CAP2: Second covering layer CAP3: Third covering layer CCL: Color conversion section Cst: Storage capacitor CFL: Color filter section CF1,CF2,CF3: Color filters CNE1: First contact electrode CNE2: Second contact electrode CNT1: First contact part CNT2: Second contact part CNL1: First connection electrode CNL2: Second connection electrode DA: Display area DD,DD1,DD2,DD3,DD4: Display devices DL: Data line DPL1: First display element section DPL2: Second display element section DPL3: Third display element section DPL4: Fourth display element section DR1: First direction DR2: Second direction DR3: Third direction ELT1: First electrode ELT2: Second electrode EMA: Emission area EMA1: First emission area EMA2: Second emission area EMA3: Third emission area EP1: First end EP2: Second end GE: Gate electrode GI: Gate insulating layer ILD1: First interlayer insulating layer ILD2: Second interlayer insulating layer INS1: First insulating layer INS2: Second insulating layer INS3: Third insulating layer INP1: First insulating pattern INP2: Second insulating pattern LBL: Light blocking layer LD: Light emitting element LRL: Low refractive index layer NEA: Non-emitting area NDA: Non-display area N1: First node N2: Second node OC: Protection layer OPL: Optical layer PDL: Pixel definition layer PXC: Pixel circuit PXL: Pixel PCL1: First pixel circuit part PCL2: Second pixel circuit part PCL3: Third pixel circuit part PCL4: Fourth pixel circuit part PL: Power line PLA: Planarization layer PNL1: First panel PNL2: Second panel PNL3: Third panel PNL4: Fourth panel PSV: Passivation layer SEL: Sensing signal line SENL: Sensing line SL: Scanning line SPXA1: First sub-pixel area SPXA2: Second sub-pixel area SPXA3: Third sub-pixel area SPXL1: First sub-pixel SPXL2: Second sub-pixel SPXL3: Third sub-pixel SUB1: First substrate SUB2: Second substrate SUB3: Third substrate SUB4: Fourth substrate TDD: Tiled display device TFE: Thin film encapsulation layer T1: First transistor T2: Second transistor T3: Third transistor TE1: First transistor electrode TE2: Second transistor electrode UFL: Upper film layer VDD: First power supply line VSS: Second power supply line

Claims

1. A splicing display device, comprising: a first panel including a first display element layer; a second panel including a second display element layer; and a shared layer including a color conversion unit; wherein the shared layer includes a first portion and a second portion; wherein the first portion overlaps with the first panel in a plan view, wherein the second portion overlaps with the second panel in a plan view, and wherein the color conversion unit changes the wavelength of light provided from the first panel and the second panel.

2. The splicing display device as claimed in claim 1, wherein the first panel and the second panel form a lower panel of the splicing display device, and the shared layer forms an upper panel of the splicing display device.

3. The splicing display device as claimed in claim 1, wherein the first panel and the second panel are disposed on the same layer, the first panel and the second panel are separated from each other, and a joint area is disposed between the first panel and the second panel.

4. The splicing display device as described in claim 3, wherein the splicing area overlaps with the shared layer in a plan view.

5. The splicing display device as claimed in claim 1, wherein the color conversion unit comprises: a first color unit that provides light of a first color; a second color unit that provides light of a second color; and a third color unit that provides light of a third color, wherein the first color unit, the second color unit, and the third color unit overlap with the first panel and the second panel in a plan view.

6. The splicing display device as claimed in claim 5, further comprising: a first sub-pixel region that emits light of the first color and overlaps with the first color portion in a planar view; a second sub-pixel region that emits light of the second color and overlaps with the second color portion in a planar view; and a third sub-pixel region that emits light of the third color and overlaps with the third color portion in a planar view.

7. The splicing display device as claimed in claim 6, wherein the shared layer further comprises: a first color filter that overlaps with the first sub-pixel region in a planar view; a second color filter that overlaps with the second sub-pixel region in a planar view; and a third color filter that overlaps with the third sub-pixel region in a planar view.

8. The splicing display device as claimed in claim 6, wherein the first display element layer includes a first light-emitting element, and the second display element layer includes a second light-emitting element, wherein the splicing display device further includes: an emitting region wherein the first light-emitting element and the second light-emitting element are disposed, wherein the emitting region is defined by components included in the first display element layer and the second display element layer.

9. The splicing display device as claimed in claim 8, wherein each of the first display element layer and the second display element layer includes a barrier wall projecting in the display direction of the splicing display device, and the barrier wall has a shape that surrounds the emission area.

10. The splicing display device as claimed in claim 8, wherein the emitting region comprises: a first emitting region that overlaps with the first sub-pixel region in a planar view; a second emitting region that overlaps with the second sub-pixel region in a planar view; and a third emitting region that overlaps with the third sub-pixel region in a planar view.

11. The splicing display device as claimed in claim 10, wherein the first color system is configured to be misaligned with the first emission area in a plan view, the second color system is configured to be misaligned with the second emission area in a plan view, and the third color system is configured to be misaligned with the third emission area in a plan view.

12. The splicing display device as claimed in claim 10, wherein at least a portion of the first color portion overlaps with the first emission region in a plan view, and other portions of the first color portion do not overlap with the first emission region in a plan view.

13. The splicing display device as claimed in claim 10, wherein the first panel and the first portion of the shared layer form a first display device, the second panel and the second portion of the shared layer form a second display device, in the first display device and the second display device, the first sub-pixel region, the second sub-pixel region and the third sub-pixel region are adjacent to each other and separated from each other by a first separation distance, a first adjacent sub-pixel region of the first display device and a second adjacent sub-pixel region of the second display device are separated from each other by a second separation distance, the first adjacent sub-pixel region is the region closest to the second display device among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region disposed in the first display device, the second adjacent sub-pixel region is the region closest to the first display device among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region disposed in the second display device, and the first separation distance is equal to the second separation distance.

14. The splicing display device as claimed in claim 13, wherein in the first display device and the second display device, the first emitting area, the second emitting area, and the third emitting area are adjacent to each other and separated from each other by a first emitting separation distance; a first adjacent emitting area of ​​the first display device and a second adjacent emitting area of ​​the second display device are separated from each other by a second emitting separation distance; the first adjacent emitting area is the area closest to the second display device among the first emitting area, the second emitting area, and the third emitting area disposed in the first display device; the second adjacent emitting area is the area closest to the first display device among the first emitting area, the second emitting area, and the third emitting area disposed in the second display device; and the first emitting separation distance and the second emitting separation distance are different.

15. The splicing display device as described in claim 14, wherein the second transmission separation distance is greater than the second separation distance.

16. The splicing display device as claimed in claim 14, wherein when viewed from the outside, light of the first color is observed in the first sub-pixel region, light of the second color is observed in the second sub-pixel region, and light of the third color is observed in the third sub-pixel region.

17. The splicing display device as claimed in claim 14, wherein the first panel and the second panel are disposed on the same layer, the first panel and the second panel are separated from each other, a joint area is disposed between the first panel and the second panel, and the thickness of the joint area is less than the second separation distance.

18. The splicing display device as claimed in claim 5, wherein the first color portion includes a first quantum dot that converts light of the third color into light of the first color, and the second color portion includes a second quantum dot that converts light of the third color into light of the second color.

19. The splicing display device as claimed in claim 18, wherein the first display element layer includes a first light-emitting element, and the second display element layer includes a second light-emitting element, and wherein each of the first light-emitting element and the second light-emitting element emits light of the third color.

20. The splicing display device as claimed in claim 13, wherein the color of the light provided by the first adjacent sub-pixel region is different from the color of the light provided by the second adjacent sub-pixel region.

21. The splicing display device as claimed in claim 1, wherein the first display element layer includes a first light-emitting element, and the second display element layer includes a second light-emitting element, and wherein the first light-emitting element and the second light-emitting element are organic light-emitting diodes or light-emitting diodes having dimensions ranging from nanometer to micrometer.

22. A splicing display device, comprising: a first display device, comprising: a first substrate; a first display element layer disposed on the first substrate; and a first upper layer disposed on the first display element layer; and a second display device, comprising: a second substrate; a second display element layer disposed on the second substrate; and a second upper layer disposed on the second display element layer, wherein the first upper layer and the second upper layer are integral with each other, and each of the first upper layer and the second upper layer comprises: a first color portion comprising a first quantum dot; and a second color portion comprising a second quantum dot.

23. A splicing display device, comprising: a first sub-pixel region emitting light of a first color; a second sub-pixel region emitting light of a second color; a third sub-pixel region emitting light of a third color; a first panel comprising: a first substrate; and a first display element layer disposed on the first substrate and including a first light-emitting element emitting light of the third color; a second panel comprising: a second substrate; and a second display element layer disposed on the second substrate and including a second light-emitting element emitting light of the third color; and a shared layer comprising: a first region overlapping the first panel in a plan view; and a second region overlapping the second panel in a plan view, wherein the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region are defined by the shared layer.

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