Semiconductor devices and methods of manufacturing semiconductor devices

Abstract

In one example, a semiconductor device includes a substrate comprising a substrate conductor material. An electronic component has a first component terminal comprising a first component terminal conductor material and a second component terminal comprising a second component terminal conductor material. An interconnect includes an interconnect conductor material, a component end, and a substrate end. The second component terminal is attached to the substrate via a first intermetallic bond, the component end of the interconnect is attached to the first component terminal via a second intermetallic bond, and the substrate end of the interconnect is attached to the substrate via a third intermetallic bond. Other examples and related methods are also disclosed herein.

Description

[Technical Field]

[0001] This disclosure generally relates to electronic devices, and more specifically to semiconductor devices and methods of manufacturing semiconductor devices. [Previous Technology]

[0002] Previous semiconductor packaging methods and methods for forming semiconductor packages are inappropriate, for example, resulting in excessive costs, reduced reliability, relatively low performance, or excessively large package sizes. By comparing such methods with the present disclosure and referring to the drawings, those skilled in the art will understand other limitations and disadvantages of conventional and traditional methods. [Summary of the Invention]

[0003] This invention includes apparatus and associated methods relating to semiconductor packaging, as well as other features. In some instances, multiple sub-components of a semiconductor package are interconnected using direct bonding at low temperatures and low stress, without the use of solder.

[0004] In one example, a semiconductor device includes a substrate comprising a substrate conductor material. An electronic component has a first component terminal comprising a first component terminal conductor material and a second component terminal comprising a second component terminal conductor material. An interconnect includes an interconnect conductor material, a component end, and a substrate end. The second component terminal is attached to the substrate via a first intermetallic bond, the component end of the interconnect is attached to the first component terminal via a second intermetallic bond, and the substrate end of the interconnect is attached to the substrate via a third intermetallic bond.

[0005] In one example, a semiconductor device includes a substrate comprising a substrate conductor material, terminals, and pads. An electronic component includes an electronic component top side, an electronic component bottom side opposite the top side, a first component terminal including a first component terminal conductor material near the top side, and a second component terminal including a second component terminal material near the bottom side. An interconnect includes an interconnect conductor material, a component end, and a substrate end. The second component terminal is attached to the pad via a first intermetallic bond, the component end of the interconnect is attached to the first component terminal via a second intermetallic bond, and the substrate end of the interconnect is attached to the terminal via a third intermetallic bond.

[0006] In an example, the method includes a substrate conductor material and a substrate dielectric material disposed on a first conductor material. The method includes providing an electronic component comprising: a first component terminal including a first component terminal conductor material and a first component terminal dielectric material disposed on a second conductor material; and a second component terminal including a second component terminal conductor material and a second component terminal dielectric material disposed on a third conductor material. The method includes providing an interconnect comprising an interconnect conductor material, a component end, a substrate end, and an interconnect dielectric material disposed on the interconnect conductor material. The method includes attaching a second component terminal to a substrate by forming a first intermetallic bond, attaching a component end of the interconnect to a first component terminal by forming a second intermetallic bond, and attaching a substrate end of the interconnect to the substrate by forming a third intermetallic bond.

Implementation Method

[0011] The following describes various examples of providing a semiconductor device and methods of manufacturing a semiconductor device. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0012] The figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary confusion regarding the content of this disclosure. Furthermore, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in each figure may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different figures denote the same elements.

[0013] The term “or” refers to any one or more items in a list connected by “or”. As an example, “x or y” refers to any element in the three-element set {(x), (y), (x, y)}. As another example, “x, y or z” refers to any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0014] The terms “comprises / comprising” and / or “includes / including” are “open” terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0015] The terms “first,” “second,” etc., may be used herein to describe various elements, and these elements shall not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element discussed in this disclosure may be referred to as the second element.

[0016] Unless otherwise specified, the term “coupled” can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, then element A can be in direct contact with element B or indirectly connected to element B through intervening element C. Similarly, the terms “on top of” or “on” can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0017] This disclosure contains other examples. Such examples can be found in the drawings, request forms and / or the description of this disclosure.

[0018] FIG1A shows a plan view of the example electronic device 10. FIG1B shows a cross-sectional view of the example electronic device 10.

[0019] In the examples shown in Figures 1A and 1B, the electronic device 10 may include a substrate 11, an electronic component 12, an encapsulation 15, interconnects 13, and keys 141, 142, and 143. The substrate 11 may include terminals 111 and pads 112, a conductor material 115, and a dielectric 115'. The electronic component 12 may include a component body 125, component terminals 121 and 123, and a component dielectric 125'. The encapsulation 15 covers the substrate 11, the electronic component 12, and the interconnect 13. The interconnect 13 may include a conductor material 135 and a dielectric 135'.

[0020] The substrate 11, the encapsulation 15, and the interconnect 13 may be referred to as a semiconductor package, and the package protects the electronic component 12 from exposure to external components and / or the environment. The substrate 11 and the interconnect 13 provide electrical coupling between the external components and the electronic component 12.

[0021] Figures 2A, 2B, 2C, 2D, 2E, 2D, 2F, 2G and 2H show cross-sectional views of an example method for manufacturing an electronic device 10.

[0022] FIG. 2A shows a cross-sectional view of an electronic device 10 in an early stage of manufacturing. In the example shown in FIG. 2A, the substrate 11 may include terminals 111, pads 112, conductor material 115, and dielectric 115'. In some examples, the substrate 11, terminals 111, and pads 112 may be provided with dielectric 115' surrounding or coated with conductor material 115.

[0023] In some instances, substrate 11 may include or be referred to as lead frame, lead frame substrate, printed circuit board, printed circuit board, rigid substrate, flexible substrate, prepreg substrate, cored substrate, coreless substrate, molded plastic substrate, ceramic substrate, etched foil process substrate, additive process substrate, buildup substrate, pre-molded lead frame or other substrates known to those skilled in the art.

[0024] In some instances, substrate 11 may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which (a) may be formed layer-by-layer over an electronic device electrically coupled to the RDL substrate, or (b) may be formed layer-by-layer over a carrier that can be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be fabricated layer-by-layer as a wafer-level substrate on a circular wafer in a wafer-level process, and / or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive stacking process, which may include alternating stacking of one or more dielectric layers and one or more conductive layers to define a corresponding conductive redistribution pattern or trace, the conductive redistribution pattern or trace being configured to collectively (a) fan out traces outside the coverage area of ​​the electronic device, and / or (b) fan in traces within the coverage area of ​​the electronic device. The conductive pattern may be formed using a plating process, such as an electroplating process or a chemical plating process. Conductive patterns may include conductive materials, such as copper or other plated metals. The location of the conductive patterns can be formed using photolithography processes such as optical lithography and photoresist materials to form an optical lithography mask. The dielectric layer of the RDL substrate can be patterned using a photolithography process, which may involve exposing a light pattern of a desired feature, such as a via in the dielectric layer, through the optical lithography mask. Therefore, the dielectric layer can be made of a photodefinable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials can be spin-coated or otherwise coated in liquid form, rather than attached as a preform film. To allow the desired photodefinable feature to be properly formed, such photodefinable dielectric materials may omit structural reinforcing agents or may be unfilled and free of strands, braids, or other particles that could interfere with light from the photolithography process. In some instances, this filler-free characteristic of filler-free dielectric materials can reduce the thickness of the resulting dielectric layer. While the photodefinable dielectric materials described above can be organic, in other instances, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2), and / or SiON. Inorganic dielectric layers can be formed by growing inorganic dielectric layers using oxidation or nitriding processes, rather than using photodefinable organic dielectric materials. Such inorganic dielectric layers can be filler-free and do not contain strands, braids, or other dissimilar inorganic particles. In some instances, the RDL substrate can omit a permanent core structure or carrier, for example, dielectric materials including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates.

[0025] In other examples, substrate 11 may be a preformed substrate. The preformed substrate may be manufactured prior to attachment to an electronic device and may include dielectric layers located between respective conductive layers. The conductive layers may include copper and may be formed using an electroplating process. The dielectric layers may be relatively thick, non-photodefinable layers that may be attached as preformed films rather than liquids and may contain resins with fillers, such as strands, braids, and / or other inorganic particles for rigid and / or structural support. Because the dielectric layer is non-photodefinable, features such as through-holes or openings can be formed using drilling or lasers. In some examples, the dielectric layer may include prepreg material or Ajinomoto Accumulation Film (ABF). The preformed substrate may include a permanent core structure or carrier, for example, a dielectric material comprising bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other instances, the preformed substrate may be a coreless substrate that omits a permanent core structure, and dielectric and conductive layers may be formed on a sacrificial carrier, which is removed after the dielectric and conductive layers are formed and before attachment to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such preformed substrates can be formed using semi-additive or modified semi-additive processes.

[0026] In some embodiments, terminal 111 may include a substantially flat upper side, a substantially flat lower side opposite the upper side, and a lateral side located between the upper and lower sides. Terminals 111 may be configured to be substantially coplanar with each other, wherein the lateral sides of terminal 111 face but are spaced apart from the lateral side of pad 112. In some embodiments, terminal 111 may include, or be referred to as, a lead.

[0027] In some embodiments, pad 112 may include a substantially flat upper side, a substantially flat lower side opposite the upper side, and a lateral side located between the upper and lower sides. In some embodiments, adjacent ends of pad 112 and terminal 111 may be spaced apart from each other, but other portions of pad 112 and terminal 111 may initially be coupled to each other via substrate 11, for example, via lead frame connecting rods. The structure of pad 112 may be similar to that of terminal 111. In some embodiments, pad 112 may include, or be referred to as, a flag or pad.

[0028] Terminals 111 and pads 112 are defined by different portions of conductor material 115. In some instances, conductor material 115 may include a substantially flat upper side, a substantially flat lower side opposite the upper side, and a lateral side located between the upper and lower sides. Dielectric 115' may cover the upper, lower, or lateral side of conductor material 115. In some instances, conductor material 115 may include, or be referred to as, a conductive structure, conductive material, conductive layer, redistribution layer (RDL), wiring pattern, trace pattern, or circuit pattern. In some instances, conductor material 115 may include copper, aluminum, gold, or silver. Illustratively, conductor material 115 may be provided or defined in any of a variety of ways, such as by stamping, punching, bending, pressing, etching, or plating. In some instances, the thickness of conductor material 115 may be in the range of approximately 0.1 mm to 0.5 mm.

[0029] Dielectric 115' may be coated or surround the outer side of conductor material 115. For example, dielectric 115' may cover the upper, lower, or lateral side of terminal 111, and dielectric 115' may cover the upper, lower, or lateral side of pad 112. Electronic component 12 may be disposed on the upper side of dielectric 115' of substrate 11. In some instances, dielectric 115' may comprise an oxide or native oxide of conductor material 115. In some instances, dielectric 115' may comprise an inorganic dielectric or an organic dielectric. In some instances, the thickness of dielectric 115' may be at most approximately 0.1 μm.

[0030] Electronic component 12 may be disposed on the upper side of dielectric 115' of substrate 11. In some embodiments, electronic component 12 may include, or be referred to as, a die, a wafer, or a semiconductor package. In some embodiments, electronic component 12 may include, or be referred to as, a power device or a power semiconductor device, such as a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT), a bipolar transistor device, or a thyristor device. Electronic component 12 may include component body 125, component terminals 121 and 123 respectively located on the top and bottom sides of component body 125, terminal dielectrics 121' and 123', and component dielectric 125' located on the upper side of component body 125.

[0031] In some instances, the thickness of the component body 125 may be in the range of approximately 50 μm to 800 μm. The size of the component body 125 may be smaller than that of the pad 112. The component terminals 121 and terminal dielectrics 121' may be located on the upper side of the component body 125, and the component terminals 123 and terminal dielectrics 123' may be located on the lower side of the component body 125.

[0032] In some instances, component terminal 121 may include, or be referred to as, a source terminal or pad or a gate terminal or pad. For example, current can flow from the source terminal to the drain terminal (or vice versa) via a control signal provided to the gate terminal. In some instances, component terminal 121 may be a metallized structure, including Cu, Au, Ni, Al, Ag, Ti, or Pd. In some instances, component terminal 121 may be provided or coated by deposition or plating. In some instances, the thickness of component terminal 121 may be up to approximately 10 μm. The area of ​​component terminal 121 may be smaller than the area of ​​component body 125.

[0033] The terminal dielectric 121' may be located on the top side of the component terminal 121. In some embodiments, the terminal dielectric 121' may include oxides or native oxides generated by oxidation of the component terminal 121. In some embodiments, the thickness of the terminal dielectric 121' may be up to approximately 0.1 μm.

[0034] The component dielectric 125' may be located on the top side of the component body 125 or on some or all of the exposed portions of the component body 125. In some instances, the component dielectric 125' may cover the exposed top side of the component body 125. In some instances, the component dielectric 125' may include, or be referred to as, an oxide or grain passivation layer. In some instances, the component dielectric 125' may include an inorganic dielectric, such as silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or hafnium oxide. In some instances, the component dielectric 125' may be zirconium oxide in the form of a polymer suspension (e.g., PVP). In some instances, the component dielectric 125' may include polyimide, polymers, organic materials such as polyimide silicone, other silicones, elastomers, UV-curable materials, thermosetting liquid crystal polymers such as polybenzoxazole (PBO), or combinations thereof. In some instances, the component dielectric 125' can be provided by deposition, dispensing, coating, or screen printing techniques, or cured after deposition. In some instances, the thickness of the component dielectric 125' can range from approximately 0.1 μm to 10 μm.

[0035] In some embodiments, component terminal 123 may be located on the underside of component body 125. In some embodiments, component terminal 123 may include, or be referred to as, a drain terminal or pad. For example, current can flow from the source terminal to the drain terminal (or vice versa) via a control signal provided to the gate terminal. In some embodiments, component terminal 123 may be a metallized structure, including Cu, Au, Ni, Al, Ag, Ti, or Pd. In some embodiments, component terminal 123 may be provided or coated by deposition or plating. In some embodiments, the thickness of component terminal 123 may be up to approximately 10 μm. The area of ​​component terminal 123 may be substantially the same as the area of ​​the underside of component body 125.

[0036] The terminal dielectric 123' may be located on the underside of the component terminal 123. In some embodiments, the terminal dielectric 123' may include oxides or native oxides generated by oxidation of the component terminal 123. In some embodiments, the thickness of the terminal dielectric 123' may be up to approximately 0.1 μm.

[0037] Figures 2B and 2C each show a cross-sectional view of the electronic device 10 in the later stages of manufacturing. In the example shown in Figure 2B, where the electronic component 12 is located on the substrate 11, ultrasonic vibrations and pressure can be applied to the upper portion of the electronic component 12 using an ultrasonic bonding tool 20 to create bonds 143 that bond the pads 112 of the substrate 11 to the component terminals 123 of the electronic component 12. The bonding tool 20 causes the electronic component 12 to vibrate back and forth, thereby rubbing the component terminals 123 against the pads 112 of the substrate 11, as indicated by the arrows in Figure 2C. The substrate 11 and the electronic component 12 can be bonded to each other by the ultrasonic vibrations and pressure induced by the bonding tool 20. The friction or heat generated by ultrasonic bonding can remove or eliminate the terminal dielectric 123' and the substrate dielectric 115' (FIG. 2B) between the component terminal 123 and the pad 112, and can create a direct solder joint or bond 143 (FIG. 2C) between the terminal 123 and the pad 112 without the use of solder, conductive film, conductive paste, or other conductive agents therebetween. Such ultrasonic bonding can be described with reference to the enlarged illustrations and descriptions of FIG. 3A to 3D.

[0038] In some examples, the bond 143 connecting the component terminal 123 of the electronic component 12 to the pad 112 of the substrate 11 may be referred to as an interatomic bond, an intermetallic bond, a solid-state bond, or a solderless bond. In some examples, the area of ​​the bond 143 may substantially cover the area of ​​the underside of the electronic component 12. In some examples, the thickness of the bond 143 may be in the range of 0 nm to 10 nm. In some examples, the bond 143 may diffuse into or within one or both of the component terminal 123 of the electronic component 12 or the pad 112 of the substrate 11. Figure 2C shows an example in which the dielectric 115' of the substrate 11 laterally abuts the bond 143 around its perimeter after the bond 143 is formed.

[0039] FIG. 2D shows a cross-sectional view of the electronic device 10 in the late stage of manufacturing. In the examples shown in FIG. 1A and 2D, interconnects 13 may be disposed on the upper side of the electronic assembly 12 and the upper side of the terminal 111. In some examples, interconnects 13 may include or be referred to as clamps, clamping structures, conductors, conductive bridges, conductive connectors, conductive rods, or conductive interfaces. In some examples, interconnects 13 in FIG. 2D may include or represent source interconnects 13a or gate interconnects 13b in FIG. 1A. Correspondingly, component terminal 121 in FIG. 2D may include or represent a first current carrying terminal, such as source terminal 121a or a control terminal, such as gate terminal 121b of the electronic assembly 12 in FIG. 1A. In some examples, the area of ​​source interconnect 13a may be relatively larger than the size of gate interconnect 13b. Therefore, a relatively large current (e.g., source-drain current) can flow through source interconnect 13a, and a relatively small current (e.g., gate control signal) can flow through gate interconnect 13b. In some instances, component terminal 123 may include or represent a second current-carrying terminal, such as drain terminal 123.

[0040] The interconnect 13 may include a conductor material 135 and a dielectric 135' covering the conductor material 135. In some embodiments, the conductor material 135 of the interconnect 13 may be similar to the conductor material 115 of the substrate 11. In some embodiments, the fabrication or formation of the conductor material 135 of the interconnect 13 may also be similar to the fabrication or formation of the conductor material 115 of the substrate 11. In some embodiments, the interconnect 13 may be defined by etching or stamping. In some embodiments, the material of the dielectric 135' of the interconnect 13 may be similar to the dielectric 115' of the substrate 11.

[0041] In some embodiments, the conductor material 135 may include a component end 131 and a substrate end 132 connected via an interconnect bridge 133. The component end 131 may be coupled to the top side of the electronic component 12, and the substrate end 132 may be coupled to the top side of the terminal 111 of the substrate 11. In some embodiments, the height of the interconnect bridge 133 may differ from the height of the component end 131, whether it is higher or lower. Therefore, the interconnect 13 may include a tilted pin located between the interconnect bridge 133 and the component end 131. In some embodiments, the height of the interconnect bridge 133 may be relatively higher than the height of the substrate end 132. Therefore, the interconnect 13 may include a tilted pin located between the interconnect bridge 133 and the substrate end 132.

[0042] FIG. 2E shows a cross-sectional view of the electronic device 10 in the late stage of manufacturing. In the example shown in FIG. 2E, the component end 131 of the interconnect 13 is located on the upper side of the electronic component 12, and ultrasonic vibration and pressure can be applied to the component end 131 using an ultrasonic grain bonding tool 20 to create a bond 141 that bonds the component end 131 of the interconnect 13 to the component terminal 121 of the electronic component 12. In some examples, such a bond may be similar to the bond described with respect to the bond 143 between the pad 112 of the substrate 11 and the component terminal 123 of the electronic component 12 in FIG. 2B-2C.

[0043] The bonding tool 20 causes the component end 131 of the interconnect 13 to vibrate back and forth, thereby rubbing the component end 131 of the interconnect 13 against the component terminal 121 of the electronic component 12, as indicated by the arrow in FIG2E. The interconnect 13 and the electronic component 12 can be bonded to each other by the ultrasonic vibration and pressure induced by the bonding tool 20. The friction or heat caused by the ultrasonic bonding can remove or eliminate the terminal dielectric 121' and the interconnect dielectric 135' (FIG. 2D) between the component end 131 and the component terminal 121, and can create a direct solder joint or bond 141 (FIG. 2E) between the component end 131 and the component terminal 121 without the use of solder, conductive film or conductive paste or other conductive agent therebetween. Such ultrasonic bonding can be described with reference to the enlarged illustrations and descriptions of FIG3A to 3D.

[0044] In some embodiments, the bond 141 connecting the component end 131 of the interconnect 13 and the component terminal 121 of the electronic component 12 may be referred to as an interatomic bond, an intermetallic bond, a solid-state bond, or a solderless bond. In some embodiments, the area of ​​the bond 141 may substantially cover the area of ​​the component terminal 121. In some embodiments, the thickness of the bond 141 may be in the range of 0 nm to 10 nm. In some embodiments, the bond 141 may diffuse into or within one or both of the component end 131 of the interconnect 13 or the component terminal 121 of the electronic component 12.

[0045] FIG. 2F shows a cross-sectional view of the electronic device 10 in the later stages of manufacturing. In the example shown in FIG. 2F, the substrate end 132 of the interconnect 13 is located on the upper side of the terminal 111 of the substrate 11, and ultrasonic waves and pressure can be applied to the substrate end 132 using an ultrasonic die bonding tool 20 to create a bond 142 that bonds the substrate end 132 of the interconnect 13 to the terminal 111 of the substrate 11. In some examples, such a bond may be similar to the bond 143 described with respect to the bond 143 between the pad 112 of the substrate 11 and the component terminal 123 of the electronic component 12 in FIG. 2B-2C.

[0046] The bonding tool 20 causes the substrate end 131 of the interconnect 13 to vibrate back and forth, thereby rubbing the substrate end 131 of the interconnect 13 against the terminal 111 of the substrate 11, as shown by the arrow in FIG2F. The interconnect 13 and the substrate 11 can be bonded to each other by the ultrasonic vibration and pressure induced by the bonding tool 20. The friction or heat caused by the ultrasonic bonding can remove or eliminate the substrate dielectric 115' and the interconnect dielectric 135' (FIG. 2D) between the substrate end 132 and the terminal 111, and can create a direct solder joint or bond 142 (FIG. 2F) between the substrate end 132 and the terminal 111 without the use of solder, conductive film or conductive paste or other conductive agent therebetween. Such ultrasonic bonding can be described with reference to the enlarged illustrations and descriptions of FIG3A to 3D.

[0047] In some examples, the bond 142 connecting the substrate end 132 of the interconnect 13 to the terminal 111 of the substrate 11 may be referred to as an interatomic bond, an intermetallic bond, a solid-state bond, or a solderless bond. In some examples, the thickness of the bond 142 may be in the range of 0 nm to 10 nm. In some examples, the bond 142 may diffuse into or within one or both of the substrate end 132 of the interconnect 13 or the terminals 111 of the substrate 11. Figure 2G shows an example in which the dielectric 115' of the substrate 11 laterally abuts the bond 142 around the bond 142 after the bond 142 is formed.

[0048] FIG. 2G shows a cross-sectional view of the electronic device 10 in the later stages of manufacturing. In the example shown in FIG. 2G, an encapsulation 15 may be provided to cover the upper side of the substrate 11, the electronic components 12, and the interconnects 13. The bottom and lateral sides of the terminals 111 and pads 112 of the substrate 11 may remain exposed from the encapsulation 15. In some embodiments, the encapsulation 115 may extend to completely cover the upper side of the terminals 111 or pads 112 of the substrate 11.

[0049] In some instances, the encapsulant 15 may include, or be referred to as, an epoxy molding compound, epoxy molding resin, or sealant. In some instances, the encapsulant 15 may include, or be referred to as, a molding portion, a sealing portion, an encapsulating portion, a protective portion, or a body. In some instances, the encapsulant 15 may include organic resins, inorganic fillers, curing agents, catalysts, coupling agents, colorants, and / or flame retardants. In some instances, the encapsulant 15 may be provided by compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, paste printing, or film-assisted molding. For example, the thickness of the encapsulant 15 may range from approximately 0.5 mm to 3.5 mm. In some instances, a portion of the top side of the interconnect 13 may be exposed from the encapsulant 15.

[0050] FIG2H shows a cross-sectional view of the electronic device 10 in the later stages of manufacturing. In the example shown in FIG2H, the conductive coating 117 may be provided on the exposed portion of the substrate 11, for example, on the underside or lateral side of the terminals 111 or pads 112 of the substrate 11.

[0051] In some embodiments, portions of dielectric 115' may be removed from exposed portions of substrate 11 before the conductive coating 117 is applied, while portions of dielectric 115' may remain covering portions of substrate 11 encapsulated by encapsulant 15. In some embodiments, portions of dielectric 115' may remain on some exposed portions of substrate 11, such as those on the upper side of terminals 111 or pads 112. In some embodiments, dielectric 115' may be removed from exposed portions on the upper side of terminals 111 or pads 112, which may also be coated with conductive coating 117.

[0052] The material of the conductive coating 117 may include solder, solder-wetting conductor, Ag, Ti, Pd, Au, or Ni. In some instances, the conductive coating 117 may be applied by plating, whether electroplating or electroless plating. In some instances, the thickness of the conductive coating 117 may be in the range of approximately 1 μm to 30 μm.

[0053] Figures 3A, 3B, 3C and 3D show enlarged cross-sectional views of an example ultrasonic bonding method for manufacturing an example electronic device. Such views correspond to the formation of ultrasonic bonds 141, 142, 143 described throughout Figures 1-2 for electronic device 10.

[0054] In some instances, regarding the formation of the bond 143 (FIGs 2B, 2C), the element 38 having dielectric 38' may correspond to the component terminal 123 of the electronic component 12 having dielectric 123', while the element 39 having dielectric 39' may correspond to the pad 112 of the substrate 11 having substrate dielectric 115'.

[0055] In some instances, regarding the formation of the bond 141 (FIGs 2D, 2E), the element 38 having dielectric 38' may correspond to the component terminal 131 of the interconnect 13 having dielectric 135', while the element 39 having dielectric 39' may correspond to the component terminal 121 of the electronic component 12 having dielectric 121'.

[0056] In some examples, regarding the formation of the bond 142 (FIGs 2D, 2F), the element 38 having dielectric 38' may correspond to the substrate end 132 of the interconnect 13 having dielectric 135', while the element 39 having dielectric 39' may correspond to the terminal 111 of the substrate 11 having substrate dielectric 115'.

[0057] Figure 3A shows a cross-sectional view of a portion of an electronic device 10 in the early stages of ultrasonic bonding. In the example of Figure 3A, element 38 may be positioned on element 39 such that ultrasonic vibrations or pressure can be applied to element 38 against element 39. In some examples, elements 38 and 39 comprise different conductive materials containing different metals.

[0058] As seen in the enlarged view, an irregular or jagged surface may initially exist between elements 38 and 39. At the boundary between dielectric 38' and dielectric 39', some portions may be in contact with each other, while others may not. Ultrasonic vibrations and pressure may be applied to the upper portion of element 38. In some instances, the applied ultrasonic frequency may be in the range of 20 kHz to 60 kHz. In some instances, the applied pressure may be in the range of 1 N to 1000 N.

[0059] In the example shown in Figure 3B, when ultrasonic vibration and pressure are applied to element 38, the irregular surfaces of dielectric 38' and dielectric 39' can rub against each other and eventually begin to be removed or removed from element 38 and element 39 by friction. With dielectric 38' and 39' removed, the conductive materials of elements 38 and 39 come into contact with each other, and ultrasonic vibration and pressure begin to create solder joints 37' at such contact areas between elements 38 and 39.

[0060] In the example shown in Figure 3C, the applied ultrasonic vibration and pressure continue to further remove dielectrics 38' and 39', enlarge solder joints 37', and flatten the irregular surfaces between components 38 and 39.

[0061] In the example shown in FIG. 3D, bond 37 between elements 38 and 39 is completed, dielectrics 38' and 39' are removed, and solder joints 37' are merged to define bond 37 as a continuous bond. In some examples, bond 37 may correspond to any one of bonds 141, 142, 143 (FIGs 1-2). In some examples, the formation of bond 37 may cause conductive material or particles of element 38 to diffuse into element 39, or vice versa. In some examples, such bond 37 may include or be referred to as an intermetallic bond. Thus, dielectrics 38' and 39' may be removed or eliminated from the upper side of element 39 and the lower side of element 38, and elements 38 and 39 may be firmly bonded to each other by bond 37. In some examples, bond 37 may include or be referred to as a solderless bond, an interatomic bond, a solid-phase bond, a cryogenic bond, an ultrasonic bond, or a thermocompressible bond.

[0062] According to this specification, conductor material 115 may be different from the material of component terminal 123, and conductor material 135 may be different from the material of component terminal 121. Component terminals 121 and 123 may be the same or different materials. Conductor material 115 and conductor material 135 may be the same or different materials. Component terminals 121a and 121b may be the same or different materials. In some instances, the different materials comprise materials having at least one different constituent material at a level higher than industry-accepted background impurity levels.

[0063] This disclosure contains references to certain examples; however, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, the disclosed examples can be modified without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather that it encompasses all examples within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0007] [Figure 1A] shows a plan view of the example electronic device.

[0008] [Figure 1B] shows a cross-sectional view of the example electronic device.

[0009] [Figure 2A], [Figure 2B], [Figure 2C], [Figure 2D], [Figure 2E], [Figure 2F], [Figure 2G] and [Figure 2H] show cross-sectional views of an example method for manufacturing an example electronic device.

[0010] [Figure 3A], [Figure 3B], [Figure 3C] and [Figure 3D] show cross-sectional views of an example ultrasonic bonding method for manufacturing example electronic devices.

Claims

1. A semiconductor device comprising: substrate, It includes substrate conductor material; An electronic component includes a first component terminal and a second component terminal, wherein the first component terminal includes a first component terminal conductor material and the second component terminal includes a second component terminal conductor material; And an interconnect, comprising an interconnect conductor material, a component end, and a substrate end; wherein: the second component terminal is attached to the substrate by a first intermetallic bond; the component end of the interconnect is attached to the first component terminal by a second intermetallic bond; and the substrate end of the interconnect is attached to the substrate by a third intermetallic bond.

2. The semiconductor device according to claim 1, further comprising: An encapsulation covering the upper side of the electronic components, the interconnects, and the substrate; wherein a portion of the substrate is exposed from the encapsulation.

3. The semiconductor device according to claim 2, further comprising: A conductive coating is disposed on the exposed portion of the substrate.

4. The semiconductor device according to claim 1, wherein: The substrate includes a first terminal, a second terminal, and a pad; the second component terminal is attached to the pad; the substrate end of the interconnect is attached to the first terminal; the electronic component includes a third component terminal, the third component terminal including a third component terminal conductor material; the semiconductor device further includes a second interconnect, the second interconnect including a second interconnect conductor material and including a second interconnect substrate end and a second interconnect component end; the second interconnect substrate end is attached to the second terminal via a fourth intermetallic bond; and the second interconnect component end is attached to the third component terminal via a fifth intermetallic bond.

5. The semiconductor device according to claim 4, wherein: The electronic component includes a power semiconductor device; the first component terminal includes a first current-carrying terminal; the second component terminal includes a second current-carrying terminal; the third component terminal includes a control terminal; and the substrate conductor material and the second component terminal conductor material are different materials.

6. The semiconductor device according to claim 1, wherein: The first intermetallic bond, the second intermetallic bond, and the third intermetallic bond are solderless bonds.

7. A semiconductor device comprising: substrate, It includes: a substrate conductor material; a terminal; a pad; and a substrate dielectric covering the substrate conductor material; an electronic component including: a top side of the electronic component; a bottom side of the electronic component opposite to the top side of the electronic component; a first component terminal including a first component terminal conductor material adjacent to the top side of the electronic component; and a second component terminal including a second component terminal material adjacent to the bottom side of the electronic component; and an interconnect including: an interconnect conductor material; a component end; and a substrate end; wherein: the second component terminal is attached to the pad by a first intermetallic bond; the first intermetallic bond extends downward through the substrate dielectric; the component end of the interconnect is attached to the first component terminal by a second intermetallic bond; and the substrate end of the interconnect is attached to the terminal by a third intermetallic bond.

8. The semiconductor device according to claim 7, wherein: The first component terminal conductor material and the interconnect conductor material are different materials.

9. The semiconductor device according to claim 7, wherein: The substrate dielectric includes an organic dielectric; and the substrate dielectric is laterally adjacent to the first intermetallic bond around the first intermetallic bond.

10. The semiconductor device according to claim 7, wherein: The interconnect includes a clamp; and the substrate includes a lead frame.

11. The semiconductor device according to claim 7, wherein: The first intermetallic bond, the second intermetallic bond, and the third intermetallic bond are ultrasonic bonds.

12. The semiconductor device according to claim 7, further comprising: An encapsulation covering the upper side of the electronic components, the interconnects, and the substrate; wherein a portion of the terminals and the pads are exposed from the encapsulation.

13. The semiconductor device according to claim 7, wherein: The substrate includes a second terminal; the electronic component includes a third component terminal; the semiconductor device further includes a second interconnect, the second interconnect including a second interconnect conductor material and including a second interconnect substrate end and a second interconnect component end; the second interconnect substrate end is attached to the second terminal by a fourth intermetallic bond; and the second interconnect component end is attached to the third component terminal by a fifth intermetallic bond.

14. A method of manufacturing a semiconductor device, comprising: A substrate is provided, the substrate comprising a substrate conductor material and a substrate dielectric material disposed on the substrate conductor material; An electronic component is provided, the electronic component comprising: a first component terminal including: a first component terminal conductor material; and a first component terminal dielectric material disposed on the first component terminal conductor material; and a second component terminal including: a second component terminal conductor material; and a second component terminal dielectric material disposed on the second component terminal conductor material; an interconnect is provided, the interconnect including: an interconnect conductor material; a component end; a substrate end; and an interconnect dielectric material disposed on the interconnect conductor material; attaching the second component terminal to the substrate by forming a first intermetallic bond; attaching the component end of the interconnect to the first component terminal by forming a second intermetallic bond; and attaching the substrate end of the interconnect to the substrate by forming a third intermetallic bond, wherein: attaching the second component terminal to the substrate includes using ultrasonic vibration applied to the electronic component and the substrate without first removing the substrate dielectric material; using the ultrasonic vibration includes: using the ultrasonic vibration to remove the substrate dielectric material and the second component terminal dielectric material; A solder joint is formed between the substrate conductor material and the second component terminal conductor material; and the solder joint is merged to form the first intermetallic bond as a continuous bond; and after the second component terminal is attached, the substrate dielectric is adjacent to the edge of the first intermetallic bond.

15. The method according to request item 14, wherein: Attaching the second component terminal to the substrate includes using an ultrasonic vibration frequency in the range of 20 kHz to 60 kHz.

16. The method according to request item 15, wherein: Attaching the second component terminal to the substrate includes applying downward pressure to the electronic component while using the ultrasonic vibration; and applying the downward pressure includes applying the downward pressure in the range of 1N to 1000N.

17. The method according to claim 14, further comprising: An encapsulation is provided that covers the upper side of the electronic components, the interconnects, and the substrate.

18. The method according to request item 14, wherein: Providing the substrate includes providing a first terminal, a second terminal, and a pad; attaching the second component terminal to the substrate includes attaching the second component terminal to the pad; attaching the substrate end of the interconnect to the substrate includes attaching the substrate end of the interconnect to the first terminal; And providing the electronic component includes providing the electronic component with a third component terminal comprising a third component terminal conductor material; The method further includes: providing a second interconnect, the second interconnect including a second interconnect conductor material and including a second interconnect substrate end and a second interconnect assembly end; attaching the second interconnect assembly end to the third assembly terminal by forming a fourth intermetallic bond; and attaching the second interconnect substrate end to the second terminal by forming a fifth intermetallic bond.

19. The method according to request item 18, wherein: Providing the interconnect includes providing a first clamp; Providing the second interconnect includes providing a second clamp; The electronic component includes: providing a power semiconductor device; providing a first component terminal including a first current-carrying terminal; providing a second component terminal including a second current-carrying terminal; and providing the third component terminal including a control terminal.

20. The method according to request item 14, wherein: The first intermetallic bond, the second intermetallic bond, and the third intermetallic bond are solderless; and providing the substrate dielectric includes providing an organic dielectric.

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