Image display method and image display device

Abstract

The purpose of this invention is to provide an image display method and an image display device that can improve the quality of the displayed image. In the image display method of the present invention, the voltage applied to each pixel of the liquid crystal panel is sequentially switched along the first direction to a value corresponding to the k-th input image, according to each second region. The process of sequentially controlling the output of the light source of each light-emitting region of the backlight along the first direction, according to each first region, is repeated during the period when the voltage applied to each pixel is switched to a value corresponding to the k-th input image. After the process of switching the voltage applied to each pixel located directly above to a value corresponding to the k-th input image begins, the output of the light source of each light-emitting region included in each first region is switched to an output corresponding to the k-th input image.

Description

Technical Field

[0001] The embodiment relates to an image display method and an image display device. Prior Technology

[0002] Previously, an image display device was known, comprising: a backlight having a plurality of light-emitting areas arranged in a matrix, with light sources disposed in each light-emitting area; and a liquid crystal panel disposed above the backlight, having a plurality of pixels. Using this image display device, the brightness of each light-emitting area can be individually set according to the image to be displayed on the liquid crystal panel, and the grayscale of each pixel on the liquid crystal panel can be set according to the brightness of each light-emitting area. This improves the contrast of the image displayed on the liquid crystal panel. This technique is called "local dimming." [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2008-145966 Summary of the Invention

[0004] [The problem the invention aims to solve]

[0005] The purpose of this embodiment is to provide an image display method and an image display device that can improve the quality of the displayed image. [Technical means to solve the problem]

[0006] An embodiment of an image display method includes the following steps: switching the voltage applied to each pixel and the output of the light source from each light-emitting region based on each of a plurality of input images sequentially input to a control unit; the control unit comprises a backlight having a plurality of light-emitting regions arranged in a matrix in a first direction and a second direction intersecting the first direction, and a control unit of a liquid crystal panel disposed on the backlight having a plurality of pixels arranged in a matrix in the first and second directions. The backlight is divided into a plurality of first regions arranged in the first direction. Each first region includes a plurality of light-emitting regions. The liquid crystal panel is divided into a plurality of second regions arranged in the first direction. Each second region includes a plurality of pixels. In the step of switching the voltage applied to each pixel and the output of the light source of each light-emitting region according to the kth input image among the plurality of input images, the voltage applied to each pixel is sequentially switched to a value corresponding to the kth input image along the first direction in each of the second regions, and the output of the light source of each light-emitting region is sequentially controlled along the first direction in each of the first regions. This process is repeated during the period when the voltage applied to each pixel is switched to a value corresponding to the kth input image. After the process of switching the voltage applied to each pixel located directly above to a value corresponding to the kth input image begins in each of the first regions, the output of the light source of each light-emitting region included in each of the first regions is switched to an output corresponding to the kth input image.

[0007] An image display device according to one embodiment includes: a backlight having a plurality of light-emitting regions arranged in a matrix along a first direction and a second direction intersecting the first direction; a liquid crystal panel disposed on the backlight having a plurality of pixels arranged in a matrix along the first direction and the second direction; and a control unit that can switch the voltage applied to each of the pixels and the light output of each of the light-emitting regions according to each of a plurality of sequentially input images. The backlight is divided into a plurality of first regions arranged in the first direction. Each of the first regions includes a plurality of the light-emitting regions. The liquid crystal panel is divided into a plurality of second regions arranged in the first direction. Each of the second regions includes a plurality of the pixels. The control unit sequentially switches the voltage applied to each of the pixels along the first direction according to each of the second regions, based on the kth input image among the plurality of input images, to a value corresponding to the kth input image. During the period when the control unit switches the voltage applied to each pixel to a value corresponding to the k-th input image, it repeatedly performs the process of sequentially controlling the output of the light source of each light-emitting region along the first direction in each of the first regions. After the control unit starts the process of switching the voltage applied to each pixel located directly above to a value corresponding to the k-th input image in each of the first regions, it switches the output of the light source of each light-emitting region included in each of the first regions to an output corresponding to the k-th input image. [Effects of the Invention]

[0008] Depending on the implementation, an image display method and an image display device may be provided that can improve the quality of the displayed image. Simple Explanation of the Diagram

[0009] Figure 1 is an exploded perspective view of the image display device in the first embodiment. Figure 2 is a top view showing the planar light source of the backlight of the image display device in the first embodiment. Figure 3 is a cross-sectional view along line III-III of Figure 2. Figure 4 is a top view of the liquid crystal panel of the image display device according to the first embodiment. Figure 5 is a block diagram showing the image display device of the first embodiment. Figure 6A is a schematic diagram showing the relationship between the pixels of the input image, the light-emitting area of ​​the backlight, and the pixels of the liquid crystal panel in the first embodiment. Figure 6B is a schematic diagram showing the area of ​​the backlight in the first embodiment, which simultaneously controls the output. Figure 6C is a schematic diagram showing the area where grayscale is controlled in the liquid crystal panel of the first embodiment. Figure 7 is a schematic diagram illustrating the method for creating brightness setting data. Figure 8 is a schematic diagram showing the method of creating grayscale setting data. Figure 9A is a schematic diagram showing the time variation of the synchronization signal in the first embodiment. Figure 9B is a schematic diagram showing the time-varying potential of pixels in the upper region of the liquid crystal panel belonging to the first embodiment. Figure 9C is a schematic diagram showing the time-varying potential of a pixel in the central region of a liquid crystal panel belonging to the first embodiment. Figure 9D is a schematic diagram showing the time-varying potential of a pixel in the lower region of the liquid crystal panel belonging to the first embodiment. Figure 9E shows a schematic diagram illustrating the time variation of the sub-synchronization signal in the first implementation configuration. Figure 9F is a schematic diagram showing the timing of the output of the light source in the upper region of the backlight subordinate to the first embodiment. Figure 9G is a schematic diagram showing the timing of the output of the light source in the central region of the backlight belonging to the first embodiment. Figure 9H is a schematic diagram showing the timing of the output of the light source in the lower region of the backlight subordinate to the first embodiment. Figure 10A is a schematic diagram showing the image displayed on the LCD panel during the period from time t1 to time t2 of Figure 9A. Figure 10B is a schematic diagram showing the image displayed on the LCD panel during the period from time t3 to time t4 in Figure 9A. Figure 10C is a schematic diagram showing the image displayed on the LCD panel during the period from time t5 to time t6 of Figure 9A. Figure 11A is a top view showing an example of a variation of a planar light source. Figure 11B is a cross-sectional view of line XIB-XIB in Figure 11A. Figure 12A is a schematic diagram showing the area of ​​the backlight in the second embodiment, which simultaneously controls the output. Figure 12B is a schematic diagram showing the area where grayscale is controlled simultaneously in the liquid crystal panel of the second embodiment. Figure 13A is a schematic diagram showing the time variation of the synchronization signal in the second embodiment. Figure 13B is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z1 of Figure 12B. Figure 13C is a schematic diagram showing the temporal variation of the potential of pixels belonging to region 220z2 of Figure 12B. Figure 13D is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z3 of Figure 12B. Figure 13E is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z4 of Figure 12B. Figure 13F is a schematic diagram showing the time variation of the sub-synchronization signal in the second implementation. Figure 13G is a timing diagram of the output of the light source that is subordinate to region 210z1 in Figure 12A. Figure 13H is a timing diagram showing the output of the light source that is subordinate to region 210z2 in Figure 12A. Figure 13I is a timing diagram showing the output of the light source controlled by region 210z3 in Figure 12A. Figure 13J is a timing diagram showing the output of the light source controlled by region 210z4 of Figure 12A. Figure 14A is a schematic diagram showing the time variation of the synchronization signal in the third implementation. Figure 14B is a schematic diagram showing the temporal variation of the potential of the pixel belonging to region 220z1 of the third embodiment. Figure 14C is a schematic diagram showing the temporal variation of the potential of the pixel in region 220z2 belonging to the third embodiment. Figure 14D is a schematic diagram showing the temporal variation of the potential of the pixel in region 220z3 belonging to the third embodiment. Figure 14E is a schematic diagram showing the temporal variation of the potential of the pixels in region 220z4 belonging to the third embodiment. Figure 14F is a schematic diagram showing the time variation of the sub-synchronization signal in the third implementation. Figure 14G shows a timing diagram of the output of the light source in region 210z1, which is subordinate to the third implementation form, as a display control. Figure 14H is a schematic diagram showing the timing of the output of the light source in region 210z2, which is subordinate to the third implementation. Figure 14I is a schematic diagram showing the timing of the output of the light source in region 210z3, which is subordinate to the third embodiment. Figure 14J is a schematic diagram showing the timing of the output of the light source in region 210z4, which is subordinate to the third embodiment. Figure 15 is a schematic diagram showing the (k-1)th input image and the kth input image of the third embodiment. Figure 16A is a schematic diagram showing the image displayed on the LCD panel during the period from time t0 to time t1 in Figure 14A. Figure 16B is a schematic diagram showing the image displayed on the LCD panel during the period from time t1 to time t2 in Figure 14A. Figure 16C is a schematic diagram showing the image displayed on the LCD panel during the period from time t2 to time t3 in Figure 14A. Figure 16D is a schematic diagram showing the image displayed on the LCD panel during the period from time t3 to time t4 in Figure 14A. Figure 17A is a schematic diagram showing the timing of the output of the light source in region 210z1, which is subordinate to the fourth embodiment. Figure 17B is a schematic diagram showing the timing of the output of the light source in region 210z2, which is subordinate to the fourth implementation. Figure 17C is a schematic diagram showing the timing of the output of the light source in region 210z3, which is subordinate to the fourth implementation. Figure 17D is a schematic diagram showing the timing of the output of the light source in region 210z4, which is subordinate to the fourth implementation. Figure 18 is a circuit diagram showing a portion of the image display device in the fifth embodiment. Figure 19A is a schematic diagram of the timing of region 210z1 in the fifth implementation mode of the control system. Figure 19B is a schematic diagram showing the timing of region 210z2 in the fifth implementation mode of the control. Figure 19C shows a timing diagram of region 210z3 in the fifth implementation mode of the control system. Figure 19D is a schematic diagram of the timing of region 210z4 in the fifth implementation mode of the display control. Figure 20 is a circuit diagram showing a portion of the image display device according to the sixth embodiment. Figure 21 shows a circuit diagram of the switching signal generation unit in the sixth embodiment. Figure 22A is a schematic diagram showing the timing of the output of the light source in region 210z1, which is subordinate to the sixth embodiment. Figure 22B is a schematic diagram showing the timing of the output of the light source in region 210z2, which is subordinate to the sixth embodiment. Figure 22C is a schematic diagram showing the timing of the output of the light source in region 210z3, which is subordinate to the sixth embodiment. Figure 22D is a schematic diagram showing the timing of the output of the light source in region 210z4, which is subordinate to the sixth implementation. Figure 23A is a schematic diagram of the timing of region 210z1 in the sixth implementation mode of the display control. Figure 23B is a schematic diagram of the timing of region 210z2 in the sixth implementation mode of the display control. Figure 23C is a schematic diagram of the timing of region 210z3 in the sixth implementation mode of the display control. Figure 23D is a schematic diagram of the timing of region 210z4 in the sixth implementation mode of the display control. Figure 24 is a circuit diagram showing the switching signal generation unit of the first variation of the sixth embodiment. Figure 25A is a schematic diagram showing the timing pattern of region 210z1 in the first variation of the sixth implementation mode of the control. Figure 25B is a schematic diagram showing the timing pattern of region 210z2 in the first variation of the sixth implementation mode of the control. Figure 25C is a time sequence diagram of region 210z3 in the first variation of the sixth implementation mode of the control. Figure 25D is a time sequence diagram of region 210z4 in the first variation of the sixth implementation mode of the display control. Figure 26A is a schematic diagram showing the timing pattern of region 210z1 in the second variation of the sixth implementation mode of the control. Figure 26B is a schematic diagram showing the timing of region 210z2 in the second variation of the sixth implementation mode of control. Figure 26C shows a timing pattern diagram of region 210z3 in the second variation of the sixth implementation mode of the control. Figure 26D is a time sequence diagram of region 210z4 in the second variation of the sixth implementation mode of the control. Figure 27A is a schematic diagram showing the timing pattern of region 210z1 in the third variation of the sixth implementation mode of the control. Figure 27B is a time sequence diagram of region 210z2 in the third variation of the sixth implementation mode of the control. Figure 27C is a time sequence diagram of region 210z3 in the third variation of the sixth implementation mode of the control. Figure 27D is a time sequence diagram of region 210z4 in the third variation of the sixth implementation mode of the control. Figure 28A is a schematic diagram showing the timing pattern of region 210z1 in the fourth variation of the sixth implementation mode of the control. Figure 28B is a schematic diagram showing the timing pattern of region 210z2 in the fourth variation of the sixth implementation mode of the control. Figure 28C is a time sequence diagram of region 210z3 in the fourth variation of the sixth implementation mode of the control. Figure 28D is a time sequence diagram of region 210z4 in the fourth variation of the sixth implementation mode of the control. Implementation

[0010] The following description, with reference to the drawings, explains various embodiments and variations. Note that the drawings are conceptual or model-based and may not necessarily reflect the actual relationship between the thickness and width of the parts, or the proportions between the parts. Furthermore, even when representing the same parts, the drawings may depict different dimensions or proportions. Moreover, in this specification and the drawings, there are instances where the same symbols are used to describe elements found in previously presented drawings, and detailed explanations are appropriately omitted, or sectional views showing only the cut surface are used as sectional views.

[0011] Furthermore, for ease of understanding, the following explanation uses an XYZ orthogonal coordinate system to illustrate the configuration and structure of each part. The X-axis, Y-axis, and Z-axis are orthogonal to each other. The direction extending from the X-axis is designated as the "X direction," the direction extending from the Y-axis as the "Y direction," and the direction extending from the Z-axis as the "Z direction." Although the direction from the backlight towards the LCD panel in the Z-direction is designated as upward, and its opposite as downward, these directions are unrelated to the direction of gravity. For ease of understanding, in each diagram, one of the directions extending from the X-axis is called the "+X direction," and its opposite is called the "-X direction." Similarly, one of the directions extending from the Y-axis is called the "+Y direction," and its opposite is called the "-Y direction."

[0012] <First Implementation Form> First, the first implementation form will be explained. Figure 1 is an exploded perspective view of the image display device of this embodiment. The image display device 100 of this embodiment is a liquid crystal module (LCM) used in the display of an external device (not shown), such as a television, personal computer, or game console. The image display device 100 includes a backlight 110, a liquid crystal panel 120, and a control unit 130. The control unit 130 includes a timing controller 140, a backlight driver 150, and a liquid crystal panel driver 160. The various parts of the image display device 100 will be described below. Furthermore, in FIG1, for ease of understanding, the components are shown connected by solid lines to illustrate the electrical connection between them.

[0013] (Backlight) The backlight 110 can be driven by local dimming. The backlight 110 has a planar light source 111 and an optical component 112 disposed on the planar light source 111.

[0014] The optical component 112 is, for example, a thin sheet or plate with light adjustment functions such as light diffusion. In this embodiment, the number of optical components 112 used in the backlight 110 is one. However, the number of optical components used in the backlight may be two or more.

[0015] Figure 2 is a top view of the planar light source of the backlight of the image display device of this embodiment. Figure 3 is a cross-sectional view along line III-III of Figure 2. As shown in Figures 2 and 3, the planar light source 111 in this embodiment includes a substrate 113, a light-reflective sheet 114, a light guide member 115, a plurality of light sources 116, a light-transmitting member 117, a first light adjustment member 118, and a light-reflecting member 119.

[0016] The substrate 113 is a wiring substrate having an insulating member and a plurality of wirings disposed on the insulating member. The shape of the substrate 113 in top view is shown in Figure 2, and it is generally rectangular. However, the shape of the substrate is not limited to the shape described above. The upper and lower surfaces of the substrate 113 are flat surfaces, which are generally parallel to the X and Y directions (XY plane).

[0017] As shown in FIG. 3, a light-reflective sheet 114 is disposed on a substrate 113. The light-reflective sheet 114 has, for example, a first adhesive layer 114a, a light-reflective layer 114b disposed on the first adhesive layer 114a, and a second adhesive layer 114c disposed on the light-reflective layer 114b. The light-reflective sheet 114 is attached to the substrate 113 via the first adhesive layer 114a. As the light-reflective layer 114b, a resin containing, for example, a plurality of air bubbles can be used. Furthermore, the first adhesive layer 114a and the second adhesive layer 114c may contain, for example, a light-diffusing agent. In this case, the concentration of the light-diffusing agent contained in the second adhesive layer 114c is preferably lower than the concentration of the light-diffusing agent contained in the first adhesive layer 114a, which can reduce the brightness unevenness of the light-emitting region 111s, which will be described later. As a light diffusing agent, it can be appropriately selected from, for example, the light diffusing agents used in the second light adjustment member 116c and the third light adjustment member 116d, which will be described later.

[0018] A light guide member 115 is disposed on a light-reflective sheet 114. The light guide member 115 is attached to the light-reflective sheet 114 via a second adhesive layer 114c. The light guide member 115 is plate-shaped. However, the shape of the light guide member is not limited to the above. The thickness of the light guide member 115 is preferably 200 μm or more and 800 μm or less. The light guide member 115 can be composed of a single layer or a multilayer laminate.

[0019] Materials used as light guide components 115 include, for example, thermoplastic resins such as acrylic acid, polycarbonate, cyclic polyolefins, polyethylene terephthalate or polyester, thermosetting resins such as epoxy or silicone, or glass.

[0020] A plurality of light source configuration portions 115a are provided on the light guide member 115. The plurality of light source configuration portions 115a are arranged in a matrix in top view as shown in FIG2. Each light source configuration portion 115a, as shown in FIG3, is a through hole through which the light guide member 115 passes in the Z direction. However, the light source configuration portion may also be a recess provided on the lower surface of the light guide member.

[0021] Each light source 116 is disposed within a light source placement section 115a. Therefore, the plurality of light sources 116 are also arranged in a matrix as shown in FIG2. However, it is possible to embed the light source into the light guide member without providing a light source placement section. Furthermore, for planar light sources, it is not necessary to provide a light guide member. For example, for planar light sources, it is also possible to not provide a light guide member, and the planar light source is simply a plurality of light sources arranged in a matrix on the substrate.

[0022] As shown in Figure 3, each light source 116 is a light-emitting device that combines a wavelength conversion component 116b with a light-emitting element 116a. Each light source 116 further has a second light adjustment component 116c and a third light adjustment component 116d. However, each light source may also be a single light-emitting element rather than a light-emitting device.

[0023] The light-emitting element 116a is, for example, an LED (Light Emitting Diode). The light-emitting element 116a includes a semiconductor laminate 116e and two electrodes 116f and 116g that are electrically connected to the semiconductor laminate 116e and the substrate 113. A through-hole is provided in the light-reflective sheet 114, located directly below each electrode 116f and 116g. A conductive member 113m that is electrically connected to the wiring of each electrode 116f and 116g and the substrate 113 is disposed within this through-hole.

[0024] The wavelength conversion member 116b includes: a light-transmitting member 116h covering the upper surface and side surfaces of the semiconductor multilayer 116e; and a wavelength conversion material 116i disposed in the light-transmitting member 116h, which converts the wavelength of light emitted from the semiconductor multilayer 116e into different wavelengths. The wavelength conversion material 116i is, for example, a phosphor.

[0025] In this embodiment, the light-emitting element 116a emits blue light. On the other hand, the wavelength conversion member 116b includes a phosphor that emits red light and a phosphor that emits green light. Hereinafter, the phosphor that emits red light will be referred to as the "red phosphor", and the phosphor that emits green light will be referred to as the "green phosphor". Examples of the red phosphor include a CASN-based phosphor (e.g., CaAlSiN 3:Eu), a KSF-based phosphor (e.g., K 2SiF 6:Mn), a KSAF-based phosphor (e.g., K 2[Si pAl qMn rF s](0.9≦p+q+r≦1.1, 0<q≦0.1, 0<r≦0.2, 5.9≦s≦6.1)), or a quantum dot phosphor (e.g., Ag pCu 1-pIn qGa 1-qS 2(0<p≦1, 0<q≦1)). Further, examples of the green phosphor include a phosphor having a perovskite structure (e.g., CsPb(F,Cl,Br,I) 3), a β-sialon-based phosphor (e.g., (Si,Al) 3(O,N) 4:Eu), a LAG-based phosphor (e.g., Lu 3(Al,Ga) 5O 12:Ce), or a quantum dot phosphor (e.g., AgIn pGa 1-pS 2(0<p≦1)). The backlight 110 can emit white light, which is a mixed color light of the blue light emitted by the light-emitting element 116a, the red light, and the green light emitted by the wavelength conversion member 116b.

[0026] However, the wavelength conversion member 116b may also replace the light-transmitting member that does not contain a phosphor. In this case or when the light source is a single light-emitting element as described above, for example, by disposing a phosphor sheet containing a red phosphor and a green phosphor on the planar light source, or by disposing a phosphor sheet containing a red phosphor and a phosphor sheet containing a green phosphor on the planar light source, the same white light can be obtained.

[0027] The second light adjustment member 116c covers the upper surface of the wavelength conversion member 116b. The second light adjustment member 116c can control the amount or the emission direction of the light emitted from the upper surface of the wavelength conversion member 116b.

[0028] The third light adjustment member 116d covers the lower surface of the light-emitting element 116a and the lower surface of the wavelength conversion member 116b in such a manner that the lower surfaces of the electrodes 116f and 116g are exposed. The third light adjustment member 116d can control the light reflected by the reflecting surface toward the lower surface of the wavelength conversion member 116b and emitted from the upper surface and the side surfaces of the wavelength conversion member 116b.

[0029] The second light-adjusting member 116c and the third light-adjusting member 116d can be constructed from a light-transmitting resin and a light-diffusing agent contained in the light-transmitting resin, respectively. Examples of light-transmitting resins include silicone resin, epoxy resin, or acrylic resin. Examples of light-diffusing agents include particles of titanium oxide, silicon oxide, aluminum oxide, zinc oxide, magnesium oxide, zirconium oxide, yttrium oxide, calcium fluoride, magnesium fluoride, niobium pentoxide, barium titanate, tantalum pentoxide, barium sulfate, or glass. Furthermore, the second light-adjusting member 116c can also be constructed using a metal component such as aluminum or silver, so that the brightness directly above the light source 116 is not too high.

[0030] A light-transmitting member 117 is disposed within the light source configuration section 115a. The light-transmitting member 117 covers the light source 116.

[0031] A first light adjustment member 118 is disposed on the light-transmitting member 117. The first light adjustment member 118 reflects a portion of the light incident from the light-transmitting member 117 and allows the remaining portion to pass through, ensuring that the brightness directly above the light source 116 is not too high. Furthermore, the first light adjustment member 118 is preferably disposed such that it covers the interface between the light-transmitting member 117 and the light guide member 115 when viewed from above, which can suppress the increase in brightness caused by light scattering from the light source 116 at the interface between the light-transmitting member 117 and the light guide member 115. The first light adjustment member 118 can be the same as the second light adjustment member 116c or the third light adjustment member 116d.

[0032] Furthermore, as shown in Figures 2 and 3, a zoning groove 115b is provided on the light guide member 115 in a top view, surrounding each light source arrangement portion 115a. The zoning groove 115b extends in a grid-like manner in the X and Y directions. The zoning groove 115b penetrates the light guide member 115 in the Z direction. However, the zoning groove 115b may be a recess provided on the upper or lower surface of the light guide member 115. Alternatively, the zoning groove 115b may not be provided on the light guide member 115.

[0033] A light-reflecting member 119 is disposed within the zoning groove 115b. The light-reflecting member 119 may be, for example, the same member as the second light-adjusting member 116c or the third light-adjusting member 116d. The light-reflecting member 119 covers a portion of the side surface of the zoning groove 115b in a layered manner. The light-reflecting member 119 may zonify the light from the light source 116 in each light-emitting region 111s, as described later, thereby covering the light-reflective sheet 114 exposed within the zoning groove 115b, particularly extending to the upper surface of the second adhesive layer 114c. However, the light-reflecting member 119 may be disposed integrally within the zoning groove 115b. Alternatively, the light-reflecting member 119 may not be disposed within the zoning groove 115b.

[0034] The outputs of the plurality of light sources 116 can be individually controlled by a driver 150 for the backlight. Here, "controllable output" means that it can be switched on and off, and the brightness of the on state can be adjusted. Hereinafter, the areas of the planar light source 111, which are distinguished by the areas of each light source 116 containing individual control outputs, will be referred to as "light-emitting areas 111s". The light-emitting areas 111s correspond to the smallest areas of the planar light source 111 whose brightness can be controlled by local dimming.

[0035] In this embodiment, each luminescent region 111s, like the zoning trench 115b, corresponds to a region in the case where the planar light source 111 is divided into grid-like areas. Therefore, the shape of each luminescent region 111s is rectangular, as shown in Figure 2. Furthermore, one light source 116 is disposed within each luminescent region 111s. However, multiple light source groups can also be arranged in a matrix configuration within the planar light source, and the output of each light source group can be controlled. In this case, one light source group, i.e., multiple light sources, is disposed within one luminescent region.

[0036] A plurality of luminescent regions 111s are arranged in a matrix shape when viewed from above. Hereinafter, in the matrix structure of the plurality of luminescent regions 111s, the matrix elements of the luminescent regions 111s arranged side-by-side in the X direction are referred to as "columns," and the matrix elements of the luminescent regions 111s arranged side-by-side in the Y direction are referred to as "rows." The column located on the +Y side (left side of Figure 2) is designated as "column 1," and the column located on the -Y side (right side of Figure 2) is designated as "final column." Similarly, the row located on the -X side (bottom of Figure 2) is designated as "row 1," and the row located on the +X side (top of Figure 2) is designated as "final row." The same applies to the matrix-shaped data such as the input image 910, which will be described later. The plurality of luminescent regions 111s are arranged in N1 columns and M1 rows. Here, N1 and M1 are arbitrary integers. Figure 2 shows an example where N1 is 9 and M1 is 16.

[0037] (LCD panel) Figure 4 is a top view of the liquid crystal panel of the image display device according to this embodiment. A liquid crystal panel 120 is disposed on a backlight 110. The shape of the liquid crystal panel 120 when viewed from above is approximately rectangular. However, the shape of the liquid crystal panel is not limited to the above. The liquid crystal panel 120 has a plurality of pixels 120p arranged in a matrix. In Figure 4, an area surrounded by a thin two-dot chain line corresponds to one pixel 120p.

[0038] In this embodiment, the liquid crystal panel 120 can display color images. Therefore, one pixel 120p includes three sub-pixels 120sp, such as a sub-pixel that transmits blue light, green light, and red light in white light emitted from the backlight 110. The light transmittance of each sub-pixel 120sp can be individually controlled by the driver 160 for the liquid crystal panel. This allows for individual control of the grayscale of each sub-pixel 120sp.

[0039] A plurality of pixels 120p are arranged in N2 columns and M2 rows. Here, N2 and M2 are arbitrary integers, and N2>N1, M2>M1. From a top view, a plurality of pixels 120p are configured within each luminous area 111s. Furthermore, although Figure 4 shows an example of 4 pixels 120p configured within each luminous area 111s from a top view, the number of pixels on the liquid crystal panel configured within each luminous area can be 3 or less, or 5 or more.

[0040] Figure 5 is a block diagram showing the image display device of this embodiment. Figure 6A is a schematic diagram showing the relationship between the pixels of the input image, the light-emitting area of ​​the backlight, and the pixels of the liquid crystal panel in this embodiment. Figure 6B is a schematic diagram showing the area of ​​the backlight in this embodiment that controls the output. Figure 6C is a schematic diagram showing the area in the liquid crystal panel of this embodiment that simultaneously controls the grayscale. Figure 7 is a schematic diagram illustrating the method for creating brightness setting data. Figure 8 is a schematic diagram showing the method of creating grayscale setting data. Figure 9A is a schematic diagram showing the time variation of the synchronization signal in this embodiment. Figure 9B is a schematic diagram showing the time-varying potential of pixels in the upper region of the liquid crystal panel belonging to this embodiment. Figure 9C is a schematic diagram showing the time-varying potential of a pixel in the central region of a liquid crystal panel belonging to this embodiment. Figure 9D is a schematic diagram showing the time-varying potential of pixels in the lower region of the liquid crystal panel belonging to this embodiment. Figure 9E is a schematic diagram showing the time variation of the sub-synchronization signal in this embodiment. Figure 9F is a schematic diagram showing the timing of the output of the light source in the upper region of the backlight subordinate to this embodiment. Figure 9G is a schematic diagram showing the timing of the output of the light source in the central region of the backlight subordinate to this embodiment. Figure 9H is a schematic diagram showing the timing of the output of the light source in the lower region of the backlight subordinate to this embodiment.

[0041] (Timing Controller) The timing controller 140 is connected to an external machine. Also, as shown in Figure 5, the timing controller 140 is connected to the backlight driver 150 and the LCD panel driver 160.

[0042] The timing controller 140 includes an input unit 141, a brightness setting data generation unit 142, a grayscale setting data generation unit 143, a memory unit 144, a sub-synchronization signal generation unit 145, a control signal generation unit 146, and an output unit 147.

[0043] The input unit 141 is configured via an input interface, for example, connected to an external machine. The input unit 141 receives inputs of a plurality of input images 910 and synchronization signals 920 from the external machine.

[0044] As shown in Figure 6A, each input image 910 has a plurality of pixels 910p arranged in a matrix. Hereinafter, in order to easily understand the relationship with the various components of the image display device 100, the arrangement direction of the components in the matrix arrangement of the components such as pixels 910p, as in the input image 910, is represented by an XY orthogonal coordinate system.

[0045] Furthermore, the following describes an example of the correspondence between a pixel 910p of the input image 910 and a pixel 120p of the liquid crystal panel 120. That is, a plurality of pixels 910p are arranged in N2 columns and M2 rows. In the input image 910, the image area 910a corresponding to a light-emitting area 111s of the backlight 110 contains 4 pixels 910p. However, the correspondence between the pixels of the input image and the pixels of the liquid crystal panel may not be one-to-one. Furthermore, the number of pixels of the input image corresponding to each light-emitting area may be 3 or less, or 5 or more.

[0046] Gray levels are set for each pixel 910p. The input image 910 is a color image in this embodiment. Therefore, for each pixel 910p, a gray level Gb for blue, a gray level Gg for green, and a gray level Gr for red are set. Each gray level Gb, Gg, and Gr is a number between 0 and 255 when represented by, for example, 8 bits.

[0047] The synchronization signal 920 is a signal that controls the timing of switching the input image 910 displayed on the LCD panel 120. As shown in Figure 9A, the synchronization signal 920 is a pulse-shaped signal, such as a vertical synchronization signal.

[0048] As shown in Figure 7, the brightness setting data production unit 142 uses each input image 910 to produce brightness setting data D1 that determines the brightness setting values ​​of each light source 116 of the backlight 110.

[0049] Specifically, the brightness setting data production unit 142 extracts the maximum grayscale value Gmax(i,j) of a plurality of pixels 910p within the image region 910a corresponding to the luminous region 111s located in the i-th column and j-th row from the input image 910. Here, i is an integer greater than or equal to N1, and j is an integer greater than or equal to M1. The brightness setting data production unit 142 converts the extracted maximum grayscale value Gmax(i,j) into a brightness e1(i,j). The brightness setting data production unit 142 sets this brightness e1(i,j) to the value of the requirement located in the i-th column and j-th row of the brightness setting data D1. The brightness setting data production unit 142 performs this processing on all luminous regions 111s.

[0050] The brightness setting data D1 obtained in this way is a matrix of data with N1 columns and M1 rows. Furthermore, the value of the requirement of the brightness setting data D1 located in the i-th column and j-th row is the brightness setting value of the luminous area 111s located in the i-th column and j-th row. However, the method for producing the brightness setting data is not limited to the above.

[0051] As shown in Figure 8, the grayscale setting data production unit 143 uses brightness setting data D1, brightness profile D3, and each input image 910 to produce grayscale setting data D2, which determines the grayscale setting values ​​of each pixel 120p of the LCD panel 120. Brightness profile D3 displays the brightness distribution at each position on the XY plane when the light source 116 of a light-emitting area 111s is lit. In Figure 8, "ON" indicates that the light source 116 of the light-emitting area 111s is lit, and "OFF" indicates that the light source 116 of the light-emitting area 111s is off.

[0052] The grayscale setting data production unit 143, based on the brightness setting data D1 and the brightness profile D3, adds the brightness distribution within a light-emitting area 111s and the light leakage from the surrounding light-emitting areas 111s, and then calculates the brightness value V(n,m) directly below the pixel 120p in the nth column and mth row of the liquid crystal panel 120. Here, n is an integer greater than or equal to N², and m is an integer greater than or equal to M².

[0053] The grayscale setting data production unit 143 inputs the estimated brightness value V(n,m) and the blue grayscale Gb of the pixel 910p corresponding to pixel 120p in the input image 910 into the conversion formula Ef. The conversion formula Ef is, for example, a conversion formula that converts brightness to grayscale based on grayscale correction. The grayscale setting data production unit 143 sets the output value Efb of the conversion formula Ef, obtained by inputting the blue grayscale Gb into the conversion formula Ef, as the setting value of the blue grayscale of pixel 120p. The same processing is performed on the green grayscale Gg, and the output value Efg of the conversion formula Ef obtained therefrom is set as the setting value of the green grayscale of pixel 120p. The grayscale setting data production unit 143 also performs the same processing on the red grayscale Gr, and sets the output value Efr of the conversion formula Ef obtained therefrom as the setting value of the red grayscale of pixel 120p. The grayscale setting data production unit 143 sets the output values ​​Efb, Efg, and Efr of the conversion formula Ef to the value of the requirement e2(n,m) located in the nth column and mth row of the grayscale setting data D2. The grayscale setting data production unit 143 performs this processing on all pixels 120p of the liquid crystal panel 120.

[0054] The grayscale setting data D2 obtained in this way is a matrix of N2 columns and M2 rows. The three values ​​Efb, Efg, and Efr of the element e2(n,m) located in the nth column and mth row of the grayscale setting data D2 correspond to the setting values ​​of the blue, green, and red grayscale levels of the pixel 120p located in the nth column and mth row of the liquid crystal panel 120, respectively. However, the method for creating the grayscale setting data is not limited to the above.

[0055] The brightness setting data production unit 142 and the grayscale setting data production unit 143 are constructed using a processor such as a CPU (Central Processing Unit).

[0056] The memory unit 144 stores various data and programs required for controlling the backlight 110 and the LCD panel 120, such as the input image 910, brightness setting data D1, grayscale setting data D2, and brightness profile D3. The memory unit 144 is composed of, for example, ROM (Read-Only Memory) and RAM (Random-Access Memory).

[0057] The sub-synchronization signal generation unit 145 uses the synchronization signal 920 to generate a sub-synchronization signal 930. Details of the sub-synchronization signal 930 will be described later; it is a signal indicating the timing of the backlight driver 150 sequentially controlling the output of the light source 116 in each region 110z of the backlight 110. As shown in FIG. 9E, the sub-synchronization signal 930 is, for example, a pulse-shaped signal. The sub-synchronization signal 930 is synchronized with the synchronization signal 920, and within one period T of the synchronization signal 920, a plurality of pulses of the sub-synchronization signal 930 are included. In this embodiment, an example of six pulses of the sub-synchronization signal 930 within one period T is shown. The sub-synchronization signal generation unit 145 is constructed using, for example, a pulse signal generation circuit.

[0058] The control signal generation unit 146 generates a control signal D1a for the backlight 110 based on the brightness setting data D1. The control signal D1a is, for example, a PWM (Pulse Width Modulation) signal. The control signal generation unit 146 is constructed using, for example, a PWM signal generation circuit.

[0059] The output unit 147 includes an output interface connected to the backlight 110 and an output interface connected to the liquid crystal panel 120. As shown in FIG. 5, the output unit 147 outputs the control signal D1a and the sub-synchronization signal 930 of the backlight 110 to the driver 150 for the backlight. Furthermore, the output unit 147 outputs grayscale setting data D2 as the control signal D2a for the liquid crystal panel 120 to the driver 160 for the liquid crystal panel. Also, the output unit 147 outputs the synchronization signal 920 to the driver 160 for the liquid crystal panel. Alternatively, when it is necessary to convert grayscale setting data into control signals for the liquid crystal panel, the control signal generation unit can convert the grayscale setting data into control signals for the liquid crystal panel, and the output unit can output these control signals to the liquid crystal panel.

[0060] (Driver for backlight) The backlight driver 150 includes a data holding unit 151, a driving unit 152, a region switching unit 153, and a timing adjustment unit 154.

[0061] The data holding unit 151 holds the control signal D1a of the backlight 110. The data holding unit 151 is configured by, for example, a latch circuit that can hold the control signal D1a of the backlight 110.

[0062] When the driver 150 for the backlight controls the output of the light source 116 of each light-emitting region 111s, as shown in FIG6B, the backlight 110 is divided into a plurality of regions 110z arranged in the -Y direction. Each region 110z contains at least one row of light-emitting regions 111s. FIG6B shows an example where the backlight 110 is divided into 3 regions 110z, and each region 110z contains 3 rows of light-emitting regions 111s. Hereinafter, the region 110z located on the +Y side of the 3 regions 110z is referred to as the "upper region 110z1", the region 110z located on the -Y side of the upper region 110z1 is referred to as the "middle region 110z2", and the region 110z located on the -Y side of the middle region 110z2 is referred to as the "lower region 110z3". However, the number of regions of the backlight and the number of light-emitting regions contained in each region are not limited to the above-mentioned numbers. For example, the number of backlight areas can be more than four.

[0063] The driving unit 152 can simultaneously drive light sources 116 within a region 110z. The driving unit 152 is constructed by, for example, driving circuits for a plurality of light sources 116.

[0064] The area switching unit 153 sequentially switches the area 110z driven by the drive unit 152 in the -Y direction. The area switching unit 153 is disposed, for example, between the drive unit 152 and the backlight 110, and is constituted by a switching element that can switch the area 110z driven by the drive unit 152.

[0065] The timing adjustment unit 154 adjusts the timing of the control signal D1a corresponding to the k-th input image 910 sent from the data holding unit 151 to the drive unit 152. Here, k is any integer greater than or equal to 1. The timing adjustment unit 154 is constructed, for example, by a shift register circuit disposed between the data holding unit 151 and the drive unit 152. The function of the timing adjustment unit 154 will be described later.

[0066] (Driver for LCD panels) The driver 160 for the LCD panel is constructed by the driving circuit of the LCD panel 120, etc. When the driver 160 for the liquid crystal panel controls the grayscale of each pixel 120p of the liquid crystal panel 120, as shown in FIG6C, the liquid crystal panel 120 is divided into a plurality of regions 120z arranged in the -Y direction. Each region 120z contains one column of pixels 120p. Hereinafter, in the liquid crystal panel 120, the portion located directly above the upper region 110z1 of the backlight 110 is referred to as "upper part 121". Also, in the liquid crystal panel 120, the portion located directly above the middle region 110z2 of the backlight 110 is referred to as "middle part 122". Also, in the liquid crystal panel 120, the portion located directly above the lower region 110z3 of the backlight 110 is referred to as "lower part 123".

[0067] Furthermore, the region 120z located on the +Y side among the plurality of regions 120z included in the upper part 121 is also referred to as "upper region 120z1". Furthermore, the region 120z located on the +Y side among the plurality of regions 120z included in the middle part 122 is also referred to as "middle region 120z2". Furthermore, the region 120z located on the +Y side among the plurality of regions 120z included in the lower part 123 is also referred to as "lower region 120z3".

[0068] When, for example, the synchronization signal 920 rises, the driver 160 for the liquid crystal panel begins switching the voltage applied to each pixel 120p according to an input image 910. At this time, the driver 160 for the liquid crystal panel simultaneously drives pixels 120p in a region 120z. Furthermore, the driver 160 for the liquid crystal panel sequentially switches the driven region 120z in the -Y direction. Therefore, "switching the voltage applied to each pixel 120p of the liquid crystal panel 120" means a series of processes that sequentially switch the voltage applied to each pixel 120p of the liquid crystal panel 120 in the -Y direction according to each region 120z.

[0069] When the timing adjustment unit 154 of the backlight driver 150 is set to k=1, and in any region 120z of the liquid crystal panel 120 located directly above the region 110z selected by the region switching unit 153, before the switching of the voltage corresponding to the first input image 910 of each pixel 120p begins, the driving unit 154 does not send the control signal D1a to the driving unit 152. In this case, the driving unit 152 does not drive that region 110z. Furthermore, when the timing adjustment unit 154 starts switching the voltage corresponding to the first input image 910 of each pixel 120p in any region 120z located directly above the region 110z selected by the region switching unit 153, the driving unit 154 sends the control signal D1a corresponding to the first input image 910 to the driving unit 152. Therefore, in this case, the output of the light source 116 of each light-emitting region 111s in region 110z is switched to the output corresponding to the control signal D1a corresponding to the first input image 910.

[0070] Furthermore, when k ≥ 2, if the timing adjustment unit 154 has not yet started switching the voltage corresponding to the kth input image 910 of each pixel 120p in any region 120z directly above the region 110z selected by the region switching unit 153, it sends a control signal D1a corresponding to the (k-1)th input image 910 of that region 110z to the driving unit 152. Therefore, in this case, the output of the light source 116 of each light-emitting region 111s belonging to that region 110z becomes the output corresponding to the (k-1)th input image 910. Furthermore, when the timing adjustment unit 154 begins switching the voltage corresponding to the kth input image 910 of each pixel 120p in any region 120z directly above the region 110z selected by the region switching unit 153, it sends a control signal D1a corresponding to the kth input image 910 of that region 110z to the driving unit 152. Therefore, in this case, the output of the light source 116 of each light-emitting region 111s included in that region 110z is switched to the output corresponding to the kth input image 910.

[0071] Next, the image display method using the image display device 100 of this embodiment will be described. First, the timing controller 140 generates brightness setting data D1 for the k-th input image 910. Next, the timing controller 140 converts the brightness setting data D1 into a control signal D1a for the backlight 110. Then, the timing controller 140 outputs the control signal D1a and the sub-synchronization signal 930 to the driver 150 for the backlight.

[0072] Furthermore, the timing controller 140 generates grayscale setting data D2 for the k-th input image 910. Then, the timing controller 140 uses the grayscale setting data D2 as a control signal D2a, and outputs the control signal D2a and the synchronization signal 920 to the driver 160 for the liquid crystal panel.

[0073] Next, the driver 160 for the liquid crystal panel switches the voltage applied to each pixel 120p of the liquid crystal panel 120 based on the control signal D2a corresponding to the k-th input image 910, and the driver 150 for the backlight switches the output of the light source 116 of each light-emitting area 111s of the backlight 110 based on the control signal D1a corresponding to the k-th input image 910. This step will be described in detail below.

[0074] Furthermore, the case where k ≥ 2 will be explained below. Also, the control signal D2a corresponding to the kth input image 910 will be simply referred to as "the kth control signal D2a". Similarly, the control signal D1a corresponding to the kth input image 910 will be simply referred to as "the kth control signal D1a". Also, in Figure 9A, the moment when the synchronization signal 920 first rises will be set as "t0". Also, the time calculated by dividing one period T of the synchronization signal 920 by the number of pulses of the sub-synchronization signal 930 contained in one period T, i.e., 6, will be set as "unit time Δt". Also, the time elapsed for each unit time Δt from time t0 will be sequentially set as "time t1", "time t2", "time t3", "time t4", "time t5", and "time t6". In this embodiment, time t6 of a certain period T is time t0 of the next period T.

[0075] First, at time t0, when the rise of the synchronization signal 920 is detected, the driver 160 for the liquid crystal panel begins to switch the voltage applied to each pixel 120p according to the k-th control signal D2a. In this process, the driver 160 for the liquid crystal panel sequentially switches the voltage applied to a plurality of pixels 120p in each region 120z along the -Y direction from the value corresponding to the (k-1)-th control signal D2a to the value corresponding to the k-th control signal D2a.

[0076] Therefore, as shown in Figure 9B, at approximately time t0, the potentials of each pixel 120p belonging to the upper region 120z1 of the liquid crystal panel 120 are switched to the values ​​corresponding to the k-th control signal D2a. The potentials of each pixel 120p gradually reach the target potential Vf11 corresponding to the k-th control signal D2a.

[0077] Furthermore, as shown in Figure 9E, at time t0, the sub-synchronization signal 930 rises. The following describes an example of how the backlight driver 150 controls the output of the light source 116 in each light-emitting area 111s to illuminate the light source 116. However, the backlight driver 150 can also turn off the light source 116 when controlling the output of the light source 116 by the control signal D1a.

[0078] When the detection sub-synchronization signal 930 rises, the backlight driver 150, as shown in Figures 9F to 9H, sequentially controls the output of the light source 116 in each light-emitting region 111s along the -Y direction according to each region 110z. That is, during the period from time t0 to time t1, the backlight driver 150 sequentially controls the output of each light source 116 in the upper region 110z1, the middle region 110z2, and the lower region 110z3.

[0079] At this time, when the backlight driver 150 has not started switching the voltage applied to each pixel 120p in any of the regions 110z of the liquid crystal panel 120 located directly above, the output of each light source 116 contained in that region 110z is set to the output corresponding to the (k-1)th control signal D1a. Furthermore, when the backlight driver 150 starts switching the voltage applied to each pixel 120p in at least one region 120z of the liquid crystal panel 120 located directly above, the output of each light source 116 contained in that region 110z is set to the output corresponding to the kth control signal D1a.

[0080] During the period from time t0 to time t1, as shown in FIG9B, in the upper region 120z1 of the liquid crystal panel 120, the voltage applied to each pixel 120p begins to switch to the value corresponding to the k-th control signal D2a. On the other hand, as shown in FIG9C and FIG9D, in the middle region 120z2 and the lower region 120z3 of the liquid crystal panel 120, the voltage applied to each pixel 120p does not begin to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in FIG9F to FIG9H, during the period from time t0 to time t1, the backlight driver 150 switches the output of each light source 116 in the upper region 110z1 of the backlight 110 to the output corresponding to the k-th control signal D1a, and sets the output of each light source 116 in the middle region 110z2 and the lower region 110z3 to the output corresponding to the (k-1)-th control signal D1a.

[0081] Next, as shown in Figure 9E, at time t1, the sub-synchronization signal 930 rises again. When the detection sub-synchronization signal 930 rises, the backlight driver 150, as shown in Figures 9F to 9H, once again performs the processing of controlling the output of the light source 116 of each light-emitting area 111s in sequence along the -Y direction according to each area 110z.

[0082] As shown in Figures 9F to 9H, during the period from time t1 to time t2, similar to the period from time t0 to t1, the outputs of each light source 116 in the upper region 110z1 of the backlight 110 are set to the outputs corresponding to the k-th control signal D1a, and the outputs of each light source 116 in the middle region 110z2 and the lower region 110z3 are set to the outputs corresponding to the (k-1)-th control signal D1a.

[0083] Figure 10A is a schematic diagram showing the image displayed on the liquid crystal panel during the period from time t1 to time t2 shown in Figure 9A. Figure 10B is a schematic diagram showing the image displayed on the LCD panel during the period from time t3 to time t4 in Figure 9A. Figure 10C is a schematic diagram showing the image displayed on the liquid crystal panel during the period from time t5 to time t6 in Figure 9A. The following example illustrates how the (k-1)th input image 910 is a completely black image, and how the kth input image 910 is an image displaying the white text "A" on a black background.

[0084] During the period from time t1 to time t2, as shown in Figure 10A, the upper part 911 of the text "A" is displayed on the upper part 121 of the liquid crystal panel 120 according to the k-th input image 910, and a black image is displayed on the middle part 122 and the lower part 123 of the liquid crystal panel 120 according to the (k-1)-th input image 910. At this time, the brightness directly below the upper part 121 of the liquid crystal panel 120 becomes a value corresponding to the image displayed on the upper part 121, and the brightness directly below the middle part 122 and the lower part 123 becomes a value corresponding to the images displayed on the middle part 122 and the lower part 123. In this way, the image displayed on the liquid crystal panel 120 can be matched with the brightness of the backlight 110.

[0085] Next, as shown in Figure 9C, at approximately time t2, the potential of each pixel 120p in the central region 120z2 of the liquid crystal panel 120 is switched to the value corresponding to the k-th control signal D2a.

[0086] Furthermore, as shown in Figure 9E, at time t2, the sub-synchronization signal 930 rises again. When the detection sub-synchronization signal 930 rises, the backlight driver 150 once again performs the processing of controlling the output of the light source 116 of each light-emitting area 111s in sequence along the -Y direction according to each area 110z.

[0087] During the period from time t2 to time t3, as shown in Figures 9B and 9C, in the upper region 120z1 and middle region 120z2 of the liquid crystal panel 120, the voltage applied to each pixel 120p begins to switch to the value corresponding to the k-th control signal D2. On the other hand, as shown in Figure 9D, in the lower region 120z3 of the liquid crystal panel 120, the voltage applied to each pixel 120p does not begin to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figures 9F to 9H, during the period from time t2 to time t3, the backlight driver 150 sets the output of each light source 116 in the upper region 110z1 and middle region 110z2 of the backlight 110 to the output corresponding to the k-th control signal D1a, and sets the output of each light source 116 in the lower region 110z3 to the output corresponding to the (k-1)-th control signal D1a.

[0088] Next, as shown in Figure 9E, at time t3, the sub-synchronization signal 930 rises again. When the detection sub-synchronization signal 930 rises, the backlight driver 150, as shown in Figures 9F to 9H, once again performs the processing of controlling the output of the light source 116 of each light-emitting area 111s in sequence along the -Y direction according to each area 110z.

[0089] As shown in Figures 9F to 9H, during the period from time t3 to time t4, similar to the period from time t2 to time t3, the outputs of each light source 116 in the upper region 110z1 and the middle region 110z2 of the backlight 110 are set to the outputs corresponding to the k-th control signal D1a, and the outputs of each light source 116 in the lower region 110z3 are set to the outputs corresponding to the (k-1)-th control signal D1a.

[0090] During the period from time t3 to time t4, as shown in Figure 10B, the upper part 911 and the middle part 912 of the text "A" are displayed on the upper part 121 and the middle part 122 of the liquid crystal panel 120 according to the k-th input image 910. Meanwhile, a black image is continuously displayed on the lower part 123 of the liquid crystal panel 120 according to the (k-1)-th input image 910. At this time, the brightness directly below the upper part 121 and the middle part 122 of the liquid crystal panel 120 becomes a value corresponding to the images displayed on the upper part 121 and the middle part 122, and the brightness directly below the lower part 123 becomes a value corresponding to the image displayed on the lower part 123. In this way, the brightness of the image displayed on the liquid crystal panel 120 is matched with the brightness of the backlight 110.

[0091] Next, as shown in Figure 9D, at approximately time t4, the potential of each pixel 120p in the lower region 120z3 of the liquid crystal panel 120 is switched to the value corresponding to the k-th control signal D2a.

[0092] Furthermore, as shown in Figure 9E, at time t4, the sub-synchronization signal 930 rises again. As shown in Figures 9F to 9H, when the detection sub-synchronization signal 930 rises, the backlight driver 150 once again performs the processing of controlling the output of the light source 116 of each light-emitting area 111s in sequence along the -Y direction according to each area 110z.

[0093] During the period from time t4 to time t5, as shown in Figures 9B to 9D, the voltage applied to each pixel 120p in the upper region 120z1, middle region 120z2, and lower region 120z3 of the liquid crystal panel 120 begins to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figures 9F to 9H, during the period from time t4 to time t5, the backlight driver 150 sets the output of each light source 116 to the output corresponding to the k-th control signal D1a for all regions 110z of the backlight 110.

[0094] Next, as shown in Figure 9E, at time t5, the sub-synchronization signal 930 rises again. When the detection sub-synchronization signal 930 rises, the backlight driver 150, as shown in Figures 9F to 9H, once again performs the processing of controlling the output of the light source 116 of each light-emitting area 111s in sequence along the -Y direction according to each area 110z.

[0095] As shown in Figures 9F to 9H, the driver 150 for the backlight, during the period from time t5 to time t6, similar to the period from time t4 to time t5, sets the output of each light source 116 to the output corresponding to the k-th control signal D1a for all regions 110z of the backlight 110.

[0096] During the period from time t5 to time t6, as shown in Figure 10C, the upper part 911, middle part 912, and lower part 913 of the text "A" are displayed on the upper part 121, middle part 122, and lower part 123 of the liquid crystal panel 120 according to the k-th input image 910. That is, the entire text "A" is displayed. At this time, the brightness of the area directly below the upper part 121, middle part 122, and lower part 123 of the liquid crystal panel 120 becomes a value corresponding to the image displayed on the upper part 121, middle part 122, and lower part 123. In this way, the brightness of the image displayed on the liquid crystal panel 120 is matched with the brightness of the backlight 110.

[0097] After time t6, repeat the same process as from time t0 to time t5.

[0098] As explained above, when the synchronization signal 920 rises, the driver 160 for the liquid crystal panel begins to sequentially switch the voltage applied to each pixel 120p along the -Y direction according to each region 120z to the value corresponding to the k-th control signal D2a. Furthermore, during the period when the synchronization signal 920 rises again, the driver 160 switches the voltage applied to all pixels 120p of the liquid crystal panel 120 to the value corresponding to the k-th control signal D2a.

[0099] During one cycle T of the synchronization signal 920, the backlight driver 150 repeatedly performs the process of sequentially controlling the output of the light source 116 of each light-emitting area 111s along the -Y direction according to each region 110z. Furthermore, after the process of switching the voltage applied to each pixel 120p located directly above in each region 110z to the value corresponding to the k-th input image 910 begins, the output of the light source 116 of each light-emitting area 111s contained in each region 110z is switched to the output corresponding to the k-th input image 910.

[0100] Specifically, in this embodiment, when the process of switching the voltage applied to each pixel 120p located directly above to the value corresponding to the k-th input image 910 in each region 110z has not yet started, the output of the light source 116 of each light-emitting region 111s included in each region 110z is set to the output corresponding to the (k-1)-th input image 910. Furthermore, approximately simultaneously with the start of the process of switching the voltage applied to each pixel 120p located directly above to the value corresponding to the k-th input image 910 in each region 110z, the output of the light source 116 of each light-emitting region 111s included in each region 110z is switched to the output corresponding to the k-th input image 910.

[0101] However, the image display method is not limited to the method described above. For example, the number of pulses of the sub-synchronization signal 930 in each cycle T of the synchronization signal 920 may be 2 or more, and is not limited to 6. However, the number of pulses of the sub-synchronization signal 930 in each cycle T of the synchronization signal 920 is preferably an integer multiple of the total number of regions 110z of the backlight 110.

[0102] Next, the effects of this implementation will be explained. The image display method of this embodiment includes the following steps: switching the voltage applied to each pixel 120p of the liquid crystal panel 120 and the output of the light source 116 of each light-emitting region 111s of the backlight 110 according to each of the plurality of input images 910. The backlight 110 is divided into a plurality of regions 110z arranged in the -Y direction. Each region 110z contains a plurality of light-emitting regions 111s. The liquid crystal panel 120 is divided into a plurality of regions 120z arranged in the -Y direction. Each region 120z contains a plurality of pixels 120p. In the step of switching the voltage applied to each pixel 120p and the output of the light source 116 of each light-emitting region 111s according to the kth input image 910, the voltage applied to each pixel 120p is sequentially switched along the -Y direction according to each region 120z to a value corresponding to the kth input image 910. Furthermore, during the period when the voltage applied to each pixel 120p is switched to the value corresponding to the k-th input image 910, the process of sequentially controlling the output of the light source 116 of each light-emitting area 111s along the Y direction in each region 110z is repeated. After the process of switching the voltage applied to each pixel 120p located directly above in each region 110z to the value corresponding to the k-th input image 910 begins, the output of the light source 116 of each light-emitting area 111s contained in each region 110z is switched to the output corresponding to the k-th input image 910. Therefore, it is easy to match the brightness of the image displayed on the liquid crystal panel 120 with the brightness of the backlight 110. In this way, a high-quality image can be displayed.

[0103] Furthermore, in the step of switching the voltage applied to each pixel 120p and the output of the light source 116 of each light-emitting area 111s according to the k-th input image 910, if the process of switching the voltage applied to each pixel 120p located directly above in each area 110z to the value corresponding to the k-th input image 910 has not started, the output of the light source 116 of each light-emitting area 111s included in each area 110z is set to the output corresponding to the (k-1)-th input image 910 among the plurality of input images 910. Therefore, it is easy to match the brightness of the image displayed on the liquid crystal panel 120 with the brightness of the backlight 110. In this way, a high-quality image can be displayed.

[0104] Furthermore, in the step of switching the voltage applied to each pixel 120p and the output of the light source 116 of each light-emitting area 111s according to the k-th input image 910, the processing of switching the voltage applied to each pixel 120p of the liquid crystal panel 120 begins according to the pulse-shaped synchronization signal 920. Moreover, according to the sub-synchronization signal 930, which contains a plurality of pulses within one period T of the synchronization signal 920, the processing of sequentially controlling the output of the light source 116 of each light-emitting area 111s along the Y direction according to each area 110z of the backlight 110 is initiated. Therefore, by using the simple method of the synchronization signal 920 and the sub-synchronization signal 930, the switching timing of the voltage applied to each pixel 120p of the liquid crystal panel 120 and the switching timing of the output of each light source 116 of the backlight 110 can be adjusted.

[0105] Next, examples of variations of planar light sources will be explained. Figure 11A is a top view showing an example of a variation of a planar light source. Figure 11B is a cross-sectional view of line XIB-XIB in Figure 11A. Furthermore, in the following description, as a matter of principle, only the differences from the above-described embodiments will be explained. The same applies to the embodiments described below, except for matters otherwise. The same applies to other embodiments described later.

[0106] The planar light source 211 of this variation has a substrate 113, an adhesive member 215, a light-reflective sheet 214, and a plurality of light sources 216.

[0107] A light-reflective sheet 214 is attached to a substrate 113 via an adhesive member 215. A plurality of through holes 214a are provided in the light-reflective sheet 214. The plurality of through holes 214a are arranged in a matrix in the X and Y directions. A light source 216 is disposed within each through hole 214a.

[0108] Furthermore, a curved portion 214b is provided on the light-reflective sheet 214 to surround each through hole 214a, i.e., each light source 216. The curved portion 214b is formed by folding the light-reflective sheet 214 inward in such a way that it protrudes upward. In the planar light source 211, a region surrounded by the upper end of the curved portion 214b corresponds to a light-emitting region 211s.

[0109] As the light-reflective sheet 214, a resin sheet containing numerous air bubbles (e.g., a foamed resin sheet) or a resin sheet containing a light-diffusing material can be used. Examples of resins used in the light-reflective sheet 214 include thermoplastic resins such as acrylic resin, polycarbonate resin, cyclic polyolefin resin, polyethylene terephthalate resin, or polyester resin, or thermosetting resins such as epoxy resin or silicone resin. Examples of light-diffusing materials used in the light-reflective sheet 214 include titanium dioxide, silicon dioxide, aluminum oxide, zinc oxide, or glass.

[0110] Each light source 216 has a light-emitting element 216a and a wavelength conversion member 216b. The light-emitting element 216a is electrically connected to the substrate 113. The wavelength conversion member 216b covers the side and top surface of the light-emitting element 216a.

[0111] As explained above, if the structure of a planar light source is a matrix arrangement of light-emitting areas, then the structure is not limited to any particular form.

[0112] <Second Implementation Form> Next, the second embodiment will be described. Figure 12A is a schematic diagram showing the area of ​​the backlight in this embodiment that controls the output. Figure 12B is a schematic diagram showing the area in the liquid crystal panel of this embodiment that simultaneously controls the grayscale.

[0113] In this embodiment, when the backlight 210 is controlled by the backlight driver 150 to output the light source 116 of each light-emitting region 111s, it is divided into four regions 210z arranged in the -Y direction, as shown in FIG12A. Each region 210z contains two rows of light-emitting regions 111s. Hereinafter, the region 210z located on the +Y side of the four regions 210z is referred to as "region 210z1", the region 210z located on the -Y side of region 210z1 is referred to as "region 210z2", the region 210z located on the -Y side of region 210z2 is referred to as "region 210z3", and the region 210z located on the -Y side of region 210z3 is referred to as "region 210z4".

[0114] In this embodiment, when the liquid crystal panel 220 is controlled by the driver 160 for the liquid crystal panel to control the grayscale of each pixel 120p, it is divided into a plurality of regions 220z arranged in the -Y direction, as shown in FIG12B. Each region 220z contains one column of pixels 120p. Hereinafter, in the liquid crystal panel 220, the portion located directly above region 210z1 of the backlight 210 is referred to as "part 1 221". Also, in the liquid crystal panel 220, the portion located directly above region 210z2 of the backlight 210 is referred to as "part 2 222". Also, in the liquid crystal panel 220, the portion located directly above region 210z3 of the backlight 210 is referred to as "part 3 223". Also, in the liquid crystal panel 220, the portion located directly above region 210z4 of the backlight 210 is referred to as "part 4 224".

[0115] The region 220z located on the +Y side among the plurality of regions 220z in Part 1 221 is designated as "Region 220z1". The region 220z located on the +Y side among the plurality of regions 220z in Part 222 is designated as "Region 220z2". The region 220z located on the +Y side among the plurality of regions 220z in Part 3 223 is designated as "Region 220z3". The region 220z located on the +Y side among the plurality of regions 220z in Part 4 224 is designated as "Region 220z4".

[0116] Figure 13A is a schematic diagram showing the time variation of the synchronization signal in this embodiment. Figure 13B is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z1 of Figure 12B. Figure 13C is a schematic diagram showing the temporal variation of the potential of pixels belonging to region 220z2 of Figure 12B. Figure 13D is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z3 of Figure 12B. Figure 13E is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z4 of Figure 12B. Figure 13F is a schematic diagram showing the time variation of the sub-synchronization signal in this embodiment. Figure 13G is a timing diagram of the output of the light source that is subordinate to region 210z1 in Figure 12A. Figure 13H is a timing diagram showing the output of the light source that is subordinate to region 210z2 in Figure 12A. Figure 13I is a timing diagram showing the output of the light source controlled by region 210z3 in Figure 12A. Figure 13J is a timing diagram showing the output of the light source controlled by region 210z4 of Figure 12A.

[0117] In this embodiment, as shown in Figures 13A and 13F, the total number of pulses of the sub-synchronization signal 930a contained within one period T of the synchronization signal 920 is not an integer multiple of the total number of regions 210z of the backlight 210, which differs from the first embodiment. Specifically, in this embodiment, the number of pulses of the sub-synchronization signal 930a contained within one period T is 5, and the total number of regions 210z of the backlight 210 is 4.

[0118] Furthermore, in this embodiment, the backlight driver 150, for each region 210z, in at least one region 220z of the liquid crystal panel 220 located directly above, begins the process of switching the voltage applied to each pixel 120p to a value corresponding to the k-th input image 910. After a delay time Δtd, the output of the light source 116 of each light-emitting area 111s contained in that region 210z is switched to an output corresponding to the k-th input image 910. This differs from the first embodiment. The delay time Δtd is, for example, as shown in FIG13F, the value calculated by dividing the period T by the total number of pulses of the sub-synchronization signal 930a contained in the period T. However, the delay time is not limited to the above-mentioned time. For example, the delay time Δtd may also be more than twice the unit time calculated by dividing the period T by the total number of pulses of the sub-synchronization signal 930a contained in the period T. That is, the delay time Δtd can be an integer multiple of the unit time calculated by dividing the period T of the synchronization signal 920 by the total number of pulses.

[0119] Specifically, as shown in Figure 13F, at time t0, the sub-synchronization signal 930a rises. When detecting the rise of the sub-synchronization signal 930a, the backlight driver 150, as shown in Figures 13G to 13J, performs processing to sequentially control the output of the light source 116 of each light-emitting area 111s along the -Y direction according to each area 210z of the backlight 210.

[0120] As shown in Figure 13B, around time t0, the voltage of each pixel 120p belonging to region 220z1 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. However, as shown in Figure 13G, during the period from time t0 to time t1, the time at which the output of each light source 116 belonging to region 210z1 of the backlight 210 begins to be controlled is also around time t1. Furthermore, as shown in Figures 13C to 13E, during the period from time t0 to time t1, in regions 220z2, 220z3, and 220z4 of the liquid crystal panel 220, the voltage applied to each pixel 120p does not begin to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figures 13G to 13J, the driver 150 for the backlight sets the output of each light source 116 in each region 210z1, 210z2, 210z3, and 210z4 of the backlight 210 to the output corresponding to the (k-1)th control signal D1a during the period from time t0 to time t1.

[0121] Next, as shown in Figure 13F, at time t1, the sub-synchronization signal 930a rises again. As shown in Figure 13G, the backlight driver 150 starts controlling the output of each light source 116 belonging to region 210z1 of the backlight 210 at time t1. At time t1, a delay time Δtd has elapsed since time t0. Therefore, during the period from time t1 to time t2, the backlight driver 150 switches the output of each light source 116 in region 210z1 of the backlight 210 to the output corresponding to the k-th control signal D1a.

[0122] Furthermore, as shown in Figure 13C, during the period from time t1 to time t2, at time ta, the potential of each pixel 120p belonging to region 220z2 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. However, as shown in Figure 13H, during the period from time t1 to time t2, the time at which the output of each light source 116 belonging to region 210z2 of the backlight 210 is controlled also approximately at time ta. Therefore, the driver 150 for the backlight sets the output of each light source 116 in region 210z2 of the backlight 210 to the output corresponding to the (k-1)-th control signal D1a.

[0123] Furthermore, as shown in Figures 13I and 13J, the driver 150 for the backlight uses the same method as during the period from time t1 to time t2, where the output of each light source 116 in regions 210z3 and 210z4 of the backlight 210 is set to the output corresponding to the (k-1)th control signal D1a.

[0124] Next, as shown in Figure 13F, at time t2, the sub-synchronization signal 930a rises again. As shown in Figure 13G, the driver 150 for the backlight, during the period from time t2 to time t3, similarly to the period from time t1 to time t2, sets the output of each light source 116 in region 210z1 of the backlight 210 to the output corresponding to the kth control signal D1a.

[0125] Furthermore, as shown in Figure 13H, the backlight driver 150 begins controlling the output of each light source 116 belonging to region 210z2 of the backlight 210 at time tx during the period from time t2 to time t3. At time tx, a delay time Δtd has elapsed since time ta. Therefore, during the period from time t2 to time t3, the backlight driver 150 switches the output of each light source 116 in region 210z2 of the backlight 210 to the output corresponding to the k-th control signal D1a.

[0126] Furthermore, as shown in Figure 13D, at time tb during the period from t2 to t3, the potential of each pixel 120p belonging to region 220z3 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. However, as shown in Figure 13I, the time at which the output of each light source 116 belonging to region 210z3 of the backlight 210 begins to be controlled during the period from t2 to t3 is also approximately time tb. Therefore, the driver 150 for the backlight sets the output of each light source 116 in region 210z3 of the backlight 210 to the output corresponding to the (k-1)-th control signal D1a.

[0127] Furthermore, as shown in Figure 13J, during the period from time t2 to time t3, similarly to the period from time t1 to time t2, the output of each light source 116 in region 210z4 of the backlight 210 is set to the output corresponding to the (k-1)th control signal D1a.

[0128] Next, as shown in Figure 13F, at time t3, the sub-synchronization signal 930a rises again. As shown in Figures 13G and 13H, the driver 150 for the backlight uses the same method as during the period from time t3 to time t4, where the outputs of each light source 116 in regions 210z1 and 210z2 of the backlight 210 are set to the outputs corresponding to the k-th control signal D1a.

[0129] Furthermore, as shown in Figure 13I, the backlight driver 150 begins controlling the output of each light source 116 belonging to region 210z3 of the backlight 210 at time ty, during the period from time t3 to time t4. At time ty, a delay time Δtd has elapsed since time tb. Therefore, during the period from time t3 to time t4, the backlight driver 150 switches the output of each light source 116 in region 210z3 of the backlight 210 to the output corresponding to the k-th control signal D1a.

[0130] Furthermore, as shown in Figure 13E, at time tc during the period from t3 to t4, the potential of each pixel 120p belonging to region 220z4 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. However, as shown in Figure 13J, the time when the output of each light source 116 belonging to region 210z4 of the backlight 210 begins to be controlled during the period from t3 to t4 is also approximately time tc. Therefore, the driver 150 for the backlight sets the output of each light source 116 in region 210z4 of the backlight 210 to the output corresponding to the (k-1)-th control signal D1a.

[0131] Next, as shown in Figure 13F, at time t4, the sub-synchronization signal 930a rises again. As shown in Figures 13G to 13I, during the period from time t4 to time t5, similarly to the period from time t3 to time t4, the outputs of each light source 116 in regions 210z1, 210z2, and 210z3 of the backlight 210 are set to the outputs corresponding to the k-th control signal D1a.

[0132] Furthermore, as shown in Figure 13J, the backlight driver 150 begins controlling the output of each light source 116 belonging to region 210z4 of the backlight 210 at time tz during the period from time t4 to time t5. At time tz, a delay time Δtd has elapsed since time tc. Therefore, during the period from time t4 to time t5, the backlight driver 150 switches the output of each light source 116 in region 210z4 of the backlight 210 to the output corresponding to the k-th control signal D1a.

[0133] After time t5, the same processing as that from time t0 to time t5 is repeated. In this embodiment, time t5 of a certain period T is time t0 of the next period T.

[0134] Next, the effects of this implementation will be explained. In this embodiment, after the processing of switching the voltage applied to each pixel 120p of the liquid crystal panel 220 located directly above it to a value corresponding to the k-th input image 910 begins in each region 210z of the backlight 210, the output of the light source 116 of each light-emitting region 111s contained in each region 210z is switched to an output corresponding to the k-th input image 910. Therefore, it is easy to match the brightness of the image displayed on the liquid crystal panel 220 with the brightness of the backlight 210. This allows for the display of high-quality images.

[0135] Furthermore, it takes time for the potential of each pixel 120p of the liquid crystal panel 220 to reach the value corresponding to the k-th control signal D2a. In this embodiment, for each region 210z of the backlight 210, starting from the process of switching the voltage applied to each pixel 120p located directly above to the value corresponding to the k-th input image 910, after a delay time Δtd, the output of the light source 116 of each light-emitting region 111s contained in each region 210z is switched to the output corresponding to the k-th input image 910. Therefore, it is easy to match the brightness of the image displayed by the liquid crystal panel 220 with the brightness of the backlight 210. This allows for the display of high-quality images. Additionally, the delay time Δtd can be appropriately adjusted based on the length of unit time calculated by dividing the total number of pulses of the sub-synchronization signal 930a contained within the period T, or the time it takes for the potential of the pixel 120p of the liquid crystal panel 120 to reach the potential corresponding to the control signal.

[0136] <Third Implementation Form> Next, the third embodiment will be described. Figure 14A is a schematic diagram showing the time variation of the synchronization signal in this embodiment. Figure 14B is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z1 of this embodiment. Figure 14C is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z2 of this embodiment. Figure 14D is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z3 of this embodiment. Figure 14E is a schematic diagram showing the temporal variation of the potential of the pixels belonging to region 220z4 of this embodiment. Figure 14F is a schematic diagram showing the time variation of the sub-synchronization signal in this embodiment. Figure 14G is a schematic diagram showing the timing of the output of the light source of region 210z1, which is subordinate to this embodiment, as displayed by the display control. Figure 14H is a schematic diagram showing the timing of the output of the light source controlled by the region 210z2 belonging to this embodiment. Figure 14I is a schematic diagram showing the timing of the output of the light source controlled by the region 210z3 of this embodiment. Figure 14J is a schematic diagram showing the timing of the output of the light source controlled by region 210z4 of this embodiment. Figure 15 is a schematic diagram showing the (k-1)th input image and the kth input image of this embodiment. Figure 16A is a schematic diagram showing the image displayed on the liquid crystal panel during the period from time t0 to time t1 in Figure 14A. Figure 16B is a schematic diagram showing the image displayed on the liquid crystal panel during the period from time t1 to time t2 shown in Figure 14A. Figure 16C is a schematic diagram showing the image displayed on the liquid crystal panel during the period from time t2 to time t3 in Figure 14A. Figure 16D is a schematic diagram of the image displayed on the liquid crystal panel during the period from time t3 to time t4 shown in Figure 14A. The following describes an example where the (k-1)th input image 910 is an image with the text "C" on a white background on a black background, as shown in Figure 15, and the kth input image 910 is an image with the text "A" on a white background on a black background.

[0137] In this embodiment, similar to the second embodiment, the backlight 210 is divided into four regions 210z1, 210z2, 210z3, and 210z4, and the liquid crystal panel 220 is divided into four regions 220z1, 220z2, 220z3, and 220z4.

[0138] In this embodiment, the total number of pulses of the sub-synchronization signal 930b contained in one period T of the synchronization signal 920 is the same as the total number of regions 210z of the backlight 210, which is 4, unlike the second embodiment. Therefore, in this embodiment, the time t4 of a certain period T is the time t0 of the next period T. Furthermore, in this embodiment, after the backlight driver 150 switches the output of the light source 116 of each light-emitting region 111s to the output corresponding to the (k-1)th input image 910 for each region 210z of the backlight 210, it switches the output of the light source 116 of each light-emitting region 111s to the output corresponding to the k-th input image 910 from the time the light source 116 of each light-emitting region 111s is turned off, which is different from the second embodiment.

[0139] Specifically, as shown in Figure 14B, around time t0, the potential of each pixel 120p belonging to region 220z1 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Also, as shown in Figure 14F, at time t0, the sub-synchronization signal 930b rises. When the rise of the sub-synchronization signal 930b is detected, the backlight driver 150, as shown in Figures 14G-14J, performs processing to sequentially control the output of the light source 116 of each light-emitting region 111s along the -Y direction according to each region 210z of the backlight 210.

[0140] As shown in Figure 14G, the driver 150 for the backlight turns off each light source 116 in region 210z1 of the backlight 210 during the period from time t0 to time t1.

[0141] Furthermore, as shown in Figures 14C-14E, during the period from time t0 to time t1, the potential of each pixel 120p in regions 220z2, 220z3, and 220z4 of the liquid crystal panel 220 has not yet started to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figures 14H-14J, the backlight driver 150 sets the output of each light source 116 in regions 210z2, 210z3, and 210z4 of the backlight 210 to the output corresponding to the (k-1)-th control signal D1a during the period from time t0 to time t1.

[0142] Therefore, during the period from time t0 to time t1, as shown in Figure 16A, no image is displayed on the first part 221 of the liquid crystal panel 220. Furthermore, on the second part 222, the third part 223, and the fourth part 224 of the liquid crystal panel 220, a portion of the black background and white text "C" is displayed according to the (k-1)th input image 910.

[0143] Next, as shown in Figure 14C, at approximately time t1, the potential of each pixel 120p belonging to region 220z2 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Also, as shown in Figure 14F, at time t1, the sub-synchronization signal 930b rises again.

[0144] As shown in Figure 14B, during the period from time t1 to time t2, the potential of each pixel 120p belonging to region 220z1 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figure 14G, the backlight driver 150 switches the output of each light source 116 in region 210z1 of the backlight 210 to the output corresponding to the k-th control signal D1a during the period from time t1 to time t2.

[0145] As shown in Figure 14H, the driver 150 for the backlight turns off each light source 116 in region 210z2 of the backlight 210 during the period from time t1 to time t2.

[0146] As shown in Figures 14I and 14J, the driver 150 for the backlight is configured to output the light source 116 of each light source in regions 210z3 and 210z4 of the backlight 210 during the period from time t1 to time t2, similar to the period from time t0 to time t1. The output of each light source 116 is set to the output corresponding to the (k-1)th control signal D1a.

[0147] Therefore, during the period from time t1 to time t2, as shown in Figure 16B, a portion of the black background and white text "A" is displayed on the first part 221 of the liquid crystal panel 220 based on the k-th input image 910. Furthermore, no image is displayed on the second part 222 of the liquid crystal panel 220. Also, on the third part 223 and the fourth part 224 of the liquid crystal panel 220, a portion of the black background and white text "C" is displayed based on the (k-1)-th input image 910.

[0148] When the image displayed in part 221 is switched from the image corresponding to the (k-1)th input image 910 to the image corresponding to the kth input image 910 without turning off the area 210z1 of the backlight 210, a user may perceive the image corresponding to the (k-1)th input image 910 as a residual image immediately after the switch. To address this, in this embodiment, for the area 210z1 of the backlight 210, after switching the output of each light source 116 to the output corresponding to the (k-1)th input image 910, the output of each light source 116 is switched to the output corresponding to the kth input image 910 immediately after the light source 116 is turned off. Therefore, the user's perception of a residual image immediately after the switch can be suppressed.

[0149] Next, as shown in Figure 14D, at approximately time t2, the potential of each pixel 120p belonging to region 220z3 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Also, as shown in Figure 14F, at time t2, the sub-synchronization signal 930b rises again.

[0150] As shown in Figure 14G, the driver 150 for the backlight is configured to output the output of each light source 116 in region 210z1 of the backlight 210 during the period from time t2 to time t3, similar to the period from time t1 to time t2. This output corresponds to the kth control signal D1a.

[0151] Furthermore, as shown in Figure 14C, during the period from time t2 to time t3, the potential of each pixel 120p belonging to region 220z2 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figure 14H, the backlight driver 150 switches the output of each light source 116 in region 210z2 of the backlight 210 to the output corresponding to the k-th control signal D1a during the period from time t2 to time t3.

[0152] Furthermore, the driver 150 for the backlight, as shown in Figure 14I, turns off each light source 116 in region 210z3 of the backlight 210 during the period from time t2 to time t3.

[0153] Furthermore, as shown in Figure 14J, the driver 150 for the backlight is configured to output the light source 116 of each light source in region 210z4 of the backlight 210 during the period from time t2 to time t3, similar to the period from time t1 to time t2. This output corresponds to the (k-1)th control signal D1a.

[0154] Therefore, during the period from time t2 to time t3, as shown in Figure 16C, a portion of the text "A" with a black background and a white background is displayed on the first part 221 and the second part 222 of the liquid crystal panel 220 according to the k-th input image 910. Furthermore, no image is displayed on the third part 223 of the liquid crystal panel 220. Also, on the fourth part 224 of the liquid crystal panel 220, a portion of the text "C" with a black background and a white background is displayed according to the (k-1)-th input image 910.

[0155] Next, as shown in Figure 14E, at approximately time t3, the potential of each pixel 120p belonging to region 220z4 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Also, as shown in Figure 14F, at time t3, the sub-synchronization signal 930b rises again.

[0156] As shown in Figures 14G and 14H, the driver 150 for the backlight is configured to output the light source 116 of each light source in regions 210z1 and 210z2 of the backlight 210 during the period from time t3 to time t4, similar to the period from time t2 to time t3. The output of each light source 116 is set to the output corresponding to the k-th control signal D1a.

[0157] Furthermore, as shown in Figure 14D, during the period from time t3 to time t4, the potential of each pixel 120p belonging to region 220z3 of the liquid crystal panel 220 begins to switch to the value corresponding to the k-th control signal D2a. Therefore, as shown in Figure 14I, the backlight driver 150 switches the output of each light source 116 in region 210z3 of the backlight 210 to the output corresponding to the k-th control signal D1a during the period from time t3 to time t4.

[0158] Furthermore, the backlight driver 150, as shown in Figure 14J, turns off each light source 116 in region 210z4 of the backlight 210 during the period from time t3 to time t4.

[0159] Therefore, during the period from time t3 to time t4, as shown in Figure 16D, a portion of the black background and white text "A" is displayed on the first part 221, the second part 222, and the third part 223 of the liquid crystal panel 220 according to the k-th input image 910. Furthermore, no image is displayed on the fourth part 224 of the liquid crystal panel 220.

[0160] After time t4, repeat the same process as from time t0 to time t4.

[0161] Next, the effects of this implementation will be explained. In this embodiment, for each region 210z of the backlight 210, after switching the output of the light source 116 of each light-emitting region 111s to the output corresponding to the (k-1)th input image 910, the output of the light source 116 of each light-emitting region 111s is switched to the output corresponding to the k-th input image 910 again after the light source 116 of each light-emitting region 111s is turned off. Therefore, it is possible to prevent the image corresponding to the (k-1)th input image 910 from being identified as a residual image after the user switches.

[0162] <Fourth Implementation Form> Next, the fourth implementation will be described. Figure 17A is a schematic diagram showing the timing of the output of the light source controlled by region 210z1 of this embodiment. Figure 17B is a schematic diagram showing the timing of the output of the light source controlled by region 210z2 of this embodiment. Figure 17C is a schematic diagram showing the timing of the output of the light source controlled by region 210z3 of this embodiment. Figure 17D is a schematic diagram showing the timing of the output of the light source controlled by region 210z4 of this embodiment. In this embodiment, the point at which the light source 116 of each light-emitting region 111s contained in the region 210z of the backlight 210 is turned off, and then the light source 116 of each light-emitting region 111s contained in the controlled region 210z is also turned off, differs from that in the third embodiment.

[0163] Specifically, for example, as shown in Figures 17A and 17B, the driver 150 for the backlight turns off region 210z2 in addition to region 210z1 of the backlight 210 during the period from time t0 to time t1. Similarly, as shown in Figures 17B and 17C, the driver 150 for the backlight turns off region 210z3 in addition to region 210z2 of the backlight 210 during the period from time t1 to time t2. Similarly, as shown in Figures 17C and 17D, the driver 150 for the backlight turns off region 210z4 in addition to region 210z3 of the backlight 210 during the period from time t2 to time t3. Similarly, as shown in Figures 17A and 17D, the driver 150 for the backlight turns off region 210z1 in addition to region 210z4 of the backlight 210 during the period from time t3 to time t4.

[0164] In this way, the light sources 116 of multiple regions 210z can be turned off sequentially. In this case, it is also possible to prevent the image corresponding to the (k-1)th input image 910 from being identified as a residual image after the user switches. Especially when there are a large number of regions 210z, it is preferable to turn off the regions 210z continuously.

[0165] <Fifth Implementation Form> Next, the fifth implementation will be described. Figure 18 is a circuit diagram showing a portion of the image display device of this embodiment. This embodiment is an example of further specifying the third embodiment.

[0166] As shown in Figure 18, the backlight driver 150 includes a data holding unit 151, a driving unit 152, a region switching unit 153, and a timing adjustment unit 154. Furthermore, in Figure 18, for ease of illustration, the backlight 210 is depicted within the backlight driver 150, but in reality, the backlight 210 is located outside the driver 150. The same applies to Figure 201, which will be described later.

[0167] The data holding unit 151 receives the control signal D1a and the sub-synchronization signal 930b from the backlight 210 from the timing controller 140. The control signal D1a is a Serial Peripheral Interface (SPI) signal. The data holding unit 151 synchronizes with the sub-synchronization signal 930b, holds the control signal D1a for a specific period, and outputs it to the timing adjustment unit 154.

[0168] In the timing adjustment unit 154, a plurality of switching elements 154a and a plurality of buffers 154b are provided. The switching elements 154a and buffers 154b are arranged according to each light-emitting element 116a. In one example, the switching element 154a is an n-channel MOSFET. The source of the switching element 154a is connected to ground potential GND, the drain is connected to the cathode of the light-emitting element 116a, and the gate is connected to the output of the buffer 154b. In the timing adjustment unit 154, a drive signal 950 for driving each light-emitting element 116a of the backlight 210 is generated based on the control signal D1a and input to the gate of the switching element 154a via the buffer 154b.

[0169] A plurality of switching elements 153a are provided in the area switching section 153. In one example, the switching element 153a is a p-channel MOSFET. The switching elements 153a are provided in each area of ​​the backlight 210. The source of the switching element 153a is connected to the illumination potential VLED, and the drain is connected to the anode of the light-emitting element 116a constituting each area of ​​the backlight 210. The illumination potential VLED is the potential used to illuminate the light-emitting element 116a, that is, a potential higher than the ground potential GND. A switching signal 951 is input to the gate of the switching element 153a. That is, the switching element 153a is the element that switches whether to apply the power supply potential, i.e., the illumination potential VLED, to the light source 116a in each area of ​​the backlight 210.

[0170] In this embodiment, the switching element 153a connected to the light-emitting element 116a disposed in region 210z1 of the backlight 210 is referred to as "switching element 153z1", and the switching signal 951 input to the gate of the switching element 153z1 is referred to as "switching signal 951z1". Similarly, the switching elements 153a connected to the light-emitting elements 116a disposed in regions 210z2, 210z3, and 210z4 are referred to as switching elements 153z2, 153z3, and 153z4, respectively, and the switching signals 951 input to these gates are referred to as switching signals 951z2, 951z3, and 951z4, respectively.

[0171] Next, the actions of this embodiment will be explained. Figure 19A is a schematic diagram showing the timing of the region 210z1 that controls this embodiment. Figure 19B is a schematic diagram showing the timing of the region 210z2 that controls this embodiment. Figure 19C is a schematic diagram showing the timing of the region 210z3 controlling this embodiment. Figure 19D is a schematic diagram showing the timing of the region 210z4 that controls this embodiment.

[0172] As shown in Figures 14G and 19A, when the region 210z1 of the backlight 210 is lit, the switching signal 951z1 is set to "L" (low), and the p-channel MOSFET, i.e., the switching element 153z1, is turned on. On the other hand, at this time, the switching signals 951z2~z4 are set to "H" (high), and the switching elements 153z2~153z4 are turned off.

[0173] Therefore, as shown in Figure 18, the anode of the light-emitting element 116a in region 210z1 is connected to the lighting potential VLED. On the other hand, the anode of the light-emitting element 116a in regions 210z2 to 210z4 is not connected to the lighting potential VLED.

[0174] In this state, if the timing adjustment unit 154 inputs a drive signal 950 to the gate of each switching element 154b via the buffer 154b, the cathode of the light-emitting element 116a in region 210z1 is connected to the ground potential GND, and current flows through the light-emitting element 116a. Thus, the light-emitting element 116a is lit. At this time, the lighting time of each light-emitting element 116a is controlled by time division using the drive signal 950, thereby achieving a specific grayscale. On the other hand, in regions 210z2 to 210z4, the light-emitting elements 116a are not lit.

[0175] Furthermore, as shown in Figures 15 and 16A, when the liquid crystal panel 220 switches from the (k-1)th input image 910 to the kth input image 910, and the area 210z1 of the backlight 210 is turned off, the driving signal 950 input to the light-emitting element 116a in the area 210z1 is set to a signal with a gray level of 0.

[0176] Similarly, as shown in Figures 14H and 19B, when region 210z2 is lit, the switching signal 951z2 is set to "L", and the switching element 153z2 is turned on. Thereby, the light-emitting element 116a of region 210z2 is lit based on the drive signal 950. Furthermore, as shown in Figure 16B, when region 210z2 is turned off, the drive signal 950 input to the light-emitting element 116a of region 210z2 is set to a grayscale value of 0.

[0177] Similarly, as shown in Figures 14I and 19C, when region 210z3 is lit, the switching signal 951z3 is set to "L", and the switching element 153z3 is turned on. Thereby, the light-emitting element 116a of region 210z3 is lit based on the drive signal 950. In this case, also as shown in Figure 16C, when region 210z3 is turned off, the drive signal 950 input to the light-emitting element 116a of region 210z3 is set to a grayscale value of 0.

[0178] Similarly, as shown in Figures 14J and 19D, when region 210z4 is illuminated, the switching signal 951z4 is set to "L", turning on the switching element 153z4. Herein, the light-emitting element 116a of region 210z4 is illuminated based on the drive signal 950. In this case, also as shown in Figure 16D, when region 210z4 is extinguished, the drive signal 950 input to the light-emitting element 116a of region 210z4 is set to a grayscale value of 0.

[0179] Subsequently, by repeating the same action, the light-emitting element 116a can be turned off during the switching from the (k-1)th input image 910 to the kth input image 910. In this way, as described in the third embodiment, residual images can be suppressed.

[0180] <Sixth Implementation Form> Next, the sixth implementation will be described. Figure 20 is a circuit diagram showing a portion of the image display device of this embodiment. Figure 21 is a circuit diagram showing the switching signal generation unit of this embodiment. This embodiment is an example of an improved fifth embodiment.

[0181] As shown in Figure 20, in this embodiment, the backlight driver 150, in addition to the data holding unit 151, the driving unit 152, the area switching unit 153, and the timing adjustment unit 154, is provided with a switching signal generating unit 155. The switching signal generating unit 155 generates a switching signal 951 and outputs it to the area switching unit 153.

[0182] As shown in Figure 21, the switching signal generation unit 155 includes four D-type flip-flop circuits 155a to 155d. The number of segments in the D-type flip-flop circuits 155a to 155d is the same as the number of divisions in regions 210z1 to 210z4. A synchronization signal 920 is input to the S-terminal and R-terminal of each segment of the D-type flip-flop circuits 155a to 155d. A sub-synchronization signal 930 is input to the C-terminal of each segment of the D-type flip-flop circuits 155a to 155d. Switching signals 951z1 to 951z4 are output from the Q-terminal of the D-type flip-flop circuits 155a to 155d respectively.

[0183] The switching signals 951z1 to 951z4 are input as shielding signals to the D terminal of the initial D-type flip-flop circuit 155a. The D terminals of the subsequent D-type flip-flop circuits 155b to 155d are connected to the Q terminals of the preceding D-type flip-flop circuits 155a to 155c, and are input to the output of the preceding D-type flip-flop circuits. With this configuration, the four D-type flip-flop circuits 155a to 155d repeatedly output the same switching signals 951z1 to 951z4. As described in the fifth embodiment, the switching signals 951z1 to 951z4 are respectively input to the gates of the switching elements 153z1 to 153z4 of the zone switching unit 153. Next, the actions of this embodiment will be explained. Figure 22A is a schematic diagram showing the timing of the output of the light source controlled by region 210z1 of this embodiment. Figure 22B is a schematic diagram showing the timing of the output of the light source controlled by the region 210z2 of this embodiment. Figure 22C is a schematic diagram showing the timing of the output of the light source controlled by region 210z3 of this embodiment. Figure 22D is a schematic diagram showing the timing of the output of the light source controlled by region 210z4 of this embodiment. Figure 23A is a schematic diagram showing the timing of the region 210z1 that controls this embodiment. Figure 23B is a schematic diagram showing the timing of the region 210z2 that controls this embodiment. Figure 23C is a schematic diagram showing the timing of the region 210z3 controlling this embodiment. Figure 23D is a schematic diagram showing the timing of the region 210z4 that controls this embodiment.

[0184] Figures 22A to 22D correspond to Figures 14G to 14J of the third embodiment, respectively. Figures 23A to 23D correspond to Figures 19A to 19D of the fifth embodiment, respectively. Furthermore, for ease of observation, dashed ellipses are drawn in Figures 22A to 22D at the point of difference from Figures 14G to 14J. Similarly, in Figures 23A to 23D, the difference from Figures 19A to 19D is that dashed ellipses are drawn.

[0185] As shown in Figure 14B, during the period from time t0 to time t1, the voltage applied to each pixel 120p in region 220z1 of the liquid crystal panel 220 is switched to the value corresponding to the k-th control signal D2a. At this time, as shown in Figure 22A, the driving signal 950 input to the light-emitting element 116a in region 210z1 is set to a normal signal, that is, a signal based on the control signal D1a input from the timing controller 140.

[0186] On the other hand, as shown in FIG23A, the switching signal generation unit 155 sets the switching signal 951z1 to "H" and sets the switching element 153z1 to "OFF". As described above, the switching element 153z1 is the element that switches whether to apply a lighting potential VLED to the light source 116 disposed in the region 210z1 of the backlight 210. By setting the switching element 153z1 to "OFF", as shown in FIG20, the light-emitting element 116a connected to the switching element 153z1 is disconnected from the lighting potential VLED and is turned off regardless of the drive signal 950. As a result, the region 210z1 of the backlight 210 is turned off, and as shown in FIG16A, a black image is displayed on the first part 221 of the liquid crystal panel 220. In addition, the (k-1)th image is displayed on the second part 222, the third part 223, and the fourth part 224 of the liquid crystal panel 220.

[0187] As shown in Figure 14C, during the period from time t1 to time t2, the voltage applied to each pixel 120p in region 220z2 of the liquid crystal panel 220 is switched to the value corresponding to the k-th control signal D2a. At this time, as shown in Figure 22B, the driving signal 950 input to the light-emitting element 116a in region 210z2 is set to a normal signal, that is, a signal based on the control signal D1a input from the timing controller 140.

[0188] On the other hand, as shown in FIG23B, the switching signal generation unit 155 sets the switching signal 951z2 to "H" and sets the switching element 153z2 to open. As a result, as shown in FIG20, the light-emitting element 116a connected to the switching element 153z2 is disconnected from the illumination potential VLED and turns off regardless of the drive signal 950. Consequently, area 210z2 of the backlight 210 is turned off, and as shown in FIG16B, a black image is displayed on the second portion 222 of the liquid crystal panel 220. Furthermore, the k-th image is displayed on the first portion 221 of the liquid crystal panel 220, and the (k-1)-th image is displayed on the third portion 223 and the fourth portion 224.

[0189] As shown in Figure 14D, during the period from time t2 to time t3, the voltage applied to each pixel 120p in region 220z3 of the liquid crystal panel 220 is switched to the value corresponding to the k-th control signal D2a. At this time, as shown in Figure 22C, the driving signal 950 input to the light-emitting element 116a in region 210z3 is set to a normal signal.

[0190] On the other hand, as shown in FIG23C, the switching signal generation unit 155 sets the switching signal 951z3 to "H" and sets the switching element 153z3 to open. As a result, the light-emitting element 116a connected to the switching element 153z3 is disconnected from the illumination potential VLED and turns off regardless of the drive signal 950. Consequently, area 210z3 of the backlight 210 is turned off, and as shown in FIG16C, a black image is displayed in section 3 223. Furthermore, the k-th image is displayed in sections 1 221 and 222 of the liquid crystal panel 220, and the (k-1)-th image is displayed in section 4 224.

[0191] As shown in Figure 14E, during the period from time t3 to time t4, the voltage applied to each pixel 120p in region 220z4 of the liquid crystal panel 220 is switched to the value corresponding to the k-th control signal D2a. At this time, as shown in Figure 22D, the driving signal 950 input to the light-emitting element 116a in region 210z4 is set to a normal signal.

[0192] On the other hand, as shown in FIG23D, the switching signal generation unit 155 sets the switching signal 951z4 to "H" and sets the switching element 153z4 to open. As a result, the light-emitting element 116a connected to the switching element 153z4 is disconnected from the illumination potential VLED and turns off regardless of the drive signal 950. Consequently, area 210z4 of the backlight 210 turns off, and as shown in FIG16D, a black image is displayed on the fourth portion 224 of the liquid crystal panel 220. Furthermore, the k-th image is displayed on the first portion 221, the second portion 222, and the third portion 223 of the liquid crystal panel 220. Thereafter, the operation from time t0 to time t4 is repeated.

[0193] According to this embodiment, the switching signal generating unit 155 generates a switching signal 951, which sequentially disconnects the switching element 153a of the area switching unit 153, thereby separating the light-emitting element 116a from the illumination potential VLED and sequentially extinguishing areas 210z1 to 210z4 of the backlight 210. Therefore, even without specifically generating a drive signal 950 to set the grayscale of the light-emitting element 116a in each area to 0, a black image can be displayed on each part of the liquid crystal panel 220 using a simple mechanism that disconnects the switching element 153a. As a result, the burden on the backlight driver 150 can be reduced, and higher speeds can be achieved.

[0194] <Example of the first variation of the sixth implementation> Next, the first variation of the sixth embodiment will be explained. Figure 24 is a circuit diagram showing the switching signal generation unit of this variation example. Figure 25A is a schematic diagram showing the timing of controlling region 210z1 in this variation example. Figure 25B is a schematic diagram showing the timing of controlling region 210z2 in this variation example. Figure 25C is a schematic diagram showing the timing of the region 210z3 that controls this variation example. Figure 25D is a schematic diagram showing the timing of the control region 210z4 in this variation example. In Figures 25A-25D, dashed ellipses are added to the areas where the switching signal 951 is turned off as "H". The same applies to Figures 26A-28D, which will be described later.

[0195] As shown in Figure 24, in this variation, eight D-type flip-flop circuits 155a to 155h are connected in series in the switching signal generation unit 155. Furthermore, the output signal of the D-type flip-flop circuits 155a to 155h is input as a masking signal to the D terminal of the first D-type flip-flop circuit 155a.

[0196] Next, the actions in this variation example will be explained. As shown in Figures 25A-25D, in this variation, each period T is divided into 8 sub-periods, and one region is extinguished in each sub-period. Therefore, each region is extinguished twice in each period T. That is, region 210z1 is extinguished between time t0 and time t1, region 210z2 is extinguished between time t1 and time t2, region 210z3 is extinguished between time t2 and time t3, region 210z4 is extinguished between time t3 and time t4, region 210z1 is extinguished again between time t4 and time t5, region 210z2 is extinguished again between time t5 and time t6, region 210z3 is extinguished again between time t6 and time t7, and region 210z4 is extinguished again between time t7 and time t8. In this variation, time t8 of a certain period T is time t0 of the next period T.

[0197] Therefore, in this variation, when, for example, two images are displayed in one cycle T using an image compensation circuit, a black image can be displayed during the period after the voltage applied to each pixel 120p of the liquid crystal panel 220 is switched to the value corresponding to the next image.

[0198] <Example 2 of Implementation Form 6> Next, the second variation of the sixth embodiment will be explained. Figure 26A is a schematic diagram showing the timing of controlling region 210z1 in this variation example. Figure 26B is a schematic diagram showing the timing of the region 210z2 that controls this variation example. Figure 26C shows a time sequence diagram for controlling region 210z3 in this variation example. Figure 26D is a schematic diagram showing the timing of controlling region 210z4 in this variation example.

[0199] As shown in Figures 26A-26D, in this variation example, the emission begins to subside from region 210z2. That is, region 210z2 is extinguished between time t0 and time t1, region 210z3 is extinguished between time t1 and time t2, region 210z4 is extinguished between time t2 and time t3, and region 210z1 is extinguished between time t3 and time t4. Furthermore, region 210z2 is extinguished between time t4 and time t5, region 210z3 is extinguished between time t5 and time t6, region 210z4 is extinguished between time t6 and time t7, and region 210z1 is extinguished between time t7 and time t8.

[0200] Therefore, in this variation, when two images are displayed in one cycle T, a black image is displayed during the period before the voltage applied to each pixel 120p of the liquid crystal panel 220 switches to the value corresponding to the next image. This good image quality is also achieved through the compatibility between the backlight and the liquid crystal panel. Thus, according to this variation, driving corresponding to the characteristics of the liquid crystal panel can be performed.

[0201] <Example of the third variation of the sixth implementation> Next, the third variation of the sixth embodiment will be explained. Figure 27A is a schematic diagram showing the timing of controlling region 210z1 in this variation example. Figure 27B is a schematic diagram showing the timing of the region 210z2 that controls this variation example. Figure 27C is a schematic diagram showing the timing of the control region 210z3 in this variation example. Figure 27D is a schematic diagram showing the timing of the control region 210z4 in this variation example.

[0202] As shown in Figures 27A-27D, in this variation, each region is extinguished in two consecutive sub-cycles. Specifically, region 210z1 is extinguished between time t0 and t1, and then extinguished again between time t1 and t2. Region 210z2 is extinguished between time t2 and t3, and then extinguished again between time t3 and t4. Region 210z3 is extinguished between time t4 and t5, and then extinguished again between time t5 and t6. Region 210z4 is extinguished between time t6 and t7, and then extinguished again between time t7 and t8.

[0203] According to this variation, when one image is displayed in each period T, a black image is displayed during the period after the voltage applied to each pixel 120p of the liquid crystal panel 220 switches to the value corresponding to the next image. At this time, since the time for displaying the black image can be extended, the recognition of residual images after switching to the next image can be suppressed.

[0204] <Example of the fourth variation of the sixth implementation> Next, the fourth variation of the sixth embodiment will be explained. Figure 28A is a schematic diagram showing the timing of controlling region 210z1 in this variation example. Figure 28B is a schematic diagram showing the timing of the control of region 210z2 in this variation example. Figure 28C is a schematic diagram showing the timing of the control region 210z3 in this variation example. Figure 28D is a schematic diagram showing the timing of controlling region 210z4 in this variation example.

[0205] As shown in Figures 28A-28D, in this variation, each region is extinguished in two consecutive sub-cycles, starting with region 210z2. Specifically, region 210z2 is extinguished between time t0 and time t1, and then extinguished again between time t1 and time t2. Region 210z3 is extinguished between time t2 and time t3, and then extinguished again between time t3 and time t4. Region 210z4 is extinguished between time t4 and time t5, and then extinguished again between time t5 and time t6. Region 210z1 is extinguished between time t6 and time t7, and then extinguished again between time t7 and time t8.

[0206] As described in Embodiment 6 and its first to fourth variations, the period during which each region of the backlight 210 is turned off can be arbitrarily changed by compatibility with the liquid crystal panel. The period during which each region is turned off is not limited to the examples described above. In this way, the backlight can be optimally driven according to the characteristics of the liquid crystal panel.

[0207] The aforementioned multiple implementation forms and their variations can be appropriately combined within a non-contradictory range.

[0208] For example, it can be used in the displays of machines such as televisions, personal computers, or game consoles.

[0209] 100: Image display device 110: Backlight 110z: region 110z1: Upper region 110z2: Central Region 110z3: Lower region 111: Planar light source 111s: Emitting region 112: Optical components 113:Substrate 113m: Conductive component 114: Light-reflective thin film 114a: First layer 114b: Light-reflecting layer 114c: The second layer 115: Light guide component 115a: Light Source Configuration Department 115b: Zoning trench 116: Light source 116a: Light-emitting element 116b: Wavelength conversion component 116c: Second light adjustment component 116d: Third light adjustment component 116e: Semiconductor stack 116f: Electrode 116g: Electrode 116h: Translucent components 116i: Wavelength conversion material 117: Translucent components 118: First Light Adjustment Component 119: Light reflecting component 120: LCD panel 120p: pixels 120sp: subpixel 120z: region 120z1: Upper area 120z2: Central Region 120z3: Lower region 121: Upper part 122: Central 123:lower part 130: Control Department 140: Timing Controller 141: Input Section 142: Brightness Setting Data Production Department 143: Grayscale Setting Data Production Department 144: Memory Department 145: Sub-synchronization signal generation unit 146: Control Signal Generation Unit 147: Output Department 150: Driver for backlight 151: Data Preservation Department 152: Drive Unit 153: Area Switching Unit 153a: Switching element 153z1: Switching element 153z2: Switching element 153z3: Switching element 153z4: Switching element 154: Timing Adjustment Department 154a: Switching element 154b: Buffer 155: Switching Signal Generation Unit 155a~155h: Type D flip-flop circuit 160: Driver for LCD panels 210: Backlight 210z: region 210z1: Region 210z2: Region 210z3: Region 210z4: Region 211: Planar Light Source 211s: Emitting region 214: Light-reflective thin film 214a: Through hole 214b: Bend 215: Next component 216: Light source 216a: Light-emitting element 216b: Wavelength conversion component 220: LCD panel 220z: region 220z1: Region 220z2: Region 220z3: Region 220z4: Region 221: Part 1 222: Part 2 223: Part 3 224: Part 4 910: Input Image 910a: Pixel area 910p: pixels 911: Upper part 912: Central 913:lower part 920: Synchronization signal 930: Sub-synchronization signal 930a: Sub-synchronization signal 930b: Sub-synchronization signal 950: Drive signal 951: Switching Signal 951z1: Switching Signal 951z2: Switching Signals 951z3: Switching Signals 951z4: Switching Signal D: Terminal D1: Brightness Setting Data D1a: Control signal D2: Grayscale Setting Data D2a: Control signal D3: Brightness Profile Ef: Conversion Efb: Output value Efg: Output value Efr: Output value e1: Brightness e2: Requirements Gb: grayscale Gg: Grayscale Gmax: Maximum value GND: Grounding potential Gr: Grayscale Q:Terminal R: Terminal S: Terminal T: Period t0~t8: Time points ta: moment tb:moment tc: time tx: Moment ty: moment tz: Moment V: Brightness value VLED: Light-up potential Vf11: Potential Δt: unit time Δtd: Delay time

Claims

1. An image display method comprising the following steps: switching the voltage applied to each pixel and the output of the light source of each light-emitting region according to each of a plurality of input images sequentially input to a control unit, wherein the control unit comprises a backlight having a plurality of light-emitting regions arranged in a matrix in a first direction and a second direction intersecting the first direction, and a control unit of a liquid crystal panel disposed on the backlight having a plurality of pixels arranged in a matrix in the first direction and the second direction; wherein the backlight can be divided into a plurality of first regions arranged in the first direction; each of the first regions includes a plurality of light-emitting regions; the liquid crystal panel can be divided into a plurality of second regions arranged in the first direction; each of the second regions includes a plurality of pixels; in the step of switching the voltage applied to each pixel and the output of the light source of each light-emitting region according to the k-th input image among the plurality of input images, The voltage applied to each of the aforementioned pixels is sequentially switched along the first direction in each of the aforementioned second regions to a value corresponding to the aforementioned k-th input image; the process of sequentially controlling the output of the light source of each of the aforementioned light-emitting regions along the first direction in each of the aforementioned first regions is repeated during the period when the voltage applied to each of the aforementioned pixels is switched to a value corresponding to the aforementioned k-th input image; after the process of switching the voltage applied to each of the aforementioned pixels located directly above to a value corresponding to the aforementioned k-th input image begins in each of the aforementioned first regions, the output of the light source of each of the aforementioned light-emitting regions included in each of the aforementioned first regions is switched to an output corresponding to the aforementioned k-th input image.

2. The image display method of claim 1, wherein in the step of switching the voltage applied to each of the pixels and the output of the light source of each of the light-emitting areas according to the k-th input image, in each of the first areas, when the process of switching the voltage applied to each of the pixels located directly above to a value corresponding to the k-th input image has not started, the output of the light source of each of the light-emitting areas included in each of the first areas is set to the output corresponding to the (k-1)-th input image among the plurality of input images.

3. The image display method of claim 1, wherein, for the first region, after switching the output of the light source of each of the above-mentioned light-emitting regions to the output corresponding to the (k-1)th input image among the plurality of input images, from the moment the light source of each of the above-mentioned light-emitting regions is turned off, the output of the light source of each of the above-mentioned light-emitting regions is switched to the output corresponding to the kth input image.

4. The image display method of claim 3, wherein after the light source of each of the light-emitting areas contained in the first region is turned off, the light source of each of the light-emitting areas contained in the first region under control is also turned off.

5. The image display method according to any one of claims 1 to 4, wherein in the step of switching the voltage applied to each of the aforementioned pixels and the output of the light source of each of the aforementioned light-emitting areas according to the aforementioned k-th input image, the process of switching the voltage applied to each of the aforementioned pixels to a value corresponding to the aforementioned k-th input image is started according to a pulse-shaped synchronization signal; and the process of sequentially controlling the output of the light source of each of the aforementioned light-emitting areas along the aforementioned first direction according to each of the aforementioned first areas is started according to a sub-synchronization signal containing a plurality of pulses within a period of the aforementioned synchronization signal.

6. An image display device comprising: a backlight having a plurality of light-emitting regions arranged in a matrix along a first direction and a second direction intersecting the first direction; a liquid crystal panel disposed on the backlight having a plurality of pixels arranged in a matrix along the first direction and the second direction; and a control unit that can switch the voltage applied to each of the pixels and the light source output of each of the light-emitting regions according to each of a plurality of sequentially input images; wherein the backlight can be divided into a plurality of first regions arranged in the first direction; each of the first regions includes a plurality of the light-emitting regions; the liquid crystal panel can be divided into a plurality of second regions arranged in the first direction; each of the second regions includes a plurality of the pixels; the control unit sequentially switches the voltage applied to each of the pixels according to each of the second regions along the first direction to a value corresponding to the kth input image based on the kth input image among the plurality of input images; The process of sequentially controlling the output of the light source of each of the light-emitting regions along the first direction in each of the first regions is repeated during the period when the voltage applied to each of the pixels is switched to a value corresponding to the k-th input image; after the process of switching the voltage applied to each of the pixels located directly above to a value corresponding to the k-th input image begins in each of the first regions, the output of the light source of each of the light-emitting regions included in each of the first regions is switched to an output corresponding to the k-th input image.

7. The image display device of claim 6, wherein when the control unit does not begin the process of switching the voltage applied to each of the pixels located directly above to a value corresponding to the k-th input image in each of the first regions, the output of the light source of each of the light-emitting regions included in each of the first regions is set to the output corresponding to the (k-1)-th input image among the plurality of input images.

8. The image display device of claim 6, wherein the control unit, for the first region, after switching the output of the light source of each of the light-emitting regions to the output corresponding to the (k-1)th input image among the plurality of input images, switches the output of the light source of each of the light-emitting regions to the output corresponding to the kth input image from the moment the light source of each of the light-emitting regions is turned off.

9. The image display device of claim 8, wherein after the control unit extinguishes the light source of each of the light-emitting areas included in the first region, it also extinguishes the light source of each of the light-emitting areas included in the first region.

10. The image display device of claim 8, wherein the control unit has a switching element in each of the first regions for switching whether to apply a power supply potential to the light source; and the light source is extinguished by turning off the switching element.

11. An image display apparatus according to any one of claims 6 to 10, wherein the control unit comprises: a driver for the liquid crystal panel, which initiates a process of switching the voltage applied to each of the pixels to a value corresponding to the k-th input image based on a pulsed synchronization signal; and a driver for the backlight, which initiates a process of sequentially controlling the output of the light source of each of the light-emitting regions along the first direction according to each of the first regions based on a sub-synchronization signal containing a plurality of pulses within a period of the synchronization signal.

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