Flash memory and manufacturing method thereof

Abstract

A flash memory and its manufacturing method are disclosed. The flash memory includes a floating gate, a first dielectric layer, a second dielectric layer, a source region, a drain region, an erase gate, a select gate, and a third dielectric layer. The floating gate is disposed in a substrate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the surface of the floating gate exposed by the substrate. The source region is disposed in the substrate on one side of the floating gate and is in contact with the first dielectric layer. The drain region is disposed in the substrate on the other side of the floating gate and is separated from the first dielectric layer. The erase gate is disposed on the second dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a flash memory and a manufacturing method thereof. Prior Art

[0002] Flash memory has become a widely used memory in personal computers and other electronic devices because of its advantages of being able to store, read or erase data multiple times and the fact that the stored data will not disappear even after a power outage.

[0003] In the manufacturing process of split-gate flash memory, the polysilicon layer serving as the erase gate is typically formed above the source region. Therefore, when subsequently forming the source line contact, a portion of the polysilicon layer must be removed to create the source line contact opening. This complicates the manufacturing process. Furthermore, since the source line contact is typically located at the edge of the memory cell array, the distance between the source line contact and the memory cells varies significantly, resulting in a loading effect.

[0004] Furthermore, in typical split-gate flash memories, the floating gate is separated from other gates (such as the control gate, select gate, and erase gate) by a spacer. However, subsequent etching processes often damage the spacer, potentially causing the floating gate to contact other gates and create a short circuit, thus impacting flash memory performance. Summary of the Invention

[0005] The invention provides a flash memory, wherein a floating gate is arranged in a substrate and is covered by a dielectric layer, and a source line contact can be arranged on the source region between adjacent memory units.

[0006] The present invention provides a method for manufacturing a flash memory, wherein a floating gate is formed in a substrate and is covered by a dielectric layer, and a source line contact can be formed on the source region between adjacent memory units.

[0007] The flash memory of the present invention includes a floating gate, a first dielectric layer, a second dielectric layer, a source region, a drain region, an erase gate, a select gate, and a third dielectric layer. The floating gate is disposed in a substrate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the surface of the floating gate exposed by the substrate. The source region is disposed in the substrate on one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate on the other side of the floating gate and is separated from the first dielectric layer. The erase gate is disposed on the second dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

[0008] In one embodiment of the flash memory of the present invention, the top surface of the floating gate is higher than the top surface of the substrate.

[0009] In one embodiment of the flash memory of the present invention, the source region extends to below the floating gate.

[0010] In one embodiment of the flash memory of the present invention, a sidewall of the erase gate is located above the boundary between the first dielectric layer and the source region.

[0011] In one embodiment of the flash memory of the present invention, the third dielectric layer is also located on the source region.

[0012] In one embodiment of the flash memory of the present invention, a sidewall of the erase gate is located on the third dielectric layer above the source region.

[0013] In one embodiment of the flash memory of the present invention, a sidewall of the erase gate is located on the first dielectric layer between the floating gate and the source region.

[0014] In one embodiment of the flash memory of the present invention, both sidewalls of the erase gate are located above the floating gate.

[0015] In one embodiment of the flash memory of the present invention, a sidewall of the select gate is located on the second dielectric layer.

[0016] In one embodiment of the flash memory of the present invention, both sidewalls of the selection gate are located on the third dielectric layer.

[0017] In one embodiment of the flash memory of the present invention, the material of the erase gate and the material of the select gate each include polysilicon or metal.

[0018] In one embodiment of the flash memory of the present invention, an isolation structure is further included. The isolation structure is disposed in the substrate, and the drain region is located between the isolation structure and the selection gate.

[0019] The flash memory manufacturing method of the present invention includes the following steps: forming a groove in a substrate; forming a floating gate in the groove; forming a first dielectric layer between the floating gate and the substrate; forming a second dielectric layer on the surface of the floating gate exposed by the substrate; forming a source region in the substrate on one side of the floating gate, wherein the source region contacts the first dielectric layer; forming a third dielectric layer on the substrate on the other side of the floating gate; forming an erase gate on the second dielectric layer; forming a select gate on the third dielectric layer; and forming a drain region in the substrate on the side of the select gate away from the floating gate.

[0020] In one embodiment of the flash memory manufacturing method of the present invention, the method for forming the floating gate and the first dielectric layer includes the following steps: forming a dielectric material layer on the substrate; forming a conductive material layer on the dielectric material layer, wherein the conductive material layer fills the groove; and performing a chemical mechanical polishing process to remove a portion of the conductive material layer until the dielectric material layer is exposed.

[0021] In one embodiment of the flash memory manufacturing method of the present invention, the method for forming the source region includes the following steps: forming a mask layer on the substrate, wherein the mask layer exposes the area adjacent to the groove; performing an etching process using the mask layer as a mask to expose the surface of the substrate adjacent to the groove; performing an ion implantation process using the mask layer as a mask; and removing the mask layer.

[0022] In one embodiment of the flash memory manufacturing method of the present invention, the method for forming the third dielectric layer includes the following steps: forming a mask layer on the substrate, wherein the mask layer exposes the area adjacent to the groove; performing an etching process using the mask layer as a mask to expose the surface of the substrate adjacent to the groove; removing the mask layer; and performing a thermal oxidation process.

[0023] In one embodiment of the flash memory manufacturing method of the present invention, the method for forming the erase gate and the select gate includes the following steps: forming a conductive material layer on the second dielectric layer and the third dielectric layer; and performing a patterning process on the conductive material layer.

[0024] In one embodiment of the flash memory manufacturing method of the present invention, after performing the patterning process, a gate replacement process is further performed.

[0025] In one embodiment of the flash memory manufacturing method of the present invention, the method for forming the drain region includes the following steps: forming a mask layer on the substrate, wherein the mask layer exposes the region adjacent to the select gate; performing an ion implantation process using the mask layer as a mask; and removing the mask layer.

[0026] In one embodiment of the method for manufacturing a flash memory of the present invention, after forming the second dielectric layer and before forming the source region, the method further includes forming an isolation structure in the substrate.

[0027] In summary, in the present invention, the floating gate is disposed in the substrate and encapsulated by a dielectric layer. This effectively prevents the floating gate from contacting the erase gate and select gate, thereby preventing short circuits. Furthermore, in the present invention, because the area above the source region is not completely covered by the erase gate, no additional etching process is required during the manufacturing process to form a source line contact opening. The source line contact can be directly disposed in the area above the source region and connected to the source region.

[0028] To make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. Simple diagram description

[0029] 1A to 1H are cross-sectional diagrams illustrating the manufacturing process of a flash memory according to a first embodiment of the present invention. FIG. 2 is a cross-sectional diagram of a flash memory according to a second embodiment of the present invention. FIG3 is a cross-sectional diagram of a flash memory according to a third embodiment of the present invention. FIG. 4 is a cross-sectional diagram of a flash memory according to a fourth embodiment of the present invention. FIG. 5 is a cross-sectional diagram of a flash memory according to a fifth embodiment of the present invention. FIG. 6 is a cross-sectional diagram of a flash memory according to a sixth embodiment of the present invention. FIG. 7 is a cross-sectional diagram of a flash memory according to a seventh embodiment of the present invention. Implementation Method

[0030] The following examples are listed and illustrated in detail. However, these examples are not intended to limit the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description.

[0031] The terms "include", "including", "have", etc. used in this document are open-ended terms, which means "including but not limited to".

[0032] When terms such as "first," "second," etc. are used to describe elements, they are used only to distinguish these elements from one another and do not limit the order or importance of these elements. Therefore, in some cases, a first element can also be referred to as a second element, and a second element can also be referred to as a first element, without departing from the scope of the present invention.

[0033] Furthermore, directional terms such as "upper" and "lower" are used herein solely to refer to the directions of the drawings and are not intended to limit the present invention. Therefore, it should be understood that "upper" and "lower" are used interchangeably, and that when an element, such as a layer or film, is placed "on" another element, the element may be placed directly on the other element or intervening elements may be present. On the other hand, when an element is referred to as being "directly" placed "on" another element, there are no intervening elements between the two elements.

[0034] 1A to 1H are cross-sectional views of a flash memory according to a first embodiment of the present invention.

[0035] First, referring to FIG. 1A , a substrate 100 is provided. In this embodiment, substrate 100 is a silicon substrate, but the present invention is not limited thereto. In other embodiments, substrate 100 may also be a silicon-on-insulator (SOI) substrate. Next, a recess 102 is formed in substrate 100. In this embodiment, recess 102 is the region where a floating gate will be subsequently formed. A dielectric material layer is then conformally formed on substrate 100 to serve as a first dielectric layer 104. First dielectric layer 104 serves as a tunneling dielectric layer for the flash memory device of this embodiment. In this embodiment, first dielectric layer 104 is an oxide layer. Furthermore, in this embodiment, the first dielectric layer 104 is formed, for example, by performing a thermal oxidation process on substrate 100. Subsequently, a conductive material layer 106 is formed on first dielectric layer 104. Conductive material layer 106 serves as a floating gate for the flash memory device of this embodiment. In this embodiment, the conductive material layer 106 is a polysilicon layer. Furthermore, in this embodiment, the conductive material layer 106 is formed by, for example, a chemical vapor deposition (CVD) process. In this embodiment, the conductive material layer 106 completely fills the groove 102.

[0036] Next, referring to FIG. 1B , a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductive material layer 106 until the first dielectric layer 104 is exposed. Consequently, a floating gate 106 a is formed in the recess 102 , with the first dielectric layer 104 disposed between the floating gate 106 a and the substrate 100 . In this embodiment, because the first dielectric layer 104 serves as a polishing stop layer during the CMP process, the top surface of the floating gate 106 a is higher than the top surface of the substrate 100 . Subsequently, a second dielectric layer 108 is formed on the substrate 100 . The second dielectric layer 108 covers the surface of the floating gate 106 a exposed by the substrate 100 . Therefore, in this embodiment, the floating gate 106 a is disposed within the substrate 100 and is encapsulated by the dielectric layer, effectively preventing contact between the floating gate 106 a and other gates to be formed subsequently. That is, in this embodiment, there is no need to additionally form a spacer to ensure that the floating gate 106a does not contact other gates formed subsequently, thereby simplifying the manufacturing process steps of the flash memory.

[0037] Then, referring to FIG1C , a mask layer 110 is formed on the substrate 100. The mask layer 110 exposes areas corresponding to the isolation structures to be formed in the substrate 100. In this embodiment, the mask layer 110 is a nitride layer, but the present invention is not limited thereto. Next, an etching process is performed using the mask layer 110 as an etching mask to remove portions of the second dielectric layer 108, portions of the first dielectric layer 104, and portions of the substrate 100 to form trenches (not shown). An insulating material is then filled into the formed trenches to form the isolation structures 112. In this embodiment, the isolation structures 112 are shallow trench isolation (STI) structures, but the present invention is not limited thereto.

[0038] Next, referring to FIG. 1D , the mask layer 110 is removed. A mask layer 114 is then formed on the substrate 100. The mask layer 114 exposes the area adjacent to the recess 102. In this embodiment, the mask layer 114 is a photoresist layer, but the present invention is not limited thereto. Specifically, in this embodiment, the mask layer 114 exposes the area adjacent to the recess 102 where the source region of the flash memory is to be formed, while covering other areas outside of the area, but the present invention is not limited thereto. In other embodiments, depending on practical needs, the mask layer 114 may also expose other areas where doped regions are to be formed. Next, an etching process is performed using the mask layer 114 as an etching mask to remove portions of the second dielectric layer 108 and the first dielectric layer 104, exposing the surface of the substrate 100 adjacent to the recess 102. Subsequently, an ion implantation process is performed using the mask layer 114 as an implantation mask to implant dopants into the substrate 100 adjacent to the recess 102. As a result, a source region 116 is formed in the substrate 100 on one side of the floating gate 106a.

[0039] In this embodiment, because the sidewalls of the mask layer 114 are aligned with the sidewalls of the recess 102, the etching process does not damage the first dielectric layer 104 in the recess 102 or the second dielectric layer 108 above the floating gate 106a. This ensures that the floating gate 106a does not contact other gates that will be formed later. Furthermore, because the sidewalls of the mask layer 114 are aligned with the sidewalls of the recess 102, the source region 116 formed can contact the first dielectric layer 104 formed on the sidewalls of the recess 102. In other embodiments, the sidewalls of the mask layer 114 may not be aligned with the sidewalls of the recess 102 and may further cover the second dielectric layer 108 surrounding the recess 102. In this case, after the dopant implantation, a heat treatment may be performed to diffuse the dopant and form the source region 116 in contact with the first dielectric layer 104.

[0040] Then, referring to FIG. 1E , the mask layer 110 is removed. Next, a mask layer 118 is formed on the substrate 100. The mask layer 118 exposes the area on the other side of the recess 102. In this embodiment, the mask layer 118 is a photoresist layer, but the present invention is not limited thereto. Specifically, in this embodiment, the mask layer 118 covers the area above the recess 102 and the source region 116, and exposes the area between the recess 102 and the isolation structure 112. An etching process is then performed using the mask layer 118 as an etching mask to remove portions of the second dielectric layer 108 and portions of the first dielectric layer 104, exposing the surface of the substrate 100 adjacent to the recess 102. In this embodiment, because the sidewalls of the mask layer 118 are aligned with the sidewalls of the recess 102, the first dielectric layer 104 in the recess 102 and the second dielectric layer 108 above the floating gate 106a are not damaged during the etching process. This ensures that the floating gate 106a does not contact other gates that are subsequently formed. In other embodiments, the sidewalls of the mask layer 118 may not be aligned with the sidewalls of the recess 102 and may further cover the second dielectric layer 108 surrounding the recess 102.

[0041] Next, referring to FIG. 1F , the mask layer 118 is removed. A thermal oxidation process is then performed to form a third dielectric layer 120 on the exposed surface of the substrate 100. Therefore, in this embodiment, the third dielectric layer 120 is an oxide layer. Thus, a third dielectric layer 120 is formed on the surface of the substrate 100 outside the recess 102, and the third dielectric layer 120 covers the source region 116. A conductive material layer 122 is then formed on the substrate 100. The conductive material layer 122 covers the isolation structure 112, the second dielectric layer 108, and the third dielectric layer 120. The conductive material layer 122 is used to form the erase gate and select gate of the flash memory device of this embodiment. In this embodiment, the conductive material layer 122 is a polysilicon layer. Furthermore, in this embodiment, the conductive material layer 122 is formed by, for example, a chemical vapor deposition process.

[0042] 1G , the conductive material layer 122 is patterned to form an erase gate 124 and a select gate 126. Specifically, after the conductive material layer 122 is patterned, the erase gate 124 is formed on the second dielectric layer 108, and the select gate 126 is formed on the third dielectric layer 120 between the floating gate 106 a and the isolation structure 112. Therefore, the second dielectric layer 108 between the erase gate 124 and the floating gate 106 a serves as an inter-gate dielectric layer, and the third dielectric layer 120 between the select gate 126 and the substrate 100 serves as a gate dielectric layer.

[0043] In this embodiment, the erase gate 124 and the select gate 126 are formed from the polysilicon layer serving as the conductive material layer 122, but the present invention is not limited thereto. In other embodiments, after patterning the conductive material layer 122, a gate replacement process well known to those skilled in the art may be performed to form the erase gate 124 and the select gate 126 made of a metal material.

[0044] Next, a mask layer 128 is formed on the substrate 100. The mask layer 128 exposes the area adjacent to the select gate 126. In this embodiment, the mask layer 128 is a photoresist layer, but the present invention is not limited thereto. Specifically, in this embodiment, the mask layer 128 covers the second dielectric layer 108, the third dielectric layer 120 on the source region 116, the erase gate 124, and the select gate 126, while exposing the isolation structure 112 and the area between the select gate 126 and the isolation structure 112. In other words, the mask layer 128 exposes the isolation structure 112 and the area where the drain region of the flash memory is to be formed, but the present invention is not limited thereto. In other embodiments, depending on actual needs, the mask layer 128 may also expose other areas where doped regions are to be formed.

[0045] 1H , an ion implantation process is performed using the mask layer 128 as an implantation mask to implant dopants into the substrate 100 between the select gate 126 and the isolation structure 112, thereby forming a drain region 130. The mask layer 128 is then removed. In this manner, the flash memory device 10 of this embodiment is formed.

[0046] In the flash memory device 10 of this embodiment, the floating gate 106a is disposed in the substrate 100, the first dielectric layer 104 is disposed between the floating gate 106a and the substrate 100, and the second dielectric layer 108 covers the surface of the floating gate 106a exposed by the substrate 100. In other words, in this embodiment, the floating gate 106a is encapsulated by the first dielectric layer 104 and the second dielectric layer 108. Therefore, contact between the floating gate 106a and the erase gate 124 and the select gate 126, which could cause a short circuit, can be effectively avoided.

[0047] Furthermore, in the flash memory device 10 of this embodiment, the source region 116 is disposed in the substrate 100 on one side of the floating gate 106 a and is in contact with the first dielectric layer 104. The drain region 130 is disposed in the substrate 100 on the other side of the floating gate 106 a and is separated from the first dielectric layer 104. The erase gate 124 is disposed on the second dielectric layer 108. The select gate 126 is disposed on the substrate 100 between the floating gate 106 a and the drain region 130. The third dielectric layer 120 is disposed between the select gate 126 and the substrate 100. Because the area above the source region 116 is not completely covered by the erase gate 124, a source line contact can be formed directly in the area above the source region 116 in subsequent manufacturing processes to connect to the source region 116. That is, there is no need to perform an additional etching process to remove part of the erase gate 124 to form a source line contact opening, thereby achieving the effect of simplifying the process steps.

[0048] In addition, since the source line contact can be formed in the area above the source region 116, that is, the source line contact can be formed between two adjacent floating gates 106a, the distance between the two adjacent memory cells and the source line contact can be substantially the same, thereby avoiding a loading effect during operation.

[0049] In the flash memory 10 of this embodiment, the boundary of the source region 116 is aligned with the sidewall of the recess 102. The entire erase gate 124 is located on the second dielectric layer 108, and one sidewall of the erase gate 124 is located above the boundary between the first dielectric layer 102 and the source region 116 (the sidewall is aligned with the sidewall of the recess 102). The entire select gate 126 is located on the third dielectric layer 120, but the present invention is not limited to this. In other embodiments, the arrangement of the various components constituting the flash memory can be adjusted according to actual conditions.

[0050] 2 is a cross-sectional view of a flash memory according to a second embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail.

[0051] 2 , the flash memory device 20 of this embodiment differs from the flash memory device 10 in that, in the flash memory device 20, the source region is not only located in the substrate 100 adjacent to the trench 102 but also extends below the floating gate 106 a. In other words, in the step shown in FIG1D , after dopants are implanted into the substrate 100 adjacent to the recess 102, a heat treatment may be performed to diffuse the implanted dopants below the floating gate 106 a, but the present invention is not limited thereto.

[0052] 3 is a cross-sectional view of a flash memory according to a third embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail.

[0053] 3 , the flash memory 30 of this embodiment differs from the flash memory 10 in that, in the flash memory 30, the entire erase gate 124 is located on the second dielectric layer 108, and one sidewall of the erase gate 124 is located on the first dielectric layer 104 between the floating gate 106 a and the source region 116. In other words, the sidewall of the erase gate 124 is not aligned with the sidewall of the recess 102.

[0054] Figure 4 is a cross-sectional view of a flash memory according to a fourth embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail.

[0055] 4 , the flash memory 40 of this embodiment differs from the flash memory 10 in that, in the flash memory 40, the entire erase gate 124 is located on the second dielectric layer 108, and both sidewalls of the erase gate 124 are located directly above the floating gate 106a. In other words, the sidewalls of the erase gate 124 are not aligned with the sidewalls of the recess 102.

[0056] 5 is a cross-sectional view of a flash memory according to a fifth embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail.

[0057] 5 , the flash memory 50 of this embodiment differs from the flash memory 10 in that, in the flash memory 50, the erase gate 124 is not only located on the second dielectric layer 108, but also further located on the third dielectric layer 116. That is, in this embodiment, one sidewall of the erase gate 124 is located on the second dielectric layer 108 directly above the floating gate 106 a, and the other sidewall is located on the third dielectric layer 120. Therefore, the erase gate 124 can be located above both the floating gate 106 a and the source region 116.

[0058] 6 is a cross-sectional view of a flash memory according to a sixth embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail.

[0059] 6 , the flash memory 60 of this embodiment differs from the flash memory 10 in that, in the flash memory 60, one sidewall of the select gate 126 is located on the second dielectric layer 108. Specifically, in this embodiment, one sidewall of the select gate 126 is located on the third dielectric layer 120, and the other sidewall is located on the first dielectric layer 104 between the floating gate 106a and the sidewall of the recess 102, and does not contact the erase gate 124.

[0060] 7 is a cross-sectional view of a flash memory according to a seventh embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described in detail again.

[0061] 7 , the flash memory 70 of this embodiment differs from the flash memory 10 in that, in the flash memory 70, one sidewall of the select gate 126 is located on the second dielectric layer 108. Specifically, in this embodiment, one sidewall of the select gate 126 is located on the third dielectric layer 120, and the other sidewall is located on the second dielectric layer 108 directly above the floating gate 106 a. Therefore, the select gate 126 can be located simultaneously on the floating gate 106 a and on the substrate 100 between the drain region 116 and the recess 102, without contacting the erase gate 124.

[0062] Furthermore, in other embodiments, the configuration of the components constituting the flash memory may be adjusted according to actual circumstances, for example, the architectures of the above embodiments may be combined, and the present invention is not limited thereto.

[0063] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Anyone having ordinary knowledge in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

[0064] 10, 20, 30, 40, 50, 60, 70: Flash memory 100: Base 102: Groove 104: first dielectric layer 106, 122: conductive material layer 106a: floating gate 108: second dielectric layer 110, 114, 118, 128: mask layer 112: Isolation Structure 116: Source region 120: third dielectric layer 124: Erase Gate 126: Select gate 130: Drain area

Claims

1. A flash memory, comprising: Floating gate, disposed in the substrate; A first dielectric layer is disposed between the floating gate and the substrate; A second dielectric layer covers the surface of the floating gate exposed by the substrate; a source region is disposed in the substrate on one side of the floating gate and is in contact with the first dielectric layer; a drain region is disposed in the substrate on the other side of the floating gate and is separated from the first dielectric layer; an erase gate is disposed on the second dielectric layer; and a select gate is disposed on the substrate between the floating gate and the drain region. A third dielectric layer is disposed between the selected gate and the substrate, wherein one sidewall of the erase gate is located on the first dielectric layer between the floating gate and the source region.

2. The flash memory as claimed in claim 1, wherein the top surface of the floating gate is higher than the top surface of the substrate.

3. The flash memory as claimed in claim 1, wherein the source region extends below the floating gate.

4. The flash memory as claimed in claim 1, wherein one sidewall of the erase gate is located above the boundary between the first dielectric layer and the source region.

5. The flash memory as claimed in claim 1, wherein the third dielectric layer is also located on the source region.

6. The flash memory as claimed in claim 1, wherein both sidewalls of the erase gate are located above the floating gate.

7. The flash memory as claimed in claim 1, wherein one sidewall of the selected gate is located on the second dielectric layer.

8. The flash memory as claimed in claim 1, wherein both sidewalls of the selected gate are located on the third dielectric layer.

9. The flash memory as claimed in claim 1, wherein the material of the erase gate and the material of the select gate each comprise polysilicon or metal.

10. The flash memory as claimed in claim 1 further includes an isolation structure disposed in the substrate, and the drain region is located between the isolation structure and the selected gate.

11. A method for manufacturing flash memory, comprising: A groove is formed in the substrate; a floating gate is formed in the groove; A first dielectric layer is formed between the floating gate and the substrate; A second dielectric layer is formed on the surface of the floating gate exposed by the substrate; a source region is formed in the substrate on one side of the floating gate, wherein the source region is in contact with the first dielectric layer; a third dielectric layer is formed on the substrate on the other side of the floating gate; an erase gate is formed on the second dielectric layer; a select gate is formed on the third dielectric layer; and a drain region is formed in the substrate on the side of the select gate away from the floating gate, wherein a sidewall of the erase gate is located on the first dielectric layer between the floating gate and the source region.

12. The method of manufacturing flash memory as claimed in claim 11, wherein the method of forming the floating gate and the first dielectric layer comprises: A dielectric material layer is formed on the substrate; A conductive material layer is formed on the dielectric material layer, wherein the conductive material layer fills the groove; And perform a chemical mechanical polishing process to remove portions of the conductive material layer until the dielectric material layer is exposed.

13. The method of manufacturing flash memory as claimed in claim 11, wherein the method of forming the source region comprises: A masking layer is formed on the substrate, wherein the masking layer exposes the area adjacent to the groove; Using the mask layer as a mask, an etching process is performed to expose the surface of the substrate next to the groove; Using the aforementioned mask layer as a mask, an ion implantation process is performed; And remove the covering layer.

14. The method of manufacturing flash memory as claimed in claim 11, wherein the method of forming the third dielectric layer comprises: A masking layer is formed on the substrate, wherein the masking layer exposes the area adjacent to the groove; Using a mask layer as a mask, an etching process is performed to expose the surface of the substrate next to the groove; Remove the covering layer; and perform a thermal oxidation process.

15. The method of manufacturing flash memory as claimed in claim 11, wherein the method of forming the erase gate and the select gate comprises: Conductive material layers are formed on the second dielectric layer and the third dielectric layer; And a patterning process is performed on the conductive material layer.

16. The method of manufacturing flash memory as claimed in claim 15, wherein after performing the patterning process, a gate replacement process is further performed.

17. The method of manufacturing flash memory as claimed in claim 11, wherein the method of forming the drain region comprises: A masking layer is formed on the substrate, wherein the masking layer exposes the area adjacent to the selected gate; Using the aforementioned mask layer as a mask, the ion implantation process is performed. And remove the covering layer.

18. The method of manufacturing a flash memory as claimed in claim 11, wherein after forming the second dielectric layer and before forming the source region, an isolation structure is further formed in the substrate.

Images