Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The reliability of the semiconductor device is improved. The semiconductor device includes a clamping member electrically connected to a main transistor source pad via a first silver paste and connected to a lead via a second silver paste. The clamping member has a "first portion" in contact with the first silver paste, a "second portion" in contact with the second silver paste, and a "third portion" located between the "first portion" and the "second portion". A protruding member is formed on the surface of the main transistor source pad, and the "first portion" contacts the protruding member.

Description

Semiconductor devices and manufacturing methods thereof This invention relates to a semiconductor device and its manufacturing technology, and for example to a technology and manufacturing technology that can be effectively applied to a semiconductor device as a constituent element of an inverter. The publicly available technologies are listed below. [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2018-121035 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2009-200338 Japanese Unexamined Patent Application Publication No. 2018-121035 (Patent Document 1) describes a technology related to the packaging structure of a semiconductor device used as a constituent element of an inverter. Japanese Unexamined Patent Application Publication No. 2009-200338 (Patent Document 2) describes a technique for electrically connecting a plate-shaped member to the source pad of a semiconductor wafer in a semiconductor device via a conductive material, such as solder or silver paste. The semiconductor device includes leads used as external terminals and a semiconductor wafer in which power metal-oxide-semiconductor field-effect transistors (MOSFETs) are formed. The leads and the semiconductor wafer are electrically connected to each other via a plate-shaped member called a "copper clip". For example, in a semiconductor device that seals a semiconductor wafer in which power transistors are formed, there exist semiconductor devices on the surface of the semiconductor wafer that have electrodes including leads and pads, and the leads and electrodes are connected to each other by a plate-like member called a "clamping member". In this semiconductor device, it is desirable to improve the reliability of the connection between the pads and the plate-like member. One embodiment of a semiconductor device includes a plate-like member electrically connected to a first electrode via a first conductive material and connected to a lead via a second conductive material. The plate-like member has a first portion in contact with the first conductive material, a second portion in contact with the second conductive material, and a third portion located between the first and second portions. A protruding member is formed on the surface of the first electrode, and the first portion contacts the protruding member. One embodiment of a semiconductor device includes a plate-like member electrically connected to a first electrode via a first conductive material and connected to a lead via a second conductive material. The plate-like member has a first portion in contact with the first conductive material, a second portion in contact with the second conductive material, and a third portion located between the first and second portions. A protruding member in contact with the third portion is formed on a protective film covering a peripheral portion of the first electrode. A method of manufacturing a semiconductor device in one embodiment includes the following steps: electrically connecting the first electrode and the lead to each other via the plate member by disposing a first portion of the plate member on a first electrode via a first conductive material and disposing a second portion of the plate member on a lead via a second conductive material. In this step, by bringing the first or third portion of the plate-shaped member into contact with the protruding member, the plate-shaped member is disposed on the first electrode and the lead wire with the first portion having a positive inclination, such that the height of the protruding member is greater than the height of the portion between the end of the plate-shaped member included in the first portion and the surface of the first electrode. According to one embodiment, the reliability of a semiconductor device can be improved. Related state please cross-references The disclosure of Japanese Patent Application No. 2021-176262, filed on October 28, 2021 (including the specification, drawings and abstract) is incorporated herein by reference in its entirety. In all the accompanying drawings used to illustrate the implementation, the same elements are represented by the same reference numerals in principle, and repeated descriptions will be omitted. Note that shading lines may be used even in plan views to make the drawings easier to read. <12-phase brushless DC motor control system> In the 12-phase brushless DC motor control system that controls the 12-phase brushless DC motor, four sets of conventional three-phase (U-phase, V-phase, W-phase) are used. The inverter circuit is used as a phase control circuit, and the AC power supplied from the inverter circuit is supplied to the coils of the corresponding phase of the brushless DC motor. Therefore, in a brushless DC motor control system that controls a 6-phase or 12-phase brushless DC motor, 6 or 12 inverter circuits are used. Figure 1 is a schematic diagram showing the configuration of a 12-phase brushless DC motor control system. The motor MOT shown in Figure 1 is a 12-phase brushless DC motor with 12 coils CL. Each coil CL is connected to an inverter circuit INV. In other words, the inverter circuits INV are configured to correspond to each of the 12 coils of the motor MOT. Therefore, the 12-phase brushless DC motor control system shown in Figure 1 has a total of 12 inverter circuits INV. The inverter circuits INV are connected to a control circuit CT located in a microcontroller unit (MCU), and the inverter circuits are controlled by this control circuit CT. AC power is supplied from the inverter circuits INV controlled by the control circuit CT to the coils CL connected to the corresponding inverter circuits INV. As a result, the motor MOT is driven. <Inverter Circuit Configuration> Next, the circuit structure of the inverter circuit INV, which is a component of the aforementioned 12-phase brushless DC motor control system, will be explained. Figure 2 is a diagram showing the circuit configuration of the inverter circuit INV. In Figure 2, the inverter circuit INV has a high-voltage side switching circuit 10, a low-voltage side switching circuit 20, and a control circuit 30. The high-voltage side switching circuit 10 includes a main transistor 11 made of a power transistor and a sensing transistor 12. On the other hand, the low-voltage side switching circuit 20 includes a main transistor 21 made of a power transistor and a sensing transistor 22. In the high-voltage side switching circuit 10 and the low-voltage side switching circuit 20 configured as described above, the main transistor 11 included in the high-voltage side switching circuit 10 and the main transistor 21 included in the low-voltage side switching circuit 20 are connected in series between the power supply potential VIN and the ground potential GND. In Figure 2, the connection node between main transistor 11 and main transistor 21 is "OUT", and this connection node is connected to the coil CL shown in Figure 1. Next, the control circuit 30 includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor 11 or the gate electrode of the sensing transistor 12, and a pre-driver that applies a gate voltage to the gate electrode of the main transistor 21 or the gate electrode of the sensing transistor 22. The inverter circuit INV is configured as described above. The control circuit 30 is configured to control the on / off state of the main transistor 11 included in the high-voltage side switching circuit 10 and the on / off state of the main transistor 21 included in the low-voltage side switching circuit 20 based on the control signal output from the control circuit CT shown in FIG1. ​​In other words, the control circuit 30 controls the on / off state of the main transistor 11 by switching the gate voltage applied to the gate electrode of the main transistor 11, and controls the on / off state of the main transistor 21 by switching the gate voltage applied to the gate electrode of the main transistor 21. In this way, AC power is supplied from the connection node (“OUT”) between the main transistor 11 and the main transistor 21 to the coil CL shown in FIG1 by means of the on / off control of the main transistor 11 and the main transistor 21. The inverter circuit INV is configured as described above. <Packaging Structure> The installation and configuration of the inverter circuit INV will then be described. Figure 3 is a diagram showing the installation configuration of the semiconductor device PKG that implements the inverter circuit. In Figure 3, the semiconductor device PKG has a hermetically sealed body MR, which has a rectangular planar shape. The hermetically sealed body MR has a long side S1, an opposite side S2, a short side S3 intersecting with both sides S1 and S2, and an opposite side S4. Leads LD protrude from the long sides S1 and S2. In Figure 3, the outline of the seal MR is shown by dashed lines, and the constituent elements sealed within the seal MR are shown. The internal configuration of the seal MR will be described below. The semiconductor device PKG includes a die pad (DPC), a die pad (DPL), and a die pad (DPH) serving as a wafer mounting section. Specifically, the die pads DPL, DPC, and DPH are arranged sequentially in the x-direction. In other words, the die pad DPL is located on the left side, the die pad DPC is located in the center, and the die pad DPH is located on the right side. The semiconductor wafer CPC is mounted on the die pad DPC. The control circuit 30 shown in FIG. 2 is formed on the semiconductor wafer CPC. Multiple pads, including multiple pads PDC1 and multiple pads PDC2, are formed on the surface of the semiconductor wafer CPC. In this way, the semiconductor wafer CPC mounted on the die pad DPC is positioned in the central portion of the semiconductor device PKG. A semiconductor wafer CPL is mounted on a die pad DPL. The low-side switching circuit 20 shown in Figure 2 is formed on the semiconductor wafer CPL. More specifically, a main transistor 21 and a sensing transistor 22 constituting the low-side switching circuit 20 are formed on the semiconductor wafer CPL. Each of the main transistor 21 and the sensing transistor 22 is made of a vertical trench power transistor that allows current to flow in the thickness direction of the semiconductor wafer CPL. Multiple pads PDL are formed on the surface of the semiconductor wafer CPL together with the main transistor source pads SPL. The multiple pads PDL include source pads for the sensing transistor, gate pads shared between the main transistor 21 and the sensing transistor 22, etc. As shown in Figure 3, a clamping member CLL, which is a plate-shaped member made of copper, is provided on the source pad SPL of the main transistor. As shown in Figure 3, the clamping member CLL is electrically connected to the lead LDL. On the other hand, multiple pads PDL are electrically connected to corresponding multiple pads PDC2 formed on the surface of the semiconductor wafer CPC via bonding wires W. Subsequently, the semiconductor wafer CPH is mounted on the die pad DPH. The high-voltage side switching circuit 10 shown in FIG2 is formed on the semiconductor wafer CPH. In this embodiment, the semiconductor wafer CPL on which the low-voltage side switching circuit 20 is formed and the semiconductor wafer CPH on which the high-voltage side switching circuit 10 is formed are the same type of semiconductor wafer. Therefore, the description of the semiconductor wafer CPH is omitted. In this embodiment, the planar shape of the semiconductor device PKG is substantially rectangular (specifically, a rectangle with chamfered corners), as shown in FIG3. In this embodiment, the planar shape of each semiconductor wafer is also rectangular, as shown in FIG3. In this embodiment, as shown in FIG3, the semiconductor wafers CPC, CPL, and CPH are configured such that the short side of the semiconductor wafers is along the long side of the semiconductor device PKG. In this way, the size of the semiconductor wafers and the size of the semiconductor device PKG are reduced. As described above, a semiconductor device PKG made of system-in-package (SiP) is configured to be mounted in a package structure, wherein semiconductor wafers CPC, CPL, and CPH, on which circuits constituting inverter circuit INV are formed, are mounted. <Research on Improvement> Hereinafter, the clamping member CLL will be exemplified as a plate-shaped component, and the potential for improvement of the semiconductor device PKG will be explained. However, as shown in Figure 3, the semiconductor device PKG also has a clamping member CLH in addition to the clamping member CLL. Both the clamping member CLH and the clamping member CLL have similar potential for improvement. However, the following description focuses on the clamping member CLL to describe the potential for improvement of the semiconductor device PKG. In the aforementioned semiconductor device PKG, from the viewpoint of improving heat dissipation efficiency, in some cases, a configuration is adopted in which the back side of the die pads DPL (die pads DPC, die pads DPH) is exposed from the lower surface of the seal MR, in order to improve heat dissipation efficiency. The inventors have recently discovered that a semiconductor device PKG with this configuration has the following potential for improvement. Figure 4 is a diagram illustrating the newly discovered improvement by the inventors and is a cross-sectional view showing the molding steps for forming the seal body MR. In Figure 4, leads 60A and 60B, present in the lead frame, are sandwiched between lower mold 70A and upper mold 70B. In the cavity CAV, a die pad DPL, a semiconductor wafer CPL mounted on the die pad DPL via silver paste 50A, and a clamping member CLL mounted on the main transistor source pad SPL formed on the semiconductor wafer CPL via silver paste 50B are provided. The clamping member CLL is connected to the lead 60A via silver paste 50C. In other words, the clamping member CLL has the function of electrically connecting the main transistor source pad SPL and the lead 60A. In the molding step shown in Figure 4, a seal is formed by injecting resin into the cavity CAV. In this step, if a gap exists between the lower mold 70A and the die pad DPL in Figure 4, resin will also flow into this gap. Therefore, to prevent the formation of a gap between the lower mold 70A and the die pad DPL that allows resin to flow into, for example, the molding step is performed while applying pressure from the lower mold 70A towards the die pad DPL toward the cavity CAV, as shown in Figure 4. In this configuration, leads 60A and 60B are clamped and fixed between the lower mold 70A and the upper mold 70B. Meanwhile, the die pad DPL is pressed into the cavity CAV by the aforementioned pressing force. As a result, the "offset X," representing the height difference between leads 60A (60B) and the die pad DPL shown in FIG. 4, decreases. Then, a force is applied in the direction indicated by the arrow in FIG. 4 to the clamping member CLL connecting leads 60A and the semiconductor wafer CPL. As a result, for example, as shown in Figure 5, the clamping member CLL deforms. Specifically, the clamping member CLL, which connects to both lead 60A and the main transistor source pad SPL formed on the semiconductor wafer CPL, is typically positioned parallel to the semiconductor wafer CPL. However, as shown in Figure 5, the deformation that causes the end of the clamping member CLL to be higher than the root of the clamping member CLL is caused by the pressing force applied to the die pad DPL as described above. In this specification, the shape in which the end of the clamping member CLL is higher than the root of the clamping member CLL, as shown in Figure 5, is referred to as "negative tilt". In this way, during the molding step of manufacturing the semiconductor device PKG for exposing the back side of the die pad DPL from the lower surface of the seal MR, a pressing pressure is applied from the lower mold 70A toward the die pad DPL toward the cavity CAV to prevent the formation of a gap between the lower mold 70A and the die pad DPL that would allow resin to flow into it. As a result, for example, as shown in FIG5, the shape of the clamping member CLL becomes "negatively tilted". When the shape of the clamping member CLL is "negatively tilted", a portion of the silver paste 50B that contacts the root 80 of the clamping member CLL becomes thinner than the rest of the silver paste 50B. As a result, due to the structural stress applied to the semiconductor device, for example, a portion 90 of the silver paste 50B shown in FIG. 5 peels off. Regarding this, the silver paste 50B functions to electrically connect the clamping member CLL and the main transistor source pad SPL formed on the semiconductor wafer CPL, and serves as a current path through which current flows. Therefore, when the silver paste 50B, as a current path, is peeled off, the peeled area becomes a high-impedance region, resulting in a higher on-resistance of the semiconductor device. Furthermore, in the case of a semiconductor device with a sensing transistor mounted on it, this causes a change in the sensing ratio. In other words, the peeling off of the silver paste 50B adversely affects the performance of the semiconductor device. Therefore, it is desirable to suppress the "negative tilt" of the clamping member CLL that causes the peeling off of the silver paste 50B. <Description of related technologies> The following techniques exist for suppressing the "negative tilt" of the clamping component CLL. The “related technologies” described in this specification are not publicly known technologies, but rather technologies in which the inventors have discovered problems, and which are the premise of this invention. Figure 6 is a schematic diagram used to illustrate the relevant technology. As shown in Figure 6, in related technologies, the end of the clamping member CLL is pre-shaped to be lower than the root of the clamping member CLL. Here, in this specification, the shape shown in Figure 6, in which the end of the clamping member CLL becomes lower than the root of the clamping member CLL, is referred to as "positive tilt". In this way, in related technologies, the clamping member CLL is shaped into a "positive tilt" by pre-processing the clamping member CLL. As a result, according to the relevant technology, even when applying a pressing pressure towards the cavity CAV from the lower mold 70A to the die pad DPL to prevent the formation of a gap between the lower mold 70A and the die pad DPL where resin flows in, the shape of the clamping member CLL can be suppressed from having a "negative tilt" caused by the pressing pressure because the shape of the clamping member CLL is pre-designed to be "positively tilted" rather than flat. Therefore, the relevant technology is effective from the viewpoint of suppressing the "negative tilt" of the clamping member CLL, which is the cause of the peeling of the silver paste 50B. Here, for example, as a method to shape the clamping member CLL into having a "positive tilt," deformation processing of the clamping member CLL is conceivable. However, according to the inventors' research, the maximum processing accuracy of the clamping member CLL is ±20 μm, making it difficult to shape the clamping member CLL into a stable "positive tilt." In other words, from the viewpoint of suppressing the "negative tilt" of the clamping member CLL, which is the cause of the peeling of the silver paste 50B, the concept of pre-forming the clamping member CLL into a "positive tilt" is advantageous. However, from the viewpoint of stable processing of the clamping member CLL, the related technology has disadvantages. As described above, the related technologies have room for improvement. Therefore, in this embodiment, a design was implemented to address the aforementioned shortcomings in the related technologies. The technical concept of this embodiment of the present invention will be explained below. <Basic Idea of ​​the Implementation Examples> The basic idea of ​​this embodiment is to pre-shape the clamping member CLL with a "positive tilt," and to provide a protruding member in a portion of the surface of the main transistor source pad SPL when the "positively tilted" clamping member CLL is connected to the main transistor source pad SPL via silver paste 50B, with the protruding member contacting the "positively tilted" clamping member CLL. According to this basic idea, the "positively tilted" clamping member CLL can be supported by the protruding member. As a result, the "positive tilt" state of the clamping member CLL can be stably maintained. Therefore, even if the "positive tilt" varies depending on the processing accuracy of the clamping member CLL, a stable "positive tilt" can be achieved through the corrective effect of the contact of the protruding member. The following will describe specific models that embody this basic idea. <Specific Mode> Figure 7 is a schematic diagram used to illustrate the specific pattern. Specifically, the upper diagram in Figure 7 is a plan view, and the lower diagram in Figure 7 is a cross-sectional view. As shown in Figure 7, the semiconductor wafer CPL is mounted on the die pad DPL via silver paste 50A. The main transistor source pad SPL (first electrode) is formed on the surface of the semiconductor wafer CPL, and the peripheral portion of the main transistor source pad SPL is covered by a protective film PAS. In other words, the surface of the main transistor source pad SPL not covered by the protective film PAS is exposed. Lead 60A is positioned next to the semiconductor wafer CPL to separate it from the die pad DPL. Here, the term "separated" means "separated in distance," and indicates, for example, that the die pad DPL and lead 60A are separated from each other in distance, as shown in Figure 7. The main transistor source pad SPL and lead 60A are electrically connected by a clamping member CLL, which is a plate-like member made of copper. Specifically, the clamping member CLL is electrically connected to the main transistor source pad SPL via silver paste 50B and to lead 60A via silver paste 50C. The clamping member CLL consists of a "first portion P1" in contact with silver paste 50B, a "second portion P2" in contact with silver paste 50C, and a "third portion P3" located between the "first portion P1" and the "second portion P2". Here, the "first portion P1" of the clamping member CLL is tilted such that as the "first portion P1" gets closer to the "third portion P3" of the clamping member CLL, the distance between the "first portion P1" and the upper surface of the seal body decreases. In other words, the "first portion P1" of the clamping member CLL has a "positive tilt" in which the end of the clamping member CLL is lower than the root of the clamping member CLL. Here, although not shown in Figure 7, the structure shown in Figure 7 is sealed with a sealing body. For example, the sealing body has an upper surface and a lower surface on the opposite side of the upper surface, and seals the semiconductor wafer CPL and the clamping member CLL such that while a portion of the lead 60A is exposed, a portion of the back side of the die pad DPL is exposed from the lower surface. In the structure shown in Figure 7, a protruding member 100 is formed on the surface of the main transistor source pad SPL exposed from the protective film PAS, protruding towards the upper surface of the seal body compared to the protective film PAS. In other words, in the thickness direction of the semiconductor wafer CPL, the height from the surface of the main transistor source pad SPL to the upper surface of the protruding member 100 is greater than the height from the surface of the main transistor source pad SPL to the upper surface of the protective film PAS. Here, as shown in Figure 7, the "first portion P1" of the clamping member CLL contacts the protruding member 100. The material constituting the protruding member 100 is not particularly limited, and for example, it is made of an insulating material. In Figure 7, the planar shape of the main transistor source pad SPL is a quadrilateral (polygon), in which a "first side SD1" intersects with the "third part P3" of the clamping member CLL and a "second side SD2" is located on the opposite side of the "first side SD1" in the plan view, and the protruding member 100 is located closer to the "first side SD1" than the "second side SD2" in the plan view. <<Size Relationships>> An example of dimensional relationships will then be provided. Figure 8 is a diagram illustrating an example of dimensional relationships. As shown in Figure 8, regarding the surface of the main transistor source pad SPL, in a first direction extending from one side of the "first side SD1" and the "second side SD2" to the other, the main transistor source pad SPL has a "first region R1" that is closer to the "first side SD1" than the center line CL, and a "second region R2" that is closer to the "second side SD2" than the center line CL. Here, as shown in Figure 8, the protruding member 100 is provided in the "first region R1" and is separated from the boundary of the "first region R1" and the "second region R2" as the center line CL. Next, in Figure 8, the planar shape of the protruding member 100 is square. As shown in the enlarged view of the protruding member 100 surrounded by region RA, the protruding member 100 is, for example, composed of a silicon oxynitride film 110 (thickness: about 0.9 μm), a first polyimide film 120 (thickness: about 8 μm) formed on the silicon oxynitride film 110, and a second polyimide film 130 (thickness: about 8 μm) formed on the first polyimide film 120. Note that the silicon oxynitride film 110 can be a silicon nitride film (SiN), a silicon carbonitride film (SiCN), etc., or further, it can be a multi-type laminated film including silicon oxide films. Here, the dimensions shown in Figures 7 and 8 are described below. (1) “A0” = 3mm (2) “A1” = 1mm (3) “A2” = 2mm (4) “L” = 70μm (5) “L1” = 20μm (6) “L2” = 10μm (7) “L3” = 15μm Consider the thickness of the following membrane as described below. Nitrogen oxide silicon film 110: 0.9μm First polyimide membrane 120: 8μm Second polyimide membrane 130: 8μm The dimensions shown in Figures 9 and 10 are described below. (8) "A" = approximately 10 μm (9) "B" = 10.35 μm (10) "C" = 6.9 μm <<Characteristics of the Structure of a Specific Pattern>> Next, we will describe the feature points of the specific pattern. The key feature of this embodiment is the protruding member 100, for example, having the layout and dimensions shown in Figures 7 to 10. This protruding member is positioned in a portion of the surface of the main transistor source pad SPL, and contacts a clamping member CLL with a positive tilt. In this way, since the clamping member CLL with a positive tilt can be supported by the protruding member 100, the positive tilt of the clamping member CLL can be stably maintained. Therefore, even if the positive tilt changes depending on the processing accuracy of the clamping member CLL, the change in positive tilt is corrected by the correction effect caused by the contact of the protruding member 100, and thus, a stable positive tilt can be achieved. In this way, this embodiment can suppress the negative tilt of the clamping member CLL caused by pressing pressure and can prevent the peeling of the silver paste 50B. In other words, this embodiment provides an excellent effect of improving the reliability of the semiconductor device by preventing the peeling of the silver paste 50B. Furthermore, for example, as shown in FIG8, this embodiment also has the feature that the protruding member 100 is made of a laminated film including a first polyimide film 120 and a second polyimide film 130. This is because, even if stress is generated during the molding step due to the pressing pressure applied to the die pad DPL, the protruding member 100, which is in contact with the clamping member CLL, is configured to include a polyimide film with cushioning properties, thus the protruding member 100 can be used as a buffer against stress. As described above, the protruding member 100 has the function of achieving a stable "positive tilt" of the clamping member CLL and the function of acting as a buffer to absorb stress. This embodiment is of significant technical importance in effectively suppressing the peeling of the silver paste 50B caused by stress generated during the molding step through the synergistic effect of these functions. Furthermore, in this embodiment, the protruding member 100 is provided, for example, at the position of "A2:A1=2:1" shown in FIG. 7. According to a recent discovery by the inventors, the position of "A2:A1=2:1" is the location where the silver paste 50B is most likely to peel off. Therefore, in this embodiment, considering the aforementioned recent discovery, the protruding member 100 is provided at the location where the silver paste 50B is most likely to peel off. In this way, in this embodiment, since the silver paste 50B is not present at the location where peeling is most likely, the possibility of the silver paste 50B peeling off can be reduced, and thus the reliability of the semiconductor device can be improved. <<Methods for Manufacturing Semiconductor Devices>> Next, the method for manufacturing a semiconductor device according to this embodiment will be described. <<Steps for Manufacturing Semiconductor Wafers>> First, a semiconductor wafer (WF) with multiple wafer regions is fabricated. Then, using conventional semiconductor manufacturing processes, power transistors, including main transistors and sensing transistors, are formed in the wafer regions. Next, a main transistor source pad (SPL) is formed on the surface of each wafer region of the semiconductor wafer (WF), as shown in Figure 11. This main transistor source pad (SPL) is, for example, made of aluminum. Note that Figures 11 through 14 below show one of the multiple wafer regions included in a semiconductor wafer (WF). Next, as shown in Figure 12, a silicon oxynitride film 110 covering the main transistor source pad SPL is formed, for example, using chemical vapor deposition (CVD). Then, the silicon oxynitride film 110 is patterned using photolithography and etching techniques. During the patterning of the silicon oxynitride film 110, as shown in Figure 12, the peripheral portion of the main transistor source pad SPL is covered, while the silicon oxynitride film 110 in the protruding member formation region of the main transistor source pad SPL is retained. In this patterning, other areas of the main transistor source pad SPL are exposed. Subsequently, after applying the first polyimide film 120 to the entire surface of the semiconductor wafer WF, the first polyimide film 120 is patterned using photolithography. During the patterning of the first polyimide film 120, for example, as shown in FIG13, the first polyimide film 120 on the silicon oxynitride film 110 formed on the peripheral portion of the main transistor source pad SPL is retained, while the silicon oxynitride film 110 formed in the protruding member formation region is covered. As a result, a protective film PAS composed of a laminate of the silicon oxynitride film 110 and the first polyimide film 120 is formed at the peripheral portion of the main transistor source pad SPL. Then, for example, a curing process is performed on the patterned first polyimide film 120. Then, after applying the second polyimide film 130 to the entire surface of the semiconductor wafer WF, the second polyimide film 130 is patterned using photolithography, as shown in FIG14. In the patterning of the second polyimide film 130, for example, as shown in FIG14, the first polyimide film 120 formed in the protrusion member formation region of the main transistor source pad SPL is covered, while the second polyimide film 130 in other regions is removed. As a result, a protrusion member 100 made of a laminate of silicon oxynitride film 110, first polyimide film 120, and second polyimide film 130 is formed in the protrusion member formation region of the main transistor source pad SPL. Then, for example, a curing process is performed on the patterned second polyimide film 130. Note that in the patterning of the second polyimide film 130 in this embodiment, as shown in FIG14, the first polyimide film 120 formed in the protruding member formation region of the main transistor source pad SPL is covered, while the second polyimide film 130 in other regions is removed. However, the patterning of the second polyimide film 130 is not limited to this, but can be performed such that, for example, the second polyimide film 130 formed on the first polyimide film 120 at the peripheral portion is also retained. In this case, the protective film PAS is also made of a laminate of silicon oxynitride film 110, first polyimide film 120 and second polyimide film 130. Then, as needed, a coating such as a nickel film, palladium film, or gold film is formed on the exposed surface of the source pad SPL of the main transistor using a non-electrolytic plating method. After a back-side grinding step on the semiconductor wafer WF, the semiconductor wafer WF is diced. As a result, multiple wafer regions of the semiconductor wafer WF are diced and divided into multiple semiconductor wafers. In this way, the semiconductor wafer of this embodiment can be manufactured. <<<Steps for Assembling a Semiconductor Device>>> The steps for assembling a semiconductor device will be explained next. Figure 15 is a flowchart illustrating the assembly steps of a semiconductor device. First, a die pad and a lead frame having leads separate from the die pad are prepared. Then, the semiconductor wafer manufactured by the above-described semiconductor wafer manufacturing steps is mounted on the die pad. Specifically, after applying silver paste to the die pad, the semiconductor wafer is mounted on the die pad via the silver paste (S101). Next, silver paste is applied to the leads and source pads of the main transistor formed on the surface of the semiconductor wafer (S102). Then, a clamping member is provided to connect the source pads of the main transistor and the leads. In this step, the clamping member is connected to the source pads of the main transistor via silver paste, and also to the leads via silver paste. As a result, the source pads of the main transistor and the leads are electrically connected to each other through the clamping member (S103). Next, a curing step (heat treatment at approximately 150°C to 300°C) is performed to harden the silver paste (S104). Subsequently, for example, leads and other pads formed on the surface of the semiconductor wafer are connected to each other by gold wires or conductive wires. In other words, gold wires or copper wires are used to wire bond the leads and other pads formed on the surface of the semiconductor wafer (S105). Then, a sealing body is formed by resin sealing (molding) (S106). Next, as needed, a plating layer is formed on the outer lead portion of the leads exposed from the sealing body. Then, outside the sealing body, the leads are cut at predetermined positions to separate the sealing body from the lead frame. Subsequently, the outer lead portion of the leads protruding from the sealing body is processed to bend. In this manner, a semiconductor device can be manufactured. <<Characteristics of Manufacturing Methods>> In this embodiment, the structure shown in FIG16 is implemented through step S103 of FIG15. In other words, in FIG16, the clamping member CLL is composed of a "first portion P1" that contacts the silver paste 50B, a "second portion P2" that contacts the silver paste 50C, and a "third portion P3" located between the "first portion P1" and the "second portion P2". In step S103 of FIG15, the clamping member CLL is disposed on the main transistor source pad SPL and the lead 60A with the "first portion P1" in a positive tilt state, wherein the height of the protruding member 100 is higher than the height of the portion between the end of the clamping member CLL included in the "first portion P1" and the surface of the main transistor source pad SPL caused by the contact between the "first portion P1" and the protruding member 100. In this way, the clamping member CLL with a "positive tilt" can be supported by the protruding member 100. As a result, the "positive tilt" state of the clamping member CLL can be stably maintained. Therefore, even if the "positive tilt" varies depending on the processing accuracy of the clamping member CLL, a stable "positive tilt" can be achieved, and the change in "positive tilt" can be corrected by the correction effect caused by the contact of the protruding member 100. Here, a key feature of the manufacturing method in this embodiment is that the protruding member 100 is formed using the protective film PAS forming step shown in Figures 11 to 14. This only requires adding the steps of forming the second polyimide film 130 and patterning the second polyimide film 130, thus reducing the burden of adding a new step to form the protruding member 100. Therefore, one advantage provided is the ease of forming the protruding member 100. In particular, in this manufacturing method, the height of the protruding member 100 can be easily adjusted by adjusting the film thickness of the second polyimide film 130. Next, in this embodiment, step S106 of FIG15 is performed as shown in FIG17. FIG17 is a schematic diagram showing the resin sealing step (molding step) of this embodiment. As shown in FIG17, the resin sealing step (S106) of this embodiment includes the following steps: clamping the lead frame obtained after the clamping member connection step (S103) between the lower mold 70A and the upper mold 70B to form a cavity space CAV; and forming a seal by allowing resin to flow into the cavity space CAV. In this step, while applying a force to press the die pad DPL into the cavity space CAV through the lower mold 70A, the step of clamping the lead frame between the lower mold 70A and the upper mold 70B is performed. In the resin sealing step configured as described above, the intrusion of the resin into the portion between the downward mold 70A and the die pad DPL can be suppressed by applying the aforementioned pressing pressure. However, when a pressing force is applied from the lower mold 70A toward the die pad DPL toward the cavity CAV to prevent the formation of a gap between the lower mold 70A and the die pad DPL that allows resin to flow into it, if no measures are taken, the clamping member CLL will be shaped with a “negative tilt” as shown in Figure 5, resulting in the risk of silver paste 50B peeling off. In this regard, in the clamping member connection step (S103) of this embodiment, a clamping member CLL that already has a "positive tilt" is used, and the "positive tilt" of the clamping member CLL is stably maintained by the protruding member 100. As a result, even when a force is applied in the resin sealing step to press the die pad DPL into the cavity space CAV, this embodiment can suppress the "negative tilt" of the clamping member CLL. Therefore, this embodiment can suppress the "negative tilt" of the clamping member CLL, and thus, can suppress the peeling of the silver paste 50B caused by the "negative tilt" of the clamping member CLL. Therefore, this embodiment can improve the reliability of the semiconductor device. <First Modification Example> Figures 18A to 18G are diagrams showing the changes in the planar shape of the protruding member 100. In the above embodiments, an example in which the planar shape of the protruding member 100 is a "square" is described (refer to FIG. 7). However, the planar shape of the protruding member 100 is not limited to this, but can be formed to have shapes such as "rectangle", "circle", "triangle" or "polygon", as shown in FIG. 18A to FIG. 18G. <Second Modification Example> In the above embodiments, an example has been described in which the protruding member 100 is made of a laminate of a silicon oxynitride film 110, a first polyimide film 120, and a second polyimide film 130. However, the protruding member 100 is not limited thereto, but may be made of a so-called "permanent resist". "Permanent resist" is a type of resist used to leave a residue after processing (development), and is used, for example, in the fabrication of mechanical and electrical systems (MEMS). Conventional resists are removed (by ashing) after being patterned using a photolithography exposure and development process, and are then used in etching processes on the target film. "Permanent resist," on the other hand, is a type of resist used to leave a residue without ashing. As an advantage of forming the protruding member 100 with the "permanent resist" as described above, the ease of forming the protruding member 100 with an optional height equal to or greater than 10 μm can be exemplified. This is because, by adjusting the viscosity of the resist and the coating speed, the "permanent resist" can achieve an optional film thickness in the range of several μm to hundreds of μm. In a manufacturing method for forming a protruding member 100 made of a "permanent resist", for example, a protective film PAS is formed covering the peripheral portion of the main transistor source pad SPL, and then a "permanent resist" thicker than the protective film PAS is applied. This formation can then be achieved by patterning the "permanent resist" using photolithography so that the "permanent resist" remains only in the protruding member formation area on the exposed surface of the main transistor source pad SPL. Note that the protruding member 100 may be made of a laminate of, for example, a "permanent resist" and a polyimide film with excellent cushioning properties. <Third Modification Example> Figure 19 is a diagram showing an example of the configuration of the prominent component in the third modified example. As shown in Figure 19, this third modified example illustrates an example of multiple protruding members. Specifically, in Figure 19, protruding members 100A and 100B are provided, arranged along the y-direction. This configuration improves the stability of the arrangement of the clamping member CLL. Figure 20 is a diagram showing another configuration example of the prominent component in the third modified example. As shown in Figure 20, in another configuration example, an example is illustrated where the planar shape of the protruding member 100 is a rectangle with a short side in the x-direction and a long side in the y-direction. This configuration can improve the stability of the arrangement of the clamping member CLL. <Fourth Modification Example> In the basic idea of ​​the above embodiments, the constituent material of the protruding member can be either a conductive material or an insulating material, and there are no particular limitations. However, in a specific model embodying the basic idea, the constituent material of the protruding member 100 is an insulating material. Regarding this, if the protruding member 100 is made of a conductive material, it is considered difficult to form the protruding member 100 into the desired shape (size) and difficult to form the protruding member 100 by appropriately utilizing conventional manufacturing steps. On the other hand, if the protruding member 100 is made of an insulating material, the protruding member 100 can be easily formed, for example, by utilizing the step of forming a protective film PAS as shown in Figures 11 to 14. Therefore, although both conductive materials and insulating materials can be used as materials for the protruding member 100, it is desirable to make the protruding member 100 from an insulating material considering the ease of actual manufacturing. However, if the protruding member 100 is made of an insulating material, then the protruding member 100 made of insulating material is placed on the silver paste 50B that serves as the current path. This means that the current path is narrowed, and therefore there is a risk of performance degradation of the semiconductor device, represented by an increase in on-resistance. In particular, if the protruding member 100 is placed in a position where "A1:A2=1:2", as shown in FIG7, since the protruding member 100 is placed in a position where peeling is likely to occur, it is considered to be very effective in preventing peeling. On the other hand, the protruding member 100 becomes a major obstacle to the current path. Therefore, in this fourth modified example, the configuration of the protruding member 100 was studied with particular attention to methods for minimizing the obstruction to the current path. The following describes a fourth modification example of the present invention. Figure 21 is a schematic diagram illustrating this fourth modification example. In Figure 21, the clamping member CLL has a "first portion P1" that contacts the silver paste 50B, a "second portion P2" that contacts the silver paste 50C, and a "third portion P3" located between the "first portion P1" and the "second portion P2". A protruding member 100 that contacts the "third portion P3" is formed on a protective film PAS formed at the root of the clamping member CLL. In this way, in this fourth modified example, the protruding member 100 is not provided at the position contacting the "first portion P1", as shown in Figure 7, but is provided at the position contacting the "third portion P3", as shown in Figure 21. Here, the protruding member 100 is formed on the protective film PAS, which is composed of a laminated film of silicon oxynitride film 110 and a first polyimide film 120, and the protruding member 100 is composed of a laminated film of a second polyimide film 130 and a third polyimide film 140. In this case, the film thickness is as follows: (1) Nitrogen oxide silicon film 110: film thickness 0.9 μm (2) First polyimide film 120: film thickness 8μm (3) Second polyimide membrane 130: membrane thickness 8μm (4) Third polyimide membrane 140: membrane thickness 8μm Therefore, the total height of the protective film PAS and the protruding member 100 is 24.9 μm, ensuring sufficient height. In this way, this fourth modified example allows the clamping member CLL with a "positive tilt" to be supported by the protruding member 100, while configuring the "third part P3" and the protruding member 100 to contact each other, without allowing the protruding member 100 to contact the "first part P1" which contacts the silver paste 50B. As a result, the "positive tilt" state of the clamping member CLL can be stably maintained. In particular, in this fourth modified example, since the protruding member 100 is provided to avoid the formation area of ​​the silver paste 50B, the obstruction of the current path of the silver paste 50B by the protruding member 100 is suppressed. As a result, this fourth modified example allows the clamping member CLL with a "positive tilt" to be supported by the protruding member 100, while suppressing the increase in on-resistance. <Fifth Revision Example> In the above embodiments, a structure in which the surface of the die pads DPL (die pads DPC, die pads DPH) is exposed from the lower surface of the seal MR has been described as an example. However, the basic idea of ​​the above embodiments is not limited to this, but can be applied to, for example, a configuration in which the surface of the die pads DPL (die pads DPC, die pads DPH) is exposed from the upper surface of the seal MR. In the configuration of this fifth modified example, the resin sealing step (molding step) can be performed in a configuration in which the exposed surface of the die pad DPL contacts the upper mold or in a configuration in which the exposed surface of the die pad DPL contacts the lower mold. In the above embodiments, the die pad DPL is exposed from the lower surface of the seal, and the protruding member 100 is configured to protrude towards the upper surface of the seal. On the other hand, in this fifth modified example, the die pad DPL is exposed from the upper surface of the seal, and the protruding member 100 is configured to protrude towards the lower surface of the seal. In the claims, the terms "first surface" and "second surface" are used so that this specification includes the configuration of the above-described embodiments and the configuration of this fifth modified example. In the configuration of the above-described embodiments, "first surface" corresponds to the lower surface and "second surface" corresponds to the upper surface. On the other hand, in the configuration of this fifth modified example, "first surface" corresponds to the upper surface and "second surface" corresponds to the lower surface. The invention has been described above with reference to specific embodiments. However, it should be noted that the invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the invention. The above embodiments have been described assuming that a power MOSFET is used as a power transistor formed on a semiconductor wafer. However, the technical concept of the above embodiments is not limited thereto, but can be widely applied to semiconductor devices, for example, using insulated gate bipolar transistors (IGBTs) as power transistors. In this context, "transistor source pad" is replaced with "transistor emitter pad". In the embodiments, "first electrode" is used as a term encompassing both "transistor source pad" and "transistor emitter pad". In other words, the "first electrode" described in the embodiments is used to include both "transistor source pad" and "transistor emitter pad". The above embodiments are illustrated using silver paste as an example. However, the technical concept of the above embodiments is not limited to this, but can be widely applied to semiconductor devices, for example, those using solder. In the claims, terms such as "first conductive material" and "second conductive material" are used to include both "silver paste" and "solder". In other words, the "first conductive material" and "second conductive material" described in the embodiments are used to include both "silver paste" and "solder". 10: High-voltage side switching circuit 11: Main transistor 12: Sensing transistor 20: Low-voltage side switching circuit 21: Main transistor 22: Sensing transistor 30: Control circuit 50A: Silver paste 50B: Silver paste 50C: Silver paste 60A: Lead wire 60B: Lead wire 70A: Lower mold 70B: Upper mold 80: Root 90: Part 100: Protruding member 100A: Protruding member 100B: Protruding member 110: Silicon oxynitride film 120: First polyimide film 130: Second polyimide film 140: Third polyimide film CAV: Cavity CL: Coil CLH: Clamping member CLL: Clamping member CPC: Semiconductor crystal CPH: Semiconductor wafer CPL: Semiconductor CT: Control Circuit; DPC: Die Pad; DPH: Die Pad; DPL: Die Pad; GND: Ground Potential; INV: Inverter Circuit; LD: Lead; LDL: Lead; MOT: Motor; MR: Seal; PAS: Protective Film; PDC1: Pad; PDC2: Pad; PDL: Pad; PKG: Semiconductor Device; RA: Region; R1: First Region; R2: Second Region; SD1: First Side; SD2: Second Side; SPL: Main Transistor Source Pad; S1: Side; S2: Side; S3: Side; S4: Side; S101: Step; S102: Step; S103: Step; S104: Step; S105: Step; S106: Step; VIN: Power Supply Potential; WF: Semiconductor Wafer Figure 1 is a schematic diagram showing the configuration of a 12-phase brushless DC motor control system; Figure 2 is a diagram showing the circuit configuration of the inverter circuit; Figure 3 is a diagram showing the installation configuration of the semiconductor device that implements the inverter circuit; Figure 4 is a diagram illustrating the improved space newly discovered by the inventors, and is a cross-sectional view showing the molding steps for forming the seal. Figure 5 is a diagram showing the state in which the clamping element has a "negative tilt"; Figure 6 is a schematic diagram illustrating the relevant technology; Figure 7 is a schematic diagram illustrating a specific mode; Figure 8 is an example diagram used to illustrate dimensional relationships; Figure 9 is an example diagram used to illustrate dimensional relationships; Figure 10 is an example diagram used to illustrate dimensional relationships; Figure 11 is a cross-sectional view showing the manufacturing steps of a semiconductor wafer; Figure 12 is a cross-sectional view showing the manufacturing steps of the semiconductor wafer following Figure 11; Figure 13 is a cross-sectional view showing the manufacturing steps of the semiconductor wafer following Figure 12; Figure 14 is a cross-sectional view showing the manufacturing steps of the semiconductor wafer following Figure 13; Figure 15 is a flowchart illustrating the assembly steps of a semiconductor device; Figure 16 is a diagram illustrating the connection steps of the clamping member in Figure 15; Figure 17 is a diagram illustrating the resin sealing steps of Figure 15; Figure 18A is a diagram showing the planar changes of the protruding member; Figure 18B is a diagram showing the planar variation of the protruding member; Figure 18C is a diagram showing the planar variation of the protruding member; Figure 18D is a diagram showing the planar changes of the protruding member; Figure 18E is a diagram showing the planar variation of the protruding member; Figure 18F is a diagram showing the planar variation of the protruding member; Figure 18G is a diagram showing the planar variation of the protruding member; Figure 19 is a diagram illustrating an example of the configuration of the prominent component in the third modified example; Figure 20 is a diagram illustrating another configuration example of the prominent component in the third modified example; and Figure 21 is a schematic diagram illustrating the fourth modification example. CLH: Clamping component CLL: Clamping component CPC: Semiconductor Crystal CPH: Semiconductor wafer CPL: Semiconductor wafer DPC: Die Pad DPH: Die Pad DPL: Die Pad GND: Grounding potential LD: Lead wire LDL: Lead wire MR: Sealing body PDC1: Pad PDC2: Pad PDL: Pads PKG: Semiconductor Device SPL: Transistor source pad S1: Edge S2: Edge S3: Edge S4: Edge VIN: Power supply potential

Claims

1. A semiconductor device comprising: a die solder pads; A semiconductor wafer includes a first electrode and a protective film covering a peripheral portion of the first electrode, the semiconductor wafer being mounted on a die pad; a lead disposed adjacent to the semiconductor wafer and separated from the die pad; a plate-like member electrically connected to the first electrode and the lead; and a sealing body having a first surface and a second surface opposite to the first surface, the sealing body sealing the semiconductor wafer and the plate-like member such that a portion of the die pad is exposed from the first surface and a portion of the lead is exposed, wherein the plate-like member is electrically connected to the first electrode via a first conductive material and electrically connected to the lead via a second conductive material, wherein the plate-like member includes: a first portion in contact with the first conductive material; and a second portion in contact with the second conductive material. And a third portion, located between the first portion and the second portion, wherein a protruding member is formed on the surface of the first electrode exposed from the protective film, protruding toward the second surface compared to the protective film, wherein the first portion contacts the protruding member, and wherein in a cross-sectional view, the first portion is inclined such that the distance between the first portion and the second surface decreases as the first portion gets closer to the third portion.

2. The semiconductor device of claim 1, wherein the planar shape of the first electrode is multi-sided, the multi-sided shape having: a first side, which intersects with the third part in a plan view; and a second side, which is opposite to the first side, and wherein, in a plan view, the protruding member is disposed closer to the first side than the second side.

3. The semiconductor device of claim 2, wherein, in a first direction extending from either the first side or the second side to the other side, the surface of the first electrode has: a first region located closer to the first side than the centerline of the first electrode; and a second region located closer to the second side than the centerline of the first electrode, wherein the protruding member is disposed in the first region and separated from the side boundary between the second region and the first region, which serves as the centerline.

4. The semiconductor device of claim 1, wherein the aforementioned protruding member is an insulating member.

5. The semiconductor device of claim 4, wherein the protective film comprises a first polyimide resin film, and wherein the protruding member comprises: The aforementioned first polyimide resin film; And a second polyimide resin film, formed on the first polyimide resin film.

6. The semiconductor device of claim 4, wherein the aforementioned protruding member is made of a permanent photoresist.

7. The semiconductor device of claim 1, wherein the number of the aforementioned protruding members is plurality of.

8. The semiconductor device of claim 1, wherein the plate-shaped member is a clamping member made of copper.

9. A semiconductor device comprising: a die solder pads; A semiconductor wafer includes a first electrode and a protective film covering a peripheral portion of the first electrode, the semiconductor wafer being mounted on a die pad; a lead disposed adjacent to the semiconductor wafer and separated from the die pad; a plate-like member electrically connected to the first electrode and the lead; and a sealing body having a first surface and a second surface opposite to the first surface, the sealing body sealing the semiconductor wafer and the plate-like member such that a portion of the die pad is exposed from the first surface and a portion of the lead is exposed, wherein the plate-like member is electrically connected to the first electrode via a first conductive material and to the lead via a second conductive material, wherein the plate-like member includes: a first portion in contact with the first conductive material; and a second portion in contact with the second conductive material. And a third part, located between the first part and the second part, wherein a protruding member is formed on the protective film, and the third part contacts the protruding member.

10. A method of manufacturing a semiconductor device, the method comprising the steps of: (a) preparing a lead frame including a die pad and leads separate from the die pad; (b) preparing a semiconductor wafer including a first electrode, a protective film covering a peripheral portion of the first electrode, and a protruding member formed on a surface of the first electrode exposed from the protective film; (c) mounting the semiconductor wafer on the die pad; (d) forming a first conductive material on the first electrode and forming a second conductive material on the leads; (e) providing a first portion of a plate-like member on the first electrode via the first conductive material, and providing a second portion of the plate-like member on the leads via the second conductive material, thereby electrically connecting the first electrode and the leads to each other via the plate-like member; and (f) sealing the semiconductor wafer and the plate-like member, wherein the plate-like member has: the first portion, the first conductive material being in contact with the first portion; The second part, the second conductive material is in contact with the second part; and the third part is located between the first part and the second part, wherein by contacting the first part or the third part with the protruding member in step (e), the plate-shaped member is positioned in a state in which the first part is positively inclined, such that in a cross-sectional view, the height of the portion between the end of the plate-shaped member included in the first part and the surface of the first electrode is lower than the height of the protruding member, wherein step (f) includes the following steps: (f1) after step (e), clamping the lead frame between the first mold and the second mold opposite to the first mold, such that a cavity space is formed between the first mold and the second mold; and (f2) forming a seal by allowing resin to flow into the cavity space, and wherein while performing step (f1), a force is applied by the first mold to press the die pad into the cavity space.

11. The method of manufacturing the semiconductor device as claimed in claim 10, wherein in step (f1), the resin is prevented from entering the gap between the first mold and the die pad.

12. The method of manufacturing the semiconductor device as claimed in claim 10, wherein by giving the first portion the positive tilt in step (e), the negative tilt of the first portion is suppressed even when the force that presses the die pad into the cavity space is applied in step (f).

13. The method of manufacturing the semiconductor device as claimed in claim 10, wherein the semiconductor wafer prepared in step (b) is provided by the following steps (b1) to (b4): (b1) forming the first electrode on each of a plurality of wafer regions of a semiconductor wafer; (b2) after step (b1), forming a first insulating film constituting the protective film on the peripheral portion and in a first region on the surface region of the first electrode; (b3) after step (b2), forming a second insulating film on the first insulating film formed in the first region; and (b4) after step (b3), providing a plurality of semiconductor wafers by dicing the plurality of wafer regions.

14. The method of manufacturing the semiconductor device as claimed in claim 10, wherein the semiconductor wafer prepared in step (b) is provided by the following steps (b1) to (b4): (b1) forming the first electrode in each of a plurality of wafer regions of the semiconductor wafer; (b2) after step (b1), forming a protective film at the peripheral portion of the first electrode; (b3) after step (b2), forming an insulating film on a first region of the surface region of the first electrode exposed from the protective film, the insulating film having a thickness greater than the protective film; and (b4) after step (b3), providing a plurality of semiconductor wafers by dicing the plurality of wafer regions.

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