Control device for quantum computers

Abstract

This invention provides a control device for a quantum computer with excellent usability, scalability, and robustness. The control device 110 of the quantum computer 100 includes: a server 130 that calculates waveform signals for controlling a qubit system 120 comprising a plurality of qubits; and a plurality of signal processing units 140-1 to 140-N that generate electromagnetic wave signals irradiating the qubit system based on the waveform signals. Each signal processing unit includes: a logic device that performs digital signal processing on the waveform signals to generate a fundamental frequency signal; a digital oscillator that generates an oscillation signal; a mixer that mixes the fundamental frequency signal and the oscillation signal to output a mixed signal; a DA (Digital-Analog) converter that performs DA conversion on the mixed signal to obtain an analog signal; an RF (Radio Frequency) circuit that generates electromagnetic wave signals from the analog signal; and an AD (Analog-Digital) converter that performs AD conversion on the input signal from the RF circuit.

Description

Technical Field

[0001] This invention relates to a control device for a quantum computer. Prior Technology

[0002] In recent years, research on quantum computers, which utilize quantum mechanical phenomena for computation, has attracted considerable attention. High-precision control of qubits is indispensable for realizing quantum computers, leading to the development of various technologies related to quantum computer control (see, for example, Patent Document 1, Patent Document 2, Non-Patent Document 1, and Non-Patent Document 2). Currently, superconducting qubits, which are becoming mainstream in quantum computers, are controlled by microwave pulses.

[0003] Figure 1 shows the general configuration of a conventional quantum computer. The conventional quantum computer 1 includes a control device 10 and a qubit system 20 containing a plurality of qubits. The control device 10 includes a server 30, a plurality of fundamental frequency circuits 40, an oscillation circuit 50, and an analog circuit 60.

[0004] The server 30 calculates the state control of the qubits in the quantum bit system 20 or reads out the required waveform signals, or analyzes the input signals from each baseband circuit 40. Each baseband circuit 40 includes: a logic device 42, which performs digital signal processing on the waveform signals calculated by the server 30 to generate baseband signals, or is responsible for timing control; and a digital-to-analog converter / analog-to-digital converter (DAC / ADC) 44, which performs conversion between analog signals and digital signals. The logic device 42 is, for example, a programmable logic device such as a field programmable gate array (FPGA), and is equipped with memory such as dynamic random access memory (DRAM).

[0005] The oscillation circuit 50 is equipped with a plurality of oscillators that generate microwaves as carrier waves. The analog circuit 60 is connected to each of the baseband circuits 40, the oscillation circuit 50, and the qubit system 20, and performs mixing, multiplexing, and other operations on the input analog signals to generate high-frequency signals. Since the qubits of the qubit system 20 need to be irradiated with microwave pulses of a plurality of frequencies, the analog circuit 60 has a complex structure with mixers, dividers, combiners, and other components. [Previous Technical Documents] [Patent Literature]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0049495 [Patent Document 2] U.S. Patent Application Publication No. 2020 / 0065696 [Non-patent literature]

[0007] [Non-Patent Literature 1] Colm A. Ryan, Blake R. Johnson, Diego Riste, Brian Donovan, Thomas A. Ohki, “Hardware for Dynamic Quantum Computing,” Review of Scientific Instruments 88 (10), 104703 (2017) [Non-patent document 2] Yilun Xu, Gang Huang, Jan Balewski, Ravi Naik, Alexis Morvan, Bradley Mitchell, Kasra Nowrouzi, David I. Santiago, Irfan Siddiqi, "QubiC: An open source FPGA-based control and measurement system for superconducting quantum information processors," IEEE Transactions on Quantum Engineering, vol. 2, pp. 1-11, 2021, Art no. 6003811 Summary of the Invention

[0008] [The problem the invention aims to solve]

[0009] However, because the control device 10 of the previous quantum computer 1 separated the baseband circuit 40, oscillation circuit 50, and analog circuit 60, calibration was not easy, resulting in low usability. Furthermore, since high-frequency signals are generated centrally in the analog circuit 60, increasing the number of qubits in the quantum bit system 20 would result in a bulky circuit size for the analog circuit 60, leading to lower scalability. Moreover, the circuit configuration of the analog circuit 60, which mixes and combines input signals in an analog manner, is also disadvantageous in terms of stability and adjustability.

[0010] The present invention was made in view of the above-mentioned problems, and its purpose is to provide a control device for a quantum computer with excellent usability, scalability, and robustness. [Technical means to solve the problem]

[0011] The control device of the quantum computer of the present invention comprises: a server that calculates a waveform signal for controlling or reading from a quantum bit system containing a plurality of qubits; and a plurality of signal processing units that generate electromagnetic wave signals irradiating the quantum bit system based on the waveform signal. Each of the plurality of signal processing units comprises: a logic device that performs digital signal processing on the waveform signal to generate a fundamental frequency signal; one or more digital oscillators that generate digital oscillation signals of a specific frequency band; one or more mixers that output one or more mixed signals by mixing the fundamental frequency signal with the digital oscillation signal and performing upconversion; a digital-to-analog converter that performs digital-to-analog conversion on one or more mixed signals to obtain an analog signal; a high-frequency circuit that generates electromagnetic wave signals from the analog signal; and an analog-to-digital converter that performs analog-to-digital conversion on the input signal from the high-frequency circuit to obtain a digital signal. [Effects of the Invention]

[0012] The quantum computer control device of the present invention, since each of the plurality of signal processing units has the functions of generating fundamental frequency signals, digital-to-analog conversion, analog-to-digital conversion, generating oscillation signals, mixing, and generating electromagnetic wave signals, can improve availability and easily cope with the scale of quantum bit systems, thereby improving scalability. Furthermore, robustness can be improved by mixing fundamental frequency signals digitally. Simple Explanation of the Diagram

[0013] Figure 1 is a block diagram showing the structure of a previous quantum computer. Figure 2 is a block diagram showing the configuration of a quantum computer according to an embodiment of the present invention. Figure 3 is a schematic diagram showing the circuit configuration of each signal processing unit. Figure 4A is a schematic diagram showing a portion of the circuit configuration within the DAC unit. Figure 4B shows the configuration of the converter on the high-frequency circuit. Figure 4 shows the configuration of the converter under the C-series feedback circuit. Figure 4D is a diagram of the converter configuration for receiving readout signals from a qubit system. Figure 5 is a block diagram showing the structure of the clock distribution unit. Figure 6 is a schematic diagram illustrating the synchronization between different signal processing units. Figure 7A is a schematic diagram illustrating an example of signal asynchrony between different channels of a logic device and a DAC / ADC module. Figure 7B is a schematic diagram illustrating the synchronization of signals between different channels of the logic device and the DAC / ADC module. Implementation

[0014] The embodiments of the present invention are described in detail below with reference to the drawings.

[0015] In the following embodiments, a superconducting quantum computer controlled by microwave is described as an example of a quantum computer. However, as will be described later, the present invention can also be applied to various quantum computers.

[0016] Figure 2 shows the configuration of the quantum computer 100 of this embodiment. The quantum computer 100 includes a control device 110 and a qubit system 120 containing a plurality of qubits.

[0017] The control device 110 includes a server 130, a plurality of signal processing units 140-i (i=1, 2, ..., N: N is an integer greater than 2), a clock distribution unit 150, and a master clock 160.

[0018] Server 130 is connected to each signal processing unit 140-i, clock distribution unit 150, and master clock 160. Clock distribution unit 150 is connected to each signal processing unit 140-i, and master clock 160 is also connected to each signal processing unit 140-i. Each signal processing unit 140-i is connected to quantum bit system 120. Quantum bit system 120 is located inside an ultra-low temperature freezer.

[0019] The server 130 receives instructions from the user, calculates the state control of the qubits in the qubit system 120 or reads out the required waveform signals, and outputs them to each signal processing unit 140-i. Furthermore, the server 130 reads the input signals and analysis results from each signal processing unit 140-i and performs specific processing.

[0020] Clock allocation unit 150 allocates a common clock to each signal processing unit 140-i. Master clock 160 allocates a common time to each signal processing unit 140-i according to a timing synchronization protocol. Details of clock allocation by clock allocation unit 150 and timing allocation by master clock 160 will be described later.

[0021] Multiple signal processing units 140-i are disposed in different housings. Each signal processing unit 140-i integrates the functions of the previous baseband circuit 40, oscillation circuit 50 and analog circuit 60 shown in FIG1 into a single unit, and generates microwave signals (electromagnetic wave signals) irradiating the quantum bit system 120 based on the waveform signals calculated by the server 130.

[0022] Figure 3 shows the circuit configuration of each signal processing unit 140-i. Each signal processing unit 140-i includes a logic device 310, a DAC / ADC module 330, and a high-frequency (RF) circuit 350. A portion of the logic device 310, the DAC / ADC module 330, and the RF circuit 350 (the converter 360 described later) are disposed on the same substrate 300.

[0023] The logic device 310 is a programmable logic device such as an FPGA, which performs digital signal processing on the waveform signal calculated by the server 130 to generate a baseband signal or is responsible for timing control. The logic device 310 includes an I / F (Interface) 312, a high bandwidth memory (HBM) 314, a transmitting logic 316, a receiving logic 318, and an I / F 320.

[0024] I / F312 is an interface for connecting logic device 310 to server 130, clock distribution unit 150, and master clock 160.

[0025] The HBM314 retains the waveform signal data output from the server 130 and saves the data written by the receiving logic 318. Because the logic device 310 incorporates the HBM314, high-density installation can be achieved, and large amounts of data can be processed in real time.

[0026] The transmission logic 316 maintains parameters 316a related to the control of the transmission timing, performs digital signal processing on the waveform signal maintained in HBM314 to generate a baseband signal, and transmits the baseband signal via I / F320 in accordance with the timing according to parameters 316a, in conjunction with the frame counter and flip-flops described later. In this embodiment, the period from the start of transmitting the baseband signal according to parameters 316a to the end is defined as the data application period.

[0027] The receiving logic 318 holds the parameters 318a required for processing within the logic, and according to the parameters 318a, acquires and parses the input signal from the RF circuit 350. The input signal and the parsing result are then written to HBM314.

[0028] The I / F320 is an interface used to connect the logic device 310 to the DAC / ADC module 330. The I / F320, for example, supports the PCIe (Peripheral Component Interconnect Express) interface standard used by personal computers (PCs) and enables high-speed data communication. Thus, in this embodiment, since the interface standard used for connecting to general-purpose computers such as PCs is used for connecting to the DAC / ADC module 330, a dedicated substrate is not required, and component selection becomes easier.

[0029] The DAC / ADC module 330 includes a digital-to-analog converter (DAC) unit 332 and an analog-to-digital converter (ADC) unit 334.

[0030] The DAC unit 332 generates an intermediate frequency (IF) signal based on the base frequency signal generated by the transmitting logic 316, performs a digital-to-analog conversion on the IF signal, and outputs the obtained analog signal to the RF circuit 350. The IF signal generated by the DAC unit 332 is, for example, a signal with a center frequency of 1~3 GHz and a bandwidth of 1~3 GHz.

[0031] Figure 4A shows a portion of the circuit configuration of the DAC unit 332. The circuit configuration shown in Figure 4A illustrates an example of a circuit that generates one IF signal based on two baseband signals (hereinafter referred to as the first and second baseband signals). The DAC unit 332 includes mixers 410, 420, and 440, a combiner 430, numerically controlled oscillators (NCOs) 412, 422, and 442 as digital oscillators, and a DAC 450. NCOs 412, 422, and 442 each generate a digital oscillation signal in a specific frequency band (e.g., 1~3 GHz) as a carrier, but their oscillation frequencies are different.

[0032] Mixer 410 outputs a first mixed signal by mixing and upconverting the first baseband signal input from transmit logic 316 with the oscillation signal of NCO 412. Mixer 420 outputs a second mixed signal by mixing and upconverting the second baseband signal input from transmit logic 316 with the oscillation signal of NCO 422. Combiner 430 combines the first mixed signal from mixer 410 and the second mixed signal from mixer 420 to output a combined signal. Mixer 440 obtains an IF signal by mixing and upconverting the combined signal from combiner 430 with the oscillation signal of NCO 442. DAC 450 converts the IF signal output from mixer 440 into an analog signal and outputs it to converter 360 on RF circuit 350.

[0033] For example, suppose the frequency band corresponding to logic device 310 is 0~500 MHz, and it is configured to generate an IF signal with a center frequency of 3.2 GHz and a bandwidth of 1 GHz. In this case, the oscillation frequencies of NCO412, 422, and 442 are set to 1 GHz, 1.5 GHz, and 3.2 GHz, respectively. First, the first and second baseband signals with a bandwidth of 500 MHz input from the transmitting logic 316 are mixed with the oscillation signals of NCO412 and NCO422, respectively, and up-converted to generate first and second mixed signals with the same bandwidth but different center frequencies. Then, the first and second mixed signals are combined by combiner 430 to obtain a combined signal with a center frequency of 1.25 GHz and a bandwidth of 1 GHz. By mixing the combined signal with the oscillation signal of NCO442 and further upconverting it, an IF signal with a center frequency of 3.2 GHz and a bandwidth of 1 GHz can be obtained.

[0034] Unlike the mixing and combining in the previous analog method, in the DAC unit 332, the input signal can be mixed and combined digitally by using mixers 410, 420, 440 and combiner 430, thereby improving stability and reproducibility compared to the analog method.

[0035] Furthermore, Figure 4A shows a portion of the circuit configuration of the DAC unit 332, but corresponding to the number of converters 360 above the output section, it has multiple circuits similar to those in Figure 4A. Also, Figure 4A shows the circuit configuration for generating one IF signal from two baseband signals, but the necessary number of baseband signals and NCOs varies depending on the bandwidth of the generated IF signal. For example, when the bandwidth corresponding to logic device 310 is 0~500 MHz, to generate an IF signal with a bandwidth of 3 GHz, firstly, the six baseband signals with a bandwidth of 500 MHz are mixed with the oscillation signals of six NCOs with different oscillation frequencies, thereby generating six mixed signals with the same bandwidth but different center frequencies. By combining these six mixed signals, a combined signal with a bandwidth of 3 GHz is obtained. By further upconverting the combined signal and increasing the center frequency, an IF signal with a bandwidth of 3 GHz and the desired center frequency can be obtained.

[0036] Returning to Figure 3, the ADC unit 334 converts the analog signal input from the RF circuit 350 into a digital signal, and outputs the obtained digital signal to the receiving logic 318 via the I / F 320.

[0037] Furthermore, Figure 3 shows an example where the DAC unit 332 has 8 outputs and the ADC unit 334 has 4 inputs, but the number of output ports of the DAC unit 332 and the number of input ports of the ADC unit 334 are not limited. Also, the DAC / ADC module 330 can be composed of a plurality of DAC units (e.g., two 4-output DAC units) and a plurality of ADC units (e.g., two 2-input ADC units).

[0038] The RF circuit 350 includes a plurality of up-converters 360, a plurality of filters, a multiplier unit 370, a plurality of distributors 372, a feedback circuit 380 with a plurality of down-converters 384, and a plurality of down-converters 390.

[0039] A plurality of up-converters 360 are connected to a plurality of output ports of DAC unit 332. A plurality of filter and multiplier units 370 are connected to the output segments of the plurality of up-converters 360.

[0040] The output segments of the plurality of down-converters 384 and the output segments of the plurality of down-converters 390 of the feedback circuit 380 are connected to the plurality of input ports of the ADC unit 334. For example, when the ADC unit 334 has 4 inputs, the output segments of 2 down-converters 384 are connected to 2 input ports respectively, and the output segments of 2 down-converters 390 are connected to the remaining 2 input ports respectively.

[0041] As shown in Figure 4B, each upconverter 360 includes a local oscillator (LO) 362, a mixer 364, and a balun 366. The LO 362 is an analog oscillator that generates an analog oscillation signal as a carrier at a higher frequency band (e.g., 10 GHz) than the aforementioned NCOs. The mixer 364 is an analog mixer that outputs a high-frequency signal (e.g., a signal with a center frequency of 10 GHz) by mixing and upconverting the analog IF signal output from the DAC unit 332 with the oscillation signal of the LO 362. The high-frequency signal obtained by the mixer 364 is output via the balun 366. The oscillation signal of the LO 362 is also output to downconverters 384 and 390.

[0042] In this embodiment, to suppress crosstalk between adjacent RF output channels, the signal wiring on the substrate 300 is configured as differential wiring. Specifically, it is preferable to configure the outputs of the DAC unit 332, LO 362, mixer 364, and ADC unit 334 as differential wiring. The balun 366 converts the differential signal from the mixer 364 into a single-ended signal. Furthermore, since most components in the RF circuit 350 located outside the substrate 300 are single-ended, it is recommended to cover them with a shielded enclosure. This configuration ensures isolation between channels (data paths) and reduces crosstalk between channels.

[0043] Each filter and multiplier unit 370, in addition to a multiplier that converts the high-frequency signal output from the corresponding converter 360 to an integer multiple of the frequency, and a filter that allows signals of a specific frequency band to pass through, also has an amplifier that amplifies the signal level and outputs a microwave signal (electromagnetic wave signal). The frequency band of the signal obtained from the multiplier and filter is preferably different depending on the channel.

[0044] Each distributor 372 is located at the output section of each filter and multiplier unit 370. The microwave signal from the filter and multiplier unit 370 is divided into two by the distributor 372 (first microwave signal OUT1 and second microwave signal OUT2). The first microwave signal OUT1 is transmitted to the qubits of the qubit system 120 via a cable, and the second microwave signal OUT2 is output to the feedback circuit 380.

[0045] As shown in Figure 3, a plurality of first microwave signals OUT1 are output from a single signal processing unit 140-i to the qubit system 120. A portion of the plurality of first microwave signals OUT1 are control signals used to control the state of the qubits, while the remaining first microwave signals OUT1 include readout pulses for reading out the qubits and pump pulses for amplifying the readout signals. For example, when each signal processing unit 140-i has 8 outputs, 8 first microwave signals OUT1 can be constituted by 6 control signals used to control the states of 6 qubits respectively, 1 readout pulse, and 1 pump pulse.

[0046] The feedback circuit 380 includes a plurality of down-converters 384 and a plurality of switches and multiplexing units 382 disposed on their input sections.

[0047] Each switch / multiplexer unit 382 receives a portion of the plurality of second microwave signals OUT2 output from the plurality of distributors 372, along with the output signal from other (adjacent) signal processing units 140-j, as the external signal EXT. For example, as shown in Figure 3, if there are 8 second microwave signals OUT2 and the feedback circuit 380 has 2 switches / multiplexers 382, ​​then 4 second microwave signals OUT2 and 1 external signal EXT are input to one switch / multiplexer unit 382, ​​and the remaining 4 second microwave signals OUT2 and 1 external signal EXT are input to the other switch / multiplexer unit 382. The external signal EXT from other signal processing units 140-j is acquired and sent to the signal processing unit 140-i (i≠j) within the data application period.

[0048] Each switch and multiplexing unit 382, ​​according to the instructions from the server 130, selects one or more input signals from a plurality of input signals (OUT2, EXT) via a switch. When one input signal is selected, the input signal is directly output to the corresponding down-converter 384. When two or more input signals are selected, the input signals are multiplexed, and the multiplexed signal is output to the corresponding down-converter 384. When the second microwave signal OUT2 is selected, the second microwave signal OUT2, as described later, is used to correct the baseband signal. On the other hand, when the external signal EXT from other signal processing units 140-j is selected, the external signal EXT is used to monitor the synchronization between different signal processing units 140-i and 140-j (i≠j).

[0049] As shown in Figure 4C, each down-converter 384 includes a mixer 386. The oscillation signal of LO362 of the up-converter 360 is also input to the mixer 386. The mixer 386 mixes the input signals from the corresponding switch and multiplexing unit 382 with the oscillation signal of LO362, down-converts it to a frequency that the logic device 310 can correspond to, and outputs the obtained analog signal as a monitoring signal to the ADC unit 334.

[0050] The ADC unit 334 converts the monitoring signal output from the self-feedback circuit 380 into a digital signal and outputs the obtained digital monitoring signal to the receiving logic 318. The receiving logic 318 acquires the input monitoring signal, parses it, and writes the monitoring signal and parsing result to the HBM314.

[0051] When the monitoring signal corresponds to the second microwave signal OUT2, the receiving logic 318 calculates the difference between the monitoring signal and the baseband signal output by the transmitting logic 316, and sets the correction parameter to parameter 316a of the transmitting logic 316 to zero. The transmitting logic 316 corrects the baseband signal generated from the waveform signal held in HBM314 according to parameter 316a, and outputs the corrected baseband signal. In this way, by performing automatic correction based on the monitoring signal, availability can be improved, and high performance and high stability can be achieved.

[0052] When the monitoring signal corresponds to the external signal EXT input from other signal processing units 140-j to signal processing unit 140-i (i≠j), the receiving logic 318 of signal processing unit 140-i compares the monitoring signal with the reference signal, analyzes the synchronization between different signal processing units 140-i and 140-j, and writes the analysis result to HBM314.

[0053] As shown in Figure 4D, each down-converter 390 of the RF circuit 350 includes a mixer 392. The oscillation signal of LO362 of the up-converter 360 is also input to the mixer 392. The mixer 392 mixes the READ signal read from the qubit by irradiating the readout pulse and the pump pulse with the oscillation signal of LO362, down-converts it to the frequency corresponding to the logic device 310, and outputs the obtained analog signal to the ADC unit 334.

[0054] The ADC unit 334 converts the analog signals output from each downconverter 390 into digital signals and outputs the obtained digital signals to the receiving logic 318. The receiving logic 318 acquires the input signals from the ADC unit 334, parses them, and writes the input signals and parsing results to the HBM 314.

[0055] Next, the configuration of the clock distribution unit 150 will be described. As shown in FIG5, the clock distribution unit 150 includes a clock generation source 510, a first clock generation device 521, a second clock generation device 522, and a third clock generation device 523. The clock generation source 510 generates a clock at a specific frequency (e.g., 10 MHz). The clock generated by the clock generation source 510 is distributed to the first clock generation device 521, the second clock generation device 522, and the third clock generation device 523.

[0056] The first clock generation device 521, the second clock generation device 522, and the third clock generation device 523 are equipped with a phase-locked loop (PLL) and a frequency divider circuit, etc., to generate first, second, and third clocks with different frequencies, respectively. The first, second, and third clocks are distributed to all signal processing units 140-1, 140-2, ..., 140-N via signal lines 531, 532, and 533, respectively.

[0057] The first clock is the system operating clock at a first frequency (e.g., 125 MHz). The second clock is a second frequency (e.g., 62.5 kHz) with a longer period than the first clock, used for synchronization between different channels of the logic device 310 and the DAC / ADC module 330 (see Figure 7B). The third clock is a third frequency (e.g., 100 MHz) as the reference clock that forms the basis for the oscillation signals of the aforementioned oscillators (NCO, LO).

[0058] In the logic device 310 of each signal processing unit 140-i, a higher frequency operating clock is generated from the first clock, and in the DAC / ADC module 330, in conjunction with the operating clock generated in the logic device 310, a signal is acquired or output. For example, in the logic device 310, a 250 MHz operating clock is generated from the first clock of 125 MHz.

[0059] The oscillation signals of NCO412, 422, and 442 shown in Figure 4A and the oscillation signal of LO362 shown in Figure 4B are generated based on the third clock cycle, but the oscillation frequency of these oscillators can be changed according to the individual differences of qubits and manufacturing deviations.

[0060] The control device 110 of this embodiment differs from the previous control device 10 shown in FIG1. ​​Since each signal processing unit 140-i individually generates high-frequency signals, it is necessary to achieve synchronization of the entire control device 110. Therefore, in this embodiment, the following four synchronization methods I to IV are used. Synchronization Method I: Achieving synchronization between different signal processing units 140-i; Synchronization Method II: Achieving synchronization between different channels of logic device 310 and DAC / ADC module 330; Synchronization Method III: Ensuring phase consistency of the output signal between different data application cycles within the same channel; Synchronization Method IV: Allocate a common timing to all signal processing units 140-i.

[0061] The following explains each synchronization method. <Synchronization Method I> As shown in Figure 5, the first, second, and third clocks are distributed to all signal processing units 140-1, 140-2, ..., 140-N via the clock distribution unit 150. In synchronization method I, as shown in Figure 6, the clock period is kept constant (t1=t2) within each signal processing unit 140-i, and the timing offset (phase difference) of the clock rise between different signal processing units 140-i and 140-j (i≠j) is kept constant (t3=t4), thereby generating and distributing the first to third clocks with high precision.

[0062] To achieve high-precision clock generation and distribution, it is only necessary to improve the accuracy of clock generation in the clock generation source 510 and maintain the clock distribution unit 150, signal lines 531, 532, and 533 at a constant temperature. For example, signal lines 531, 532, and 533 can be fixed without moving, and the temperature can be kept constant by using a Peltier thermostat. Furthermore, the influence of temperature changes on the phase change of the clock signal can be reduced by using a temperature compensation circuit with a thermistor.

[0063] <Synchronization Method II> Next, synchronization method II will be described with reference to Figures 7A and 7B. In Figures 7A and 7B, the high-frequency operating clock generated from the first clock by the logic device 310 is denoted as CLK1, and the second clock at the second frequency is denoted as CLK2. For example, when the frequency of CLK1 is 250 MHz and the frequency of CLK2 is 62.5 kHz, CLK2 becomes a long-period clock with a period approximately 4000 times that of CLK1.

[0064] In the DAC / ADC module 330, signals are acquired or sent in conjunction with CLK1. As shown in Figure 3, there are multiple channels between the logic device 310 and the DAC / ADC module 330, but the signal transmission delay differs between different channels. When different channels are not synchronized, an offset occurs in the timing of signal acquisition between channels. If a signal is acquired during the rising phase of CLK1, for example, as shown in Figure 7A, a situation arises where the signal transmitted in channel m is acquired one clock cycle later than the signal transmitted in channel n (m≠n).

[0065] Therefore, in this embodiment, synchronization between channels is achieved according to the interface specification between the logic device and the DAC / ADC, namely JESD204C. The synchronization determined by JESD204C uses a long-period clock (CLK2) with a longer period than the operating clock (CLK1), called SYSREF, and the Local Extended Multi-Block Clock (LEMC). In LEMC, 64 samples (32-tuples) are processed as one frame, and the duration of one frame is 256 ns. In JESD204C, the LEMC frame is preceded by the rising phase of CLK2. As shown in FIG7B, the logic device 310 adds a marker M (e.g., a digit marker) to the baseband signal, indicating the beginning of each frame (with a period of 256 ns), and the marker M is periodically coordinated with the rising phase of CLK2, thereby controlling the timing of the acquisition and reception of the baseband signal between the logic device 310 and the DAC / ADC module 330. In this way, the timing of the transmission and reception of the baseband signal can be made consistent in each channel in 256 ns units, thereby suppressing the offset of the timing of the transmission and reception of the baseband signal or the deviation between different channels.

[0066] In addition, in Figures 7A and 7B, for ease of understanding, the period of the operating clock CLK1 is depicted as longer than the oscillation period of the base frequency signal, but the actual period of the operating clock CLK1 is shorter than the oscillation period of the base frequency signal.

[0067] <Synchronization Method III> Next, synchronization method III will be described with reference to Figures 4A and 4B. In the JESD204C, the timing of the output signal is determined to be 1 frame (256 ns) of LEMC once. However, since the oscillation frequencies of NCO412, 422, and 442 of DAC unit 332 and LO362 of upconverter 360 are different, and the oscillation frequencies can vary depending on the characteristics of the quantum bits or manufacturing deviations, the phase of the output signal may be offset according to each frame during mixing in each mixer.

[0068] Specifically, if the duration of one frame of LEMC is expressed as t (=256 ns), and the oscillation frequencies of NCO412, 422, 442, and LO362 are expressed as f1, f2, f3, and f4 respectively, then during mixing in each mixer, an offset of 2πf it mod 2π is generated according to each frame (i=1, 2, 3, 4). If this offset value is constant for all oscillators, no phase offset is generated, but there may be deviations in the offset value due to the difference in the oscillation frequencies of these oscillators. For example, if we set f1=1 GHz, f2=1.5 GHz, f3=3.2 GHz, and f4=10 GHz, then for NCO412, 422, and LO362, the offset value of each frame is zero, but for NCO442, the offset value is 0.4π, which is the reason for the phase offset of the output signal according to each frame. Therefore, a phase shift in the output signal occurs between different data application cycles.

[0069] Therefore, in this embodiment, the LEMC frames are grouped in a manner that eliminates the phase offset during the applied cycle of different data, thereby controlling the timing of the start of the baseband signal output. In the example above, from the first to the fourth frame, the offset values ​​for NCO442 are 0.4π, 0.8π, 1.2π, and 1.6π, respectively, but in the fifth frame, the offset value is zero for all oscillators. Therefore, by setting 5 frames as a group and using a timing of 5 frames (256 ns × 5) once, the baseband signal output can be started.

[0070] That is, if the number of frames to be mixed in mixers 410, 420, 440, and 364 is expressed as n1, n2, n3, and n4 (all integers greater than 1), then the LEMC frames are grouped by the number of frames nc. This number of frames nc is the least common multiple of the smallest integers n1, n2, n3, and n4 that satisfy 2πf itn imod 2π=0 or a constant value (i=1, 2, 3, 4) for all oscillators. The transmit logic 316 has a frame counter for counting LEMC frames, and the output of the baseband signal can be started by the frame counter and flip-flops in a manner that allows the output of the baseband signal to begin at the timing of one frame increment of nc. Thus, by determining the timing of the start of the baseband signal output based on the oscillation frequency of each oscillator, the phase of the output signal can be made consistent between different data application periods, and the state of the qubits can be controlled with high precision, or read out from the qubits.

[0071] <Synchronization Method IV> In synchronization method IV, the master clock 160 allocates a common time to all signal processing units 140-i according to a time synchronization protocol and specifies the start time of signal processing. For example, IEEE 1588 is cited as a time synchronization protocol. Here, considering the aforementioned LEMC frame, it is preferable that the offset of the start time of data transmission for each signal processing unit 140-i does not exceed 256 ns. Furthermore, since various logics with different operating frequencies exist within the logic device 310 and perform data handover, clock domain crossing (CDC) is considered, and it is preferable to suppress the offset to less than 200 ns. In IEEE 1588, a 10 GHz Ethernet network is used in the connection between the master clock 160 and each signal processing unit 140-i, and the reference clock for data transmission is set to 156.25 MHz (= period 6.4 ns). That is, the preferred suppression is an offset of less than 200 ns ÷ 6.4 ns ≈ 30 cycles. In this way, by allocating a common time to all signal processing units 140-i, the offset of the start time can be reduced within the data application period among multiple signal processing units 140-i.

[0072] As explained above, the control device 110 of the quantum computer 100 in this embodiment includes a plurality of signal processing units 140-i, and each signal processing unit 140-i integrates the functions of previous logic devices, DAC / ADC, oscillator circuits, and mixers into a single unit. This configuration allows for calibration of each signal processing unit 140-i and improves availability. Furthermore, it easily accommodates increases in the number of qubits in the quantum bit system 120, thus improving scalability. Moreover, the control device 110 can be made into a compact unit. Additionally, by digitally mixing and combining the fundamental frequency signal, robustness and reproducibility are improved.

[0073] Furthermore, the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the spirit of the present invention. Other embodiments and variations made by those skilled in the art are also included in the present invention.

[0074] For example, as a logic device 310, it can also replace programmable logic devices such as FPGAs and other logic devices such as application-specific integrated circuits (ASICs).

[0075] Furthermore, it is believed that, in addition to superconducting quantum computers, this invention can also be applied to the control of various quantum computers, including semiconductor quantum dot quantum computers that can be controlled by microwaves, quantum computers with cooled atomic gas systems that can be controlled by microwaves, quantum computers that use molecular or nanotechnology to arrange electron spins, and quantum computers controlled by electromagnetic waves other than microwaves. Furthermore, it is believed that this invention can also be applied to the control of quantum simulators or quantum sensors using qubits and quantum repeaters that are controlled by microwaves.

[0076] 1: Quantum Computer 10: Control device 20: Quantum Bit System 30: Server 40: Baseband Circuit 42: Logic Devices 44: Digital-to-Analog Converter / Analog-to-Digital Converter 50: Oscillating Circuit 60: Analog Circuits 100: Quantum Computer 110: Control device 120: Quantum Bit System 130: Server 140-1, 140-2, ..., 140-N: Signal processing unit 140-i: Signal Processing Unit 140-j: Signal Processing Unit 150: Clock Allocation Unit 160: Master Clock 300:Substrate 310: Logic Devices 312, 320:I / F 314: HBM 316: Sending Logic 316a: Parameters 318: Receiving Logic 318a: Parameters 330: DAC / ADC module 332: DAC Unit 334: ADC unit 350: RF circuit 360: Converter 362: LO 364: Mixer 366: Balanced-to-Unbalanced Converter 370: Filter and multiplier unit 372: Distributor 380: Feedback Circuit 382: Switching and multiplexing unit 384, 390: Down converter 386: Mixer 392: Mixer 410, 420, 440: Mixers 412, 422, 442: NCO 430: Combiner 450: DAC 510: The Source of Clock Generation 521: First Clock Generator 522: Second Clock Generator 523: Third Clock Generator 531, 532, 533: Signal lines CLK1: Action Clock CLK2: Long-period clock EXT: External Signal m: Channel M: Marker n: channel OUT1: First microwave signal OUT2: Second microwave signal READ: signal

Claims

1. A control device for a quantum computer, comprising: a server that calculates a waveform signal for controlling or reading from a quantum bit system containing a plurality of qubits; and a plurality of signal processing units that generate electromagnetic wave signals irradiating the quantum bit system based on the waveform signal; and each of the plurality of signal processing units comprising: a logic device that performs digital signal processing on the waveform signal to generate a fundamental frequency signal; one or more digital oscillators that generate digital oscillation signals of a specific frequency band; one or more mixers that output one or more mixed signals by mixing the fundamental frequency signal with the digital oscillation signals and performing upconversion; and a digital-to-analog converter that performs digital-to-analog conversion on the one or more mixed signals to obtain an analog signal. A high-frequency circuit that generates the electromagnetic wave signal from the analog signal; and an analog-to-digital converter that performs analog-to-digital conversion on the input signal from the high-frequency circuit to obtain a digital signal.

2. The control device for the quantum computer as claimed in claim 1, wherein the high-frequency circuit comprises: a distributor that distributes the generated electromagnetic wave signal into a first electromagnetic wave signal for output to the quantum bit system and a second electromagnetic wave signal for feedback; and a feedback circuit that down-converts the second electromagnetic wave signal and outputs it as a monitoring signal; and the analog-to-digital converter performs analog-to-digital conversion on the monitoring signal to output a digital monitoring signal; and the logic device corrects the baseband signal based on the digital monitoring signal.

3. The control device for a quantum computer as claimed in claim 1 or 2, wherein the oscillation frequencies of the plurality of digital oscillators are different from each other; the plurality of mixers output the plurality of mixed signals with different center frequencies; and the control device for the quantum computer further comprises: a combiner that combines the plurality of mixed signals to generate a combined signal with a bandwidth wider than the fundamental frequency signal; and the digital-to-analog converter performs digital-to-analog conversion on the combined signal.

4. The control device for a quantum computer as claimed in claim 3, wherein a single module is configured to integrate at least the plurality of mixers, the plurality of digital oscillators, the combiner, the digital-to-analog converter, and the analog-to-digital converter.

5. The control device for the quantum computer of claim 4 further comprises: a clock distribution unit that generates a plurality of clocks of different frequencies at a constant temperature and distributes the plurality of clocks to each of the plurality of signal processing units; and the plurality of clocks includes at least an operating clock for activating the plurality of signal processing units and a reference clock for generating the digital oscillation signals of the plurality of digital oscillators.

6. The control device of the quantum computer as claimed in claim 5, wherein the plurality of clocks further includes a long-period clock with a period longer than the operating clock; and the logic device determines the lead of the baseband signal with a specific period determined by the local expansion of multiple blocks and the clock, and makes the lead periodically coordinate with the long-period clock, thereby controlling the timing of the transfer of the baseband signal between the logic device and the module.

7. The control device for a quantum computer as claimed in claim 6, wherein the logic device determines the timing of the output of the baseband signal to the module based on the specific period determined by the local expansion multi-block, the clock, and the oscillation frequency of each of the plurality of digital oscillators.

8. The control device of the quantum computer as claimed in claim 1 further comprises: a master clock that allocates common time to the plurality of signal processing units in accordance with a time synchronization protocol.

9. The control device for the quantum computer as claimed in claim 4, wherein the aforementioned logic device has an interface that supports an interface specification for connecting to a general-purpose computer, serving as an interface for connecting to the aforementioned module.

10. The control device for a quantum computer as claimed in claim 1, wherein the high-frequency circuit comprises an upconverter, and the upconverter comprises: an analog oscillator that generates an analog oscillation signal at a higher frequency band than the one or more digital oscillators; and an analog mixer that mixes the analog oscillation signal with the analog signal output from the digital-to-analog converter and performs upconversion.

11. The control device for a quantum computer as claimed in claim 10, wherein at least the output of the digital-to-analog converter, the output of the analog oscillator, the output of the analog mixer, and the input of the analog-to-digital converter are differential wiring; the upconverter further comprises: a balun that converts the output signal from the analog mixer into a single-ended signal and outputs the single-ended signal as the electromagnetic wave signal.

12. The control device for the quantum computer as claimed in claim 1, wherein at least a portion of the aforementioned high-frequency circuitry is covered by a shielding enclosure.

13. The control device for the quantum computer of claim 1, wherein the logic device has a high-bandwidth memory that holds data of the waveform signal calculated by the server.

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