Semiconductor device

Abstract

This invention provides a semiconductor device comprising: an active pattern including a lower pattern extending in a first direction and a plurality of wafer patterns spaced apart from the lower pattern in a second direction; a gate structure located on the lower pattern including a gate insulating layer, a gate spacer, and a gate electrode extending upward in a third direction perpendicular to the first direction; a source / drain pattern located on the lower pattern and in contact with each of the wafer patterns and the gate insulating layer; and a first etch-stop pattern located between the gate spacer and the source / drain pattern. The gate spacer includes an inner sidewall facing the gate electrode and extending upward in a third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source / drain pattern includes a semiconductor fill layer located on a semiconductor liner layer, the semiconductor liner layer being in contact with the wafer patterns and including a facet surface extending from the connection sidewall of the gate spacer. The first etch-stop pattern is in contact with the facet surface of the semiconductor liner layer and the connection sidewall.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a multi-bridge channel field effect transistor (MBCFET™) and a method of manufacturing the same. [Cross-reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10-2022-0009280, filed on Jan. 21, 2022, and Korean Patent Application No. 10-2022-0031447, filed on Mar. 14, 2022, in the Korean Intellectual Property Office, and all the rights arising therefrom, the entire contents of which are incorporated herein by reference. Prior Art

[0003] As a scaling technology for increasing the density of semiconductor devices, multi-gate transistors have been proposed. In multi-gate transistors, a multi-channel active pattern (or silicon body) having a fin or nanowire shape may be formed on a substrate, and a gate may be formed on the surface of the multi-channel active pattern.

[0004] Such multi-gate transistors may have a three-dimensional channel, and thus they may be more easily scaled. In addition, the current control ability may be improved without increasing the gate length of the multi-gate transistors. Furthermore, the short channel effect (SCE) (where the potential of the channel region is affected by the drain voltage) may be effectively suppressed. Summary of the Invention

[0005] Aspects of the present disclosure provide a semiconductor device capable of improving device performance and reliability.

[0006] Aspects of the present disclosure also provide a method of manufacturing a semiconductor device capable of improving device performance and reliability.

[0007] However, aspects of the present disclosure are not limited to those aspects set forth herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0008] According to an aspect of the present disclosure, a semiconductor device includes: an active pattern including a lower pattern extending in a first direction and a plurality of fin patterns spaced apart from the lower pattern in a second direction; a gate structure located on the lower pattern and including a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode extending in a third direction perpendicular to the first direction; a source / drain pattern located on the lower pattern and in contact with the fin patterns and the gate insulating layer; and a first etch stop pattern located between the gate spacer and the source / drain pattern, wherein the gate spacer includes an inner sidewall facing the gate electrode and extending in the third direction, and a connecting sidewall extending from the inner sidewall of the gate spacer in the first direction, the source / drain pattern includes a semiconductor liner layer and a semiconductor fill layer located on the semiconductor liner layer, the semiconductor liner layer is in contact with the fin patterns and includes a faceted surface extending from the connecting sidewall of the gate spacer, and the first etch stop pattern is in contact with the faceted surface of the semiconductor liner layer and the connecting sidewall of the gate spacer.

[0009] According to another aspect of the present disclosure, a semiconductor device includes: an active pattern including a lower pattern extending in a first direction and a plurality of fin patterns spaced apart from the lower pattern in a second direction; a gate structure located on the lower pattern and including a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode extending in a third direction perpendicular to the first direction; and a source / drain pattern located on the lower pattern and in contact with the fin patterns and the gate insulating layer, wherein the source / drain pattern includes a semiconductor liner layer and a semiconductor fill layer located on and in contact with the semiconductor liner layer, the semiconductor liner layer is in contact with the fin patterns and includes a faceted surface extending from the gate spacer, and in a plan view at a level of one of the fin patterns, a first width including a maximum width of the semiconductor liner layer in the third direction is greater than a second width of an interface between the semiconductor liner layer and the semiconductor fill layer in the third direction.

[0010] According to yet another aspect of the present disclosure, a semiconductor device includes: a first active pattern including a first lower pattern extending in a first direction and a plurality of first fin patterns spaced apart from the first lower pattern in a second direction; a first gate structure located on the first lower pattern and including a first gate insulating layer, a first gate electrode, and a first gate spacer, the first gate electrode extending in a third direction perpendicular to the first direction; a second active pattern including a second lower pattern extending in the first direction and a plurality of second fin patterns spaced apart from the second lower pattern in the second direction, an upper surface width of the second lower pattern in the third direction being smaller than an upper surface width of the first lower pattern in the third direction; a second gate structure located on the second lower pattern and including a second gate insulating layer, a second gate electrode, and a second gate spacer, the second gate electrode extending in the third direction; a first source / drain pattern located on the first lower pattern and in contact with the first fin patterns and the first gate insulating layer; a second source / drain pattern located on the second lower pattern and in contact with the second fin patterns and the second gate insulating layer; and a first etch stop pattern located between the first gate spacer and the first source / drain pattern, wherein the first gate spacer includes an inner sidewall facing the first gate electrode and extending in the third direction and a connection sidewall extending from the inner sidewall of the first gate spacer in the first direction, the first source / drain pattern includes a semiconductor liner layer and a semiconductor fill layer located on the semiconductor liner layer, the semiconductor liner layer is in contact with the first fin patterns, and includes a facet surface extending from the connection sidewall of the first gate spacer, and the first etch stop pattern is in contact with the facet surface of the semiconductor liner layer and the connection sidewall of the first gate spacer. Brief Description of the Drawings

[0011] The above and other aspects and features of the present disclosure will become more apparent by referring to the detailed description of its exemplary embodiments with reference to the accompanying drawings, in which: FIG. 1 is an illustrative plan view for describing a semiconductor device according to some embodiments. FIGS. 2 and 3 are cross-sectional views taken along lines A-A and B-B of FIG. 1, respectively. FIG. 4 is a view for describing the shape of the first fin pattern of FIG. 2. FIG. 5 is a plan view taken along line C-C of FIG. 2 and viewed from above. FIG. 6 is a plan view taken along line D-D of FIG. 2 and viewed from above. FIG. 7 is an enlarged view of region P of FIG. 2. FIG. 8 is an enlarged view of part Q of FIG. 5. FIGS. 9 and 10 are views for describing a semiconductor device according to some embodiments. FIG. 11 and FIG. 12 are diagrams for describing a semiconductor device according to some embodiments. FIG. 13, FIG. 14, FIG. 15, and FIG. 16 are diagrams for describing a semiconductor device according to some embodiments. FIG. 17, FIG. 18, and FIG. 19 are diagrams for describing a semiconductor device according to some embodiments. FIG. 20 and FIG. 21 are diagrams for describing a semiconductor device according to some embodiments. FIG. 22 and FIG. 23 are diagrams for describing a semiconductor device according to some embodiments. FIG. 24 is a diagram for describing a semiconductor device according to some embodiments. FIG. 25, FIG. 26, and FIG. 27 are diagrams for describing a semiconductor device according to some embodiments, respectively. FIG. 28, FIG. 29, FIG. 30, and FIG. 31 are diagrams for describing a semiconductor device according to some embodiments. FIG. 32 is a diagram for describing a semiconductor device according to some embodiments. FIG. 33, FIG. 34, and FIG. 35 are diagrams for describing a semiconductor device according to some embodiments. FIG. 36, FIG. 37, FIG. 38, FIG. 39, FIG. 40, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 45, FIG. 46, FIG. 47, FIG. 48, FIG. 49, FIG. 50, FIG. 51, FIG. 52, and FIG. 53 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. FIG. 54 and FIG. 55 are diagrams for describing a semiconductor device according to some embodiments, respectively. FIG. 56, FIG. 57, FIG. 58, and FIG. 59 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Embodiments

[0012] A semiconductor device according to some embodiments may include a tunneling field effect transistor (FET), a three-dimensional (3D) FET, or a two-dimensional material-based FET and their heterostructures. Additionally, a semiconductor device according to some embodiments may include a bipolar junction transistor, a lateral double-diffused metal oxide semiconductor (LDMOS) transistor, or the like.

[0013] A semiconductor device according to some embodiments will be described with reference to FIGS. 1 to 8.

[0014] FIG. 1 is an illustrative plan view for describing a semiconductor device according to some embodiments. FIGS. 2 and 3 are cross-sectional views taken along line A-A and line B-B of FIG. 1, respectively. FIG. 4 is a view for describing the shape of a first pattern of FIG. 2. FIG. 5 is a plan view taken along line C-C of FIG. 2 and viewed from above. FIG. 6 is a plan view taken along line D-D of FIG. 2 and viewed from above. FIG. 7 is an enlarged view of region P of FIG. 2. FIG. 8 is an enlarged view of portion Q of FIG. 5.

[0015] For reference, FIG. 1 schematically shows a semiconductor device in addition to a first gate insulating layer 130, an etch stop layer 185, an interlayer insulating layer 190, a wiring structure 205, and the like.

[0016] Referring to FIGS. 1 to 8, a semiconductor device according to some embodiments may include a first active pattern AP1, a plurality of first gate structures GS1, a first source / drain pattern 150, and a first side etch stop pattern 160. The terms "first", "second", "third", etc. may be used herein only to distinguish one element from another.

[0017] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0018] The first active pattern AP1 may be disposed on the substrate 100. The first active pattern AP1 may extend in a first direction D1. As an example, the first active pattern AP1 may be disposed in a region where a P-channel metal oxide semiconductor (PMOS) is formed. As another example, the first active pattern AP1 may be disposed in a region where an N-channel metal oxide semiconductor (NMOS) is formed. In the following description, the first active pattern AP1 disposed in the region where the PMOS is formed will be described.

[0019] The first active pattern AP1 can be a multi-channel active pattern. The first active pattern AP1 can include a first lower pattern BP1 and a plurality of first strip patterns NS1. The first lower pattern BP1 can protrude from the substrate 100. The first lower pattern BP1 can extend in a first direction D1.

[0020] The plurality of first strip patterns NS1 can be disposed on the upper surface BP1_US of the first lower pattern. The plurality of first strip patterns NS1 can be spaced apart from the first lower pattern BP1 in a third direction D3. Each individual first strip pattern NS1 can be spaced apart from each other in the third direction D3.

[0021] Each of the first strip patterns NS1 can include an upper surface NS1_US and a lower surface NS1_BS. The upper surface NS1_US of the first strip pattern is a surface opposite to the lower surface NS1_BS of the first strip pattern in the third direction D3. Each of the first strip patterns NS1 can include a first sidewall NS1_SW1 opposite to each other in the first direction D1 and a second sidewall NS1_SW2 opposite to each other in a second direction D2. The third direction D3 can be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 can be the thickness direction of the substrate 100. The first direction D1 can be a direction intersecting the second direction D2.

[0022] The upper surface NS1_US and the lower surface NS1_BS of the first strip pattern can be connected to each other by the first sidewall NS1_SW1 and the second sidewall NS1_SW2 of the first strip pattern. The first sidewall NS1_SW1 of the first strip pattern is connected to and in contact with a first source / drain pattern 150 to be described later. Elements described as "in contact with" can include direct contact therebetween. Elements described as "direct" contact or "direct" on or connected do not have intervening elements therebetween. The first sidewall NS1_SW1 of the first strip pattern can include the end of the first strip pattern NS1. For example, the end of the first strip pattern NS1 can be located at the center line between the upper surface NS1_US and the lower surface NS1_BS of the first strip pattern, but is not limited thereto.

[0023] Three first strip patterns NS1 are shown disposed in the third direction D3, but this is for convenience of explanation only, and the present disclosure is not limited thereto.

[0024] The first lower pattern BP1 can be formed by etching a portion of the substrate 100 and can include an epitaxial layer grown from the substrate 100. The first lower pattern BP1 can include silicon or germanium, which are elemental semiconductor materials. Additionally, the lower pattern BP1 can include compound semiconductors, such as IV-IV group compound semiconductors or III-V group compound semiconductors.

[0025] The IV-IV group compound semiconductor can be, for example, a binary compound or a ternary compound containing two or more than two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with group IV elements.

[0026] The III-V group compound semiconductor can be, for example, one of the binary compounds, ternary compounds, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0027] The first sheet pattern NS1 can include one of silicon or germanium, which are elemental semiconductor materials, IV-IV group compound semiconductors, or III-V group compound semiconductors. Each of the first sheet patterns NS1 can include the same material as the first lower pattern BP1 or a material different from the material of the first lower pattern BP1.

[0028] In a semiconductor device according to some embodiments, the first lower pattern BP1 can be a silicon lower pattern including silicon, and the first sheet pattern NS1 can be a silicon sheet pattern including silicon.

[0029] The width of the first sheet pattern NS1 in the second direction D2 can be increased or decreased proportionally to the width of the first lower pattern BP1 in the second direction D2. By way of example, it has been shown that the widths of the first sheet patterns NS1 stacked in the third direction D3 are the same in the second direction, but this is only for convenience of explanation and the present disclosure is not limited thereto. Different from what is shown in the drawings, as the first sheet pattern NS1 becomes farther from the first lower pattern BP1, the width of the first sheet pattern NS1 stacked in the third direction D3 in the second direction D2 can be decreased.

[0030] The field insulating layer 105 can be formed on the substrate 100. The field insulating layer 105 can be disposed on the sidewalls of the first lower pattern BP1. The field insulating layer 105 is not disposed on the upper surface BP1_US of the first lower pattern.

[0031] As an example, the field insulating layer 105 may completely cover the sidewalls of the first lower pattern BP1. Different from that shown in the drawings, the field insulating layer 105 may cover a part of the sidewalls of the first lower pattern BP1. In this case, a part of the first lower pattern BP1 may protrude in the third direction D3 beyond the upper surface of the field insulating layer 105.

[0032] Each of the first fin patterns NS1 is disposed at a respective level higher than the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, a nitroxide layer, or a combination thereof. The field insulating layer 105 is shown as a single layer, but this is only for convenience of explanation and the present disclosure is not limited thereto.

[0033] A plurality of first gate structures GS1 may be disposed on the substrate 100. Each of the first gate structures GS1 may extend in the second direction D2. The first gate structures GS1 may be disposed to be spaced apart from each other in the first direction D1. The first gate structures GS1 may be adjacent to each other in the first direction D1. For example, the first gate structures GS1 may be disposed on both sides of the first source / drain pattern 150 in the first direction D1.

[0034] The first gate structure GS1 may be disposed on the first active pattern AP1. The first gate structure GS1 may cross the first active pattern AP1. The first gate structure GS1 may cross the first lower pattern BP1. The first gate structure GS1 may surround each of the first fin patterns NS1. The first gate structure GS1 may include, for example, a first gate electrode 120, a first gate insulating layer 130, a first gate spacer 140, and a first gate capping pattern 145.

[0035] The first gate structure GS1 may include a plurality of internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 disposed between first fin patterns NS1 adjacent to each other in a third direction D3 and between a first lower pattern BP1 and the first fin pattern NS1. The internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 may be disposed between an upper surface BP1_US of the first lower pattern and a lower surface NS1_BS of the first lowermost fin pattern and between an upper surface NS1_US of the first fin pattern and a lower surface NS1_BS of the first fin pattern facing each other in the third direction D3. For example, the number of the internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 may be the same as the number of the first fin pattern NS1.

[0036] The internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 are in contact with the upper surface BP1_US of the first lower pattern, the upper surface NS1_US of the first fin pattern, and the lower surface NS1_BS of the first fin pattern. The internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 may be in direct contact with a first source / drain pattern 150 to be described later.

[0037] The first gate structure GS1 may include a first internal gate structure INT1_GS1, a second internal gate structure INT2_GS1, and a third internal gate structure INT3_GS1. The first internal gate structure INT1_GS1, the second internal gate structure INT2_GS1, and the third internal gate structure INT3_GS1 may be sequentially disposed on the first lower pattern BP1.

[0038] The third internal gate structure INT3_GS1 may be disposed between the first lower pattern BP1 and the first fin pattern NS1. The third internal gate structure INT3_GS1 may be disposed at the lowermost portion among the internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1. The third internal gate structure INT3_GS1 may be the lowermost internal gate structure.

[0039] The first internal gate structure INT1_GS1 and the second internal gate structure INT2_GS1 can be disposed between first pattern pieces NS1 adjacent to each other in the third direction D3. The first internal gate structure INT1_GS1 can be disposed at the uppermost part among the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1. The first internal gate structure INT1_GS1 can be the uppermost internal gate structure. The second internal gate structure INT2_GS1 is disposed between the first internal gate structure INT1_GS1 and the third internal gate structure INT3_GS1.

[0040] The internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 include a first gate electrode 120 and a first gate insulating layer 130 disposed between first pattern pieces NS1 adjacent to each other and between a first lower pattern BP1 and the first pattern piece NS1.

[0041] As an example, the width of the first internal gate structure INT1_GS1 in the first direction D1 can be the same as the width of the second internal gate structure INT2_GS1 in the first direction D1. The width of the third internal gate structure INT3_GS1 in the first direction D1 can be the same as the width of the second internal gate structure INT2_GS1 in the first direction D1.

[0042] As another example, the width of the third internal gate structure INT3_GS1 in the first direction D1 can be greater than the width of the second internal gate structure INT2_GS1 in the first direction D1. The width of the first internal gate structure INT1_GS1 in the first direction D1 can be the same as the width of the second internal gate structure INT2_GS1 in the first direction D1.

[0043] Taking the second internal gate structure INT2_GS1 as an example, the width of the second internal gate structure INT2_GS1 can be measured at an intermediate position between the upper surface NS1_US of the first pattern pieces facing each other in the third direction D3 and the lower surface NS1_BS of the first pattern pieces.

[0044] For reference, a plan view at the level of the second internal gate structure INT2_GS1 (i.e., the height relative to the substrate 100 or other reference features) is shown in FIG. 5. A plan view at the level of the first bottommost sheet pattern NS1 of the first sheet pattern NS1 that is closest to the first lower pattern BP1 is shown in FIG. 6. Although not shown in the drawings, when excluding the part where the first source / drain contact 180 is formed, the plan views at the levels of the other internal gate structures INT1_GS1 and internal gate structure INT3_GS1 may be similar to FIG. 5. Although not shown in the drawings, when excluding the part where the first source / drain contact 180 is formed, the plan views at the levels of the other first sheet patterns NS1 may be similar to FIG. 6.

[0045] The first gate electrode 120 may be disposed on the first lower pattern BP1. The first gate electrode 120 may cross the first lower pattern BP1. The first gate electrode 120 may surround the first sheet pattern NS1. Portions of the first gate electrode 120 may be disposed between the first sheet patterns NS1 adjacent to each other and between the first lower pattern BP1 and the first sheet pattern NS1.

[0046] The first gate electrode 120 may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxynitride. The first gate electrode 120 may include, for example, at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but not limited thereto. The conductive metal oxides and conductive metal oxynitrides may include the oxidized forms of the materials described above, but not limited thereto.

[0047] The first gate electrode 120 may be disposed on both sides of the first source / drain pattern 150 to be described later. The first gate structure GS1 may be disposed on both sides of the first source / drain pattern 150 in the first direction D1.

[0048] As an example, both of the first gate electrodes 120 disposed on both sides of the first source / drain pattern 150 may be normal gate electrodes serving as the gates of transistors. As another example, the first gate electrode 120 disposed on one side of the first source / drain pattern 150 may be used as the gate of a transistor, but the first gate electrode 120 disposed on the other side of the first source / drain pattern 150 may be a dummy gate electrode.

[0049] The first gate insulating layer 130 may extend along the upper surface of the field insulating layer 105 and the upper surface BP1_US of the first lower pattern. The first gate insulating layer 130 may surround a plurality of first fin patterns NS1. The first gate insulating layer 130 may be disposed along the periphery of the first fin pattern NS1. The first gate electrode 120 is disposed on the first gate insulating layer 130. The first gate insulating layer 130 is disposed between the first gate electrode 120 and the first fin pattern NS1. A portion of the first gate insulating layer 130 may be disposed between the first fin patterns NS1 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the first fin pattern NS1.

[0050] The first gate insulating layer 130 may include silicon oxide, silicon-germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0051] The first gate insulating layer 130 has been shown as a single layer, but this is only for convenience of explanation, and the present disclosure is not limited thereto. The first gate insulating layer 130 may include multiple layers. The first gate insulating layer 130 may include an interface layer disposed between the first fin pattern NS1 and the first gate electrode 120 and a high-k insulating layer.

[0052] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate insulating layer 130 may include a ferroelectric material layer having ferroelectric characteristics and a paraelectric material layer having paraelectric characteristics.

[0053] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each individual capacitor has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0054] When the ferroelectric material layer having a negative capacitance and the paraelectric material layer having a positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series with each other may increase. Using the increase in the total capacitance value, a transistor including the ferroelectric material layer may have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0055] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of the following: hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, and lead zirconate titanate. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0056] The ferroelectric material layer may further include a dopant. For example, the dopant may include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the type of ferroelectric material included in the ferroelectric material layer.

[0057] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of the following: gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0058] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 atomic % to 8 atomic % (at%) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0059] When the dopant is silicon (Si), the ferroelectric material layer may contain 2 atomic % to 10 atomic % of silicon. When the dopant is yttrium (Y), the ferroelectric material layer may contain 2 atomic % to 10 atomic % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 atomic % to 7 atomic % of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may contain 50 atomic % to 80 atomic % of zirconium.

[0060] The paraelectric material layer may have paraelectric characteristics. The paraelectric material layer may contain at least one of, for example, silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material layer may contain at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0061] The ferroelectric material layer and the paraelectric material layer may contain the same material. The ferroelectric material layer may have ferroelectric characteristics, but the paraelectric material layer may not have ferroelectric characteristics. For example, when the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer is different from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0062] The ferroelectric material layer may have a thickness with ferroelectric characteristics. The thickness of the ferroelectric material layer may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness for generating ferroelectric characteristics may vary for each ferroelectric material, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0063] As an example, the first gate insulating layer 130 may include a ferroelectric material layer. As another example, the first gate insulating layer 130 may include a plurality of ferroelectric material layers spaced apart from each other. The first gate insulating layer 130 may have a stacked layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0064] The first gate spacer 140 may be disposed on the sidewall of the first gate electrode 120. The first gate spacer 140 may not be disposed between the first lower pattern BP1 and the first sheet pattern NS1 and between the first sheet patterns NS1 adjacent to each other in the third direction D3.

[0065] The first gate spacer 140 may include an inner sidewall 140_ISW, a connecting sidewall 140_CSW, and an outer sidewall 140_OSW. The inner sidewall 140_ISW of the first gate spacer faces the sidewall of the first gate electrode 120 extending in the second direction D2. The inner sidewall 140_ISW of the first gate spacer may extend in the second direction D2. The inner sidewall 140_ISW of the first gate spacer may be a surface opposite to the outer sidewall 140_OSW of the first gate spacer facing the first interlayer insulating layer 190. The connecting sidewall 140_CSW of the first gate spacer connects the inner sidewall 140_ISW and the outer sidewall 140_OSW of the first gate spacer to each other. The connecting sidewall 140_CSW of the first gate spacer may extend in the first direction D1.

[0066] The first gate insulating layer 130 may extend along the inner sidewall 140_ISW of the first gate spacer. The first gate insulating layer 130 may be in contact with the inner sidewall 140_ISW of the first gate spacer.

[0067] The first gate spacer 140 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The first gate spacer 140 is shown as a single layer, but this is for convenience of explanation only, and the present disclosure is not limited thereto.

[0068] The first gate capping pattern 145 may be disposed on the first gate electrode 120 and the first gate spacer 140. The upper surface of the first gate capping pattern 145 may be coplanar with the upper surface of the interlayer insulating layer 190. Different from that shown in the drawings, the first gate capping pattern 145 may be disposed between the first gate spacers 140.

[0069] The first gate capping pattern 145 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The first gate capping pattern 145 may include a material having an etching selectivity with respect to the interlayer insulating layer 190.

[0070] The first source / drain pattern 150 may be disposed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 is connected to the first sheet pattern NS1.

[0071] The first source / drain pattern 150 can be disposed on the side of the first gate structure GS1. The first source / drain pattern 150 can be disposed between the first gate structures GS1 adjacent to each other in the first direction D1. For example, the first source / drain pattern 150 can be disposed on both sides of the first gate structure GS1. Compared with the illustration in the drawings, the first source / drain pattern 150 can be disposed on one side of the first gate structure GS1 and may not be disposed on the other side of the first gate structure GS1.

[0072] The first source / drain pattern 150 can be included in the source / drain of a transistor using the first pattern NS1 as the channel region.

[0073] The first source / drain pattern 150 can be disposed in the first source / drain recess 150R. The first source / drain recess 150R extends in the third direction D3. The first source / drain recess 150R can be defined between the first gate structures GS1 adjacent to each other in the first direction D1.

[0074] The bottom surface of the first source / drain recess 150R is defined by the first lower pattern BP1. The sidewalls of the first source / drain recess 150R can be defined by the first pattern NS1 and the internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1. The internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 can define portions of the sidewalls of the first source / drain recess 150R. In FIGS. 5 and 6, the first source / drain recess 150R includes the connection sidewalls 140_CSW of the first gate spacer.

[0075] The internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 may include an upper surface facing the lower surface NS1_BS of the first patterned layer. The internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 include a lower surface facing the upper surface NS1_US of the first patterned layer or the upper surface BP1_US of the first lower patterned layer. The internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 include sidewalls connecting the upper surface and the lower surface of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 to each other. The sidewalls of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 may define a part of the sidewalls of the first source / drain recess 150R.

[0076] Between the first patterned layer NS1 and the first lower patterned layer BP1 disposed at the lowermost portion, the boundary between the first gate insulating layer 130 and the first lower patterned layer BP1 may be the upper surface BP1_US of the first lower patterned layer. The upper surface BP1_US of the first lower patterned layer may be the boundary between the third internal gate structure INT3_GS1 and the first lower patterned layer BP1.

[0077] The width extension region 150R_ER of the first source / drain recess may be defined between the first patterned layers NS1 adjacent to each other in the third direction D3. The width extension region 150R_ER of the first source / drain recess may be defined between the first lower patterned layer BP1 and the first patterned layer NS1. The width extension region 150R_ER of the first source / drain recess may extend between the first patterned layers NS1 adjacent to each other in the third direction D3. The width extension region 150R_ER of the first source / drain recess may be defined between the internal gate structures INT1_GS1, INT2_GS1, and INT3_GS1 adjacent to each other in the first direction D1.

[0078] As the width extension region 150R_ER of each of the first source / drain recesses moves away from the upper surface BP1_US of the first lower pattern, it may include a portion where its width increases in the first direction D1 and a portion where its width decreases in the first direction D1. For example, the width of the width extension region 150R_ER of the first source / drain recess may increase and then decrease in a direction away from the upper surface BP1_US of the first lower pattern.

[0079] In the width extension region 150R_ER of each of the first source / drain recesses, the point where the width extension region 150R_ER of the first source / drain recess has the maximum width is positioned between the first fin pattern NS1 and the first lower pattern BP1 or between the first fin patterns NS1 adjacent to each other in the third direction D3.

[0080] The first source / drain pattern 150 may contact the first fin pattern NS1 and the first lower pattern BP1. A portion of the first source / drain pattern 150 may contact the connecting sidewall 140_CSW of the first gate spacer. The first gate insulating layer 130 of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 may contact the first source / drain pattern 150.

[0081] The first source / drain pattern 150 may include an epitaxial pattern. The first source / drain pattern 150 includes a semiconductor material. The first source / drain pattern 150 may include a first semiconductor liner layer 151 and a first semiconductor fill layer 152. The first semiconductor fill layer 152 has been shown as a single layer, but this is for convenience of explanation only, and the present disclosure is not limited thereto.

[0082] The first semiconductor liner layer 151 may be continuously formed along the first source / drain recess 150R. The first semiconductor liner layer 151 may be formed along the sidewalls and the bottom surface of the first source / drain recess 150R. The first semiconductor liner layer 151 formed along the first source / drain recess 150R defined by the first fin pattern NS1 is directly connected to the first semiconductor liner layer 151 formed along the first source / drain recess 150R defined by the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1. The first semiconductor liner layer 151 contacts the first gate insulating layer 130, the first fin pattern NS1, and the first lower pattern BP1.

[0083] The first semiconductor liner layer 151 may include an outer sidewall 151_OSW and an inner sidewall 151_ISW. The outer sidewall 151_OSW of the first semiconductor liner layer 151 contacts the first gate insulating layer 130, the first pattern NS1, and the first lower pattern BP1. The outer sidewall 151_OSW of the first semiconductor liner layer is directly connected to the first sidewall NS1_SW1 of the first pattern. The outer sidewall 151_OSW of the first semiconductor liner layer contacts the sidewalls of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1. The outer sidewall 151_OSW of the first semiconductor liner layer may represent the contour of the first source / drain recess 150R.

[0084] The inner sidewall 151_ISW of the first semiconductor liner layer may be a surface opposite to the outer sidewall 151_OSW of the first semiconductor liner layer. In FIGS. 5 and 6, the first semiconductor liner layer 151 may include a portion where its width in the second direction D2 decreases in a direction away from the outer sidewall 151_OSW of the first semiconductor liner layer. The inner sidewall 151_ISW of the first semiconductor liner layer may include a facet surface 151_FSW and a connecting surface 151_CSW.

[0085] The facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor liner layer may extend from the connecting sidewall 140_CSW of the first gate spacer. The facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor liner layer may form an acute angle with the connecting sidewall 140_CSW of the first gate spacer. The first semiconductor liner layer 151 includes a facet surface 151_FSW extending from the connecting sidewall 140_CSW of the first gate spacer. The facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor liner layer may be the facet surface of the first semiconductor liner layer 151.

[0086] The connecting surface 151_CSW of the inner sidewall 151_ISW of the first semiconductor liner layer may extend in the second direction D2. The connecting surface 151_CSW of the inner sidewall 151_ISW of the first semiconductor liner layer may include a curved portion.

[0087] As shown in FIGS. 2, 5, and 6, the thickness of the first semiconductor liner layer 151 in contact with the first sidewall NS1_SW1 of the first pattern in the first direction D1 is less than the thickness of the first semiconductor liner layer 151 in contact with the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 in the first direction D1, but the present disclosure is not limited thereto.

[0088] The first semiconductor liner layer 151 may include, for example, silicon-germanium. The first semiconductor liner layer 151 may include a silicon-germanium layer. The first semiconductor liner layer 151 may include a doped p-type impurity. For example, the p-type impurity may be boron (B), but is not limited thereto.

[0089] The first semiconductor fill layer 152 is disposed on the first semiconductor liner layer 151. The first semiconductor fill layer 152 is in contact with the first semiconductor liner layer 151. In FIG. 2, the first semiconductor fill layer 152 may fill the remaining portion of the first source / drain recess 150R.

[0090] The first semiconductor fill layer 152 is disposed on the inner sidewall 151_ISW of the first semiconductor liner layer. For example, the first semiconductor fill layer 152 may be in contact with the inner sidewall 151_ISW of the first semiconductor liner layer.

[0091] The first semiconductor fill layer 152 may cover a portion of the inner sidewall 151_ISW of the first semiconductor liner layer. In FIGS. 5 and 6, the first semiconductor fill layer 152 may not cover at least a portion of the facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor liner layer. The first semiconductor fill layer 152 may cover at least a portion of the connection surface 151_CSW of the inner sidewall 151_ISW of the first semiconductor liner layer.

[0092] The first semiconductor fill layer 152 may include, for example, silicon-germanium. The first semiconductor fill layer 152 may include a silicon-germanium layer. The first semiconductor fill layer 152 may include a doped p-type impurity. The germanium fraction in the first semiconductor liner layer 151 is less than the germanium fraction in the first semiconductor fill layer 152.

[0093] Although not shown in the figures, as an example, a semiconductor capping layer containing silicon may be disposed on the first semiconductor fill layer 152. As another example, a semiconductor capping layer containing silicon-germanium may be disposed on the first semiconductor fill layer 152. In this case, the germanium fraction in the semiconductor capping layer may be less than the germanium fraction in the first semiconductor fill layer 152.

[0094] The first side etching stop pattern 160 is disposed between the first gate spacer 140 and the first source / drain pattern 150. The first side etching stop pattern 160 may be disposed between the first gate spacer 140 and the first semiconductor lining layer 151.

[0095] In FIGS. 5 and 6, the first side etching stop pattern 160 may extend between the first gate spacer 140 and the first source / drain pattern 150 along the third direction D3.

[0096] In FIGS. 2 and 5, the first side etching stop pattern 160 is disposed between the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, the internal gate structure INT3_GS1, and the first semiconductor filling layer 152.

[0097] The first side etching stop pattern 160 is disposed between the facet surface 151_FSW of the connecting sidewall 140_CSW of the first gate spacer and the inner sidewall 151_ISW of the first semiconductor lining layer. That is, the first side etching stop pattern 160 is disposed between the connecting sidewall 140_CSW of the first gate spacer and the facet surface of the first semiconductor lining layer 151.

[0098] The first side etching stop pattern 160 contacts the first gate spacer 140 and the first source / drain pattern 150. For example, the first side etching stop pattern 160 directly contacts the first gate spacer 140 and the first source / drain pattern 150. The first side etching stop pattern 160 contacts the connecting sidewall 140_CSW of the first gate spacer and the facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor lining layer.

[0099] The width of the first side etching stop pattern 160 in the second direction D2 may increase in the direction away from the first gate electrode 120. In a plan view, the first side etching stop pattern 160 may have a substantially triangular shape.

[0100] The first side etch stop pattern 160 (referred to herein with reference to the first inclined surface 160_SS1 and the second inclined surface 160_SS2) may include at least one substantially linear surface and a (non-linear) connecting surface 160_CS. The first inclined surface 160_SS1 of the first side etch stop pattern faces the connecting sidewall 140_CSW of the first gate spacer. The first inclined surface 160_SS1 of the first side etch stop pattern contacts the connecting sidewall 140_CSW of the first gate spacer. The second inclined surface 160_SS2 of the first side etch stop pattern faces the facet surface of the first semiconductor liner layer 151. The second inclined surface 160_SS2 of the first side etch stop pattern contacts the facet surface of the first semiconductor liner layer 151.

[0101] The connecting surface 160_CS of the first side etch stop pattern connects the first inclined surface 160_SS1 of the first side etch stop pattern and the second inclined surface 160_SS2 of the first side etch stop pattern to each other. According to some embodiments, the entirety of the connecting surface 160_CS of the first side etch stop pattern may contact the first source / drain pattern 150. For example, the entirety of the connecting surface 160_CS of the first side etch stop pattern may contact the first semiconductor fill layer 152.

[0102] In FIG. 5, the first side etch stop pattern 160 may protrude less toward the first gate electrode 120 than the outer sidewall 151_OSW of the first semiconductor liner layer. In FIG. 6, the first side etch stop pattern 160 protrudes less toward the first pattern NS1 than the outer sidewall 151_OSW of the first semiconductor liner layer.

[0103] In a plan view, the first side etch stop pattern 160 covers at least a portion of the facet surface of the first semiconductor liner layer 151. The first semiconductor fill layer 152 may contact a portion of the facet surface of the first semiconductor liner layer 151. Compared to the illustration in the figures, when the first side etch stop pattern 160 covers the entirety of the facet surface of the first semiconductor liner layer 151, the first semiconductor fill layer 152 does not contact the facet surface of the first semiconductor liner layer 151.

[0104] In FIG. 5, the maximum width of the first semiconductor liner layer 151 in the second direction D2 is the first width W11. The width of the interface between the first semiconductor liner layer 151 and the first semiconductor fill layer 152 in the second direction D2 is the second width W21. Since the first side etch stop pattern 160 covers a part of the inner sidewall 151_ISW of the first semiconductor liner layer, the first width W11 is greater than the second width W21. Here, the interface between the first semiconductor liner layer 151 and the first semiconductor fill layer 152 is the contact surface between the first semiconductor liner layer 151 and the first semiconductor fill layer 152.

[0105] In FIG. 6, the maximum width of the first semiconductor liner layer 151 in the second direction D2 is the third width W12. The width of the interface between the first semiconductor liner layer 151 and the first semiconductor fill layer 152 in the second direction D2 is the fourth width W22. The third width W12 is greater than the fourth width W22.

[0106] In FIG. 5, the thickness or dimension of the first side etch stop pattern 160 in the first direction D1 is the first thickness T11. In FIG. 6, the thickness or dimension of the first side etch stop pattern 160 in the first direction D1 is the second thickness T12. The thickness T11 of the first side etch stop pattern 160 at the level of the internal gate structure is shown to be greater than the thickness T12 of the first side etch stop pattern 160 at the level of the first dummy pattern in FIGS. 5 and 6, but this is for convenience of explanation only and the present disclosure is not limited thereto.

[0107] As an example, the first side etch stop pattern 160 may include an insulating material. For example, the first side etch stop pattern 160 may include at least one of silicon nitride and silicon carbide, but is not limited thereto. As another example, the first side etch stop pattern 160 may include a semiconductor material. For example, the first side etch stop pattern 160 may include silicon, but is not limited thereto. As another example, the first side etch stop pattern 160 may include a metal.

[0108] In the following description, the first side etch stop pattern 160 includes an insulating material. For example, the first side etch stop pattern 160 may include silicon nitride.

[0109] In FIGS. 48 and 53, although the sacrificial pattern SC_L is removed, the etchant used to remove the sacrificial pattern SC_L may penetrate into the adjacent area of the connecting sidewall 140_CSW of the first gate spacer. The penetrating etchant etches the first semiconductor fill layer 152, and thus, the reliability and performance of the semiconductor device may deteriorate.

[0110] However, the first side etch stop pattern 160 is formed between the first gate spacer 140 and the first semiconductor lining layer 151, and thus, the etchant can be prevented from penetrating into the adjacent area of the connecting sidewall 140_CSW of the first gate spacer. Therefore, the first side etch stop pattern 160 can prevent the first semiconductor filling layer 152 from being etched by the etchant.

[0111] The source / drain etch stop layer 185 can extend along the outer sidewall 140_OSW of the first gate spacer and the contour of the first source / drain pattern 150. Although not shown in the figure, the source / drain etch stop layer 185 can be disposed on the upper surface of the field insulation layer 105.

[0112] The source / drain etch stop layer 185 can include a material having etch selectivity with respect to the first interlayer insulation layer 190 to be described later. The source / drain etch stop layer 185 can include, for example, at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), boron oxy silicon nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0113] The first interlayer insulation layer 190 can be disposed on the source / drain etch stop layer 185. The first interlayer insulation layer 190 can be disposed on the first source / drain pattern 150. The first interlayer insulation layer 190 may not cover the upper surface of the first gate capping pattern 145. For example, the upper surface of the first interlayer insulation layer 190 can be coplanar with the upper surface of the first gate capping pattern 145.

[0114] The first interlayer insulating layer 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials. The low-k materials may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but is not limited thereto.

[0115] The first source / drain contact 180 is disposed on the first source / drain pattern 150. The first source / drain contact 180 is connected to the first source / drain pattern 150. The first source / drain contact 180 may penetrate through the first interlayer insulating layer 190 and the source / drain etch stop layer 185 to be connected to the first source / drain pattern 150.

[0116] The first metal silicide layer 155 may be further disposed between the first source / drain contact 180 and the first source / drain pattern 150.

[0117] The first source / drain contact 180 is shown as a single layer, but this is for convenience of explanation only, and the present disclosure is not limited thereto. The first source / drain contact 180 may include, for example, at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional (2D) material.

[0118] The first metal silicide layer 155 may include metal silicide.

[0119] The second interlayer insulating layer 191 is disposed on the first interlayer insulating layer 190. The second interlayer insulating layer 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-k material.

[0120] The wiring structure 205 is disposed in the second interlayer insulating layer 191. The wiring structure 205 may be connected to the first source / drain contact 180. The wiring structure 205 may include a wiring line 207 and a wiring via 206.

[0121] The wiring line 207 and the wiring via 206 are shown separated from each other, but this is for convenience of explanation only, and the present disclosure is not limited thereto. That is, as an example, after forming the wiring via 206, the wiring line 207 may be formed. As another example, the wiring via 206 and the wiring line 207 may be formed at the same time.

[0122] The wiring line 207 and the wiring via 206 are each shown as a single layer, but this is for convenience of explanation only, and the present disclosure is not limited thereto. Each of the wiring line 207 and the wiring via 206 may include, for example, at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional (2D) material.

[0123] For example, the upper surface of the first source / drain contact 180 at a portion connected to the wiring structure 205 may be coplanar with the upper surface of the first source / drain contact 180 at a portion not connected to the wiring structure 205.

[0124] FIG. 9 and FIG. 10 are diagrams for describing a semiconductor device according to some embodiments. FIG. 11 and FIG. 12 are diagrams for describing a semiconductor device according to some embodiments. For convenience of explanation, contents different from those described with reference to FIGS. 1 to 8 will be mainly described. For reference, FIG. 9 and FIG. 11 are plan views taken along line C-C of FIG. 2 and viewed from above. FIG. 10 is an enlarged view of part Q of FIG. 9, and FIG. 12 is an enlarged view of part Q of FIG. 11.

[0125] Referring to FIGS. 9 and 10, in a semiconductor device according to some embodiments, a first side etching stop pattern 160 may include an etching stop liner 161 and an etching stop fill layer 162.

[0126] The etching stop liner 161 extends along a connection sidewall 140_CSW of a first gate spacer and a faceted surface of a first semiconductor liner layer 151. The etching stop liner 161 extends along a faceted surface 151_FSW of an inner sidewall 151_ISW of the first semiconductor liner layer.

[0127] The etching stop liner 161 includes a first inclined surface 160_SS1 and a second inclined surface 160_SS2 of the first side etching stop pattern.

[0128] An etching stop stripping layer 162 is disposed on the etching stop liner 161. The etching stop fill layer 162 is disposed between the etching stop liner 161 and a first semiconductor fill layer 152. A part of a connection surface 160_CS of the first side etching stop pattern is defined by the etching stop fill layer 162.

[0129] The etching stop liner 161 may include, for example, silicon oxide, but is not limited thereto. The etching stop fill layer 162 may include, for example, silicon nitride, but is not limited thereto.

[0130] Referring to FIGS. 11 and 12, in a semiconductor device according to some embodiments, a first source / drain pattern 150 may include a side air gap 160_AG.

[0131] The side air gap 160_AG may be disposed between the first side etching stop pattern 160 and the first semiconductor fill layer 152. At least a part of the connection surface 160_CS of the first side etching stop pattern does not contact the first semiconductor fill layer 152.

[0132] Although not shown in the drawings, in a plan view at the level of the first pattern NS1, the side surface air gap 160_AG may be disposed between the first side etch stop pattern 160 and the first semiconductor fill layer 152. The side air gap 160_AG may extend in a third direction D3 between the first side etch stop pattern 160 and the first semiconductor fill layer 152.

[0133] The number of side air gaps 160_AG has been shown in FIG. 11 to be the same as the number of the first side etch stop patterns 160, but the present disclosure is not limited thereto. The number of side air gaps 160_AG may be less than the number of the first side etch stop patterns 160.

[0134] FIGS. 13 to 16 are diagrams for describing a semiconductor device according to some embodiments. For convenience of explanation, contents different from those described with reference to FIGS. 1 to 8 will be mainly described. For reference, FIG. 14 is a plan view taken along line D-D of FIG. 13 and viewed from above. FIG. 15 is an enlarged view of the pinning region 151_PIN of FIG. 13, and FIG. 16 is an enlarged view of a portion R of FIG. 14.

[0135] Referring to FIGS. 13 to 16, a semiconductor device according to some embodiments may further include a first internal etch stop pattern 165 disposed in the first source / drain pattern 150.

[0136] The first semiconductor liner layer 151 may include a pinning region 151_PIN. The first semiconductor liner layer 151 extending along the sidewalls of the first source / drain recess 150R may include a pinning region 151_PIN. For example, the pinning region 151_PIN may be formed at a position overlapping the first pattern NS1 in a first direction D1.

[0137] In the cross-sectional view shown in FIG. 3, the thickness of the first semiconductor liner layer 151 in the pinning region 151_PIN may rapidly decrease. In the pinning region 151_PIN, the thickness of the first semiconductor liner layer 151 decreases as it moves away from the first lower pattern BP1 and then increases.

[0138] In the plan view shown in FIG. 14, the inner sidewall 151_ISW of the first semiconductor liner layer in the pinning region 151_PIN can be divided into two parts. For example, in the pinning region 151_PIN, the inner sidewall 151_ISW of the first semiconductor liner layer can be connected to the outer sidewall 151_OSW of the first semiconductor liner layer. Different from that shown in FIG. 14, in the pinning region 151_PIN, the inner sidewall 151_ISW of the first semiconductor liner layer can be spaced apart from the outer sidewall 151_OSW of the first semiconductor liner layer in the first direction D1.

[0139] A first semiconductor liner layer 151 including a pinning region 151_PIN has been shown, but the present disclosure is not limited thereto. A first semiconductor liner layer 151 may also include multiple pinning regions 151_PIN.

[0140] Some of the first source / drain patterns 150 have been shown to include the pinning region 151_PIN, and others of the first source / drain patterns 150 do not include the pinning region 151_PIN, but the present disclosure is not limited thereto.

[0141] Different from that shown in the drawings, the pinning region 151_PIN can be formed at a position overlapping with the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 in the first direction D1.

[0142] The first internal etch stop pattern 165 can be disposed in the pinning region 151_PIN. The first internal etch stop pattern 165 is disposed between the first semiconductor liner layer 151 and the first semiconductor fill layer 152. The first internal etch stop pattern 165 is in direct contact with the first semiconductor liner layer 151.

[0143] In a plan view, the width of the first internal etch stop pattern 165 in the second direction D2 may increase in a direction away from the first gate electrode 120 and the first spacer pattern NS1. The first internal etch stop pattern 165 may have a substantially triangular shape. The first internal etch stop pattern 165 may include a first sloped surface 165_SS1, a second sloped surface 165_SS2, and a connecting surface 165_CS. The first sloped surface 165_SS1 of the first internal etch stop pattern and the second sloped surface 165_SS2 of the first internal etch stop pattern are in contact with the first semiconductor liner layer 151. The connecting surface 165_CS of the first internal etch stop pattern connects the first sloped surface 165_SS1 of the first internal etch stop pattern and the second sloped surface 165_SS2 of the first internal etch stop pattern to each other.

[0144] In a cross-sectional view, the width of the first internal etch stop pattern 165 in the third direction D3 may increase in a direction away from the first gate electrode 120 and the first spacer pattern NS1. The first internal etch stop pattern 165 may have a triangular shape. The first internal etch stop pattern 165 may include a third sloped surface 165_SS3 and a fourth sloped surface 165_SS4. The third sloped surface 165_SS3 of the first internal etch stop pattern and the fourth sloped surface 165_SS4 of the first internal etch stop pattern are in contact with the first semiconductor liner layer 151. The connecting surface 165_CS of the first internal etch stop pattern connects the third sloped surface 165_SS3 of the first internal etch stop pattern and the fourth sloped surface 165_SS4 of the first internal etch stop pattern to each other.

[0145] In a semiconductor device according to some embodiments, the entire connecting surface 165_CS of the first internal etch stop pattern may be in contact with the first semiconductor fill layer 152.

[0146] The first internal etch stop pattern 165 includes the same material as the first sidewall etch stop pattern 160. When the first sidewall etch stop pattern 160 has a multi-layer structure as shown in FIG. 9, the first internal etch stop pattern 165 has the same multi-layer structure as the first sidewall etch stop pattern 160.

[0147] FIGS. 17 to 19 are diagrams for describing a semiconductor device according to some embodiments. For convenience of explanation, contents different from those described with reference to FIGS. 13 to 16 will be mainly described. For reference, FIG. 17 is a plan view taken along line D-D of FIG. 13 and viewed from above. FIG. 18 is an enlarged view of the pinned region 151_PIN of FIG. 13, and FIG. 19 is an enlarged view of a portion R of FIG. 17.

[0148] Referring to FIGS. 17 to 19, in a semiconductor device according to some embodiments, the first source / drain pattern 150 may include an internal air gap 165_AG.

[0149] The internal air gap 165_AG may be disposed between the first internal etch stop pattern 165 and the first semiconductor fill layer 152. At least a portion of the connection surface 165_CS of the first internal etch stop pattern does not contact the first semiconductor fill layer 152.

[0150] Although not shown in the drawings, in a plan view at the level of the internal gate structure, the internal air gap 165_AG may be disposed between the first internal etch stop pattern 165 and the first semiconductor fill layer 152.

[0151] FIGS. 20 and 21 are diagrams for describing a semiconductor device according to some embodiments. FIGS. 22 and 23 are diagrams for describing a semiconductor device according to some embodiments. For convenience of explanation, contents different from those described with reference to FIGS. 1 to 8 will be mainly described. For reference, FIGS. 20 and 22 are enlarged views of a portion P of FIG. 2. FIGS. 21 and 23 are plan views taken along line C-C of FIG. 2 and viewed from above.

[0152] Referring to FIGS. 2, 20, and 21, a semiconductor device according to some embodiments may further include a semiconductor residue pattern SP_R disposed between the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, the internal gate structure INT3_GS1, and the first semiconductor liner layer 151.

[0153] In the cross-sectional view shown in FIG. 20, the semiconductor residue pattern SP_R may contact the first pattern NS1. The semiconductor residue pattern SP_R may contact the outer sidewall 151_OSW of the first semiconductor liner layer and the sidewalls of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1.

[0154] In the plan view shown in FIG. 21, the semiconductor residue pattern SP_R can be in contact with the outer sidewall 151_OSW of the first semiconductor liner layer, the sidewalls of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1, and the connecting sidewall 140_CSW of the first gate spacer.

[0155] The semiconductor residue pattern SP_R can include, for example, silicon-germanium. The germanium fraction in the semiconductor residue pattern SP_R is greater than the germanium fraction in the first semiconductor liner layer 151. The semiconductor residue pattern SP_R can be the residue remaining after removing the sacrificial pattern SC_L (see FIG. 48).

[0156] Different from that described above, as an example, the semiconductor residue pattern SP_R may appear in the cross-sectional view shown in FIG. 20, but may not appear in the plan view shown in FIG. 21. As another example, the semiconductor residue pattern SP_R may appear in the plan view shown in FIG. 21, but may not appear in the cross-sectional view shown in FIG. 20.

[0157] Referring to FIGS. 2, 22, and 23, the semiconductor device according to some embodiments may further include an internal gate air gap INT_AG disposed between the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, the internal gate structure INT3_GS1, and the first semiconductor liner layer 151.

[0158] In the cross-sectional view shown in FIG. 22, the internal gate air gap INT_AG can be disposed between the first semiconductor liner layer 151 of the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1 and the first gate insulating layer 130. The internal gate air gap INT_AG can be defined between the first semiconductor liner layer 151, the first pattern NS1, and the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, and the internal gate structure INT3_GS1.

[0159] In the plan view shown in FIG. 23, the internal gate air gap INT_AG can be disposed between the first semiconductor liner layer 151, the internal gate structure INT1_GS1, the internal gate structure INT2_GS1, the internal gate structure INT3_GS1, and the first gate spacer 140.

[0160] Different from what is described above, as an example, an internal gate air gap INT_AG may appear in the cross-sectional view shown in FIG. 22, but may not appear in the plan view shown in FIG. 23. As another example, an internal gate air gap INT_AG may appear in the plan view shown in FIG. 23, but may not appear in the cross-sectional view shown in FIG. 22.

[0161] FIG. 24 is a diagram for describing a semiconductor device according to some embodiments. FIGS. 25 to 27 are diagrams for describing a semiconductor device according to some embodiments. For convenience of explanation, the content different from that described with reference to FIGS. 1 to 8 will be mainly described. For reference, FIG. 24 is a plan view taken along line C-C of FIG. 2 and viewed from above.

[0162] Referring to FIG. 24, in a semiconductor device according to some embodiments, the first side etching stop pattern 160 may protrude toward the first gate electrode 120 beyond the outer sidewall 151_OSW of the first semiconductor liner layer.

[0163] In the process of removing the sacrificial pattern SC_L (see FIG. 48), a part of the first semiconductor liner layer 151 may be removed. Accordingly, the first side etching stop pattern 160 may protrude beyond the outer sidewall 151_OSW of the first semiconductor liner layer.

[0164] Although not shown in the drawings, in the plan view at the level of the first pattern, the first side etching stop pattern 160 may protrude less toward the first pattern NS1 than the outer sidewall 151_OSW of the first semiconductor liner layer.

[0165] Referring to FIG. 25, in a semiconductor device according to some embodiments, the first source / drain recess 150R does not include a plurality of width extension regions 150R_ER (see FIG. 2).

[0166] The sidewalls of the first source / drain recess 150R do not have a wavy shape (i.e., the sidewalls may be substantially straight or planar). The width of the upper portion of the sidewall of the first source / drain recess 150R in the first direction D1 may decrease as it moves away from the first lower pattern BP1.

[0167] Referring to FIG. 26, in a semiconductor device according to some embodiments, the upper surface of the first source / drain contact 180 at a portion not connected to the wiring structure 205 is lower than the upper surface of the first gate capping pattern 145.

[0168] The upper surface of the first source / drain contact 180 at the portion connected to the wiring structure 205 is lower than the upper surface of the first source / drain contact 180 at the portion not connected to the wiring structure 205.

[0169] Referring to FIG. 27, in a semiconductor device according to some embodiments, the first source / drain contact 180 includes a lower source / drain contact 181 and an upper source / drain contact 182.

[0170] The upper source / drain contact 182 may be disposed at a portion connected to a part of the wiring structure 205. On the other hand, the upper source / drain contact 182 may not be disposed at a portion not connected to a part of the wiring structure 205.

[0171] The wiring line 207 may be connected to the first source / drain contact 180 without a wiring via 206 (see FIG. 2). The wiring structure 205 may not include a wiring via 206 (see FIG. 2).

[0172] Each of the lower source / drain contact 181 and the upper source / drain contact 182 is shown as a single layer in FIG. 27, but this is only for convenience of explanation, and the present disclosure is not limited thereto. Each of the lower source / drain contact 181 and the upper source / drain contact 182 may include at least one of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0173] FIGS. 28 to 31 are diagrams for describing a semiconductor device according to some embodiments. For reference, FIG. 28 is an illustrative plan view for describing a semiconductor device according to some embodiments. FIG. 29 is a cross-sectional view taken along line E-E of FIG. 28. FIG. 30 is a plan view taken along line F-F of FIG. 28 and viewed from above. FIG. 31 is a plan view taken along line G-G of FIG. 28 and viewed from above.

[0174] Meanwhile, a cross-sectional view taken along line A-A of FIG. 28 may be the same as one of FIGS. 2, 13, and 25 to 27. In addition, the description of the first region I of FIG. 28 may be substantially the same as that of the first region I described with reference to FIGS. 1 to 27. Therefore, in the following description, the content of the second region II of FIG. 28 will be mainly described.

[0175] Referring to FIGS. 28 to 31, a semiconductor device according to some embodiments may include a first active pattern AP1, a plurality of first gate structures GS1, a first source / drain pattern 150, a first side etch stop pattern 160 (see FIG. 5), a second active pattern AP2, a plurality of second gate structures GS2, a second source / drain pattern 250, and a second side etch stop pattern 260.

[0176] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions where PMOS is formed.

[0177] The first active pattern AP1, the plurality of first gate structures GS1, the first source / drain pattern 150, and the first side etch stop pattern 160 are disposed in the first region I of the substrate 100. The second active pattern AP2, the plurality of second gate structures GS2, the second source / drain pattern 250, and the second side etch stop pattern 260 are disposed in the second region II of the substrate 100.

[0178] The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second fin patterns NS2. The plurality of second fin patterns NS2 may be spaced apart from the second lower pattern BP2 in a third direction D3. The second fin pattern NS2 includes an upper surface NS2_US and a lower surface NS2_BS that are opposite to each other in the third direction D3. Each of the second lower pattern BP2 and the second fin pattern NS2 may include one of silicon or germanium, which is an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. In a semiconductor device according to some embodiments, the second lower pattern BP2 may be a silicon lower pattern including silicon, and the second fin pattern NS2 may be a silicon fin pattern including silicon.

[0179] The width W32 of the upper surface BP2_US of the second lower pattern in the second direction D2 is smaller than the width W31 of the upper surface BP1_US of the first lower pattern in the second direction D2. The width of the second fin pattern NS2 in the second direction D2 is smaller than the width of the first fin pattern NS1 in the second direction D2.

[0180] A plurality of second gate structures GS2 can be disposed on the substrate 100. The second gate structure GS2 can be disposed on the second active pattern AP2. The second gate structure GS2 can cross the second active pattern AP2. The second gate structure GS2 can cross the second lower pattern BP2. The second gate structure GS2 can surround each of the second sheet patterns NS2. The second gate structure GS2 can include a plurality of internal gate structures INT1_GS2, internal gate structure INT2_GS2, and internal gate structure INT3_GS2 disposed between the second sheet patterns NS2 adjacent to each other in the third direction D3 and between the second lower pattern BP2 and the second sheet pattern NS2.

[0181] The second gate structure GS2 can include, for example, a second gate electrode 220, a second gate insulating layer 230, a second gate spacer 240, and a second gate capping pattern 245. The second gate spacer 240 can include an inner sidewall 240_ISW, a connecting sidewall 240_CSW, and an outer sidewall 240_OSW. The descriptions of the second gate electrode 220, the second gate insulating layer 230, the second gate spacer 240, and the second gate capping pattern 245 are substantially the same as the descriptions of the first gate electrode 120, the first gate insulating layer 130, the first gate spacer 140, and the first gate capping pattern 145, and thus will be omitted hereinafter.

[0182] The second source / drain pattern 250 can be disposed on the second active pattern AP2. The second source / drain pattern 250 can be disposed on the second lower pattern BP2. The second source / drain pattern 250 can be connected to the second sheet pattern NS2. The second source / drain pattern 250 can be included in the source / drain of a transistor using the second sheet pattern NS2 as a channel region.

[0183] The second source / drain pattern 250 can be disposed in the second source / drain recess 250R. The second source / drain recess 250R can include a plurality of width extension regions 250R_ER. As the width extension region 250R_ER of each of the second source / drain recesses moves away from the upper surface BP2_US of the second lower pattern, it can include a portion where its width increases in the first direction D1 and a portion where its width decreases in the first direction D1.

[0184] The second source / drain pattern 250 can be in contact with the second fin pattern NS2 and the second lower pattern BP2. A portion of the second source / drain pattern 250 can be in contact with the connecting sidewall 240_CSW of the second gate spacer. The second gate insulating layer 230 of the internal gate structure INT1_GS2, the internal gate structure INT2_GS2, and the internal gate structure INT3_GS2 can be in contact with the second source / drain pattern 250.

[0185] The second source / drain pattern 250 can include an epitaxial pattern. The second source / drain pattern 250 includes a semiconductor material. The second source / drain pattern 250 can include a second semiconductor liner layer 251 and a second semiconductor fill layer 252. The second semiconductor fill layer 252 is shown as a single layer, but this is for convenience of explanation only, and the present disclosure is not limited thereto.

[0186] The second semiconductor liner layer 251 can include an outer sidewall 251_OSW and an inner sidewall 251_ISW. The inner sidewall 251_ISW of the second semiconductor liner layer can include a facet surface 251_FSW and a connecting surface 251_CSW. The description of the shape and material of the second source / drain pattern 250 is substantially the same as the description of the shape and material of the first source / drain pattern 150, and thus will be omitted hereinafter.

[0187] The second side etch stop pattern 260 can be disposed between the second gate spacer 240 and the second source / drain pattern 250. The second side etch stop pattern 260 can be disposed between the second gate spacer 240 and the second semiconductor liner layer 251.

[0188] In FIGS. 30 and 31, the second side etch stop pattern 260 can extend in a third direction D3 between the second gate spacer 240 and the second source / drain pattern 250.

[0189] The second side etch stop pattern 260 can be disposed between the connecting sidewall 240_CSW of the second gate spacer and the facet surface 251_FSW of the inner sidewall 251_ISW of the second semiconductor liner layer. The second side etch stop pattern 260 can be disposed between the connecting sidewall 240_CSW of the second gate spacer and the facet surface of the second semiconductor liner layer 251.

[0190] The second side etch stop pattern 260 can be in direct contact with the second gate spacer 240 and the second source / drain pattern 250. The second side etch stop pattern 260 can be in contact with the connecting sidewall 240_CSW of the second gate spacer and the facet surface of the second semiconductor liner layer 251.

[0191] The width of the second side etch stop pattern 260 in the second direction D2 can increase in the direction away from the second gate electrode 220. In a plan view, the second side surface etch stop pattern 260 can have a substantially triangular shape.

[0192] In a plan view, the second side etch stop pattern 260 covers at least a portion of the facet surface of the second semiconductor liner layer 251. The second semiconductor fill layer 252 can be in contact with a portion of the facet surface of the second semiconductor liner layer 251.

[0193] In FIG. 30, since the second side etch stop pattern 260 covers a portion of the inner sidewall 251_ISW of the second semiconductor liner layer 251, the maximum width W41 of the second semiconductor liner layer 251 in the second direction D2 is greater than the width W51 of the interface between the second semiconductor liner layer 251 and the second semiconductor fill layer 252 in the second direction D2.

[0194] In FIG. 31, the maximum width W42 of the second semiconductor liner layer 251 in the second direction D2 is greater than the width W52 of the interface between the second semiconductor liner layer 251 and the second semiconductor fill layer 252 in the second direction D2.

[0195] In FIG. 30, the thickness of the second side surface etch stop pattern 260 in the first direction D1 is the third thickness T21. In FIG. 31, the thickness of the second side surface etch stop pattern 260 in the first direction D1 is the fourth thickness T22. The thickness T21 of the second side surface etch stop pattern 260 at the level of the internal gate structure is shown in FIGS. 30 and 31 to be greater than the thickness T22 of the second side surface etch stop pattern 260 at the level of the second sheet pattern, but this is for convenience of explanation only and the present disclosure is not limited thereto.

[0196] In FIGS. 5 and 30, the thickness T11 of the first side etch stop pattern 160 in the first direction D1 is greater than the thickness T21 of the second side etch stop pattern 260 in the first direction D1.

[0197] In FIGS. 6 and 31, the thickness T21 of the first side etch stop pattern 160 in the first direction D1 is greater than the thickness T22 of the second side etch stop pattern 260 in the first direction D1.

[0198] As an example, the internal etch stop pattern described with reference to FIGS. 13 to 19 may not be disposed in the second source / drain pattern 250.

[0199] As another example, the internal etch stop pattern described with reference to FIGS. 13 to 19 may be disposed in the second source / drain pattern 250. In this case, the thickness of the internal etch stop pattern in the second source / drain pattern 250 in the first direction D1 is less than the thickness of the first internal etch stop pattern 165 (see FIG. 14) in the first source / drain pattern 150 in the first direction D1.

[0200] The second source / drain contact 280 is disposed on the second source / drain pattern 250. The second source / drain contact 280 is connected to the second source / drain pattern 250. The second metal silicide layer 255 may be further disposed between the second source / drain contact 280 and the second source / drain pattern 250.

[0201] FIG. 32 is a diagram for describing a semiconductor device according to some embodiments. For convenience of explanation, the content different from that described with reference to FIGS. 28 to 31 will be mainly described. For reference, FIG. 32 is a plan view taken along line F-F of FIG. 28 and viewed from above.

[0202] Referring to FIG. 32, in a semiconductor device according to some embodiments, the second side etch stop pattern 260 (see FIG. 30) is not disposed between the second source / drain pattern 250 and the second gate spacer 240.

[0203] The maximum width W41 of the second semiconductor liner layer 251 in the second direction D2 may be the same as the width W51 of the interface between the second semiconductor liner layer 251 and the second semiconductor fill layer 252 in the second direction D2.

[0204] Although not shown in the drawings, those of ordinary skill in the art to which the present disclosure pertains can perceive a plan view taken along line G-G of FIG. 29 and viewed from above via FIG. 32.

[0205] Figures 33 to 35 are diagrams for describing a semiconductor device according to some embodiments. For reference, FIG. 33 is an illustrative plan view for describing a semiconductor device according to some embodiments. FIGS. 34 and 35 are cross-sectional views taken along line H-H of FIG. 33.

[0206] In addition, a cross-sectional view taken along line A-A of FIG. 33 may be the same as one of FIGS. 2, 13, and 25 to 27. In addition, the description of the first region I of FIG. 33 may be substantially the same as that of the first region I described with reference to FIGS. 1 to 27. Therefore, in the following description, the content of the third region III of FIG. 33 will be mainly described.

[0207] Referring to FIGS. 33 to 35, a semiconductor device according to some embodiments may include a first active pattern AP1, a plurality of first gate structures GS1, a first source / drain pattern 150, a first side etch stop pattern 160 (see FIG. 5), a third active pattern AP3, a plurality of third gate structures GS3, and a third source / drain pattern 350.

[0208] The substrate 100 may include a first region I and a third region III. The first region I may be a region where PMOS is formed, and the third region III may be a region where NMOS is formed.

[0209] The first active pattern AP1, the plurality of first gate structures GS1, the first source / drain pattern 150, and the first side etch stop pattern 160 are disposed in the first region I of the substrate 100. The third active pattern AP3, the plurality of third gate structures GS3, and the third source / drain pattern 350 are disposed in the third region III of the substrate 100.

[0210] The third active pattern AP3 may include a third lower pattern BP3 and a plurality of third sheet patterns NS3. The plurality of third sheet patterns NS3 are disposed on the upper surface BP3_US of the third lower pattern. The third sheet pattern NS3 includes an upper surface NS3_US and a lower surface NS3_BS that face each other in the third direction D3. Each of the third lower pattern BP3 and the third sheet pattern NS3 may include one of silicon or germanium, which is an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. In the semiconductor device according to some embodiments, the third lower pattern BP3 may be a silicon lower pattern including silicon, and the third sheet pattern NS3 may be a silicon sheet pattern including silicon.

[0211] A plurality of third gate structures GS3 can be disposed on the substrate 100. The third gate structure GS3 can be disposed on the third active pattern AP3. The third gate structure GS3 can intersect the third active pattern AP3. The third gate structure GS3 can intersect the third lower pattern BP3. The third gate structure GS3 can surround each of the third fin patterns NS3. The third gate structure GS3 can include a plurality of internal gate structures INT1_GS3, internal gate structure INT2_GS3, and internal gate structure INT3_GS3 disposed between the third fin patterns NS3 adjacent to each other in the third direction D3 and between the third lower pattern BP3 and the third fin pattern NS3. The third gate structure GS3 can include, for example, a third gate electrode 320, a third gate insulating layer 330, a third gate spacer 340, and a third gate capping pattern 345.

[0212] In FIG. 34, the third gate spacer 340 is not disposed between the plurality of internal gate structures INT1_GS3, internal gate structure INT2_GS3, and internal gate structure INT3_GS3 and the third source / drain pattern 350. The third gate insulating layer 330 included in the internal gate structures INT1_GS3, internal gate structure INT2_GS3, and internal gate structure INT3_GS3 can contact the third source / drain pattern 350.

[0213] In FIG. 35, the third gate structure GS3 can include an internal spacer ISP_GS3. The internal spacer ISP_GS3 can be disposed between the third fin patterns NS3 adjacent to each other in the third direction D3 and between the third lower pattern BP3 and the third fin pattern NS3. The internal spacer ISP_GS3 can contact the third gate insulating layer 330 included in the internal gate structures INT1_GS3, internal gate structure INT2_GS3, and internal gate structure INT3_GS3. The internal spacer ISP_GS3 can define a part of the third source / drain recess 350R.

[0214] The third source / drain pattern 350 can be formed on the third active pattern AP3. The third source / drain pattern 350 can be formed on the third lower pattern BP3. The third source / drain pattern 350 can be connected to the third fin pattern NS3. The third source / drain pattern 350 can be included in the source / drain of a transistor using the third fin pattern NS3 as a channel region.

[0215] The third source / drain pattern 350 may be disposed in the third source / drain recess 350R. The bottom surface of the third source / drain recess 350R may be defined by the third lower pattern BP3. The sidewalls of the third source / drain recess 350R may be defined by the third spacer pattern NS3 and the third gate structure GS3.

[0216] The third source / drain pattern 350 may include an epitaxial pattern. The third source / drain pattern 350 may include, for example, silicon or germanium, which are elemental semiconductor materials. Additionally, the third source / drain pattern 350 may include, for example, a binary compound or a ternary compound containing two or more than two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with group-IV elements. For example, the third source / drain pattern 350 may include silicon, silicon-germanium, silicon carbide, or the like, but is not limited thereto.

[0217] The third source / drain pattern 350 may include impurities doped into the semiconductor material. For example, the third source / drain pattern 350 may include n-type impurities. The doped impurities may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0218] In FIG. 34, the third source / drain recess 350R may include a plurality of width extension regions 350R_ER.

[0219] In FIG. 35, the third source / drain recess 350R does not include a plurality of width extension regions 350R_ER.

[0220] The third source / drain contact 380 is disposed on the third source / drain pattern 350. The third source / drain contact 380 is connected to the third source / drain pattern 350. The third metal silicide layer 355 may be further disposed between the third source / drain contact 380 and the third source / drain pattern 350.

[0221] Figures 36 to 53 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Figures 36 to 39, 42, 45, and 50 to 52 may be cross-sectional views taken along line A-A of FIG. 1. Figures 40 and 41 are plan views taken along line C-C and line D-D of FIG. 39, respectively, and viewed from above. Figures 43 and 44 are plan views taken along line C-C and line D-D of FIG. 42, respectively, and viewed from above. Figures 46 to 49 are plan views taken along line C-C and line D-D of FIG. 45, respectively, and viewed from above. Figure 53 is a plan view taken along line C-C of FIG. 52 and viewed from above.

[0222] Referring to FIG. 36, a first lower pattern BP1 and an upper pattern structure U_AP may be formed on a substrate 100.

[0223] The first lower pattern BP1 extends in a first direction D1. The upper pattern structure U_AP may be disposed on the first lower pattern BP1. The upper pattern structure U_AP may include a sacrificial pattern SC_L and an active pattern ACT_L alternately stacked on the first lower pattern BP1. For example, the sacrificial pattern SC_L may include a silicon-germanium layer. The active pattern ACT_L may include a silicon layer. The germanium fraction in the sacrificial pattern SC_L is greater than the germanium fraction in the first semiconductor liner layer 151 of FIG. 2.

[0224] Next, a dummy gate structure extending in a second direction D2 is formed on the upper pattern structure U_AP. The dummy gate structure may include a dummy gate insulating layer 130p, a dummy gate electrode 120p, a dummy gate capping layer 120_HM, and a pre-gate spacer 140p. The dummy gate insulating layer 130p may include, for example, silicon oxide, but is not limited thereto. The dummy gate electrode 120p may include, for example, polysilicon, but is not limited thereto. The gate capping layer 120_HM may include, for example, silicon nitride, but is not limited thereto.

[0225] The pre-gate spacer 140p may include an inner sidewall 140_ISW (see FIG. 40), a connecting sidewall 140_CSW (see FIG. 40), and an outer sidewall 140_OSW (see FIG. 40).

[0226] The inner sidewall 140_ISW of the pre-gate spacer faces the sidewall of the dummy gate electrode 120p extending in the second direction D2. The outer sidewall 140_OSW of the pre-gate spacer is the surface opposite to the inner sidewall 140_ISW of the pre-gate spacer. The connecting sidewall 140_CSW of the pre-gate spacer connects the inner sidewall 140_ISW and the outer sidewall 140_OSW of the pre-gate spacer to each other.

[0227] Referring to FIG. 37, the first source / drain recess 150R can be formed in the upper pattern structure U_AP using the dummy gate structure as a mask.

[0228] A part of the first source / drain groove 150R can be formed in the first lower pattern BP1.

[0229] Referring to FIG. 38, the part of the sacrificial pattern SC_L exposed by the first source / drain recess 150R can be removed.

[0230] Therefore, the width extension region 150R_ER of the plurality of first source / drain recesses can be formed. The first source / drain recess 150R can include the width extension region 150R_ER of the first source / drain recess.

[0231] In FIGS. 37 and 38, the first source / drain recess 150R can expose at least a part of the connecting sidewall 140_CSW (see FIG. 40) of the pre-gate spacer.

[0232] Referring to FIGS. 39 and 41, the first semiconductor liner layer 151 can be formed along the contour of the first source / drain recess 150R.

[0233] The first semiconductor liner layer 151 can include an outer sidewall 151_OSW and an inner sidewall 151_ISW. The outer sidewall 151_OSW of the first semiconductor liner layer can be in direct contact with the sacrificial pattern SC_L and the active pattern ACT_L. The inner sidewall 151_ISW of the second semiconductor liner layer can include a facet surface 151_FSW and a connecting surface 151_CSW. The facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor liner layer can extend from the connecting sidewall 140_CSW of the pre-gate spacer.

[0234] Referring to FIGS. 42 to 44, the pre-etching blocking layer 160p is formed on the first semiconductor liner layer 151.

[0235] The pre-etching blocking layer 160p is formed along the contour of the first semiconductor lining layer 151. The pre-etching blocking layer 160p is formed along the inner sidewall 151_ISW of the first semiconductor lining layer. The pre-etching blocking layer 160p covers the first semiconductor lining layer 151.

[0236] The pre-etching blocking layer 160p may cover the outer sidewall 140_OSW of the pre-gate spacer and the connecting sidewall 140_CSW of the pre-gate spacer.

[0237] The pre-etching blocking layer 160p may be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto.

[0238] Referring to FIGS. 45 to 47, the pre-etching blocking oxide layer 160p_OX may be formed on the first semiconductor lining layer 151.

[0239] The pre-etching blocking oxide layer 160p_OX may be formed by oxidizing a part of the pre-etching blocking layer 160p. The pre-etching blocking layer 160p may include a residual pre-etching blocking layer 160p_R and a pre-etching blocking oxide layer 160p_OX.

[0240] The residual pre-etching blocking layer 160p_R is disposed between the connecting sidewall 140_CSW of the pre-gate spacer and the facet surface 151_FSW of the inner sidewall 151_ISW of the first semiconductor lining layer. In a plan view, the residual pre-etching blocking layer 160p_R covers at least a part of the facet surface of the first semiconductor lining layer 151.

[0241] Referring to FIGS. 48 and 49, the first side surface etching blocking pattern 160 is formed by removing the pre-etching blocking oxide layer 160p_OX.

[0242] The first side etching blocking pattern 160 may be the residual pre-etching blocking layer 160p_R. The first side etching blocking pattern 160 contacts the facet surface of the first semiconductor lining layer 151 and the connecting sidewall 140_CSW of the pre-gate spacer.

[0243] The first side etching blocking pattern 160 may extend in the third direction D3.

[0244] Referring to FIG. 50, the first semiconductor filling layer 152 is formed on the first semiconductor lining layer 151.

[0245] The first semiconductor fill layer 152 may fill the remainder of the first source / drain recess 150R. In FIGS. 5 and 6, the first semiconductor fill layer 152 is formed on the first side-etching barrier pattern 160.

[0246] Referring to FIG. 51, a source / drain etch stop layer 185 and a first interlayer dielectric layer 190 are sequentially formed on the first source / drain pattern 150. Next, an upper surface of the dummy gate electrode 120p is exposed by removing a portion of the first interlayer dielectric layer 190, a portion of the source / drain etch stop layer 185, and the dummy gate capping layer 120_HM. When the upper surface of the dummy gate electrode 120p is exposed, a first gate spacer 140 may be formed. For example, a connection sidewall 140_CSW of a pre-gate spacer becomes a connection sidewall of the first gate spacer.

[0247] Referring to FIGS. 52 and 53, an upper pattern structure U_AP between the first gate spacers 140 may be exposed by removing the dummy gate insulating layer 130p and the dummy gate electrode 120p.

[0248] Next, a first pattern NS1 may be formed by removing the sacrificial pattern SC_L. Accordingly, a first gate trench 120t is formed between the first gate spacers 140. In addition, a first active pattern AP1 including a first lower pattern BP1 and the first pattern NS1 is formed.

[0249] Next, referring to FIG. 2, a first gate insulating layer 130 and a first gate electrode 120 may be formed in the first gate trench 120t. In addition, a first gate capping pattern 145 may be formed.

[0250] FIGS. 54 and 55 are diagrams for describing a semiconductor device according to some embodiments.

[0251] Referring to FIGS. 54 to 55, a semiconductor device according to some embodiments may include a substrate 500, a durability structure 500_RS, and a blocking pattern 510.

[0252] The substrate 500 may include a surface 500_SF. The substrate 500 may include at least one of, for example, a semiconductor material, an insulating material, and a material including a metal.

[0253] The durability structure 500_RS can be a structure recessed from a surface 500_SF of a substrate.

[0254] The blocking pattern 510 fills the durability structure 500_RS. The blocking pattern 510 is in direct contact with the surface of the durability structure 500_RS. The blocking pattern 510 is not disposed on a surface 500_SF of the substrate.

[0255] The blocking pattern 510 can include at least one of, for example, a semiconductor material, an insulating material, and a material containing a metal. In a semiconductor device according to an embodiment of the present disclosure, the blocking pattern 510 can be made of an insulating material.

[0256] In FIG. 54, the durability structure 500_RS can be formed in a substrate made of a material.

[0257] In FIG. 55, the substrate 500 can include a first portion 500A and a second portion 500B. The durability structure 500_RS can be formed in a boundary region between the first portion 500A and the second portion 500B of the substrate.

[0258] FIGS. 56 to 59 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0259] Referring to FIG. 56, the durability structure 500_RS is formed on a surface 500_SF of a substrate.

[0260] The durability structure 500_RS can be formed by a deposition process, an etching process, or the like, but is not limited thereto.

[0261] Referring to FIG. 57, a pre-blocking layer 510p is formed on a surface 500_SF of a substrate. The pre-blocking layer 510p fills the durability structure 500_RS.

[0262] Referring to FIG. 58, a pre-blocking oxide layer 510p_OX is formed on a surface 500_SF of a substrate.

[0263] The pre-blocking oxide layer 510p_OX can be formed by oxidizing a part of the pre-blocking layer 510p. The pre-blocking layer 510p can include a residual pre-blocking layer 510p_R and the pre-blocking oxide layer 510p_OX.

[0264] Referring to FIG. 59, the blocking pattern 510 is formed by removing the pre-blocking oxide layer 510p_OX. The blocking pattern 510 fills the durability structure 500_RS.

[0265] The blocking pattern 510 can be the residual pre-blocking layer 510p_R.

[0266] In summary, those of ordinary skill in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention concept. Therefore, the disclosed preferred embodiments of the present invention are for general and descriptive purposes only and are not for restrictive purposes.

[0267] 100: Substrate 105: Field insulation layer 120: First gate insulation layer 120_HM: dummy gate capping layer 120p: dummy gate electrode 120t: First gate trench 130: First gate insulation layer 130p: dummy gate insulation layer 140: First gate spacer 140p: pre-gate spacer 140_CSW, 240_CSW: connecting sidewall 140_ISW, 151_ISW, 240_ISW, 251_ISW: inner sidewall 140_OSW, 151_OSW, 240_OSW, 251_OSW: outer sidewall 145: First gate capping pattern 150: First source / drain pattern 150R: First source / drain recess 150R_ER, 250R_ER, 350R_ER: width extension region 151: First semiconductor liner layer 151_CSW, 160_CS, 165_CS, 251_CSW: connecting surface 151_FSW, 251_FSW: facet surface 151_PIN: pinning region 152: First semiconductor fill layer 155: First metal silicide layer 160: First side etching stop pattern 160_AG: Side air gap / side surface air gap 160_SS1, 165_SS1: First inclined surface 160_SS2, 165_SS2: Second inclined surface 160p: Pre-etching stop layer 160p_OX: Pre-etching stop oxide layer 160p_R: Residual pre-etching stop layer 161: Etching stop liner 162: Etching stop filling layer 165: First internal etching stop pattern 165_AG: Internal air gap 165_SS3: Third inclined surface 165_SS4: Fourth inclined surface 180: First source / drain contact 181: Lower source / drain contact 182: Upper source / drain contact 185: Source / drain etching stop layer 190: First interlayer insulating layer 191: Second interlayer insulating layer 205: Wiring structure 206: Wiring via hole 207: Wiring line 220: Second gate electrode 230: Second gate insulating layer 240: Second gate spacer 245: Second gate capping pattern 250: Second source / drain pattern 250R: Second source / drain recess 251: Second semiconductor liner layer 252: Second semiconductor filling layer 255: Second metal silicide layer 260: Second side etching stop pattern / second side surface etching stop pattern 280: Second source / drain contact 320: Third gate electrode 330: Third gate insulating layer 340: Third gate spacer 345: Third gate capping pattern 350: Third source / drain pattern 350R: Third source / drain recess 355: Third metal silicide layer 380: Third source / drain contact 500: Substrate 500_RS: Durability structure 500_SF: Surface 500A: First part 500B: Second part 510: Blocking pattern 510p: Pre-blocking layer 510p_OX: Pre-blocking oxide layer 510p_R: Residual pre-blocking layer A-A, B-B, C-C, D-D, E-E, F-F, G-G, H-H: Lines ACT_L: Active pattern AP1: First active pattern AP2: Second active pattern AP3: Third active pattern BP1: First lower pattern BP1_US, BP2_US, BP3_US, NS1_US, NS2_US, NS3_US: Upper surface BP2: Second lower pattern BP3: Third lower pattern D1: First direction D2: Second direction D3: Third direction GS1: First gate structure GS2: Second gate structure GS3: Third gate structure I: First region II: Second region III: Third region INT_AG: Internal gate air gap INT1_GS1: First internal gate structure INT1_GS2, INT1_GS3, INT2_GS2, INT2_GS3, INT3_GS2, INT3_GS3: Internal gate structures INT2_GS1: Second internal gate structure INT3_GS1: Third internal gate structure ISP_GS3: Internal spacer NS1: First pattern NS1_BS, NS2_BS, NS3_BS: Lower surface NS1_SW1: First sidewall NS1_SW2: Second sidewall NS2: Second pattern NS3: Third pattern P: Region Q, R: Portion SC_L: Sacrificial pattern SP_R: Semiconductor residual pattern T11: First thickness T12: Second thickness T21: Third thickness T22: Fourth thickness U_AP: Upper pattern structure W11: First width W21: Second width W12: Third width W22: Fourth width W31, W32, W51, W52: Width W41, W42: Maximum width

Claims

1. A semiconductor device, comprising: An active pattern includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; A gate structure, on the lower pattern and including a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode extending upward in a third direction perpendicular to the first direction; a source / drain pattern, on the lower pattern and in contact with the wafer pattern and the gate insulating layer; and a first etch-block pattern, between the gate spacer and the source / drain pattern, wherein the gate spacer includes an inner sidewall facing the gate electrode and extending upward in the third direction, and a connecting sidewall extending from the inner sidewall of the gate spacer in the first direction; the source / drain pattern includes a semiconductor liner layer and a semiconductor fill layer on the semiconductor liner layer; the semiconductor liner layer is in contact with the wafer pattern and includes a facet surface extending from the connecting sidewall of the gate spacer; and the first etch-block pattern is in contact with the facet surface of the semiconductor liner layer and the connecting sidewall of the gate spacer.

2. The semiconductor device of claim 1, wherein the width of the first etch barrier pattern in the third direction increases with the distance away from the gate electrode in the first direction.

3. The semiconductor device as claimed in claim 1, wherein the first etch stop pattern comprises an insulating material.

4. The semiconductor device of claim 1, wherein the first etched barrier pattern includes a barrier liner and a barrier fill layer, the barrier liner extending along the facet surface of the semiconductor liner layer and the connection sidewall of the gate spacer, and the barrier fill layer on the barrier liner.

5. The semiconductor device of claim 1, wherein the gate structure includes an internal gate structure between the lower pattern and the wafer pattern and between the wafer patterns adjacent to each other, the internal gate structure including the gate electrode and the gate insulating layer, and the first etch-blocking pattern is between the internal gate structure and the semiconductor fill layer.

6. The semiconductor device of claim 1, wherein the first etch stop pattern includes a first surface facing the facet surface of the semiconductor liner, a second surface facing the connection sidewall of the gate spacer, and a connection surface extending from the first surface to the second surface, and the entire connection surface of the first etch stop pattern is in contact with the semiconductor filler layer.

7. The semiconductor device of claim 1, wherein the source / drain pattern includes an air gap between the first etch barrier pattern and the semiconductor fill layer.

8. The semiconductor device as claimed in claim 1, further comprising: A second etch-block pattern is provided in the source / drain pattern, wherein the second etch-block pattern is between the semiconductor liner layer and the semiconductor fill layer, and the width of the second etch-block pattern in the third direction increases with the distance away from the gate electrode in the first direction.

9. The semiconductor device of claim 8, wherein the source / drain pattern includes an air gap between the second etch barrier pattern and the semiconductor fill layer.

10. The semiconductor device of claim 8, wherein the second etch stop pattern includes a first surface and a second surface in contact with the semiconductor liner layer and a connecting surface extending from the first surface to the second surface, and the entire connecting surface of the second etch stop pattern is in contact with the semiconductor fill layer.

11. The semiconductor device of claim 1, wherein each of the semiconductor liner layer and the semiconductor fill layer comprises silicon-germanium.

12. A semiconductor device, comprising: An active pattern includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; A gate structure, on the lower pattern and including a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode extending in a third direction perpendicular to the first direction; a source / drain pattern, on the lower pattern and in contact with the wafer pattern and the gate insulating layer, wherein the source / drain pattern includes a semiconductor liner and a semiconductor filler layer on and in contact with the semiconductor liner, the semiconductor liner in contact with the wafer pattern and including a facet surface extending from the gate spacer, and in a plan view at the level of one of the wafer patterns, a first width including the maximum width of the semiconductor liner in the third direction is greater than a second width of the interface between the semiconductor liner and the semiconductor filler layer in the third direction; and an etch stop pattern between the gate spacer and the source / drain pattern.

13. The semiconductor device of claim 12, wherein in the plan view, the semiconductor filler layer is in contact with a portion of the facet surface of the semiconductor liner layer.

14. The semiconductor device of claim 12, wherein the gate spacer includes an inner sidewall facing the gate electrode and extending upward in the third direction and a connection sidewall extending from the inner sidewall of the gate spacer in the first direction, and the etch-blocking pattern contacts the facet surface of the semiconductor liner and the connection sidewall of the gate spacer.

15. The semiconductor device of claim 14, wherein, in the plan view, the etch barrier pattern further includes a third surface extending between the facet surface of the semiconductor liner and the connection sidewall of the gate spacer, and the third surface is concave.

16. A semiconductor device, comprising: The first active pattern includes a first lower pattern extending in a first direction and a plurality of first pattern pieces spaced apart from the first lower pattern in a second direction. A first gate structure is on the first lower pattern and includes a first gate insulating layer, a first gate electrode, and a first gate spacer, wherein the first gate electrode extends in a third direction perpendicular to the first direction; a second active pattern includes a second lower pattern extending in the first direction and a plurality of second patterns spaced apart from the second lower pattern in the second direction, wherein the width of the upper surface of the second lower pattern in the third direction is smaller than the width of the upper surface of the first lower pattern in the third direction. A second gate structure, on the second lower pattern, includes a second gate insulating layer, a second gate electrode, and a second gate spacer, the second gate electrode extending upward in the third direction; a first source / drain pattern, on the first lower pattern and in contact with the first sheet pattern and the first gate insulating layer; a second source / drain pattern, on the second lower pattern and in contact with the second sheet pattern and the second gate insulating layer; and a first etch-stop pattern, between the first gate spacer and the first source / drain pattern, wherein the first gate spacer includes an inner sidewall facing the first gate electrode and extending upward in the third direction, and a connecting sidewall extending from the inner sidewall of the first gate spacer in the first direction; the first source / drain pattern includes a semiconductor liner layer and a semiconductor fill layer on the semiconductor liner layer; the semiconductor liner layer is in contact with the first sheet pattern and includes a facet surface extending from the connecting sidewall of the first gate spacer; and the first etch-stop pattern is in contact with the facet surface of the semiconductor liner layer and the connecting sidewall of the first gate spacer.

17. The semiconductor device of claim 16, wherein there is no etched barrier pattern between the second gate spacer and the second source / drain pattern.

18. The semiconductor device as claimed in claim 16, further comprising: A second etch barrier pattern is located between the second gate spacer and the second source / drain pattern, wherein the size of the first etch barrier pattern in the first direction is greater than the size of the second etch barrier pattern in the first direction.

19. The semiconductor device of claim 16, wherein the first etch stop pattern includes a stop liner and a stop fill layer, the stop liner extending along the facet surface of the semiconductor liner layer and the connection sidewall of the first gate spacer, and the stop fill layer on the stop liner.

20. The semiconductor device as claimed in claim 16, further comprising: A second etch-blocking pattern is formed within the first source / drain pattern, wherein the second etch-blocking pattern is formed between the semiconductor liner layer and the semiconductor fill layer, the width of the second etch-blocking pattern in the third direction increases with distance from the first gate electrode, and there is no etch-blocking pattern in the second source / drain pattern.

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