Semiconductor device and method of operating electro-static discharge protection device

Abstract

This disclosure provides a semiconductor device including an n-type buried layer, a p-type well region located above the n-type buried layer, an n-type channel MOSFET including an n-type drain region, and a vertical NPN BJT. The vertical NPN BJT has a collector as an n-type drain region and a base as a p-type well region. The p-type well region is floating.

Description

Semiconductor Device and Method of Operating Electrostatic Discharge Protection Device The present disclosure relates to a semiconductor device, and more particularly to an electrostatic discharge protection device having a bipolar junction transistor. Semiconductor devices are becoming faster and smaller. In one aspect, semiconductor manufacturers improve the performance of semiconductor devices and reduce the size of semiconductor devices by shrinking the process geometry. Generally, semiconductor devices with smaller process geometry are more prone to degradation and damage due to electrostatic discharge (ESD). To protect the device from ESD degradation and damage, ESD protection devices are added to the semiconductor device. Generally, ESD implants are included in metal-oxide semiconductor field-effect transistor (MOSFET) semiconductor devices (e.g., resistive protective oxide (RPO) MOSFET devices) for ESD protection. However, one or more additional photomasks used to fabricate the ESD implants increase the cost of the semiconductor device. Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an n-type buried layer, a p-type well region located above the n-type buried layer, an n-type channel metal-oxide semiconductor field-effect transistor including an n-type drain region, and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has an n-type drain region as its collector and a p-type well region as its base. The p-type well region is floating. Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an n-type buried layer electrically connected to a reference voltage Vss or a power supply voltage Vdd; a p-type well region located above the n-type buried layer; an n-type channel metal-oxide semiconductor field-effect transistor including an n-type drain region electrically connected to an input / output pad; and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has an n-type drain region as its collector, an n-type buried layer as its emitter, and a p-type well region as its base. The p-type well region is floating. The embodiments disclosed herein provide an operation method for an electrostatic discharge protection device. The operation method of the electrostatic discharge protection device includes: receiving an electrostatic discharge at an n-type drain region of an n-channel metal oxide semiconductor field effect transistor; in response to the electrostatic discharge, biasing to turn on a vertical NPN bipolar junction transistor, where the collector of the vertical NPN bipolar junction transistor is the n-type drain region, and the base thereof is a p-type well region located above the n-type buried layer, and the p-type well region is floating; and releasing the electrostatic discharge to the n-type buried layer via the emitter of the vertical NPN bipolar junction transistor. The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the components and arrangements of the present disclosure are described below for simplicity. Of course, these are only examples and are not intended to limit the present disclosure. For example, if it is described that a first feature is formed on or above a second feature, it may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature, such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The purpose of this repetition is to simplify and make it easy to understand, and it does not itself specify the relationship between the various embodiments and / or configurations discussed. Furthermore, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower than", "above", "on top", and similar terms, to facilitate the description of the relationship between one element or feature in a diagram and other elements or features. In addition to the orientation depicted in the diagram, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein can be interpreted accordingly. The embodiments disclosed herein provide a semiconductor device including a parasitic vertical NPN bipolar junction transistor (BJT) for discharging ESD current. The advantages of the parasitic vertical NPN BJT for ESD protection include a lower ESD triggering voltage Vt1. In some embodiments, the semiconductor device is an RPO MOS device. The above semiconductor device includes an n-type buried layer, a p-type well region above the n-type buried layer, and a snapback device for ESD protection. The snapback device includes an n-type channel MOSFET, which includes an n-type drain region and an n-type source region. The parasitic vertical NPN BJT includes a collector located in the n-type drain region, an emitter located in the n-type buried layer, and a base located in the p-type well region, where the p-type well region is floating and not connected to a reference voltage or a power voltage. Through the floating p-type well region, the parasitic vertical NPN BJT has a lower ESD trigger voltage Vt1. In some embodiments, the n-type drain region is a heavily doped n-type (n+) drain region, and in some embodiments, the n-type source region is an n+ source region. FIG. 1 is a schematic cross-sectional view of a semiconductor device 20 including a parasitic vertical NPN BJT 22 for releasing ESD current, according to some embodiments of the present disclosure. The semiconductor device 20 is a snapback device for releasing ESD current. The semiconductor device 20 includes a MOSFET 24 above a p-type well region 26, where the p-type well region 26 is above an n-type buried layer 28. In some embodiments, the MOSFET 24 is an RPO MOSFET. The MOSFET 24 includes an n-type drain region 30, an n-type source region 32, and a gate 34. The p-type well region 26 includes a p+ contact 36, and the MOSFET 24 further includes isolation regions 38 located on each side of the MOSFET 24 and adjacent to the p+ contact 36. In some embodiments, the n-type drain region 30 is an n+ drain region, and in some embodiments, the n-type source region 32 is an n+ source region. The n-type drain region 30 is the collector of the parasitic vertical NPN BJT 22, and the n-type buried layer 28 is the emitter of the parasitic vertical NPN BJT 22. The p-type well region 26 is the base of the parasitic vertical NPN BJT 22. In some embodiments, the n-type drain region 30 is electrically connected to an input / output (I / O) pad. Also, the n-type source region 32 is electrically connected to the gate 34. In operation, the n-type buried layer 28 is electrically connected to a reference voltage (e.g., ground), while the p-type well region 26 and the p+ contact 36 are floating and not connected to the reference voltage or the power supply voltage. When an ESD event strikes the n-type drain region 30 that can be electrically connected to the I / O pad, the parasitic vertical NPN BJT 22 is biased on, e.g., due to avalanche breakdown through the collector to the base and the emitter. With the base floating, the ESD trigger voltage Vt1 for biasing on the parasitic vertical NPN BJT 22 is lower, enabling the parasitic vertical NPN BJT 22 to be biased on faster. The lower ESD trigger voltage Vt1 biases on the parasitic vertical NPN BJT 22, which provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28. Compared with the ESD trigger voltage Vt1 for biasing on the parasitic lateral NPN BJT 40 in different configurations of the semiconductor device 20, the parasitic vertical NPN BJT 22 is biased on with a lower ESD trigger voltage Vt1. In this different configuration, the parasitic lateral NPN BJT 40 includes the n-type drain region 30 as the collector, the n-type source region 32 as the emitter, and the p-type well region 26 as the base. However, in order to use the parasitic lateral NPN BJT 40 to release the ESD current, each of the p+ contact 36 and the n-type source region 32 is electrically connected to a reference voltage (e.g., ground). This provides a base resistance 42 between the base of the parasitic lateral NPN BJT 40 and the p+ contact 36. When an ESD event strikes the n-type drain region 30, the parasitic lateral NPN BJT 40 is biased on, e.g., due to avalanche breakdown through the collector and the base to the p+ contact 36. The base current through the base resistance 42 builds a base voltage at the base, and the base voltage biases on the parasitic lateral NPN BJT 40 to release the ESD current through the parasitic lateral NPN BJT 40 to the n-type source region 32. The ESD trigger voltage Vt1 for biasing on the parasitic lateral NPN BJT 40 is higher than the ESD trigger voltage Vt1 for biasing on the parasitic vertical NPN BJT 22. FIG. 2 is a schematic diagram showing the semiconductor device 20 of FIG. 1 as a snapback device according to some embodiments of the present disclosure. The semiconductor device 20 is electrically connected to the I / O pad 50 and the reference voltage Vss. In some embodiments, the reference voltage Vss is ground. The n-type drain region 30 is electrically connected to the I / O pad 50 and serves as the collector of the parasitic vertical NPN BJT 22. The n-type buried layer (NBL) 28 serves as the emitter of the parasitic vertical NPN BJT 22, and the p-type well region 26 serves as the base of the parasitic vertical NPN BJT 22. In operation, the n-type buried layer 28 is electrically connected to a reference voltage Vss (e.g., ground), and the p-type well region 26 is floating. When an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, e.g., due to the avalanche breakdown through the collector-to-base and emitter. With the base floating, the ESD trigger voltage Vt1 for biasing on the parasitic vertical NPN BJT 22 is lower, enabling the parasitic vertical NPN BJT 22 to be biased faster. This provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28 and the reference voltage Vss. FIG. 3 is a diagram according to some embodiments of the present disclosure, schematically showing the I-V curve 54 of the parasitic vertical NPN BJT 22. The I-V curve includes the voltage along the x-axis 56 and the current along the y-axis 58. When the voltage across the parasitic vertical NPN BJT 22 reaches the ESD trigger voltage Vt1, the parasitic vertical NPN BJT 22 is biased on. The biased-on parasitic vertical NPN BJT 22 provides an ESD current path through the parasitic vertical NPN BJT 22 to the reference voltage Vss, and the voltage across the parasitic vertical NPN BJT 22, from the n-type drain region 30 to the n-type source region 32, decreases to the hold voltage Vh. Since the ESD trigger voltage Vt1 is less than the destructive voltage (e.g., the victim's destructive voltage Vt2), the parasitic vertical NPN BJT 22 prevents the ESD event from damaging the semiconductor device 20. FIG. 4 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 60 including the semiconductor device 20 of FIG. 1. The semiconductor device 60 includes the semiconductor device 20, an internal circuit 62, and an ESD clamp 64. The semiconductor device 20 is the snapback device of FIGS. 1 and 2. In some embodiments, the ESD clamp 64 is an ESD power supply clamp. In other embodiments, the snapback device can be a different semiconductor device. Each of the internal circuit 62 and the ESD clamp 64 is electrically connected to the power supply voltage Vdd and the reference voltage Vss. Each of the internal circuit 62 and the semiconductor device 20 is electrically connected to the I / O pad 50, and the semiconductor device 20 is electrically connected to the reference voltage Vss. In operation, before an ESD event has a chance to degrade or damage the internal circuit 62, the ESD event strikes the I / O pad 50 and the semiconductor device 20 releases the ESD current to the reference voltage Vss via the semiconductor device 20. In some embodiments, this is referred to as the PS mode. FIG. 5 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 20 having a MOSFET 24 and a parasitic vertical NPN BJT 22. The MOSFET 24 includes an n-type drain region 30 electrically connected to the I / O pad 50, wherein the n-type drain region 30 is the collector of the parasitic vertical NPN BJT 22. The MOSFET 24 further includes a gate 34 electrically connected to an n-source region 32, wherein the n-source region 32 is electrically connected to a p-type well region 26, all of which are floating. The n-type buried layer 28 is the emitter of the parasitic vertical NPN BJT 22, wherein the n-type buried layer 28 is electrically connected to the reference voltage Vss, and the p-type well region 26 is the base of the parasitic vertical NPN BJT 22, wherein the p-type well region 26 is floating. In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example, due to avalanche breakdown through the collector-to-base and emitter. In the case of a floating base, the ESD trigger voltage Vt1 for biasing on the parasitic vertical NPN BJT 22 is lower, such that the parasitic vertical NPN BJT 22 is biased more quickly. This provides an early ESD discharge path through the parasitic vertical NPN BJT 22 to the n-type buried layer 28 and the reference voltage Vss. FIG. 6 is a diagram according to some embodiments of the present disclosure, schematically showing a semiconductor device 20 having a MOSFET 24, a parasitic vertical NPN BJT 22, and a parasitic lateral NPN BJT 40. The MOSFET 24 includes an n-type drain region 30 electrically connected to the I / O pad 50, wherein the n-type drain region 30 is the collector of the parasitic vertical NPN BJT 22 and the collector of the parasitic lateral NPN BJT 40. The MOSFET 24 further includes a gate 34 electrically connected to an n-source region 32, wherein the n-source region 32 is electrically connected to the reference voltage Vss. The n-source region 32 is the emitter of the parasitic lateral NPN BJT 40. The n-type buried layer 28 is the emitter of the parasitic vertical NPN BJT 22, wherein the n-type buried layer 28 is electrically connected to the reference voltage Vss. The p-type well region 26 is the base of the parasitic vertical NPN BJT 22 and the base of the parasitic lateral NPN BJT 40. The p-type well region 26 is floating. In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, e.g., due to avalanche breakdown through the collector to base and emitter, and the parasitic lateral NPN BJT 40 is biased on, e.g., due to avalanche breakdown through the collector to base and emitter. When the parasitic vertical NPN BJT 22 and the parasitic lateral NPN BJT 40 are biased on, the ESD trigger voltage Vt1 is further reduced, enabling the ESD current to be released more quickly. This provides an earlier ESD discharge path through the parasitic vertical NPN BJT 22 and the parasitic lateral NPN BJT 40 to the reference voltage Vss. FIG. 7 is a diagram showing, schematically, a semiconductor device 60 in another ESD scheme, in accordance with some embodiments of the present disclosure. In this scheme, an ESD event strikes the I / O pad 50 and flows through the snapback device to the reference voltage Vss. Then, the ESD current flows through the ESD clamp 64 to the power supply voltage Vdd. The ESD current has a path to the power supply voltage Vdd via the metal bus of the reference voltage Vss and the internal diode (body diode) of the ESD clamp 64. Thus, the ESD current flows from the I / O pad 50 to the power supply voltage Vdd. In some embodiments, this is referred to as the PD mode. To accommodate this scheme, the semiconductor device 20 is configured to release the ESD current to the reference voltage Vss and the power supply voltage Vdd. The semiconductor device 60 includes the semiconductor device 20, the internal circuit 62, and the ESD clamp 64. Each of the semiconductor device 20, the internal circuit 62, and the ESD clamp 64 is electrically connected to the power supply voltage Vdd and the reference voltage Vss. Each of the internal circuit 62 and the semiconductor device 20 is electrically connected to the I / O pad 50. In operation, before an ESD event has a chance to degrade or damage the internal circuit 62, the ESD event strikes the I / O pad 50, and the semiconductor device 20 releases the ESD current to the reference voltage Vss and the power supply voltage Vdd via the semiconductor device 20. FIG. 8 is a diagram showing, schematically, the semiconductor device 20 (shown in FIG. 7) configured to release the ESD current to the reference voltage Vss and to the power supply voltage Vdd, in accordance with some embodiments of the present disclosure. The semiconductor device 20 includes the MOSFET 24, the parasitic vertical NPN BJT 22, and the parasitic lateral NPN BJT 40. The MOSFET 24 includes an n-type drain region 30 electrically connected to the I / O pad 50, where the n-type drain region 30 is the collector of the parasitic vertical NPN BJT 22 and the collector of the parasitic lateral NPN BJT 40. The MOSFET 24 further includes a gate 34 electrically connected to the n-type source region 32, where the n-type source region 32 is electrically connected to the reference voltage Vss. The n-type source region 32 is the emitter of the parasitic lateral NPN BJT 40. The n-type buried layer 28 is the emitter of the parasitic vertical NPN BJT 22, where the n-type buried layer 28 is electrically connected to the power supply voltage Vdd. The p-type well region 26 is the base of the parasitic vertical NPN BJT 22 and the base of the parasitic lateral NPN BJT 40. The p-type well region 26 is floating. In operation, when an ESD event strikes the I / O pad 50, the parasitic vertical NPN BJT 22 is biased on, for example due to avalanche breakdown across the collector to base and emitter, and the parasitic lateral NPN BJT 40 is biased on, for example due to avalanche breakdown across the collector to base and emitter. The parasitic vertical NPN BJT 22 is biased on to release the ESD current to the power supply voltage Vdd, and the parasitic lateral NPN BJT 40 is biased on to release the ESD current to the reference voltage Vss. When the parasitic vertical NPN BJT 22 and the parasitic lateral NPN BJT 40 are biased on, the ESD trigger voltage Vt1 is reduced, such that the ESD current is released more quickly. This provides an earlier ESD discharge path through the parasitic vertical NPN BJT 22 to the power supply voltage Vdd and through the parasitic lateral NPN BJT 40 to the reference voltage Vss. FIG. 9 is a diagram showing a method of operating an ESD protection device, schematically, according to some embodiments of the present disclosure. In some embodiments, the ESD protection device is similar to the semiconductor device 20 of FIG. 1. In operation 80, the method includes receiving an ESD strike at the n-type drain region of an n-type channel MOSFET. In some embodiments, this n-type drain region is similar to the n-type drain region 30 (shown in FIG. 1). In some embodiments, this n-type channel MOSFET is similar to the n-type channel MOSFET 24 (shown in FIG. 1). In operation 82, the method includes turning on a parasitic vertical NPN BJT in response to an ESD shock. The parasitic vertical NPN BJT has a collector that is an n-type drain region and a base that is a p-type well region, where the p-type well region is located above an n-type buried layer in the semiconductor device. The p-type well region is floating to reduce the ESD trigger voltage Vt1 of the vertical NPN BJT for ESD protection. In some embodiments, this p-type well region is similar to the p-type well region 26 (shown in FIG. 1). In some embodiments, this n-type buried layer is similar to the n-type buried layer 28 (shown in FIG. 1). In some embodiments, this parasitic vertical NPN BJT is similar to the parasitic vertical NPN BJT 22 (shown in FIG. 1). In operation 84, the method includes releasing the ESD to the n-type buried layer via the emitter of the parasitic vertical NPN BJT. In some embodiments, releasing the ESD via the emitter of the parasitic vertical NPN BJT includes releasing the ESD to the n-type buried layer at a reference voltage Vss. In some embodiments, releasing the ESD via the emitter of the parasitic vertical NPN BJT includes releasing the ESD to the n-type buried layer at a power supply voltage Vdd. In some embodiments, the method includes releasing the ESD via a parasitic lateral NPN BJT that has a collector that is an n-type drain region, an emitter that is a source region of an n-channel MOSFET, and a base that is a p-type well region. FIG. 10 is a block diagram according to some embodiments of the present disclosure, schematically showing an example of a computer system 100 configured to provide the semiconductor device and method of the present disclosure. Some or all of the design, layout, and manufacturing of the semiconductor device (also referred to as a semiconductor circuit) can be performed by or using the computer system 100. In some embodiments, the computer system 100 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an integrated circuit (IC). In some embodiments, computer system 100 is a general computing device including a processor 102 and a non-transitory computer-readable storage medium 104. The computer-readable storage medium 104 can be encoded to store, for example, computer code such as executable instructions 106. Execution of the instructions 106 by the processor 102 provides (at least in part) design tools for performing some or all of the functions of the computer system 100, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final routing for manufacturing. Further, a manufacturing machine 108 is included to further perform layout and physically execute the design and manufacture of semiconductor devices. In some embodiments, execution of the instructions 106 by the processor 102 provides (at least in part) design tools for performing some or all of the functions of the computer system 100. In some embodiments, computer system 100 includes a commercial router. In some embodiments, computer system 100 includes an automatic place and route (APR) system. The processor 102 is electrically coupled to the computer-readable storage medium 104 via a bus 110 and is electrically coupled to an I / O interface 112 via the bus 110. A network interface 114 is also electrically connected to the processor 102 via the bus 110. The network interface 114 is connected to a network 116 such that the processor 102 and the computer-readable storage medium 104 can use the network 116 to connect to external components. The processor 102 is configured to execute computer code or instructions 106 encoded in the computer-readable storage medium 104 to cause the computer system 100 to perform some or all of the functions of the computer system 100, such as providing the semiconductor devices and methods of the present disclosure or other functions of the computer system 100. In some embodiments, the processor 102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit. In some embodiments, the computer-readable storage medium 104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system or device or apparatus. For example, the computer-readable storage medium 104 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In some embodiments using an optical disk, the computer-readable storage medium 104 may include a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD). In some embodiments, the computer-readable storage medium 104 stores computer code or instructions 106, and the instructions 106 are configured to cause the computer system 100 to perform some or all of the functions of the computer system 100. In some embodiments, the computer-readable storage medium 104 also stores information that facilitates the performance of some or all of the functions of the computer system 100. In some embodiments, the computer-readable storage medium 104 stores a database 118, and the database 118 includes one or more of a component library, a digital circuit cell library, and the database. The computer system 100 includes an I / O interface 112. The I / O interface 112 is coupled to an external circuit. In some embodiments, the I / O interface 112 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor direction keys for passing information and commands to the processor 102. The network interface 114 is coupled to the processor 102 and allows the computer system 100 to communicate with the network 116, to which one or more other computer systems are connected. The network interface 114 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX (Worldwide Interoperability for Microwave Access), GPRS (General Packet Radio Service), or WCDMA (Wideband Code Division Multiple Access); or includes a wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, some or all of the functions of the computer system 100 may be performed in two or more systems similar to the computer system 100. The computer system 100 is configured to receive information via the I / O interface 112. The information received via the I / O interface 112 includes one or more of instructions, data, design criteria, libraries of components and units, and / or other parameters for processing by the processor 102. This information is transmitted to the processor 102 via the bus 110. Also, the computer system 100 is configured to receive information related to the user interface (UI) via the I / O interface 112. This UI information may be stored in the computer-readable storage medium 104 as the UI 120. In some embodiments, some or all of the functions of the computer system 100 are implemented as a stand-alone software application executed by a processor. In some embodiments, some or all of the functions of the computer system 100 are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the functions of the computer system 100 are implemented as a plug-in of a software application. In some embodiments, at least one function of the computer system 100 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of the computer system 100 are implemented as software applications used by the computer system 100. In some embodiments, tools used to generate layout patterns, such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc, or other suitable layout generation tools. In some embodiments, routing, layout, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units such as one or more optical discs such as digital video discs or digital versatile discs (DVDs), magnetic disks such as hard disks, semiconductor memories such as ROM and RAM, and memory cards, etc. As described above, an embodiment of the computer system 100 includes a manufacturing machine 108 for performing the manufacturing process of the computer system 100. For example, based on the final layout, a lithography mask can be generated, which is used to manufacture semiconductor devices through the manufacturing machine 108. Further aspects of device manufacturing are disclosed in connection with FIG. 11, which is a block diagram showing a semiconductor device manufacturing system 122 and a related semiconductor device manufacturing process according to some embodiments. In some embodiments, based on a layout pattern, the manufacturing system 122 is used to manufacture at least one component in one or more semiconductor masks and / or thin layers of a semiconductor device. In FIG. 11, the semiconductor device manufacturing system 122 (hereinafter referred to as "system 122") includes a plurality of entities, such as a design studio 124, a mask studio 126, and a semiconductor device manufacturer / fabricator ("fab") 128, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of semiconductor devices (e.g., the semiconductor devices described herein). The entities in the system 122 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to or receives services from one or more other entities. In some embodiments, two or more of the design studio 124, the mask studio 126, and the semiconductor device fab 128 are owned by a single larger company. In some embodiments, two or more of the design studio 124, the mask studio 126, and the semiconductor device fab 128 coexist in a common facility and use common resources. A design studio (or design team) 124 generates a semiconductor device design layout pattern 130. The semiconductor device design layout pattern 130 includes various geometric patterns or a semiconductor device layout pattern designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers of various components that will form the semiconductor structure to be manufactured. Various thin layers are combined to form various semiconductor device features. For example, a part of the semiconductor device design layout pattern 130 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or areas, gate electrodes, source and drain, metal lines, area vias, and openings for bonding pads. The design studio 124 executes a design process to form the semiconductor device design layout pattern 130. The semiconductor device design layout pattern 130 is presented in one or more data files with geometric pattern information. For example, the semiconductor device design layout pattern 130 can be represented in the Graphic Database System II (GDSII) file format or the DFII file format. In some embodiments, the design process includes analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, supply voltage track design, and reference voltage track design, placement and routing routines, and physical layout design. The mask studio 126 includes data preparation 132 and mask manufacturing 134. The mask studio 126 uses the semiconductor device design layout pattern 130 to manufacture one or more masks 136 for manufacturing various thin layers of a semiconductor device or semiconductor structure. The mask studio 126 executes data preparation 132 of the mask, where the semiconductor device design layout pattern 130 is converted into a representative data file (RDF). The mask data preparation 132 provides the RDF to the mask manufacturing 134. The mask manufacturing 134 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (reticle) 136 or a semiconductor wafer 138. The IC design layout 130 is manipulated by the data preparation 132 of the mask to conform to the specific characteristics of the mask writer and / or the standards of the semiconductor device manufacturer 128. In FIG. 11, the data preparation 132 of the mask and the mask manufacturing 134 are shown as separate elements. In some embodiments, the data preparation 132 of the mask and the mask manufacturing 134 can be collectively referred to as mask data preparation. In some embodiments, the mask data preparation 132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. The OPC adjusts the semiconductor device design layout pattern 130. In some embodiments, the mask data preparation 132 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, and the inverse lithography technology treats OPC as an inverse imaging problem. In some embodiments, the mask data preparation 132 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the semiconductor device design layout pattern 130 that has undergone the OPC process, where the mask creation rules include specific geometric and / or connectivity restrictions to ensure sufficient margins to account for variations in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the semiconductor device design layout pattern 130 to compensate for the limitations during mask manufacturing 134, which can undo some of the modifications performed by the OPC to meet the mask creation rules. In some embodiments, the mask data preparation 132 includes lithography process checking (LPC), which simulates the process to be performed by the semiconductor device manufacturer 128. The LPC simulates this process based on the semiconductor device design layout pattern 130 to create a simulated manufactured device. The process parameters in the LPC simulation can include parameters related to various processes in the semiconductor device manufacturing cycle, parameters related to the machines used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the simulated device is not close enough in shape to meet the design criteria, OPC and / or MRC can be repeated to further refine the semiconductor device design layout pattern 130. For clarity of explanation, the foregoing description of the mask data preparation 132 has been simplified. In some embodiments, the data preparation 132 includes additional features such as logic operation (LOP) to modify the semiconductor device design layout pattern 130 according to manufacturing criteria. In addition, the processes applied to the semiconductor device design layout pattern 130 during the data preparation 132 can be performed in various different orders. After the mask data preparation 132 and during the mask manufacturing 134, the mask 136 or a group of masks 136 is manufactured based on the modified semiconductor device design layout pattern 130. In some embodiments, the mask manufacturing 134 includes performing one or more lithographic exposures based on the semiconductor device design layout pattern 130. In some embodiments, an electron beam (e-beam) or a multiple electron beam mechanism is used to form a pattern on the mask (reticle or photomask) 136 based on the modified semiconductor device design layout pattern 130. Various techniques can be used to form the mask 136. In some embodiments, the binary technology is used to form the mask 136. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 136 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In other examples, the phase shift technology is used to form the mask 136. In the phase shift mask (PSM) version of the mask 136, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve the resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask manufacturing 134 is used in various processes. For example, this (or these) mask is used in the ion implantation process to form various doped regions in the semiconductor wafer 138, used in the etching process to form various etched regions in the semiconductor wafer 138, and / or used in other suitable processes. The semiconductor device manufacturing plant 128 includes wafer manufacturing 140. The semiconductor device manufacturing plant 128 is a semiconductor device manufacturing enterprise, including one or more manufacturing facilities for manufacturing various different semiconductor device products. In some embodiments, the semiconductor device manufacturing plant 128 is a semiconductor foundry. For example, there may be a manufacturing facility for the front-end-of-line (FEOL) manufacturing of multiple semiconductor device products, and a second manufacturing facility can provide the back-end-of-line (BEOL) manufacturing for the interconnection and packaging of semiconductor device products, and a third manufacturing facility that provides other services for the foundry enterprise. Semiconductor device manufacturer 128 manufactures the semiconductor structure or semiconductor device 142 disclosed herein using the photomask 136 manufactured by the photomask studio 126. Therefore, semiconductor device manufacturer 128 indirectly uses at least the semiconductor device design layout pattern 130 to manufacture the semiconductor structure or semiconductor device 142 disclosed herein. Further, the semiconductor wafer 138 includes a silicon substrate or other suitable substrate having a material layer formed thereon, and the conductor wafer 138 further includes one or more of various doped regions, dielectric features, multi-level interconnections, etc. (formed in subsequent manufacturing operations). In some embodiments, the semiconductor wafer 138 is manufactured by semiconductor device manufacturer 128 using the photomask 136 to form the semiconductor structure or semiconductor device 142 disclosed herein. In some embodiments, the manufacture of the semiconductor device includes performing one or more lithographic exposures based at least indirectly on the semiconductor device design layout pattern 130. The embodiments disclosed in the present application provide a semiconductor device including a parasitic vertical NPN BJT for releasing ESD current. The parasitic vertical NPN BJT is configured to release the ESD current to the reference voltage Vss or the power supply voltage Vdd. In some embodiments, the semiconductor device includes a parasitic lateral NPN BJT for releasing ESD current. In some embodiments, both the parasitic vertical NPN BJT and the parasitic lateral NPN BJT release the ESD current simultaneously. In some embodiments, the semiconductor device is an RPO MOS device. The semiconductor device includes an n-type buried layer, a p-type well region above the n-type buried layer, and a snapback device for ESD protection. The snapback device includes an n-channel MOSFET, and the n-channel MOSFET includes an n-type drain region and an n-type source region. The parasitic vertical NPN BJT includes a collector located in the n-type drain region, an emitter located in the n-type buried layer, and a base located in the p-type well region, where the p-type well region is floating and not connected to the reference voltage or the power supply voltage. Through the floating p-type well region, the parasitic vertical NPN BJT has a lower ESD trigger voltage Vt1. In some embodiments, the semiconductor device includes a parasitic lateral NPN BJT, which includes a collector located in the n-type drain region, an emitter located in the n-type source region, and a base located in the p-type well region, where the p-type well region is floating and not connected to the reference voltage or the power supply voltage. According to some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer, a p-type well region located above the n-type buried layer, an n-channel metal oxide semiconductor field effect transistor including an n-type drain region, and a vertical NPN bipolar junction transistor. The vertical NPN bipolar junction transistor has a collector as the n-type drain region and a base as the p-type well region. The p-type well region is floating. In some embodiments, the emitter of the vertical NPN bipolar junction transistor is an n-type buried layer. In some embodiments, the n-type buried layer is electrically connected to the reference voltage Vss. In some embodiments, the n-type drain region is electrically connected to the input / output pad. In some embodiments, the n-type drain region includes an n+ region. In some embodiments, the n-type channel metal oxide semiconductor field effect transistor includes a floating source. In some embodiments, the emitter of the vertical NPN bipolar junction transistor is an n-type buried layer electrically connected to the reference voltage Vss, and the source region included in the n-type channel metal oxide semiconductor field effect transistor is electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the collector of the lateral NPN bipolar junction transistor being an n-type drain region, the emitter being a source region, and the base being a floating p-type well region. In some embodiments, the emitter of the vertical NPN bipolar junction transistor is an n-type buried layer electrically connected to the power supply voltage Vdd. In some embodiments, the source region included in the n-type channel metal oxide semiconductor field effect transistor is electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the collector of the lateral NPN bipolar junction transistor being an n-type drain region, the emitter being a source region, and the base being a floating p-type well region. According to a further embodiment, the present disclosure provides a semiconductor device. The semiconductor device includes an n-type buried layer electrically connected to the reference voltage Vss or the power supply voltage Vdd; a p-type well region located above the n-type buried layer; an n-type channel metal oxide semiconductor field effect transistor including an n-type drain region electrically connected to the input / output pad; and a vertical NPN bipolar junction transistor. The collector of the vertical NPN bipolar junction transistor is an n-type drain region, the emitter is an n-type buried layer, and the base is a p-type well region. The p-type well region is floating. In some embodiments, the n-type channel metal oxide semiconductor field effect transistor includes a floating source. In some embodiments, the n-type buried layer is electrically connected to the reference voltage Vss. In some embodiments, the source region included in the n-type channel metal oxide semiconductor field effect transistor is electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, the collector of the lateral NPN bipolar junction transistor being an n-type drain region, the emitter being a source region, and the base being a floating p-type well region. In some embodiments, the n-type buried layer is electrically connected to the power supply voltage Vdd. In some embodiments, the source region included in the n-type channel metal oxide semiconductor field effect transistor is electrically connected to the reference voltage Vss, and the semiconductor device further includes a lateral NPN bipolar junction transistor, where the collector of the lateral NPN bipolar junction transistor is the n-type drain region, the emitter is the source region, and the base is a floating p-type well region. According to a further disclosed aspect, the present disclosure provides an operation method for an electrostatic discharge protection device. The operation method of the electrostatic discharge protection device includes: receiving an electrostatic discharge at the n-type drain region of the n-type channel metal oxide semiconductor field effect transistor; in response to the electrostatic discharge, biasing and turning on a vertical NPN bipolar junction transistor, where the collector of the vertical NPN bipolar junction transistor is the n-type drain region, and the base is a p-type well region located above the n-type buried layer, and the p-type well region is floating; and releasing the electrostatic discharge to the n-type buried layer via the emitter of the vertical NPN bipolar junction transistor. In some embodiments, releasing the electrostatic discharge via the emitter of the vertical NPN bipolar junction transistor includes releasing the electrostatic discharge to the n-type buried layer at the reference voltage Vss. In some embodiments, the operation method of the electrostatic discharge protection device further includes: releasing the electrostatic discharge via a lateral NPN bipolar junction transistor, where the collector of the lateral NPN bipolar junction transistor is the n-type drain region, the emitter is the source region of the n-type channel metal oxide semiconductor field effect transistor, and the base is the p-type well region. In some embodiments, releasing the electrostatic discharge via the emitter of the vertical NPN bipolar junction transistor includes releasing the electrostatic discharge to the n-type buried layer at the power supply voltage Vdd. In some embodiments, the operation method of the electrostatic discharge protection device further includes: releasing the electrostatic discharge via a lateral NPN bipolar junction transistor, where the collector of the lateral NPN bipolar junction transistor is the n-type drain region, the emitter is the source region of the n-type channel metal oxide semiconductor field effect transistor, and the base is the p-type well region. The foregoing disclosure outlines the features of various embodiments, so as to enable those of ordinary skill in the art to better understand the aspects of the present disclosure. Those of ordinary skill in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments or examples introduced herein. Those of ordinary skill in the art also need to understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made to the present disclosure without departing from the spirit and scope of the present disclosure. 20: Semiconductor device 22: Parasitic vertical NPN BJT 24: MOSFET 26: p-type well region 28: n-type buried layer 30: n-type drain region 32: n-type source region 34: Gate 36: p+ contact 38: Isolation region 40: Parasitic lateral NPN BJT 42: Base resistance 50: I / O pad 54: I-V curve 56: x-axis 58: y-axis 60: Semiconductor device 62: Internal circuit 64: ESD clamp 80: Operation 82: Operation 84: Operation 100: Computer system 102: Processor 104: Computer-readable storage medium 106: Instruction 108: Manufacturing tool 110: Bus 112: I / O interface 114: Network interface 116: Network 118: Database 120: UI 122: Manufacturing system 124: Design studio 126: Mask studio 128: Semiconductor device manufacturing plant 130: Semiconductor device design layout pattern 132: Data preparation 134: Mask manufacturing 136: Mask 138: Semiconductor wafer 140: Wafer manufacturing 142: Semiconductor device Vdd: Power supply voltage Vss: Reference voltage Vh: Holding voltage Vt1: ESD trigger voltage Vt2: Victim's destructive voltage Aspects of the present disclosure will be better understood from the following embodiments and drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased to make the description clear and understandable. In addition, the drawings are illustrative examples of the embodiments of the present disclosure and are not intended to be limiting. FIG. 1 is a schematic cross-sectional view of a semiconductor device including a parasitic vertical NPN BJT for releasing ESD current, according to some embodiments of the present disclosure. FIG. 2 is a schematic view of the semiconductor device of FIG. 1 as a snapback device, according to some embodiments of the present disclosure. FIG. 3 is a schematic view of the I-V curve of the parasitic vertical NPN BJT, according to some embodiments of the present disclosure. FIG. 4 is a schematic view of a semiconductor device including the semiconductor device of FIG. 1, according to some embodiments of the present disclosure. FIG. 5 is a schematic view of the semiconductor device of FIG. 1 having a MOSFET and a parasitic vertical NPN BJT, according to some embodiments of the present disclosure. FIG. 6 is a schematic view of the semiconductor device of FIG. 1 having a MOSFET, a parasitic vertical NPN BJT, and a parasitic lateral NPN BJT, according to some embodiments of the present disclosure. FIG. 7 is a schematic view of the semiconductor device of FIG. 4 in another ESD scheme, according to some embodiments of the present disclosure. FIG. 8 is a schematic view of the semiconductor device of FIG. 1 configured to release ESD current to a reference voltage Vss and to a power supply voltage Vdd, according to some embodiments of the present disclosure. FIG. 9 is a schematic view of a method of operating an ESD protection device, according to some embodiments of the present disclosure. FIG. 10 is a block diagram schematically showing an example of a computer system configured to provide the semiconductor device and method of the present disclosure, according to some embodiments of the present disclosure. FIG. 11 is a block diagram schematically showing a semiconductor device manufacturing system and a semiconductor device manufacturing process related thereto, according to some embodiments of the present disclosure. 20: Semiconductor device 22: Parasitic vertical NPN BJT 24: MOSFET 26: p-type well region 28: n-type buried layer 30: n-type drain region 32: n-type source region 34: Gate 40: Parasitic lateral NPN BJT 50: I / O pad Vss: Reference voltage

Claims

1. A semiconductor device, comprising: A surge-back device electrically connected to a reference voltage Vss, an input / output pad, and a power supply voltage Vdd, wherein the surge-back device comprises: an n-type buried layer; a p-type well region located above the n-type buried layer; and an n-type channel metal-oxide-semiconductor field-effect transistor including a gate, an n-type drain region, and a source region electrically connected to the reference voltage Vss and the gate. A vertical NPN bipolar junction transistor having a collector electrically connected to the n-type drain region of the input / output pads, a base being the p-type well region, and an emitter electrically connected to the n-type buried layer of the power supply voltage Vdd, wherein the p-type well region is floating; and a lateral NPN bipolar junction transistor having a collector being the n-type drain region, an emitter being the source region, and a base being the floating p-type well region; and an electrostatic discharge (ESD) clamp electrically connected to the surge return device, the reference voltage Vss, and the power supply voltage Vdd, wherein the ESD clamp includes an internal diode.

2. The semiconductor device as claimed in claim 1 further includes: An isolation region adjacent to the aforementioned n-type drain region; And a contact point adjacent to the aforementioned isolation region, and separated from the aforementioned n-type drain region by the aforementioned isolation region.

3. A semiconductor device, comprising: A surge-back device electrically connected to a reference voltage Vss, an input / output pad, and a power supply voltage Vdd, wherein the surge-back device comprises: an n-type buried layer electrically connected to the power supply voltage Vdd; a p-type well region located above the n-type buried layer; and an n-type channel metal-oxide-semiconductor field-effect transistor including a gate, an n-type drain region electrically connected to the input / output pad, and a source region electrically connected to the reference voltage Vss and the gate. A vertical NPN bipolar junction transistor having a collector as the n-type drain region, an emitter as the n-type buried layer, and a base as the p-type well region, wherein the p-type well region is floating; and a lateral NPN bipolar junction transistor having a collector as the n-type drain region, an emitter as the source region, and a base as the floating p-type well region; and an electrostatic discharge (ESD) clamp electrically connected to the surge return device, the reference voltage Vss, and the power supply voltage Vdd, wherein the ESD clamp includes an internal diode.

4. The semiconductor device as claimed in claim 3 further includes: An isolation region adjacent to the aforementioned n-type drain region; And a contact point adjacent to the aforementioned isolation region, and separated from the aforementioned n-type drain region by the aforementioned isolation region.

5. An operating method for an electrostatic discharge protection device, comprising: An electrostatic discharge (ESD) is received at an n-type drain region of an n-channel metal-oxide-semiconductor (MOSFET) connected to an input / output pad. In response to the ESD, a bias voltage is applied to a vertical NPN bipolar junction transistor (NPNJ) having a collector as the n-type drain region and a base as a p-type well region located above an n-type buried layer, wherein the p-type well region is floating. The ESD is released through an emitter of the vertical NPNJ to the n-type buried layer at a power supply voltage Vdd. The electrostatic discharge is released from a source region at a reference voltage Vss via a lateral NPN bipolar junction transistor, wherein the lateral NPN bipolar junction transistor has a collector as the n-type drain region, an emitter as the source region of the n-type channel metal-oxide-semiconductor field-effect transistor, and a base as the p-type well region, and the source region is electrically connected to a gate of the n-type channel metal-oxide-semiconductor field-effect transistor; and the electrostatic discharge is released from the reference voltage Vss to the power supply voltage Vdd via an electrostatic discharge clamp electrically connected to a jump-back device, the power supply voltage Vdd, and the reference voltage Vss, wherein the jump-back device includes the n-type channel metal-oxide-semiconductor field-effect transistor, the n-type buried layer, and the p-type well region, and the electrostatic discharge clamp includes an internal diode.

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