Structure and formation method of package

Abstract

A packaging structure and a method for forming the same are provided. The method includes receiving a first wafer structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure. The top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure. The method further includes bonding a second wafer structure to the dielectric bonding structure and the conductive bonding structure via dielectric-to-dielectric bonding and metal-to-metal bonding. The method further includes forming an insulating layer over the first wafer structure, wherein the insulating layer laterally surrounds the first wafer structure. Additionally, the method includes forming a capacitor element laterally separated from the second wafer structure, with the insulating layer partially surrounding the capacitor element.

Description

Technical Field

[0001] This disclosure relates to a packaging structure, and more particularly to a packaging structure having a capacitive element. Prior Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Continuous progress in semiconductor manufacturing processes has led to semiconductor devices having finer components and / or higher integration levels. The functional density (i.e., the number of interconnect devices per unit chip area) generally increases while the geometric size (i.e., the smallest element that can be produced using the process) decreases. This miniaturization process generally provides benefits in terms of increased production efficiency and reduced associated costs.

[0003] Chip packaging not only provides protection for semiconductor devices from environmental contamination but also provides a connection interface for the semiconductor devices encapsulated therein. Smaller area or smaller packaging structures with lower height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies. These packaging technologies for relatively new semiconductor dies face manufacturing challenges. Summary of the Invention

[0005] Embodiments of this disclosure provide a method for forming a packaging structure, including: receiving a first wafer structure, where the first wafer structure has a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, and the top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure; bonding a second wafer structure to the dielectric bonding structure and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding; forming an insulating layer above the first wafer structure, where the insulating layer laterally surrounds the first wafer structure; and forming a capacitive element, the capacitive element being laterally separated from the second wafer structure, where the insulating layer at least partially surrounds the capacitive element.

[0006] An embodiment of the present disclosure provides a packaging structure, comprising: a first chip structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, wherein a top surface of the conductive bonding structure and a top surface of the dielectric bonding structure are coplanar; a second chip structure bonded to the dielectric bonding structure and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitive element laterally separated from the second chip structure; and an insulating layer laterally surrounding the second chip structure and at least a portion of the capacitive element.

[0007] An embodiment of the present disclosure provides a packaging structure, comprising: a first chip structure; a second chip structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, wherein a top surface of the conductive bonding structure and a top surface of the dielectric bonding structure are coplanar, and the second chip structure is bonded to the first chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitive element laterally separated from the second chip structure, wherein the first chip structure extends across opposite edges of the second chip structure and opposite edges of the capacitive element; and an insulating layer laterally surrounding the second chip structure. Brief Description of the Drawings

[0008] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. FIGS. 1A-1G are cross-sectional views of various stages of a process for forming a portion of a packaging structure according to some embodiments. FIG. 2 is a cross-sectional view of a portion of a packaging structure according to some embodiments. FIG. 3 is a cross-sectional view of a portion of a packaging structure according to some embodiments. FIG. 4 is a cross-sectional view of a portion of a packaging structure according to some embodiments. FIG. 5 is a cross-sectional view of a portion of a packaging structure according to some embodiments. FIGS. 6A-6J are cross-sectional views according to some embodiments, each showing a portion of a capacitive element of a packaging structure. FIG. 7 is a plan view of a portion of a packaging structure according to some embodiments. FIG. 8 is a cross-sectional view of a portion of a packaging structure according to some embodiments. FIG. 9 is a cross-sectional view of a portion of a packaging structure according to some embodiments. Embodiments

[0009] The following disclosure provides numerous examples or embodiments for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is described that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Additionally, embodiments of the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed.

[0010] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "higher", and the like, to facilitate the description of the relationship between one or more components or features in a diagram and another or other components or features. Spatially relative terms are intended to encompass different orientations of a device in use or operation, as well as the orientations described in the diagrams. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted in accordance with the orientation after turning.

[0011] The following describes some embodiments of the present invention, in which additional steps may be provided before, during, and / or after the described multiple stages. Some of the described stages may be replaced or omitted in different embodiments. External components may be added to the semiconductor device structure. Some of the described components may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0012] It should be understood that the language or terminology in this disclosure is for descriptive purposes and not for limiting purposes, such that the language or terminology in this specification should be interpreted by those of ordinary skill in the relevant art in accordance with the teachings of this disclosure.

[0013] In some embodiments, the terms "about" and "substantially" may indicate that a given numerical value varies within 5% of this numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of this numerical value). These values are merely examples and not limitations. The terms "about" and "substantially" may refer to a percentage of the numerical value that can be interpreted by those skilled in the relevant art in accordance with the teachings herein.

[0014] Embodiments of the present disclosure may relate to three-dimensional (3D) packaging, 3D-IC devices, and 2.5D packaging. Embodiments of the present disclosure form a packaging structure including a substrate that carries one or more dies or packages, and a protection element (such as a protective lid) located beside the die or package. This protection element may also serve as a warpage-control element and / or a heat dissipation element.

[0015] Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packaging, 3D-IC devices, and / or 2.5D packaging. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allows testing using a probe or a probe card and the like. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with an intermediate verification testing method that includes known good die (KGD) to improve yield and reduce costs.

[0016] Figures 1A-1G are cross-sectional views of various stages of a process for forming a portion of a packaging structure according to some embodiments. As shown in Figure 1A, according to some embodiments, a wafer structure (or a chip-containing structure) 10 is received. In some embodiments, the wafer structure 10 is a semiconductor wafer including a plurality of semiconductor dies. After a subsequent sawing process, a plurality of semiconductor dies separated from each other can be obtained. In some other embodiments, the wafer structure 10 is a single semiconductor die.

[0017] In some embodiments, the wafer structure 10 includes a semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 may include silicon or another elemental semiconductor material, such as germanium. The semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0018] In some other embodiments, the semiconductor substrate 100 comprises a compound semiconductor. For example, the compound semiconductor comprises one or more group III-V compound semiconductors having a composition defined by the chemical formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and added together equals 1. The compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates comprising group II-VI compound semiconductors may also be used.

[0019] In some embodiments, the semiconductor substrate 100 is the active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or combinations thereof. In some other embodiments, the semiconductor substrate 100 comprises a multilayer structure. For example, the semiconductor substrate 100 comprises a silicon germanium layer formed over a bulk silicon layer.

[0020] Various device components 102 are formed in or on a semiconductor substrate 100. FIG. 1A shows one of the device components 102. Examples of the various device components 102 include transistors (such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel field effect transistors (PFETs), and / or n-channel field effect transistors (NFETs), etc.), diodes, or other suitable components. In some embodiments, the device component 102 shown in FIG. 1A includes a baseband device, a logic device, or other suitable device. Various processes can be used to form the various device components, including deposition, etching, implantation, optical lithography, annealing, and other suitable processes.

[0021] The wafer structure 10 may include a front-side interconnect structure. In some embodiments, the front-side interconnect structure includes a plurality of dielectric structures 104a, 104b, 104c and a plurality of conductive components 106a, 106b, 106c surrounded by the dielectric structures 104a, 104b, 104c. Each of the dielectric structures 104a, 104b, 104c may include one or more dielectric layers. The conductive components 106a, 106b, 106c may include conductive lines, conductive pads, conductive contacts, and conductive vias. In some embodiments, the conductive component 106c is a conductive pad of top metal connected to a conductive line. In some embodiments, the conductive component 106b is a conductive via penetrating through a plurality of dielectric layers.

[0022] The dielectric layers of the dielectric structures 104a, 104b, 104c can be made of silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, other suitable materials, or combinations thereof, or include these materials. The conductive components 106a, 106b, 106c can be made of copper, tungsten, cobalt, aluminum, tantalum, gold, other suitable materials, or combinations thereof, or include these materials. The formation of the front-side interconnect structure can involve multiple deposition processes, patterning processes, planarization processes, other applicable processes, or combinations thereof.

[0023] The device elements of the wafer structure 10 are interconnected by the front-side interconnect structure to form an integrated circuit device, such as a logic device, a memory device (e.g., a static random access memory (SRAM)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, one or more other types of devices, or combinations thereof.

[0024] As shown in FIG. 1A, according to some embodiments, the wafer structure 10 further includes a plurality of conductive bonding structures 110 and a dielectric bonding structure 108. The dielectric bonding structure 108 laterally surrounds the conductive bonding structures 110. The dielectric bonding structure 108 can be made of silicon oxide, carbon-containing silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof, or include these materials. The dielectric bonding structure 108 can be deposited over the front-side interconnect structure using a chemical vapor deposition (CVD) process.

[0025] Then, according to some embodiments, as shown in FIG. 1A, the conductive bonding structures 110 are formed within the dielectric bonding structure 108. In some embodiments, some of the conductive bonding structures 110 are electrically connected to the conductive component 106b therebelow. In some embodiments, the conductive bonding structures 110 and the conductive component 106b therebelow are two connecting portions of a single conductive structure formed in the same process.

[0026] In some embodiments, as shown in FIG. 1A, the top surface of the dielectric bonding structure 108 is coplanar with the top surface of the conductive bonding structures 110. In some embodiments, the formation of the conductive bonding structures 110 involves one or more planarization processes to ensure that the top surface of the dielectric bonding structure 108 is coplanar with the top surface of the conductive bonding structures 110. For example, a chemical mechanical polishing (CMP) process is used.

[0027] As shown in FIG. 1A, according to some embodiments, a pick-up wafer structure (or a structure including a wafer) 20 is picked up and prepared for bonding to the wafer structure 10. In some embodiments, the wafer structure 10 is wider than the wafer structure 20. In some embodiments, the wafer structure 20 is a single semiconductor wafer. In some embodiments, the wafer structure 20 is a known good die (KGD) that has been tested.

[0028] In some embodiments, similar to the wafer structure 10, the wafer structure 20 includes a semiconductor substrate 200. In some embodiments, the semiconductor substrate 200 is a bulk semiconductor substrate. The semiconductor substrate 200 may include silicon or another elemental semiconductor material, such as germanium. The semiconductor substrate 200 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 200 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0029] In some other embodiments, the semiconductor substrate 200 includes a compound semiconductor. For example, the compound semiconductor includes one or more group III-V compound semiconductors having a composition defined by the chemical formula Al X1Ga X2In X3As Y1P Y2N Y3Sb Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and when added together equals 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates including group II-VI compound semiconductors may also be used.

[0030] In some embodiments, the semiconductor substrate 200 is the active layer of a SOI substrate. The SOI substrate may be manufactured using a SIMOX process, a wafer bonding process, other applicable methods, or a combination thereof. In some other embodiments, the semiconductor substrate 200 includes a multilayer structure. For example, the semiconductor substrate 200 includes a silicon germanium layer formed on a bulk silicon layer.

[0031] Various device components 202 are formed in or on a semiconductor substrate 200. FIG. 1A shows one of the device components 202. Examples of various device components 202 include transistors (such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel field-effect transistors (PFETs), and / or n-channel field-effect transistors (NFETs), etc.), diodes, or other suitable components. In some embodiments, the device component 202 shown in FIG. 1A includes an RF device, an analog device, or other suitable devices. Various processes can be used to form various device components, including deposition, etching, implantation, optical lithography, annealing, and other suitable processes.

[0032] The wafer structure 20 may include a front-side front interconnect structure. In some embodiments, the front-side interconnect structure includes a plurality of dielectric structures 204a, 204b, 204c and a plurality of conductive components 206a, 206b, 206c surrounded by the dielectric structures 204a, 204b, 204c. Each dielectric structure 204a, 204b, 204c may include one or more dielectric layers. The conductive components 204a, 204b, 204c may include conductive lines, conductive pads, conductive contacts, and conductive vias. In some embodiments, the conductive component 206c is a conductive pad of top metal connected to a conductive line. In some embodiments, the conductive component 206b is a conductive via penetrating through a plurality of dielectric layers.

[0033] The dielectric layers of the dielectric structures 204a, 204b, 204c may be made of, or include, silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, other suitable materials, or combinations thereof. The conductive components 206a, 206b, 206c may be made of, or include, copper, tungsten, cobalt, aluminum, tantalum, gold, other suitable materials, or combinations thereof. The formation of the front-side interconnect structure may involve a plurality of deposition processes, patterning processes, planarization processes, other applicable processes, or combinations thereof.

[0034] The device components of the wafer structure 20 are interconnected by the front-side interconnect structure to form an integrated circuit device, such as an analog device, a memory device (SRAM), an RF device, an input / output (I / O) device, a SoC device, a logic device, one or more other types of device devices, or combinations thereof.

[0035] In some embodiments, the chip structure 20 includes a plurality of through-chip vias 240 extending into the semiconductor substrate 200. As shown in FIG. 1A, one of the through-chip vias 240 is shown. Each through-chip via 240 can be electrically connected to one or more conductive components 206a formed in the front-side interconnect structure. In some embodiments, an insulating layer is formed between the semiconductor substrate 200 and the through-chip vias 240 to prevent short circuits between the through-chip vias 240 and the semiconductor substrate 200. The insulating layer can be made of silicon oxide, silicon oxynitride, silicon nitride, other suitable materials, or combinations thereof, or include such materials. In some embodiments, the through-chip vias 240 penetrate the semiconductor substrate 200. In some other embodiments, the through-chip vias 240 extend into the semiconductor substrate 200 without completely penetrating the semiconductor substrate 200.

[0036] As shown in FIG. 1A, according to some embodiments, the chip structure 20 further includes a plurality of conductive bonding structures 210 and a dielectric bonding structure 208. The dielectric bonding structure 208 laterally surrounds the conductive bonding structures 210. The dielectric bonding structure 208 can be made of silicon oxide, carbon-containing silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof, or include such materials. The dielectric bonding structure 208 can be deposited over the front-side interconnect structure using a CVD process.

[0037] Then, according to some embodiments, as shown in FIG. 1A, the conductive bonding structures 210 are formed in the dielectric bonding structure 208. In some embodiments, some of the conductive bonding structures 210 are electrically connected to the conductive components 206b therebelow. In some embodiments, the conductive bonding structures 210 and the conductive components 206b therebelow are two connecting portions of a single conductive structure formed in the same process.

[0038] In some embodiments, as shown in FIG. 1A, the top surface of the dielectric bonding structure 208 is coplanar with the top surface of the conductive bonding structures 210. In some embodiments, the formation of the conductive bonding structures 210 involves one or more planarization processes to ensure that the top surfaces of the dielectric bonding structure 208 and the conductive bonding structures 210 are coplanar. For example, a CMP process is used.

[0039] As shown in FIG. 1B, according to some embodiments, the chip structure 10 and the chip structure 20 are bonded together through direct bonding. The direct bonding can be a hybrid bonding including dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, no tin-containing solder elements or solder bumps are formed between the chip structure 10 and the chip structure 20. In some embodiments, the bonding between the chip structures 10 and 20 is a bumpless thermos-compression hybrid bonding.

[0040] In some embodiments, the chip structure 20 is picked up and directly placed on top of the dielectric bonding structure 108 and on top of the conductive bonding structure 110. Accordingly, the dielectric bonding structure 108 of the chip structure 10 is in direct contact with the dielectric bonding structure 208 of the chip structure 20. The conductive bonding structure 110 of the chip structure 10 is in direct contact with the conductive bonding structure 210 of the chip structure 20.

[0041] Before placing the chip structure 20, a planarization process is performed to provide a highly planar bonding surface. In some embodiments, there is no gap between the dielectric bonding structure 108 and the dielectric bonding structure 208. In some embodiments, there is no gap between the conductive bonding structure 110 and the conductive bonding structure 210. In some embodiments, a thermal operation is then used to enhance the bonding between the conductive bonding structure 110 and the conductive bonding structure 210. The temperature of the thermal operation can be between approximately 100 degrees Celsius and approximately 500 degrees Celsius. In some embodiments, a thermocompression process is used to enhance the bonding between the chip structure 10 and the chip structure 20. The thermocompression process can be performed at a temperature of approximately 400 degrees Celsius for about 2 hours.

[0042] As shown in FIG. 1C, according to some embodiments, an insulating layer 112 is formed above the chip structure 10 to laterally surround the chip structure 20. In some embodiments, as shown in FIG. 1C, the top surface of the insulating layer 112 is coplanar with the surface of the semiconductor substrate 200 and the surface of the chip via 240. In some embodiments, the top surface of the insulating layer 112 is coplanar with the surface of the semiconductor substrate 200 and the surface of the through-chip via 240. The insulating layer 112 can be made of silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, other suitable materials, or combinations thereof, or includes these materials. In some embodiments, the insulating layer 112 is not made of a molding compound material or an epoxy-based resin material.

[0043] In some embodiments, an insulating material layer for forming the insulating layer 112 is deposited over the wafer structure 10 and over the wafer structure 20. The insulating material layer may be deposited using a CVD process, an atomic layer deposition (ALD) process, a flowable chemical vapor deposition (FCVD) process, a spin-coating process, another applicable process, or a combination thereof. Then, the insulating material layer is partially removed using a planarization process. The planarization process may be performed until the through-wafer via 240 is exposed. In some embodiments, a portion of the semiconductor substrate 200 and / or the through-wafer via 240 is removed during the planarization process. Accordingly, the remaining portion of the insulating material layer forms the insulating layer 112. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, another applicable process, or a combination thereof.

[0044] As shown in FIG. 1D, according to some embodiments, the insulating layer 112 is partially removed to form an opening 114. The opening 114 may expose one or more conductive bonding structures 110 thereunder. The opening 114 may be formed using one or more photolithography processes and one or more etching processes. For example, a patterned photoresist layer or a patterned dry film may be formed to assist in the formation of the opening 114. The opening 114 may have various cross-sectional shapes. Each opening 114 may have a circular cross-sectional shape, a rectangular cross-sectional shape, a square cross-sectional shape, an elliptical cross-sectional shape, or another suitable cross-sectional shape. Each opening 114 may have a width ranging from about 0.05 μm to about 0.5 μm.

[0045] Then, according to some embodiments, as shown in FIG. 1D, a conductive layer 116A and a conductive layer 116B are formed along the bottom and sidewalls of the left opening 114 and the bottom and sidewalls of the right opening 114, respectively. The conductive layers 116A and 116B may be made of copper, cobalt, gold, another suitable material, or a combination thereof, or may include such materials. In some embodiments, each of the conductive layers 116A and 116B is electrically connected to the same conductive bonding structure 110 thereunder. In these cases, the conductive layers 116A and 116B are electrically connected to each other. In some embodiments, the conductive layers 116A and 116B are electrically connected to one of the conductive bonding structures 208 of the wafer structure 20 through the conductive bonding structure 110 thereunder.

[0046] However, the embodiments of the present disclosure are not limited thereto. Many changes and / or modifications can be made to the embodiments of the present disclosure. In some other embodiments (as shown in FIG. 2), the conductive layer 116A and the conductive layer 116B are electrically connected to different conductive bonding structures 110 below them. Therefore, the conductive layer 116A and the conductive layer 116B are not electrically connected to each other.

[0047] In some embodiments, an electrochemical plating (ECP) process is used to form the conductive layer 116A and the conductive layer 116B. A patterned seed layer can be formed above the bottom and on the sidewalls of the opening 114. In some embodiments, a patterned mask layer is formed to cover the portions where the patterned seed layer is not designed to be formed.

[0048] Then, a metal layer is deposited above the patterned mask layer, above the bottom of the opening 114, and on the sidewalls of the opening 114. Then, the patterned mask layer is removed, and a portion of the metal layer located above the patterned mask layer is also removed. Therefore, the remaining portion of the metal layer forms the patterned seed layer. Then, one or more ECP processes are performed to electroplate a conductive material on top of the patterned seed layer. Therefore, the patterned seed layer and the electroplated conductive material together form the conductive layer 116A and the conductive layer 116B. In some embodiments, the conductive layer 116A and the conductive layer 116B are formed simultaneously.

[0049] As shown in FIG. 1E, according to some embodiments, a capacitive dielectric layer 118 is formed on top of the conductive layer 116B. In some embodiments, a portion of the capacitive dielectric layer 118 extends above the top surface of the conductive layer 116B and above the top surface of the insulating layer 112. The capacitive dielectric layer 118 can be made of a high dielectric constant material. The capacitive dielectric layer 118 can be made of hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide, hafnium silicon oxide, zirconium titanium oxide, titanium oxide, tantalum oxide, strontium titanium oxide, barium titanium oxide, barium strontium titanium oxide, lead zirconium titanium oxide, silicon nitride, other suitable materials, or a combination thereof, or include these materials.

[0050] A CVD process, an ALD process, a low-temperature plasma enhanced CVD process, a physical vapor deposition (PVD) process, a spin coating process, other applicable processes, or a combination thereof can be used to deposit a capacitive dielectric material layer over the structure shown in FIG. 1D. The deposition temperature of the capacitive dielectric material layer can be between approximately 150 degrees Celsius and approximately 400 degrees Celsius. In some other embodiments, the deposition temperature of the capacitive dielectric material layer can be between approximately 180 degrees Celsius and approximately 250 degrees Celsius. Then, one or more photolithography processes and one or more etching processes (such as one or more plasma etching processes) are used to partially remove the capacitive dielectric material layer. Thus, as shown in FIG. 1E, the remaining portion of the capacitive dielectric material layer forms the capacitive dielectric material layer 118.

[0051] Embodiments of the present disclosure can be subject to many changes and / or modifications. In some other embodiments, a liquid-phase material is used to form the capacitive dielectric layer 118. For example, a liquid-phase oxide material (such as liquid-phase silicon oxide and spin-on glass) and / or a liquid-phase polymer material (such as polyimide and polybenzoxazoles (PBO)) can be used to form the capacitive dielectric layer 118. In some embodiments, a thermal curing operation is used to harden the liquid-phase material into the capacitive dielectric layer 118.

[0052] In some embodiments, the capacitive dielectric layer 118 is a single film layer. In some other embodiments, the capacitive dielectric layer 118 includes multiple sub-layers. In some embodiments, some of the sub-layers are made of different materials. In some other embodiments, the sub-layers are made of the same material. In some embodiments, the capacitive dielectric layer 118 includes an alumina sub-layer and two zirconia sub-layers. The alumina sub-layer can be sandwiched between the zirconia sub-layers.

[0053] As shown in FIG. 1F, according to some embodiments, the conductive layer 120A and the conductive layer 120B are respectively formed above the conductive layer 116A and above the capacitive dielectric layer 118. In some embodiments, the conductive layer 120A and the conductive layer 120B fill the remaining space of the opening 114. In some embodiments, the top surface of the conductive layer 120A is substantially coplanar with the top surface of the insulating layer 112. In some embodiments, the top surface of the conductive layer 120B is substantially coplanar with the top surface of the capacitive dielectric layer 118.

[0054] The materials of the conductive layer 120A and the conductive layer 120B may be the same as or similar to the materials of the conductive layer 116A and the conductive layer 116B. In some embodiments, a conductive material layer is deposited above the structure shown in FIG. 1E to overfill the opening 114. In some embodiments, an ECP process is used to deposit the conductive material layer. A seed layer may be deposited above the structure shown in FIG. 1E to assist in the formation of the conductive material layer. Then, a planarization process is used to partially remove the conductive material layer. Thus, the remaining portions of the conductive material layer form the conductive layer 120A and the conductive layer 120B. For example, the planarization process is a CMP process or another applicable process. In some embodiments, the conductive layer 120A and the conductive layer 120B are formed simultaneously.

[0055] In some embodiments, the conductive layer 116B, the capacitive dielectric layer 118, and the conductive layer 120B together form a capacitive element C. The capacitive element C can be a decoupling capacitor. As shown in FIG. 1F, the capacitive element C is laterally separated from the wafer structure 20. The capacitive element C can help reduce signal noise during the operation of the wafer structure 20 and / or the wafer structure 10. In some embodiments, the insulating layer 112 laterally surrounds the lower portion of the capacitive element C. In some embodiments, as shown in FIG. 1F, the upper portions of the capacitive dielectric layer 118 and the conductive layer 120B protrude above the top surface of the insulating layer 112. In some embodiments, the bottommost surface of the capacitive dielectric layer 118 is disposed between the top surface and the bottom surface of the insulating layer 112.

[0056] FIGS. 6A - 6J are cross-sectional views according to some embodiments, each showing a portion of a capacitive element of a package structure. The capacitive element C can be formed to have one of the cross-sectional views shown in FIGS. 6A - 6J. The capacitance of the capacitive element C can be adjusted accordingly by fine-tuning the size, profile, and / or shape of the capacitive element. The capacitance can be adjusted in the range of approximately 100 fF to approximately 500 nF, which range is suitable for various applications.

[0057] As shown in Figure 1G, according to some embodiments, a dielectric layer 122 is deposited over the structure shown in Figure 1F. The material and formation method of the dielectric layer 122 can be the same as or similar to those of the dielectric structure 104c. Then, the dielectric layer 122 is patterned to form openings exposing the underlying conductive components. For example, the conductive layer 116A, the conductive layer 120A, the conductive layer 120B of the capacitor element C, and the through-wafer via 240 are exposed.

[0058] Then, as shown in Figure 1G, according to some embodiments, conductive components 124A, 124B, 124C are formed within the openings of the dielectric layer 122 to form electrical connections to the underlying conductive components. The material and formation method of the conductive components 124A, 124B, 124C can be the same as or similar to those of the conductive layer 120A and the conductive layer 124B.

[0059] As shown in Figure 1G, according to some embodiments, a patterned passivation layer 126 is then formed over the dielectric layer 122 and over the conductive components 124A, 124B, 124C. The patterned passivation layer 126 has a plurality of openings exposing the conductive components 124A, 124B, 124C. The patterned passivation layer 126 can be made of silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, or can include such materials. The formation of the patterned passivation layer 126 may involve one or more deposition processes and one or more patterning processes.

[0060] Then, conductive components 130A, 130B, and 130C are formed over the conductive component 124A, over the conductive component 124B, and over the conductive component 124C, respectively. The conductive components 130A, 130B, 130C can be used as conductive pads. The conductive components 130A, 130B, 130C can be made of copper, aluminum, cobalt, other suitable materials, or combinations thereof, or can include such materials.

[0061] As shown in Figure 1G, a protective layer 128 is then formed over the passivation layer 126 to laterally surround the lower portions of the conductive components 130A, 130B, 130C. The protective layer 128 can be made of a polymer material, or can include a polymer material. The polymer material can be made of PBO, polyimide, epoxy resin, other suitable polymer materials, or combinations thereof, or can include such materials. In some other embodiments, the protective layer 128 is made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, other suitable dielectric materials, or combinations thereof, or can include such materials. A spin coating process, a CVD process, other applicable processes, or combinations thereof can be used to form the protective layer 128.

[0062] Then, as shown in FIG. 1G, according to some embodiments, an under bump metallization (UBM) structure 132 is formed over the conductive components 130A, 130B, 130C. The UBM structure 132 can be used to receive and hold the tin-containing solder bumps. The UBM structure 132 can be made of nickel, palladium, gold, other suitable materials, or combinations thereof, or include such materials. Electroplating processes, ECP processes, immersion processes, other applicable processes, or combinations thereof can be used to form the UBM structure 132.

[0063] Then, in some embodiments, a sawing process is used to separate this structure into multiple package structures. One of these package structures is shown in FIG. 1G. In some embodiments, the wafer structure 10 is initially a semiconductor wafer. After the sawing process, the wafer structure 10 shown in FIG. 1G can be a single semiconductor wafer. In some embodiments, the outermost edge of the insulating layer 112 is coplanar with the outermost edge of the wafer structure 10. The package structure shown in FIG. 1G can be used as a system on integrated chips (SoIC), and the SoIC can be further integrated into a chip on wafer on substrate (CoWoS) package structure, an integrated fan-out (InFO) package structure, or a similar structure. Since the capacitor element C is formed within the SoIC package structure, the interconnect length between the capacitor element C and the wafer structure is very short, which allows for a faster operation speed.

[0064] As shown in FIG. 1G, the wafer structure 10 extends across the opposite edges of the wafer structure 20 and the opposite edges of the capacitor element C formed by the capacitor dielectric layer 118 and the conductive layers 116B and 120B. In some embodiments, as shown in FIG. 1G, the conductive layer 120B serves as an electrode of the capacitor element C and is electrically connected to the conductive component 130B. In some embodiments, the conductive component 130B is used to provide an electrical connection to ground. In some embodiments, the conductive layer 116B serves as an electrode of the capacitor element C and is electrically connected to the conductive component 130A of the wafer structure 20 and the conductive bonding structure 208 of the wafer structure 20. The conductive component 130A can be used to provide signals and / or power to the capacitor element C and the wafer structure 20.

[0065] Embodiments of the present disclosure may be subject to many changes and / or modifications. FIG. 2 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 1G is formed. In some embodiments, as shown in FIG. 2, the conductive layer 116B of the capacitor element C is not electrically connected to the conductive layer 116A and the conductive layer 120A.

[0066] Embodiments of the present disclosure may be subject to many changes and / or modifications. FIG. 3 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 2 is formed. In some embodiments, capacitor elements C1 and C2 are formed to fill the openings formed in the insulating layer 112. The materials and formation methods of the capacitor elements C1 and C2 may be the same as or similar to those of the capacitor element C shown in FIG. 1G. In some embodiments, as shown in FIG. 3, the capacitor element C1 is electrically connected to the chip structure 20, and the capacitor element C2 is electrically connected to the chip structure 10. In some embodiments, the chip structure 10 extends across the opposite edges of the capacitor element C1 and the opposite edges of the capacitor element C2.

[0067] In some embodiments, the capacitor element C1 has a capacitor dielectric layer 318B, and the capacitor element C2 has a capacitor dielectric layer 318A. The materials and formation methods of the capacitor dielectric layer 318A and the capacitor dielectric layer 318B may be the same as or similar to those of the capacitor dielectric layer 118 of the capacitor element C shown in FIG. 1G. In some embodiments, the capacitor dielectric layer 318A and the capacitor dielectric layer 318B are patterned from the same capacitor dielectric layer, so as to have the same composition. In some embodiments, the capacitor dielectric layer 318A and the capacitor dielectric layer 318B are formed simultaneously. In some embodiments, the capacitor elements C1 and C2 have the same capacitance. In some embodiments, the sizes and / or shapes of the capacitor elements C1 and C2 are different from each other. In these cases, the capacitor elements C1 and C2 may have different capacitances.

[0068] Embodiments of the present disclosure may be subject to many changes and / or modifications. FIG. 4 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 3 is formed. In some embodiments, a capacitor element C3 is formed. As shown in FIG. 4, the chip structure 20 is located between the capacitor element C1 and the capacitor element C3. The materials and formation methods of the capacitor element C3 may be the same as or similar to those of the capacitor element C1. In some embodiments, the capacitor element C3 is electrically connected to the chip structure 20.

[0069] In some embodiments, the capacitor element C3 has a capacitor dielectric layer 318C. The material and formation method of the capacitor dielectric layer 318C may be the same as or similar to those of the capacitor dielectric layer 318B of the capacitor element C1. In some embodiments, the capacitor dielectric layers 318A, 318B, and 318C are patterned from the same capacitor dielectric layer, so as to have the same composition. In some embodiments, the capacitor dielectric layers 318A, 318B, and 318C are formed simultaneously. In some embodiments, the capacitor elements C1, C2, and C3 have the same capacitance. In some embodiments, the sizes and / or shapes of the capacitor elements C1, C2, and C3 are different from each other. In these cases, two or more of the capacitor elements C1, C2, and C3 may have different capacitances.

[0070] Many changes and / or modifications can be made to the embodiments of the present disclosure. FIG. 5 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 1G is formed. In some embodiments, a capacitor element C3' is formed. As shown in FIG. 5, the wafer structure 20 is located between the capacitor element C1 and the capacitor element C3'. The material and formation method of the capacitor element C3' may be the same as or similar to those of the capacitor element C1. In some embodiments, the capacitor element C3' is electrically connected to the wafer structure 20.

[0071] In some embodiments, the capacitor element C3' has a capacitor dielectric layer 318C'. The material and formation method of the capacitor dielectric layer 318C' may be the same as or similar to those of the capacitor dielectric layer 318B of the capacitor element C1. In some embodiments, the capacitor dielectric layer 318B and the capacitor dielectric layer 318C' are patterned from different capacitor dielectric layers. In some embodiments, the capacitor dielectric layer 318B and the capacitor dielectric layer 318C' have different compositions. In some embodiments, the capacitor element C1 and the capacitor element C3' have different capacitances.

[0072] Many changes and / or modifications can be made to the embodiments of the present disclosure. FIGS. 6A-6J are cross-sectional views of parts of capacitor elements of a packaging structure according to some embodiments, respectively. Each capacitor element formed in the embodiments depicted in FIGS. 1-5 can be formed to have one of the cross-sectional views shown in FIGS. 6A-6J. The capacitance of the capacitor element can be adjusted accordingly by fine-tuning the size, profile, and / or shape of the capacitor element.

[0073] For example, a first capacitor element having a cross-sectional view shown in FIG. 6B may have a higher capacitance than a second capacitor element having a cross-sectional view shown in FIG. 6D. The contact area between the capacitance dielectric layer 118 of the first capacitor element and the conductive layer 116B of the first capacitor element is greater than the contact area between the capacitance dielectric layer 118 of the second capacitor element and the conductive layer 116B of the second capacitor element.

[0074] In some embodiments, as shown in FIGS. 6A-6J, each capacitor element has an external electrode (i.e., conductive layer 116B) and an internal electrode (i.e., conductive layer 120B). In some embodiments, the internal electrode (i.e., conductive layer 120B) serves as a ground electrode. However, the embodiments of the present disclosure are not limited thereto. In some other embodiments, the external electrode (i.e., conductive layer 116B) serves as a ground electrode.

[0075] Many changes and / or modifications can be made to the embodiments of the present disclosure. In some embodiments, more than two wafer structures are bonded to the wafer structure 10 through dielectric-to-dielectric bonding and metal-to-metal bonding. FIG. 7 is a plan view of a part of a packaging structure according to some embodiments. In some embodiments, a plurality of wafer structures 20A, 20B, 20C are disposed above the wafer structure 10. In some embodiments, the wafer structures 20A, 20B, 20C are bonded to the underlying wafer structure 10 through dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, similar to the bonding between the wafer structure 10 and the wafer structure 20 shown in FIG. 1B, no tin-containing solder elements or solder bumps are formed between the lower wafer structure and the upper wafer structure.

[0076] In some embodiments, a plurality of capacitor elements 702A-702I are formed above the wafer structure 10. The materials and formation methods of the capacitor elements 702A-702I may be the same as or similar to the capacitor elements shown in FIGS. 1-6. The capacitor elements 702A-702I may have different shapes, different profiles, and / or different capacitance dielectric layers to provide different capacitances according to requirements. In some embodiments, the capacitor elements 702A-702D are formed beside the wafer structure 20. In some embodiments, the capacitor elements 702E-702I are formed on the space between the nearby wafer structures.

[0077] Embodiments of the present disclosure can be subject to many changes and / or modifications. In some embodiments, one or more capacitive elements have two or more capacitive dielectric layers. FIG. 8 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 4 is formed. In some embodiments, a capacitive element C3’’ is formed. As shown in FIG. 8, the wafer structure 20 is located between the capacitive element C1 and the capacitive element C3’’. The material and formation method of the capacitive element C3’’ can be the same as or similar to those of the capacitive element C1. In some embodiments, the capacitive element C3’’ is electrically connected to the wafer structure 20.

[0078] In some embodiments, the capacitive element C3’’ has a first capacitive dielectric layer 318C and a second capacitive dielectric layer 818. The material and formation method of the capacitive dielectric layer 318C and the capacitive dielectric layer 818 can be the same as or similar to those of the capacitive dielectric layer 318B of the capacitive element C1. In some embodiments, the capacitive dielectric layer 318C and the capacitive dielectric layer 818 are made of different materials. In some other embodiments, the capacitive dielectric layer 318C and the capacitive dielectric layer 818 are made of the same material.

[0079] In some embodiments, the capacitive elements C1, C2, C3’’ have different capacitances. The capacitance of the capacitive element can be correspondingly fine-tuned by forming additional capacitive dielectric layers.

[0080] In some embodiments, the capacitive element has vertical sidewalls. However, the embodiments of the present disclosure are not limited thereto. Embodiments of the present disclosure can be subject to many changes and / or modifications. In some other embodiments, one or more capacitive elements have slanted sidewalls. The capacitance of the capacitive element can be correspondingly adjusted by fine-tuning the slope of the slanted sidewalls.

[0081] FIG. 9 is a cross-sectional view of a part of a packaging structure according to some embodiments. A packaging structure similar to that shown in FIG. 8 is formed. In some other embodiments, the capacitive elements C1, C2, C3’’ have slanted sidewalls. Each of the capacitive elements C1, C2, C3’’ gradually narrows in the direction towards the wafer structure 10.

[0082] Embodiments of the present disclosure can be subject to many changes and / or modifications. In some other embodiments, one or more capacitive elements have curved sidewalls.

[0083] The package structure formed by the embodiments of the present disclosure includes a stack of multiple chip structures. The upper chip structure and the lower chip structure are directly bonded to each other through dielectric-to-dielectric bonding and metal-to-metal bonding. One or more embedded capacitor elements are formed above the lower chip structure and separated from the upper chip structure. The size and material of the embedded capacitor elements can be changed to provide various capacitances. The capacitance and area of the embedded capacitor elements are adjustable, which greatly improves the routing flexibility. The embedded capacitor elements have shorter interconnect lengths, which allows for shorter time delays. The performance and reliability of the package structure are significantly improved, which is suitable for future advanced portable products, such as new generation smartphones, tablets, Internet of Things, cloud computing devices and similar products.

[0084] According to some embodiments, a method for forming a packaging structure is provided. The method includes receiving a first chip structure, and the first chip structure has a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. The top surface of the conductive bonding structures is coplanar with the top surface of the dielectric bonding structure. The method further includes bonding a second chip structure to the dielectric bonding structure and the conductive bonding structures through dielectric-to-dielectric bonding and metal-to-metal bonding. The method further includes forming an insulating layer over the first chip structure, wherein the insulating layer laterally surrounds the first chip structure. Additionally, the method includes forming a capacitive element, the capacitive element being laterally separated from the second chip structure, and the insulating layer partially surrounding the capacitive element. In some embodiments, the method further includes partially removing the insulating layer to form an opening exposing one of the conductive bonding structures; forming a first conductive layer that extends along the bottom and sidewalls of the opening; forming a capacitive dielectric layer over the first conductive layer; and forming a second conductive layer over the capacitive dielectric layer, wherein the first conductive layer, the capacitive dielectric layer, and the second conductive layer together form the capacitive element. In some embodiments, the method further includes forming a second capacitive dielectric layer over the capacitive dielectric layer before the step of forming the second conductive layer. In some embodiments, the capacitive dielectric layer and the second capacitive dielectric layer are made of the same material. In some embodiments, the capacitive dielectric layer and the second capacitive dielectric layer are made of different materials. In some embodiments, a portion of the capacitive dielectric layer is formed over the top surface of the second capacitive dielectric layer and over the top surface of the first conductive layer. In some embodiments, the method further includes partially removing the insulating layer to form a second opening penetrating the insulating layer; forming a third conductive layer that extends along the bottom and sidewalls of the second opening; and forming a fourth conductive layer over the third conductive layer to fill the second opening. In some embodiments, the third conductive layer is formed simultaneously with the first conductive layer, and the fourth conductive layer is formed simultaneously with the second conductive layer. In some embodiments, the method further includes forming a second capacitive element, the second capacitive element being laterally separated from the second chip structure, wherein the insulating layer at least partially surrounds the second capacitive element. In some embodiments, the method further includes disposing a third chip structure over the first chip structure, wherein the capacitive element is located between the second chip structure and the third chip structure.

[0085] According to some embodiments, a packaging structure is provided. The packaging structure includes a first chip structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. The top surface of the conductive bonding structures is coplanar with the top surface of the dielectric bonding structure. The packaging structure further includes a second chip structure bonded to the dielectric bonding structure and the conductive bonding structures through dielectric-to-dielectric bonding and metal-to-metal bonding. The packaging structure further includes a capacitor element laterally separated from the second chip structure; and an insulating layer laterally surrounding the second chip structure and a portion of the capacitor element. In some embodiments, the packaging structure includes a first conductive layer extending along an inner sidewall of the insulating layer; a capacitor dielectric layer located above the first conductive layer; and a second conductive layer located above the capacitor dielectric layer. In some embodiments, the capacitor dielectric layer covers the top surface of the first conductive layer and the top surface of the insulating layer. In some embodiments, the outermost edge of the insulating layer is coplanar with the outermost edge of the first chip structure. In some embodiments, no tin-containing solder element is formed between the first chip structure and the second chip structure.

[0086] According to some embodiments, a packaging structure is provided. The packaging structure includes a first chip structure and a second chip structure, the second chip structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. The top surface of the conductive bonding structures is coplanar with the top surface of the dielectric bonding structure, and the second chip structure is bonded to the first chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The packaging structure further includes a capacitor element laterally separated from the second chip structure. The first chip structure extends across opposite edges of the second chip structure and opposite edges of the capacitor element. The packaging structure further includes an insulating layer laterally surrounding the second chip structure. In some embodiments, the top surface of the insulating layer is coplanar with the top surface of the second chip structure. In some embodiments, the capacitor element has a capacitor dielectric layer covering the top surface of the insulating layer, and the bottommost surface of the capacitor dielectric layer is located between the top surface and the bottom surface of the insulating layer. In some embodiments, a second capacitor element is further included, laterally separated from the second chip structure, wherein the first chip structure extends across opposite edges of the second capacitor element. In some embodiments, the capacitor element has a first conductive layer and a first capacitor dielectric layer located above the first conductive layer, the second capacitor element has a second conductive layer and a second capacitor dielectric layer located above the second conductive layer, and a first contact area between the first conductive layer and the first capacitor dielectric layer is larger than a second contact area between the second conductive layer and the second capacitor dielectric layer.

[0087] The components of several embodiments are outlined above so that those of ordinary skill in the art to which the present invention pertains can more easily understand the viewpoints of this disclosure. Those of ordinary skill in the art to which the present invention pertains should understand that they can, based on the disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

[0088] 10, 20, 20A, 20B, 20C: Chip structures 100: Semiconductor substrate 102: Device element 104a, 104b, 104c: Dielectric structures 106a, 106b, 106c: Conductive components 108: Dielectric bonding structure 110: Conductive bonding structure / Conductive component 112: Insulating layer 114: Opening 116A, 116B: Conductive layers 118: Capacitive dielectric layer 120A, 120B: Conductive layers 122: Dielectric layer 124A, 124B, 124C: Conductive components 126: Passivation layer 128: Protective layer 130A, 130B, 130C: Conductive components 132: UBM structure 200: Semiconductor substrate 202: Device element 204a, 204b, 204c: Dielectric structures 206a, 206b, 206c: Conductive components 208: Dielectric bonding structure 210: Conductive bonding structure 240: Through-wafer via 318A, 318B, 318C: Capacitive dielectric layers 702A, 702B, 702C, 702D, 702E, 702F, 702G, 702H, 702I: Capacitive elements 818: Capacitive dielectric layer C, C1, C2, C3, C3’, C3’’: Capacitive elements

Claims

1. A method for forming a packaging structure, comprising: The method includes receiving a first wafer structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures, wherein the top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure; bonding a second wafer structure to the dielectric bonding structure and the conductive bonding structure via dielectric-to-dielectric bonding and metal-to-metal bonding; forming an insulating layer over the first wafer structure, wherein the insulating layer laterally surrounds the second wafer structure; and forming a capacitor element laterally separated from the second wafer structure, wherein the insulating layer at least partially surrounds the capacitor element, and wherein the step of forming the capacitor element includes: partially removing the insulating layer to form an opening exposing one of the conductive bonding structures; conformally forming a first conductive layer in the opening, the first conductive layer extending along a bottom and a plurality of sidewalls of the opening. A capacitor dielectric layer is conformally formed above the first conductive layer; and a second conductive layer is formed above the capacitor dielectric layer to fill the opening, wherein the first conductive layer, the capacitor dielectric layer and the second conductive layer together form the capacitor element, and wherein the capacitor element gradually narrows in the direction toward the first wafer structure.

2. The method of forming the package structure of claim 1, wherein a portion of the capacitor dielectric layer is formed above the top surface of the insulating layer and above the top surface of the first conductive layer.

3. The method for forming the encapsulation structure as described in Request 1 further includes: A second capacitor element is formed, which is laterally separated from the second wafer structure, wherein the insulating layer at least partially surrounds the second capacitor element.

4. A packaging structure, comprising: A first wafer structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures, wherein the top surface of the conductive bonding structures is coplanar with the top surface of the dielectric bonding structure; a second wafer structure bonded to the dielectric bonding structures and the conductive bonding structures via dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second wafer structure; and an insulating layer laterally surrounding the second wafer structure and at least a portion of the capacitor element, wherein the capacitor element includes: a first conductive layer conformally located in a plurality of openings in the insulating layer; a capacitor dielectric layer conformally located above the first conductive layer; and a second conductive layer located above the capacitor dielectric layer, wherein the capacitor element gradually narrows in the direction toward the first wafer structure.

5. The package structure as described in claim 4, wherein the capacitor element comprises: A first conductive layer extends along a plurality of inner sidewalls of the insulating layer; A capacitor dielectric layer is located above the first conductive layer; And a second conductive layer, located above the capacitor dielectric layer.

6. The packaging structure of claim 4, wherein an outermost edge of the insulating layer is coplanar with an outermost edge of the first wafer structure.

7. A packaging structure, comprising: First chip structure; A second wafer structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures, wherein the top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure, and the second wafer structure is bonded to the first wafer structure via dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second wafer structure, wherein the first wafer structure extends across opposite edges of the second wafer structure and opposite edges of the capacitor element; The capacitor element comprises: an insulating layer laterally surrounding the second wafer structure; a first conductive layer conformally located in a plurality of openings in the insulating layer; a capacitor dielectric layer conformally located above the first conductive layer; and a second conductive layer located above the capacitor dielectric layer, wherein the capacitor element gradually narrows in the direction toward the first wafer structure.

8. The packaging structure of claim 7, wherein the top surface of the insulating layer is coplanar with the top surface of the second wafer structure.

9. As per the encapsulation structure of request item 7, it further includes: A second capacitor element is laterally separated from the second wafer structure, wherein the first wafer structure extends across the opposite edge of the second capacitor element.

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