Semiconductor structure and method of forming the same

Abstract

The semiconductor structure disclosed herein includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation structure disposed between the first base fin and the second base fin, a first channel member disposed on the first base fin, a second channel member disposed on the second base fin, a region isolation feature extending into the substrate, a first gate structure surrounding each of the first channel members, a second gate structure surrounding each of the second channel members, a first gate cleaving feature extending through the first gate structure and into the isolation structure, and a second gate cleaving feature extending through the second gate structure and into the isolation structure. Each of the first gate cleaving feature and the second gate cleaving feature is spaced apart from the region isolation feature.

Description

Isolation Structure for Multi-Gate Devices This disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs in which each generation has smaller and more complex circuits than the previous one. In the development of ICs, the functional density, i.e., the number of interconnected devices per chip area, generally increases while the geometric size, i.e., the smallest component (or line) that can be created using a manufacturing process, decreases. This scaling process typically provides benefits by increasing production efficiency and reducing related costs. This size reduction also increases the complexity of integrated circuit processes and manufacturing. For example, as integrated circuit (IC) technology moves towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Multi-gate devices generally refer to devices having a gate structure or portions thereof disposed over more than one side of a channel region. Gate-all-around (GAA) transistors are examples of multi-gate devices and have become a popular and promising candidate for high-performance and low-leakage applications. GAA transistors have a gate structure that can extend partially or completely around a channel region to provide access to two or more sides of the channel region. Since its gate structure surrounds the channel region, a GAA transistor can also be referred to as a surrounding gate transistor (SGT). Because the channel region of a GAA transistor can include nanowires or nanosheets and its configuration is similar to a bridge, a GAA transistor can also be referred to as a multi-bridge channel (MBC) transistor, a nanowire transistor, or a nanosheet transistor. Nanosheets and nanowires are generally referred to as nanostructures. Dielectric isolation features are used to isolate the IC device features that would otherwise be in contact with each other. Depending on their application, dielectric isolation features may have different shapes and properties. The present disclosure relates to a semiconductor structure, comprising: a substrate; a first base fin and a second base fin rising from the substrate; an isolation structure disposed between the first base fin and the second base fin along a direction; a plurality of first channel members disposed on the first base fin; a plurality of second channel members disposed on the second base fin; a regional isolation feature extending through the isolation structure and into the substrate; a first gate structure surrounding each of the plurality of first channel members; a second gate structure surrounding each of the plurality of second channel members; a first gate cutting feature extending through the first gate structure and into the regional isolation feature; and a second gate cutting feature extending through the second gate structure and into the regional isolation feature, wherein along the direction, each of the first gate cutting feature and the second gate cutting feature is spaced apart from the regional isolation feature. The present disclosure also relates to a method of forming a semiconductor structure, comprising: receiving a workpiece, comprising: a substrate, a first fin structure, a second fin structure, and a third fin structure rising from a top surface of the substrate, an isolation structure between a lower portion of the first fin structure and a lower portion of the second fin structure and between the lower portion of the second fin structure and a lower portion of the third fin structure, a virtual gate dielectric layer on the isolation structure and on surfaces of upper portions of the first fin structure, the second fin structure, and the third fin structure above the isolation structure, and a virtual gate electrode layer on the virtual gate dielectric layer; forming a first opening through the virtual gate electrode layer, the first opening being directly above the second fin structure; extending the first opening by etching the exposed virtual gate dielectric layer in the first opening to expose the second fin structure and etching the second fin structure to form a second opening; forming a regional isolation feature in the second opening; after forming the regional isolation feature, replacing the virtual gate dielectric layer and the virtual gate electrode layer with a first metal gate structure on the first fin structure and a second metal gate structure on the second fin structure; forming a first gate cutting opening in the first metal gate structure between the first fin structure and the regional isolation feature; forming a second metal gate structure in the second gate cutting opening between the third fin structure and the regional isolation feature; and forming a first gate cutting feature and a second gate cutting feature in the first gate cutting opening and the second gate cutting opening, respectively. The present disclosure further relates to a method of forming a semiconductor structure, comprising receiving a workpiece, comprising: a substrate, an isolation structure over the substrate; a first active region, a second active region, and a third source region rising from the substrate and extending above the isolation structure, a virtual gate dielectric layer over the isolation structure and over the surfaces of the first active region, the second active region, and the third active region above the isolation feature, and a virtual gate electrode layer over the virtual gate dielectric layer; forming a first opening through the virtual gate electrode layer to expose the virtual gate dielectric layer above the second active region; extending the first opening by etching the exposed virtual gate dielectric layer in the first opening and etching the second active region to form a second opening; forming a region isolation feature in the second opening; after forming the region isolation feature, replacing the virtual gate dielectric layer and the virtual gate electrode layer with a first metal gate structure over the first active region and a second metal gate structure over the third active region; forming a first gate cut feature extending through the first metal gate structure, the first gate cut feature being disposed between the first active region and the region isolation feature; and forming a second gate cut feature extending through the second metal gate structure, the second gate cut feature being disposed between the third active region and the region isolation feature, wherein the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature. The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat element symbols and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. For convenience of description, spatially relative terms, such as "under", "below", "lower", "over", "upper", and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. In addition, when a number or a numerical range is described by terms such as "about", "approximately" and similar terms, such terms are intended to cover numbers within a reasonable range taking into account the variations that inherently occur during manufacturing, as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having properties related to that number, the number or numerical range covers a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances known to those of ordinary skill in the art associated with depositing the material layer are + / - 15%. To ensure the functionality of the IC device, different types of dielectric isolation features are formed to separate structures that would otherwise be connected. For example, regional isolation features can be formed to selectively remove a portion of the active region, thereby dividing the active region into two regions. In some cases, the regional isolation feature can be referred to as a continuous poly on diffusion edge (CPODE) feature. Using the CPODE feature can reduce the contacted poly pitch (CPP) and reduce the size of the standard cell. As another example, gate cut features can be formed to divide a gate structure into two gate segments. The gate cut features are typically elongated and can cut through more than one gate structure extending parallel to each other. Both the regional isolation feature and the gate cut feature can be formed before or after forming the high-k metal gate structure. The present disclosure provides a process for forming regional isolation features and gate cut features to improve yield and provide balanced performance of the resulting device. In some embodiments, the regional isolation feature is formed before replacing the dummy gate stack with the high-k metal gate structure, such that the gate dielectric layer of the high-k metal gate structure ultimately extends along the sidewalls of the regional isolation feature. The gate cut feature is formed after replacing the dummy gate stack with the high-k metal gate structure. As a result, the gate dielectric layer of the high-k metal gate structure does not extend along the sidewalls of the gate cut feature. To prevent non-uniform etching due to slow etching of the gate dielectric layer, the widths of the regional isolation feature and the gate cut feature are selected such that the formation of the gate cut feature does not involve etching the gate dielectric layer disposed along the sidewalls of the regional isolation feature. The process of the present disclosure ensures a uniform gate cut feature profile. A non-uniform gate cut feature profile may result in variations in the gate structure, thereby leading to unpredictable threshold voltages and switching characteristics. Aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. FIG. 1 illustrates a flowchart of a method 100 of forming a semiconductor structure. Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some of the described steps may be replaced, eliminated, or moved. For simplicity, not all steps are described in detail herein. Method 100 will be described below in conjunction with FIGS. 2-19, which illustrate fragmentary cross-sectional views and top views of a workpiece 200 at different manufacturing stages in accordance with an embodiment of method 100. Since the semiconductor structure will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor structure 200 as needed in the context. In FIGS. 2-19, the X, Y, and Z directions are perpendicular to each other and are used consistently. For example, the X direction in one drawing is parallel to the X direction in different drawings. Additionally, in the present disclosure, like element symbols are used to represent like features. Referring to FIGS. 1 and 2, method 100 includes block 102, where a workpiece 200 is received. As shown in FIG. 2, workpiece 200 includes a substrate 202 and a stack 204 disposed on substrate 202. In one embodiment, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure. In some embodiments, substrate 202 may include one or more well regions, such as an n-type well region doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)), or a p-type well region doped with a p-type dopant (i.e., boron (B)), for forming different types of devices. Ion implantation or thermal diffusion may be used to form the doping of the n-type wells and p-type wells. Still referring to FIG. 2, stack 204 may include a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si) and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 206 allows for the selective removal or recess of the sacrificial layers 206 without substantially damaging the channel layers 208. In some embodiments, an epitaxial process may be used to deposit the sacrificial layers 206 and the channel layers 208. CVD deposition techniques such as vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes may be used to epitaxially deposit stack 204. The sacrificial layers 206 and the channel layers 208 are alternately deposited in sequence to form stack 204. The stack 204 shown in FIG. 2 includes three (3) sacrificial layers 206 and three (3) layers, which are for illustrative purposes only and are not intended to limit the scope beyond that specifically recited in the claims. The number of layers in stack 204 depends on the desired number of channel components of semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. Referring to FIGS. 1 and 3, method 100 includes block 104, where a fin structure 210 is formed. In some embodiments, at block 104, a portion of stack 204 and substrate 202 is patterned to form fin structure 210 defined by trenches 211. As shown in FIG. 3, each of the fin structures 210 includes a base portion 210B formed from a portion of substrate 202 and a top portion 210T formed from stack 204. The top portion 210T is disposed above the base portion 210B. The fin structure 210 extends longitudinally from substrate 202 along the Y direction and extends perpendicularly along the Z direction. The fin structure 210 can be patterned using a suitable process including a double patterning or multi-patterning process. Generally, a double patterning or multi-patterning process combines a lithography process with a self-alignment process, thereby allowing the creation of patterns with pitches, for example, smaller than those obtainable using a single, direct lithography process. For example, in one embodiment, a hard mask layer is first deposited over stack 204, and then a material layer is formed over the hard mask. The material layer is patterned using a lithography process. Spacers are formed along the patterned material layer using a self-alignment process. The material layer is then removed, and then the remaining spacers or mandrels can be used to pattern the hard mask layer, and then the patterned hard mask layer can be used to pattern the fin structure 210 by etching stack 204 and substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As shown in FIG. 3, in some embodiments, the fin structures 210 are disposed at a first pitch P1, which is the sum of a first spacing S1 between two adjacent fin structures 210 along the X direction and a first width W1 of the fin structure. In some implementations, the first width W1 can be between about 5 nm and about 100 nm, and the first spacing S1 can be between about 20 nm and about 200 nm. The first pitch P1 can be between about 25 nm and about 300 nm. Referring to FIGS. 1 to 4, method 100 includes block 106 in which an isolation feature 212 is formed. After forming the fin structure 210, the isolation feature 212 shown in FIG. 4 is formed between adjacent fin structures 210. The isolation feature 212 can also be referred to as a shallow trench isolation (STI) feature 212. In an exemplary process, a dielectric material for the isolation feature 212 is first deposited on the workpiece 200, and the trenches 211 between the fin structures 210 are filled with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric material can be deposited by a CVD process, a flowable CVD (FCVD) process, spin coating, and / or other appropriate processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process until at least a portion of the fin structure 210 is exposed. The planarized dielectric material is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form the isolation feature 212. As shown in FIG. 4, the top portion 210T of the fin structure 210 rises above the isolation feature 212, while the base portion 210B is surrounded by the isolation feature 212. Referring to FIGS. 1 and 5, method 100 includes block 108 in which a virtual gate stack 220 is formed on the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is employed, where the virtual gate stack 220 serves as a placeholder for the functional gate structure. Other processes and configurations are also feasible. In some embodiments shown in FIG. 5, the virtual gate stack 220 includes a virtual dielectric layer 214 and a virtual electrode 216 disposed on the virtual dielectric layer 214. The region of the fin structure 210 covered by the virtual gate stack 220 can be referred to as the channel region. Each of the channel regions in the fin structure 210 is sandwiched between two source / drain regions along the Y direction to form the source / drain. In an exemplary process, the virtual dielectric layer 214 is deposited blanketly on the workpiece 200 by CVD. In this exemplary process, the virtual dielectric layer 214 is deposited on the top surface of the isolation feature 212 and the exposed surface of the fin structure 210. Next, a material layer for the virtual electrode 216 is deposited blanketly on the virtual dielectric layer 214. Then, a lithography process is used to pattern the virtual dielectric layer 214 and the material layer for the virtual electrode 216 to form the virtual gate stack 220. In some embodiments, the virtual dielectric layer 214 may include silicon oxide, and the virtual electrode 216 may include polysilicon. As shown in FIG. 5, when measured from the top surface of the substrate 202, each of the fin structures 210 has a first height H1. The dummy gate stack 220 may have a second height H2 measured from the top surface of the fin structure 210. In some embodiments, the first height H1 may be between about 10 nm and about 200 nm, and the second height may be between about 10 nm and about 200 nm. Although not explicitly shown in FIGS. 2 - 14, after the dummy gate stack 220 is formed, a dielectric material for at least one gate spacer 222 (shown in FIG. 15) is formed over the workpiece 200, including along the sidewalls of the dummy gate stack 220. The at least one gate spacer 222 may include two or more gate spacer layers. The dielectric material for the at least one gate spacer 222 may be selected to allow for selective removal of the dummy gate stack. Suitable dielectric materials for the at least one gate spacer 222 may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, silicon oxycarbide, silicon carbide, silicon oxynitride, and / or combinations thereof. In an exemplary process, the at least one gate spacer may be conformally deposited over the workpiece 200 using CVD, sub - atmospheric pressure CVD (SACVD), or ALD. After the dummy gate stack 220 is removed and replaced with a functional gate structure, the at least one gate spacer 222 will remain in the final structure. Now briefly referring to FIG. 15, which is a fragmentary top view of the workpiece 200, where the dummy gate stack 220 has been replaced with a gate structure 250. As shown in FIG. 15, the at least one gate spacer 222 remains disposed along the sidewalls of the gate structure 250. Referring to FIGS. 1 and 5, method 100 includes block 110, where source / drain features 236 are formed. The operation of block 110 includes recessing the source / drain regions of the fin structures 210 to form source / drain grooves, forming interior spacer features, depositing source / drain features 236 (as shown in FIG. 15) in the source / drain regions, and depositing an interlayer dielectric layer 232 (as shown in FIG. 15) over the source / drain features 236. Using the dummy gate stack 220 and the at least one gate spacer 222 (as shown in FIG. 15) as an etch mask, the workpiece 200 is anisotropically etched to form source / drain grooves over the source / drain regions of the fin structures 210. The anisotropic etching in block 110 may include a dry etching process or a suitable etching process. For example, the dry etching process may use an oxygen - containing gas, hydrogen, a fluorine - containing gas (e.g., CF 4 、SF 6 、NF 3 、CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gas (such as Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gas (such as HBr and / or CHBr 3 ), iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. Although not specifically shown in the figures, the operation of block 110 also includes forming internal spacer features to stagger the channel layer 208. After forming the source / drain recesses, the sacrificial layer 206 exposed in the source / drain recesses is first selectively and partially recessed to form internal spacer recesses, while the exposed channel layer 208 is substantially not etched. In an embodiment where the channel layer 208 is mainly composed of silicon (Si) and the sacrificial layer 206 is mainly composed of silicon germanium (SiGe), the selective and partial recess of the sacrificial layer 206 may include APM etching (such as ammonia hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recesses, an internal spacer material layer is then conformally deposited on the workpiece 200 (including above and within the internal spacer recesses) using CVD or ALD. The internal spacer material may include silicon nitride, silicon carbonitride, silicon carbide nitride, silicon oxide, silicon carbon oxide, silicon carbide, or silicon oxynitride. After the deposition of the internal spacer material layer, the internal spacer material layer is etched back to form internal spacer features. The operation of block 110 also includes depositing source / drain features 236 in the source / drain recesses (shown in dashed lines in FIG. 15 as they are covered under the interlayer dielectric (ILD) layer 232). In some embodiments, the source / drain features 236 can be selectively and epitaxially deposited on the exposed semiconductor surfaces of the channel layer 208 and the substrate 202. The source / drain features 236 can be deposited using an epitaxial process such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The source / drain features 236 can be n-type or p-type. When the source / drain features 236 are n-type, they can include silicon (Si) and can be doped with an n-type dopant such as phosphorus (P) or arsenic (As). When the source / drain features 236 are p-type, they can include silicon germanium (SiGe) or germanium (Ge) and can be doped with a p-type dopant such as boron (B) or boron difluoride (BF 2 ). The doping of the source / drain features 236 can be performed in-situ through their deposition or ex-situ using an implantation process such as a junction implant process. Although not explicitly shown in the figures, the source / drain features 236 can include multiple epitaxial layers with different doping concentrations. After depositing the source / drain features 236 over the source / drain regions of the fin structure 210, block 110 includes the operation of depositing the ILD layer 232 (shown in FIG. 15) over the source / drain features 236. The material of the ILD layer 232 includes tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 232 can be deposited by spin coating, an FCVD process, or other suitable deposition techniques. After depositing the ILD layer 232, a planarization process (such as a chemical mechanical polishing (CMP) process) can be performed on the workpiece 200 to provide a flat top surface that exposes the dummy gate stack 220. In some embodiments not explicitly shown in the figures, a contact etch stop layer (CESL) can be conformally deposited over the workpiece 200 and the source / drain features 236 before depositing the ILD layer 232. In those embodiments, the CESL can include silicon nitride and can be deposited using ALD or CVD. Referring to FIGS. 1 and 6-8, method 100 includes block 112 where a regional isolation opening 2260 is formed. The operation of block 112 may include depositing a first hard mask layer 224 over the virtual gate stack 220 (as shown in FIG. 6), forming a first opening 226 to expose the fin structure 210 (as shown in FIG. 7), and extending the first opening 226 into the exposed fin structure 210 (as shown in FIG. 8). Referring first to FIG. 6. The first hard mask layer 224 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, and may be deposited using CVD or a suitable method. A combination of lithography and etching processes may be used to pattern the first hard mask layer 224. After patterning the first hard mask layer 224, the patterned first hard mask layer 224 may be applied as an etch mask to etch the virtual electrode 216 to form the first opening 226. In some embodiments, the etching of the virtual electrode 216 may include a dry etching process using a reactive gas and a polymer gas. The reactive gas may include chlorine (Cl 2 ), hydrogen bromide (HBr), tetrafluoromethane (CF 4 ), or hydrogen (H 2 ), or other gas species that can react with the virtual electrode 216. The polymer gas refers to a gas species that can form a by-product during the etching step to form a passivation layer. Exemplary polymer gases include nitrogen (N 2 ), oxygen (O 2 ), or carbon dioxide (CO 2 ). The use of the polymer gas causes the re-deposition of the by-product, thereby slowing down the etching process. In some embodiments, the dry etching process may include a plasma source having a power of between about 50 W and about 800 W. Additionally, the dry etching process may include a bias power between 0 W and about 800 W, a pressure between 3 mTorr and about 80 mTorr, and a process temperature between about 20°C and about 60°C. As shown in FIG. 7, the dry etching process for forming the first opening 226 may be selective to the virtual electrode 216 and substantially slow down when it reaches the virtual dielectric layer 214 and the isolation feature 212 on the fin structure 210. In this case, the virtual dielectric layer 214 serves as an etch stop layer. In some embodiments, in order to provide a straight sidewall profile for the first opening 226, a cyclic etching process including alternating etching cycles and oxidation cycles may be employed. In some embodiments, although the cyclic etching process is performed, the sidewalls of the first opening 226 may be tapered downward. Now refer to FIG. 8. A dry etching process different from the dry etching process used to form the first opening 226 can be performed to extend the first opening 226 downward along the depth of the fin structure 210 to form a second opening 2260. In some embodiments, the dry etching process for extending the first opening 226 includes using a reactive gas and a polymer gas. The reactive gas may include chlorine (Cl 2 ), hydrogen bromide (HBr), tetrafluoromethane (CF 4 ), tetrafluoromethane (CF 4 ), hexafluorobutadiene (C 4 H 6 ), hydrogen gas (H 2 ), or nitrogen trifluoride (NF 3 ). A polymer gas refers to a type of gas that can form a by-product during the etching step of forming the passivation layer. Exemplary polymer gases include nitrogen gas (N 2 ), oxygen gas (O 2 ), or carbon dioxide (CO 2 ), methane (CH 4 ), silicon tetrachloride (SiCl 4 ), carbon dioxide (CO 2 ), oxygen gas (O 2 ), or sulfur dioxide (SO 2). In some embodiments, the dry etching process for forming the second opening 2260 may include a plasma source having a power supply power between about 0 W and about 1500 W. Additionally, the dry etching process may include a bias power between 0 W and about 800 W, a pressure between 3 mTorr and about 100 mTorr, and a process temperature between about 20 °C and about 100 °C. In some embodiments, the etching processes for forming the first opening 226 and the second opening 2260 are performed in different etching systems (or etchers). As shown in FIG. 8, the dry etching process for forming the second opening 2260 may be selective with respect to the substrate portion 210B such that the width of the second opening 2260 has a step change. In some other embodiments, the dry etching process for forming the second opening 2260 may be less selective with respect to the substrate portion 210B and may etch more isolation features 212 or even the substrate 202. As a result, the sidewalls of the second opening 2260 may be substantially continuous and not characterized by a step change in width along the X direction. The second opening 2260 may also be referred to as the regional isolation opening 2260. Referring to FIGS. 1 and 9, method 100 includes block 114, wherein a regional isolation feature 230 is formed in the second opening 2260. At block 114, a dielectric material for the regional isolation feature 230 is deposited over the second opening 2260 by plasma enhanced CVD (PECVD), atomic layer deposition (ALD), low pressure CVD (LPCVD), or CVD. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a suitable dielectric material. After depositing the dielectric material for the regional isolation feature 230, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to form the regional isolation feature 230 and remove excess material, including the patterned first hard mask layer 224. Referring to FIGS. 1 and 10, method 100 includes block 116, wherein the virtual gate stack 220 is removed. After forming the regional isolation feature 230, the exposed virtual gate stack 220 is removed from the workpiece 200 by a selective etching process. The selective etching process may be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the virtual dielectric layer 214 and the virtual electrode 216 without substantially damaging at least one gate spacer 222 (shown in FIG. 15), the regional isolation feature 230, and the channel region of the fin structure 210, which was not removed during the formation of the regional isolation feature 230. The removal of the virtual gate stack 220 results in a gate trench 234 over the channel region of the fin structure 210. The gate trench 234 is defined along the Y direction by at least one gate spacer 222 (as shown in FIG. 15). Referring to FIGS. 1 and 11, method 100 includes block 118, in which the channel member 2080 is released from the sacrificial layer 206. As shown in FIG. 10, after removing the virtual gate stack 220, the channel layer 208 and the sacrificial layer 206 in the channel region are exposed in the gate trench. As shown in FIG. 11, the exposed sacrificial layer 206 between the channel layers 208 can be selectively removed to release the channel layer 208, thereby forming the channel member 2080. The channel members 2080 are vertically stacked on top of each other along the Z direction and are vertically spaced from each other by the space left by removing the sacrificial layer 206. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, the selective removal includes silicon germanium oxidation, followed by removal of the silicon germanium oxide. For example, oxidation can be provided through ozone cleaning, and then the silicon germanium oxide can be removed by an etchant such as NH 4 OH. As the sacrificial layer 206 in the channel region is removed, the top surfaces of the channel member 2080 and the base portion 210B and the isolation features 212 are exposed in the gate trench 234. Referring to FIGS. 1 and 12, method 100 includes block 120, in which a gate structure 250 is formed to surround each of the channel members 2080. The gate structure 250 can include an interface layer 242 on the top surfaces of the channel member 2080 and the base portion 210B, a gate dielectric layer 244 above the interface layer 242, and a gate electrode layer 246 above the gate dielectric layer 244. In some embodiments, the interface layer 242 includes silicon oxide and can be formed by a pre-cleaning process. Example pre-cleaning processes can include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel member 2080 and the base portion 210B to form the interface layer 242. Then, the gate dielectric layer 244 is deposited on the interface layer 242 using ALD, CVD, and / or other suitable methods. The gate dielectric layer 244 can include a high-k dielectric material. As used herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, e.g., greater than the dielectric constant of thermally oxidized silicon (~3.9). In one embodiment, the gate dielectric layer 244 can include hafnium oxide. Alternatively, the gate dielectric layer 244 can include other high-k dielectrics, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO 4 ), zirconia (ZrO 2 ), zirconium silicate (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), alumina (Al 2 O 3 ), zirconia (ZrO), yttrium oxide (Y 2 O 3 ), SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicate (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO 3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming or depositing the interface layer 242 and the gate dielectric layer 244, a gate electrode layer 246 is deposited over the gate dielectric layer 244. The gate electrode layer 246 can be a multi-layer structure that includes at least one work function layer and one metal fill layer. For example, at least one work function layer can include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal fill layer can include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a planarization process such as a CMP process may be performed to remove excess material to provide a substantially flat top surface of the gate structure 250. Referring to FIG. 12, the gate structure 250 surrounds each of the channel members 2080. In FIG. 12, the regional isolation feature 230 appears to divide the gate structure 250 into different segments. It should be noted that the regional isolation feature 230 is not designed or intended to segment the gate structure 250. As shown in FIG. 15, the regional isolation feature 230 is intended to divide the active region along the Y direction, including the channel member 2080 and the substrate portion 210B. As a result, the regional isolation feature 230 and the second opening 2260 do not elongate along the Y direction but are more rounded. Although in some cases, the regional isolation feature 230 sufficiently divides the gate structure 250 into insulated gate segments along the X direction, its downwardly tapered shape often prevents it from completely segmenting the virtual gate stack 220. The remaining virtual gate stack material may then be replaced with gate structure material. For this reason, a gate cutting feature 270 (to be described below) is still needed to divide the gate structure 250 into different segments. As shown in FIG. 15, each of the gate cutting features 270 elongates along the Y direction, and such a shape and the associated lithography process are more effective in dividing the gate structure 250 in a controlled manner. Referring to FIGS. 1 and 13-15, method 100 includes block 122 where a gate cutting feature 270 is formed. The operation of block 122 may include forming a gate cutting opening 262 (as shown in FIG. 13) and forming a gate cutting feature 270 in the gate cutting opening 262 (as shown in FIGS. 14 and 15). Referring to FIG. 13, to form the gate cutting opening 262, a second hard mask layer 260 is deposited over the workpiece 200 (including over the gate structure 250). In terms of composition and formation process, the second hard mask layer 260 may be similar to the first hard mask layer 224. Then a lithography process and an etching process are performed to pattern the second hard mask layer 260. Then the patterned second hard mask layer 260 is used as an etching mask to etch a portion of the gate structure 250, the gate dielectric layer 244, and the isolation feature 212. The etching process for forming the gate cutting opening 262 may include using chlorine (Cl 2 ), hydrogen gas (H 2 ), oxygen gas (O 2), or other dry etching processes using chlorine-containing etchants. In some embodiments, the etching process applied to form the gate cut openings 262 may include multiple etching steps using an etchant that is more selective for the corresponding gate material, and may include wet etching, dry etching, or a combination thereof. As shown in FIG. 13, each of the gate cut openings 262 extends completely through the gate structure 250 and into the isolation feature 212. As shown in FIG. 13, each of the gate cut openings 262 is tapered downward. It has been observed that due to the etch-resistant nature of the high-k dielectric material, the etching process for forming the gate cut openings 262 will inevitably etch the gate dielectric layer 244 at a slower rate. When the gate cut openings 262 overlap the regional isolation feature 230 vertically in any way, the etching can be retarded by the gate dielectric layer 244 disposed along the sidewalls of the regional isolation feature 230. This retardation mixed with different degrees of overlap can result in non-uniform depths and shapes of the gate cut openings 262. In turn, each segment of the gate structure 250 can have a different shape and width (along the X direction) from the channel member 2080. The variations in shape and width in the gate cut openings 262 (and ultimately the gate cut features 270) may cause variations in the threshold voltage of the transistor, which is undesirable. For the foregoing reasons, a feature of the present disclosure is to ensure that the gate cut openings 262 do not cut into the regional isolation feature 230. As shown in FIG. 13, although the gate cut openings 262 can be close to the regional isolation feature 230, none of them cut into the regional isolation feature 230. In other words, the gate cut openings 262 are spaced apart from the regional isolation feature 230 by at least a portion of the gate electrode layer 246 and a portion of the gate dielectric layer 244. After forming the gate cut openings 262, a dielectric material for the gate cut feature 270 is deposited over the gate cut openings 262 by plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), low-pressure CVD (LPCVD), or CVD. In some embodiments, the dielectric material for the gate cut feature 270 may include silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, or a suitable dielectric material. After depositing the dielectric material for the gate cut feature 270, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to form the gate cut feature 270 as shown in FIG. 14 and remove the excess material, including the patterned second hard mask layer 260. As shown in FIG. 14, similar to the gate cut openings 262, each of the gate cut features 270 is tapered downward. Still referring to FIG. 14. In embodiments where the region isolation feature 230 includes a step change in width, it can be divided into an upper portion 230U above the level where the step change occurs and a lower portion 230L below that level. In some embodiments, each of the upper portion 230U and the lower portion 230L has a downward taper, even though they have discontinuous sidewalls. The upper portion 230U includes a second width W2 at its top surface and a second width W3 at the interface with the lower portion 230L. The lower portion 230L includes a fourth width W4 at the interface with the upper portion 230U and a fifth width W5 at its bottom surface. In some cases, due to the downward taper, the third width W3 is about 80% to about 95% of the second width W2, and the fifth width W5 is about 80% to about 95% of the fourth width W4. The third width W3 is greater than the fourth width W4. In some cases, the ratio of the fourth width W4 to the third width W3 can be between about 20% and about 100% (where there is no step change). As shown in FIG. 15, each of the gate cut features 270 can have a sixth width W6 at its top surface. In some embodiments, the sixth width W6 can be between about 10 nm and about 100 nm. To ensure that the region isolation feature 230 fits between two adjacent gate cut features 270 without any boundary merging, the second width W2 should be equal to or less than the sum of the first width W1 (as shown in FIG. 3) and the first spacing S1 (also as shown in FIG. 3) minus the sixth width W6. That is, the second width W2 is equal to or less than (W1 + S1 - W6). In any case, the second width W2 cannot be less than the first width W1. The region isolation feature 230 extends deeper into the substrate 202 than the gate cut feature 270. In some embodiments, the region isolation feature 230 extends completely through the base portion 210B and well into the substrate 202, while the gate cut feature 270 terminates in the isolation feature 212. In some embodiments, the region isolation feature 230 can have a first depth D1 from its top surface to its bottom surface in the substrate 202, and the gate cut feature 270 can have a second depth D2 from its top surface to its bottom surface in the isolation feature 212. The first depth D1 is greater than the second depth D2. For the active region not affected by the region isolation feature 230, the lateral gate thickness G along the sidewalls of the channel member 2080 can be defined as half of the difference between the first spacing S1 and the sixth width W6 (i.e., G = (S1 - W6) / 2). FIG. 15 is a top view showing a fragment of the workpiece 200 shown in FIG. 14. As shown in FIG. 15, each of the gate structures 250 (whether segmented by the gate cute feature 270 or not) extends longitudinally along the X direction. Each of the active regions including the base portion 210B and the channel member 2080 disposed on the base portion 210B extends longitudinally along the Y direction. Generally, the fin structure 210 can be regarded as an approximate representation of the active region. It can be seen that the active region and the gate structure 250 extend in directions perpendicular to each other. Each vertical stack of the channel member 2080 extends between and contacts two source / drain features 236 along the Y direction. The source / drain features 236 are shown in dashed lines because they are at least covered by the ILD layer 232. Along the Y direction, each of the gate structures 250 is sandwiched between two portions of at least one gate spacer 222. Since the isolation feature 230 is formed before the gate structure 250, the gate dielectric layer 244 is disposed along the sidewalls of the isolation feature 230. The gate cut feature 270 is formed after the gate structure 250. Therefore, the gate cut feature 270 cuts through the gate structure 250, but the gate dielectric layer 244 does not extend along the sidewalls of the gate cut feature 270. In some embodiments shown in FIG. 15, the gate cut feature 270 is more elongated along the Y direction than the isolation feature 230. In FIG. 15, the isolation feature 230 includes a first length L1 along the Y direction, and each of the gate cut features 270 includes a second length L2 along the Y direction. The second length L2 is greater than the first length L1. In some embodiments, the ratio of the second length L2 to the first length L1 is between about 1.5 and about 4.0. FIGS. 16 and 17 illustrate alternative embodiments in which the dry etching for forming the second opening 2260 in block 112 is less selective to the base portion 210B. As a result, a continuous isolation feature 2300 can be formed. The continuous isolation feature 2300 is characterized by continuous sidewalls and no step change in width. In some embodiments, the continuous isolation feature 2300 can be tapered downward in a continuous manner and terminate in the substrate 202. Although there are continuous sidewalls, no gate cute feature 270 vertically overlaps with the continuous isolation feature 2300. FIGS. 18 and 19 illustrate another alternative embodiment in which the jumbo isolation feature 2302 cuts into multiple base portions to separate multiple active regions. Although the jumbo isolation feature in FIG. 18 only spans two fin structures 210, it should be understood that the jumbo isolation feature 2302 can be used to divide more than two fin structures 210. In some embodiments, the jumbo isolation feature 2302 can span between 2 and 10 fin structures 210. In an exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate; a first base fin and a second base fin rising from the substrate; an isolation structure disposed between the first base fin and the second base fin along a direction; a plurality of first channel members disposed on the first base fin; a plurality of second channel members disposed on the second base fin; a regional isolation feature extending through the isolation structure and into the substrate; a first gate structure surrounding each of the plurality of first channel members; a second gate structure surrounding each of the plurality of second channel members; a first gate cut feature extending through the first gate structure and into the isolation feature; and a second gate cut feature extending through the second gate structure and into the isolation feature. Along the direction, each of the first gate cut feature and the second gate cut feature is spaced apart from the regional isolation feature. In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate electrode layer disposed on the first gate dielectric layer, wherein a portion of the first gate dielectric layer is disposed along a sidewall of the regional isolation feature. In some embodiments, the first gate cut feature is in direct contact with the first gate electrode layer. In some embodiments, a bottom surface of the regional isolation feature is lower than a bottom surface of the first gate cut feature. In some embodiments, the second gate cut feature is continuously tapered from a top surface of the second gate structure toward the isolation structure. In some embodiments, the regional isolation feature includes a lower portion and an upper portion above the lower portion, and a width of the regional isolation feature undergoes a step change between the lower portion and the upper portion along the direction. In some embodiments, the lower portion is tapered downward. In some embodiments, the upper portion is tapered downward. In another exemplary aspect, the present disclosure relates to a method. The method includes receiving a workpiece including: a substrate, a first fin structure, a second fin structure, and a third fin structure rising from a top surface of the substrate, an isolation structure between a lower portion of the first fin structure and a lower portion of the second fin structure and between the lower portion of the second fin structure and a lower portion of the third fin structure, a virtual gate dielectric layer over the isolation structure and over surfaces of upper portions of the first fin structure, the second fin structure, and the third fin structure above the isolation structure, and a virtual gate electrode layer over the virtual gate dielectric layer; forming a first opening through the virtual gate electrode layer, the first opening being directly above the second fin structure; extending the first opening by etching the exposed virtual gate dielectric layer in the first opening to expose the second fin structure and etching the second fin structure to form a second opening; forming an area isolation feature in the second opening; after forming the area isolation feature, replacing the virtual gate dielectric layer and the virtual gate electrode layer with a first metal gate structure over the first fin structure and a second metal gate structure over the second fin structure; forming a first gate cut opening in the first metal gate structure between the first fin structure and the area isolation feature; forming a second metal gate structure in the second gate cut opening between the third fin structure and the area isolation feature; and forming a first gate cut feature and a second gate cut feature in the first gate cut opening and the second gate cut opening, respectively. In some embodiments, neither the first gate cut opening nor the second gate cut opening penetrates the isolation feature. In some embodiments, the first opening exposes the dummy gate dielectric layer disposed on the isolation structure. In some embodiments, the second opening terminates in the substrate below the second fin structure. In some embodiments, each of the upper portions of the first fin structure, the second fin structure, and the third fin structure includes a stack that includes a plurality of channel layers interleaved by a plurality of sacrificial layers. In some embodiments, the replacement includes selectively removing the plurality of sacrificial layers to release the plurality of channel layers as a plurality of channel members. In some embodiments, the first metal gate structure includes a first gate dielectric layer and a first gate electrode layer on the first gate dielectric layer, the second metal gate structure includes a second gate dielectric layer and a second gate electrode layer on the second gate dielectric layer, a portion of the first gate dielectric layer extends along a first sidewall of the isolation feature, a portion of the second gate dielectric layer extends along a second sidewall of the isolation feature, and the second sidewall is opposite the first sidewall. In some embodiments, the formation of the first gate cut opening does not penetrate the portion of the first gate dielectric layer that extends along the first sidewall of the isolation feature, and the formation of the second gate cut opening does not penetrate the portion of the second gate dielectric layer that extends along the second sidewall of the isolation feature. In another exemplary aspect, the present disclosure relates to a method. The method includes receiving a workpiece including: a substrate, an isolation structure over the substrate; a first active region, a second active region, and a third source region rising from the substrate and extending above the isolation structure, a dummy gate dielectric layer over the isolation structure and over the surfaces of the first active region, the second active region, and the third active region above the isolation feature, and a dummy gate electrode layer over the dummy gate dielectric layer; forming a first opening through the dummy gate electrode layer to expose the dummy gate dielectric layer over the second active region; extending the first opening by etching the exposed dummy gate dielectric layer in the first opening and etching the second active region to form a second opening; forming an isolation feature in the second opening; after forming the isolation feature, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first active region and a second metal gate structure over the third active region; forming a first gate cut feature extending through the first metal gate structure, the first gate cut feature being disposed between the first active region and the isolation feature; and forming a second gate cut feature extending through the second metal gate structure, the second gate cut feature being disposed between the third active region and the isolation feature. The first gate cut feature and the second gate cut feature are spaced apart from the isolation feature. In some embodiments, the first metal gate structure includes a first gate dielectric layer and a first gate electrode layer on the first gate dielectric layer, the second metal gate structure includes a second gate dielectric layer and a second gate electrode layer on the second gate dielectric layer, a portion of the first gate dielectric layer extends along a first sidewall of the isolation feature of the region, a portion of the second gate dielectric layer extends along a second sidewall of the isolation feature of the region, and the second sidewall is opposite to the first sidewall. In some embodiments, forming the first opening includes using chlorine, hydrogen bromide, tetrafluoromethane, hydrogen, nitrogen, oxygen, or carbon dioxide. In some embodiments, extending the first opening includes using chlorine, hydrogen bromide, tetrafluoromethane, hexafluorobutadiene, hydrogen, nitrogen trifluoride, silicon tetrachloride, carbon dioxide, oxygen, or sulfur dioxide. The features of several embodiments are outlined above so that those of ordinary skill in the art can better understand aspects of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those of ordinary skill in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure. Disclosure. 100: Method 102: Block 104: Block 106: Block 108: Block 110: Block 112: Block 114: Block 116: Block 118: Block 120: Block 122: Block 200: Semiconductor structure / workpiece 202: Substrate 204: Stack 206: Sacrificial layer 208: Channel layer 210: Fin structure 210B: Base portion 210T: Top portion 211: Groove 212: Isolation feature / Shallow trench isolation (STI) feature 214: Virtual dielectric layer 216: Virtual electrode 220: Virtual gate stack 222: Gate spacer 224: First hard mask layer 226: First opening 230: Area isolation feature 230L: Lower portion 230U: Upper portion 232: Interlayer dielectric / ILD layer 234: Gate trench 236: Source / drain feature 242: Interface layer 244: Gate dielectric layer 246: Gate electrode layer 250: Gate structure 260: Second hard mask layer 262: Gate cut opening 270: Gate cut feature 2080: Channel member 2260: Area isolation opening / Second opening 2300: Continuous area isolation feature 2302: Giant area isolation feature D1: First depth D2: Second depth G: Lateral gate thickness H1: First height H2: Second height L1: First length L2: Second length S1: First spacing W1: First width W2: Second width W3: Third width W4: Fourth width W5: Fifth width W6: Sixth width The present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various features can be arbitrarily increased or decreased. FIG. 1 illustrates a flowchart of a method for forming a semiconductor structure according to one or more aspects of the present disclosure. FIGS. 2-19 illustrate fragmentary cross-sectional views of a workpiece during various manufacturing stages in the method of FIG. 1 according to one or more aspects of the present disclosure. 100: Method 102: Block 104: Block 106: Block 108: Block 110: Block 112: Block 114: Block 116: Block 118: Block 120: Block 122: Block

Claims

1. A semiconductor structure comprising: a substrate; a first base fin and a second base fin rising from the substrate; and an isolation structure disposed between the first base fin and the second base fin along a direction; A plurality of first channel components are disposed on the first base fin; a plurality of second channel components are disposed on the second base fin; A regional isolation feature extends through the isolation structure and into the substrate; A first gate structure surrounding each of a plurality of the first channel members; a second gate structure surrounding each of a plurality of the second channel members; a first gate cutting feature extending downwardly through the first gate structure and into the isolation structure; And a second gate cutting feature extends downwardly through the second gate structure and into the isolation structure, wherein each of the first gate cutting feature and the second gate cutting feature is spaced apart from the region isolation feature along the direction.

2. The semiconductor structure as claimed in claim 1, wherein the first gate structure includes a first gate dielectric layer and a first gate electrode layer disposed on the first gate dielectric layer, wherein a portion of the first gate dielectric layer is disposed along a sidewall of the region isolation feature.

3. The semiconductor structure as claimed in claim 1, wherein the second gate cleaving feature is continuously pushed from a top surface of the second gate structure toward the isolation structure.

4. The semiconductor structure of claim 1, wherein the region isolation feature comprises a lower portion and an upper portion above the lower portion, wherein a width of the region isolation feature undergoes a step change along the direction between the lower portion and the upper portion.

5. A method of forming a semiconductor structure, comprising: receiving a workpiece comprising: a substrate; a first fin structure, a second fin structure, and a third fin structure rising from a top surface of the substrate; an isolation structure between a lower portion of the first fin structure and a lower portion of the second fin structure, and between the lower portion of the second fin structure and a lower portion of the third fin structure; a dummy gate dielectric layer on the isolation structure and on the surfaces of the upper portions of the first fin structure, the second fin structure, and the third fin structure above the isolation structure; and a dummy gate electrode layer on the dummy gate dielectric layer; forming a first opening through the dummy gate electrode layer, the first opening being located directly above the second fin structure; extending the first opening by etching the exposed dummy gate dielectric layer in the first opening to expose the second fin structure and etching the second fin structure to form a second opening; and forming a region isolation feature in the second opening; After forming the regional isolation feature, the virtual gate dielectric layer and the virtual gate electrode layer are replaced by a first metal gate structure on the first fin structure and a second metal gate structure on the third fin structure; a first gate cutting opening is formed downwardly in the first metal gate structure between the first fin structure and the regional isolation feature and enters the isolation structure; a second gate cutting opening is formed downwardly in the second metal gate structure between the third fin structure and the regional isolation feature and enters the isolation structure; and a first gate cutting feature and a second gate cutting feature are formed in the first gate cutting opening and the second gate cutting opening, respectively.

6. The method as described in claim 5, wherein the first opening exposes the virtual gate dielectric layer disposed on the isolation structure.

7. The method of claim 5, wherein the second opening terminates in the substrate below the second fin structure.

8. A method of forming a semiconductor structure, comprising: receiving a workpiece comprising: a substrate; an isolation structure on the substrate; a first active region, a second active region, and a third source region rising from the substrate and extending over the isolation structure; a dummy gate dielectric layer on the isolation structure and on the surfaces of the first active region, the second active region, and the third active region above the isolation structure; and a dummy gate electrode layer on the dummy gate dielectric layer; forming a first opening through the dummy gate electrode layer to expose the dummy gate dielectric layer over the second active region; extending the first opening by etching the exposed dummy gate dielectric layer in the first opening and etching the second active region to form a second opening; forming a region isolation feature in the second opening; and after forming the region isolation feature, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first active region and a second metal gate structure over the third active region; A first gate cutting feature is formed by pushing downwards and extending through the first metal gate structure and into the isolation structure, the first gate cutting feature being disposed between the first active region and the regional isolation feature; and a second gate cutting feature is formed by pushing downwards and extending through the second metal gate structure and into the isolation structure, the second gate cutting feature being disposed between the third active region and the regional isolation feature, wherein the first gate cutting feature and the second gate cutting feature are spaced apart from the regional isolation feature.

9. The method of claim 8, wherein the first metal gate structure includes a first gate dielectric layer and a first gate electrode layer above the first gate dielectric layer, wherein the second metal gate structure includes a second gate dielectric layer and a second gate electrode layer above the second gate dielectric layer, wherein a portion of the first gate dielectric layer extends along a first sidewall of the region isolation feature, wherein a portion of the second gate dielectric layer extends along a second sidewall of the region isolation feature, the second sidewall being opposite to the first sidewall.

10. The method of claim 8, wherein forming the first opening comprises using chlorine, hydrogen bromide, tetrafluoromethane, hydrogen, nitrogen, oxygen, or carbon dioxide.

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