Semiconductor device and method of forming the same

Abstract

This disclosure provides a semiconductor device and a method for forming the same. The method for forming the semiconductor device according to an embodiment of this disclosure includes: bonding a first semiconductor substrate onto a second semiconductor substrate, the first semiconductor substrate having a (110) orientation and the second semiconductor substrate having a (100) orientation; forming a stack on the first semiconductor substrate, the stack including a plurality of channel layers and a plurality of sacrificial layers alternately disposed; patterning the stack to form a fin structure, the fin structure including channel regions and source / drain regions; etching the source / drain regions to form source / drain trenches; forming a dielectric film in the source / drain trenches; and epitaxially growing an epitaxial component on the dielectric film, the epitaxial component being in contact with the channel layers. The epitaxial component has a (110) orientation.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and in particular to a hybrid substrate and a method for forming the same. Prior Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in successive generations of ICs, each featuring smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (e.g., the number of interconnected elements per chip area) has generally increased, while geometry size (e.g., the smallest component (or trace) that can be created using a process) has decreased. This process size reduction generally provides benefits by increasing production efficiency and reducing associated costs. However, this size reduction also increases the complexity of IC fabrication.

[0003] For example, as integrated circuit technology evolves to smaller technology nodes, multi-gate metal-oxide semiconductor field-effect transistors (MOSFETs) (or multi-gate devices) are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). A multi-gate device generally refers to a device with a gate structure or portion thereof located on more than one side of the channel region. Fin field-effect transistors (finFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and proven choices for high-performance and low-leakage applications. FinFETs have an upward-pointing channel surrounded by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from the substrate). MBCs have a gate structure that partially or completely extends around the channel region, providing connections to the channel region on two or more sides. Because the gate structure surrounds the channel region, the multi-bridge channel transistor can also be called a surrounding gate transistor (SGT) or a gate all around (GAA) transistor.

[0004] To improve the performance of multi-bridge channel transistors, significant effort has been invested in developing features and structures in the source / drain regions that widen the channel and suppress substrate leakage. While existing source / drain region features and structures are generally adequate for their intended purpose, they are not satisfactory in every respect. Summary of the Invention

[0005] A method for forming a semiconductor device comprises: bonding a first semiconductor substrate to a second semiconductor substrate, the first semiconductor substrate having a (110) orientation and the second semiconductor substrate having a (100) orientation; forming a stack on the first semiconductor substrate, the stack comprising a plurality of channel layers and a plurality of sacrificial layers arranged alternately; patterning the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack on the channel region of the fin-shaped structure; depositing a gate spacer layer on the dummy gate stack; recessing The source / drain region is etched to form a source / drain trench, exposing the sidewalls of the channel layer and the sacrificial layer; the sacrificial layer is partially etched back to form a plurality of inner spacer grooves; a plurality of inner spacer components are formed in the inner spacer grooves; a dielectric film is formed in the source / drain trench; an epitaxial component is grown on the dielectric film, the epitaxial component is in contact with the channel layer, and the epitaxial component has a (110) direction; after forming the epitaxial component, the dummy gate stack is removed; the channel layer is released in the channel region to serve as a plurality of channel members; and a gate structure is formed to surround each of the channel members.

[0006] A method for forming a semiconductor device comprises: forming a hybrid substrate having a first region and a second region, the first region having a top surface of a (100) crystal plane and the second region having a top surface of a (110) crystal plane; patterning the second region to form a fin-shaped base; forming a plurality of channel components on the fin-shaped base; forming a plurality of inner spacer components arranged alternately with the channel components; depositing a dielectric material layer on the inner spacer components and on the top surface of the fin-shaped base; etching back the dielectric material layer to form a dielectric film; depositing an epitaxial component on the dielectric film, the epitaxial component being in contact with the channel component, the epitaxial component having a top surface of a (110) crystal plane; and forming a gate structure surrounding each of the channel components.

[0007] A semiconductor device comprises: a fin-shaped base protruding from a semiconductor substrate, the top surface of the fin-shaped base being a (110) crystal plane; a plurality of channel components arranged on the top surface of the fin-shaped base; a plurality of inner spacer components arranged alternately with the channel components; a gate structure surrounding each of the channel components; a source / drain component contacting the channel components and the inner spacer component, the top surface of the source / drain component being a (110) crystal plane; and a dielectric film directly below the source / drain component and above the top surface of the fin-shaped base. Simple diagram description

[0008] The following describes aspects of the disclosed embodiments in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased to clearly illustrate the features of the disclosed embodiments. FIG. 1 is a flow chart illustrating a method for forming a semiconductor device according to one or more aspects of the present disclosure. FIG. 2 is a perspective view of a workpiece during a bonding process in the method of FIG. 1 according to one or more aspects of the present disclosure. Figures 3 to 26 are schematic cross-sectional views of a workpiece during a manufacturing process in the method of Figure 1 according to one or more aspects of the present disclosure. Implementation Method

[0009] The following disclosure provides many different embodiments or examples for implementing various components of the provided services. Specific examples of components and configurations are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to limit the disclosed embodiments. For example, a description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, or may include embodiments in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. Furthermore, the disclosure may repeat reference symbols and / or letters throughout the various examples. This repetition is for the purposes of simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed.

[0010] Spatially relative terms such as "below," "beneath," "below," "above," "above," and the like may be used herein to describe the relationship of one element or component to other elements or components as depicted in the drawings. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein should be interpreted in that rotated orientation.

[0011] Furthermore, when using the terms "about," "approximately," or the like to describe a number or range of numbers, such terms are intended to encompass numbers within a reasonable range, taking into account variations inherent in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for components with the features associated with the number, a number or range encompasses a reasonable range encompassing the number, such as within ±10% of the number. For example, given that manufacturing tolerances associated with deposited material layers are known to those skilled in the art to be ±15%, a material layer having a thickness of "approximately 5 nanometers" may encompass a range of dimensions from 4.25 nanometers to 5.75 nanometers. Furthermore, reference symbols and / or letters may be repeated throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed.

[0012] The present disclosure generally relates to multi-gate transistors and fabrication methods, and more particularly to multi-layered components developed in the source / drain regions of multi-bridge channel (MBC) transistors. The channel region of a multi-bridge channel transistor can be disposed in a nanowire channel member, a stripe channel member, a nanosheet channel member, a nanostructured channel member, a columnar channel member, a gate channel member, and / or other suitable channel configurations. Depending on the shape of the channel member, a multi-bridge channel transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Despite its shape, each channel member of a multi-bridge channel transistor extends between and couples two epitaxial components formed in the source / drain region (also referred to as a source / drain epitaxial component or a source / drain component). The source / drain region may be referred to individually or collectively as a source or a drain, depending on the context. Ideal source / drain features in multi-bridge channel transistors introduce strain into the channel element and provide low resistance. During the formation of multi-bridge channel transistors, a dielectric film is inserted to separate the bottom surface of the source / drain features, helping to isolate them from the substrate and thereby suppress leakage current into the substrate. While such a dielectric film improves alternating current (AC) performance, it can degrade direct current (DC) performance in P-type transistors due to increased resistance. This degraded DC performance in P-type transistors can be caused by the loss of compressive strain.

[0013] The disclosed embodiment provides a semiconductor device having a hybrid substrate. The hybrid substrate provides a (100) crystal plane in an N-type field effect transistor (NFET) region (which forms an N-type transistor) and provides a (110) crystal plane in a P-type field effect transistor (PFET) region (which forms a P-type transistor). The epitaxial stack includes channel layers for the N-type transistor and the P-type transistor, which are epitaxially grown from the (100) crystal plane and the (110) crystal plane, respectively. The channel layer inherits the crystal orientation of the hybrid substrate, resulting in a high-mobility channel not only in the N-type transistor but also in the P-type transistor. Not only the channel layer, but also the source / drain components epitaxially grown from the ends of the individual channel layers also inherit the crystal orientation of the hybrid substrate from the individual channel layers. The (110) source / drain components in the P-type transistor alleviate the loss of compressive strain caused by the dielectric film inserted below the individual source / drain components. As a result, both the AC and DC performance of the transistors in the N-type FET and P-type FET regions are optimized without sacrificing the DC performance of the transistor in the P-type FET region. Furthermore, a pedestal epitaxial layer can optionally be formed between the substrate and the dielectric film. The pedestal epitaxial layer can be undoped to increase its resistance, further improving the suppression of leakage current from the source / drain components into the substrate.

[0014] Various aspects of the present disclosure will be described in detail with reference to the accompanying drawings. FIG1 is a flowchart illustrating a method 100 for forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. Method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to the details specifically depicted in method 100. Additional steps may be provided before, during, or after method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of method 100. For clarity of discussion, not all steps are described in detail herein. Method 100 will be described in detail below in conjunction with FIG2-26, which are perspective or cross-sectional views of a workpiece 200 at various stages of fabrication according to an embodiment of method 100 shown in FIG1. ​​Because workpiece 200 is to be fabricated into a semiconductor device, workpiece 200 may be referred to as semiconductor device 200 as appropriate. In FIG2-26, the X, Y, and Z directions are perpendicular to each other. Throughout the present disclosure, identical components may be designated by the same reference numerals unless otherwise specified.

[0015] Referring to Figures 1, 2, and 3, method 100 includes block 102, wherein a first semiconductor substrate 202 and a second semiconductor substrate 204 are bonded together to form a workpiece 200. In some embodiments, the first semiconductor substrate 202 is a first wafer (e.g., a first silicon (Si) wafer), and the second semiconductor substrate 204 is a second wafer (e.g., a second Si wafer). The first semiconductor substrate 202 and the second semiconductor substrate 204 have different crystal plane orientations.

[0016] In crystalline semiconductor materials, the atoms that form the solid are arranged in a periodic manner. If a periodic arrangement exists throughout the solid, the material is defined as crystalline. The periodic arrangement of atoms in a crystal is often called a "lattice." The lattice also contains a volume that represents the entire lattice and is called a unit that repeats regularly throughout the crystal. For example, silicon has a diamond cubic lattice structure, which can be represented as two interpenetrating face-centered cubic lattices. Therefore, the simplicity of analyzing and visualizing the properties of a cubic lattice can be extended to the properties of a silicon crystal. In this description, reference will be made to the various crystal planes in a semiconductor crystal (such as silicon), in particular the (100), (110), and (111) crystal planes. These crystal planes define the orientation of the semiconductor atoms relative to the major crystal axes. The numbers (xyz) are called Miller indices and are determined by the reciprocal of the intersection of the silicon crystal plane with the major crystal axes.

[0017] For example, in the illustrated embodiment, the first semiconductor substrate 202 may have a top surface with a (100) crystal plane, and the second semiconductor substrate 204 may have a top surface with a (110) crystal plane. The first semiconductor substrate 202 is also referred to as a (100) semiconductor substrate or a (100)-oriented semiconductor substrate. The second semiconductor substrate 204 is also referred to as a (110) semiconductor substrate or a (110)-oriented semiconductor substrate. In some embodiments, the first semiconductor substrate 202 and the second semiconductor substrate 204 are silicon substrates (e.g., silicon wafers). However, the disclosed structures and methods are not limiting and can be extended to other suitable semiconductor substrates and other suitable crystal orientations. For example, either the first semiconductor substrate 202 or the second semiconductor substrate 204 may include an elemental semiconductor, such as germanium (Ge), a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), or a combination thereof in the same or different crystalline structures.

[0018] The examples in Figures 2 and 3 illustrate bonding a first semiconductor substrate 202 and a second semiconductor substrate 204 together using a suitable bonding technique (e.g., direct bonding, eutectic bonding, fusion bonding, diffusion bonding, anodic bonding, or other suitable bonding methods). In one embodiment, the semiconductor substrates 202 and 204 are bonded together using direct silicon bonding (DSB). For example, the DSB process may include pre-treatment, pre-bonding at a relatively low temperature, and annealing at a relatively high temperature. When bonding the first semiconductor substrate 202 and the second semiconductor substrate 204 together, a buried oxide (BOX) layer (also known as a silicon oxide (SiO) layer) may be added therebetween.

[0019] Referring to Figures 1 and 4 , method 100 includes block 104 , in which semiconductor substrate 204 is thinned. In some embodiments, a thinning process is applied to thin semiconductor substrate 204 from its backside surface. The thinning process may include a mechanical grinding process and a chemical thinning process. During the mechanical grinding process, a substantial amount of substrate material may be initially removed from semiconductor substrate 204. The chemical thinning process may then apply an etching chemical to the backside of semiconductor substrate 204 to further thin semiconductor substrate 204 to an appropriate thickness. The thickness affects the crystalline quality of the epitaxial layer subsequently formed on workpiece 200. In some embodiments, the thickness of semiconductor substrate 204 ranges from approximately 30 nm to approximately 100 nm.

[0020] Referring to Figures 1 and 5 , method 100 includes block 106 , in which a patterned mask 206 is formed on a top surface of a workpiece 200 . The patterned mask 206 includes an opening that exposes a first region 208 of the workpiece 200 and covers a second region 210 of the workpiece 200 . The first region 208 is a region of the workpiece 200 defined by one or more N-type field-effect transistors, and the second region 210 is a region of the workpiece 200 defined by one or more P-type field-effect transistors. Throughout this document, the first region 208 is also referred to as the N-type field-effect transistor region, and the second region 210 is also referred to as the P-type field-effect transistor region. The patterned mask 206 can be a soft mask (e.g., a patterned photoresist layer), a hard mask (e.g., a dielectric material layer), or a combination thereof. In one embodiment, the patterned mask 206 is a hard mask, and a patterned photoresist layer (not shown) is formed on the hard mask by a lithography process. The hard mask is etched to transfer openings from the patterned photoresist layer to the hard mask. In some examples, the hard mask comprises silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), other semiconductor materials, and / or other dielectric materials. In one embodiment, the hard mask has a thickness in a range from about 1 nm to about 40 nm. The hard mask can be formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method. An exemplary lithography process can include forming a photoresist layer, exposing the photoresist through a lithography exposure process, performing a post-exposure bake process, and developing the photoresist layer to form a patterned photoresist layer. The lithography process can alternatively be replaced by other techniques, such as electron beam writing, ion beam writing, maskless patterning, or molecular printing. In some embodiments, the patterned photoresist layer can be directly used as an etch mask for a subsequent etching process. After patterning the hard mask, the patterned photoresist layer can be removed by a suitable process, such as wet stripping or plasma ashing.

[0021] Referring to Figures 1 and 6 , method 100 includes block 108 , in which an etching process is performed through the opening defined in patterned mask 206 . The etching process removes semiconductor substrate 204 from the N-type field-effect transistor region until semiconductor substrate 202 is exposed, forming recess 212 . The etching process uses patterned mask 206 as an etching mask. The etching process may further recess semiconductor substrate 202 until the top surface of semiconductor substrate 202 is lower than the bottom surface of semiconductor substrate 204 . Sidewalls of semiconductor substrate 204 are also exposed, defining the edges of recess 212 . The etching process may include dry etching, wet etching, or a combination thereof. Patterned mask 206 protects semiconductor substrate 204 in the P-type field-effect transistor region from being etched. In various examples, the etching process may include dry etching with a suitable etchant, such as a fluorine-containing etching gas or a chlorine-containing etching gas, such as chlorine (Cl2), dichlorodifluoromethane (CCl2F2), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), difluoromethane (CH2F2), or other suitable etching gases. In some other examples, the etching process may include wet etching with a suitable etchant, such as a hydrofluoric acid (HF)-based solution, a sulfuric acid (H2SO4)-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH4OH)-based solution, other suitable etching solutions, or combinations thereof. The etching process may include more than one step.

[0022] Referring to Figures 1 and 7, method 100 includes block 110, wherein epitaxial growth is performed to grow the thickness of semiconductor substrate 202 in the N-type field effect transistor region. In the example where semiconductor substrate 202 is a silicon wafer, crystalline silicon is epitaxially grown in recess 212, which carries the crystalline structure of semiconductor substrate 202. That is, the top surface of the epitaxially grown crystalline silicon has a (100) crystal plane. In the illustrated embodiment, the elevated top surface of semiconductor substrate 202 is located above the top surface of semiconductor substrate 204 and intersects the sidewalls of patterned mask 206. Crystalline silicon can be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition process (such as a metal organic chemical vapor deposition (MOCVD) process), and / or other suitable epitaxial growth process. Patterned mask 206 prevents epitaxial growth from occurring in the P-type field effect transistor region. At the end of the epitaxial growth, the top surface of the semiconductor substrate 202 may be higher than the top surface of the semiconductor substrate 204 by about 30 nm to about 100 nm.

[0023] Referring to Figures 1 and 8, method 100 includes block 112, wherein a planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to planarize the top surface of the workpiece 200. The patterned mask 206 can serve as a polishing stop layer during the CMP process and be removed by etching after the CMP process. Alternatively, the patterned mask 206 can be removed by the CMP process. After the CMP process, the top surface of the first semiconductor substrate 202 and the top surface of the second semiconductor substrate 204 are both exposed and substantially coplanar. The remaining thickness of the second semiconductor substrate 204 is in the range of about 30 nm to about 100 nm. Since the elevated portion of the first semiconductor substrate 202 is formed by (100)-plane epitaxial growth, it is in a crystalline structure and carries the same crystalline direction. That is, the top surface of the first semiconductor substrate 202 in the N-type field effect transistor region is still the (100) crystal plane, while the top surface of the second semiconductor substrate 204 in the P-type field effect transistor region is the (110) crystal plane. At the end of block 112, the first semiconductor substrate 202 and the second semiconductor substrate 204 (also referred to as a semiconductor layer) together define a hybrid substrate 205.

[0024] Referring to Figures 1 and 9, method 100 includes block 114, in which a stack 214 having alternating semiconductor layers is formed on a hybrid substrate 205. In some embodiments, prior to forming stack 214, an N-type field-effect transistor region and a P-type field-effect transistor region are doped with separate doping profiles, depending on design requirements as is known in the art. For example, the N-type field-effect transistor region may be doped with P-type dopants to form a P-type well (or P-well), and the P-type field-effect transistor region may be doped with N-type dopants to form an N-type well (or N-well). The N-type dopant forming the N-type well may include phosphorus (P) or arsenic (As). The P-type dopant forming the P-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. After dopant implantation, stack 214 is epitaxially grown on hybrid substrate 205.

[0025] In some embodiments, stack 214 includes sacrificial layers 216 of a first semiconductor composition alternating with channel layers 218 of a second semiconductor composition. The first and second semiconductor compositions can be different. In some embodiments, sacrificial layers 216 comprise silicon germanium, while channel layers 218 comprise silicon. It should be noted that the alternating arrangement of three sacrificial layers 216 and three channel layers 218 (as shown in FIG. 9 ) is for illustrative purposes only and is not intended to limit the scope of the claimed invention beyond the specific disclosure. It will be appreciated that any number of epitaxial layers can be formed in stack 214. The number of film layers depends on the desired number of channel components in workpiece 200. In some embodiments, the number of channel layers 218 is between one and twenty.

[0026] In some embodiments, all sacrificial layers 216 may have a substantially uniform first thickness between approximately 3 nm and approximately 10 nm, while all channel layers 218 may have a substantially uniform second thickness between approximately 3 nm and approximately 15 nm. The first thickness and the second thickness may be the same or different. As described in detail below, the channel layers 218 or portions thereof may serve as channel components for a subsequently formed multi-gate device, and the thickness of each channel layer 218 may be selected based on device performance considerations. The sacrificial layers 216 in the channel region may ultimately be removed and used to define the vertical spacing between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of each sacrificial layer 216 may be selected based on device performance considerations.

[0027] The film layers in the stack 214 can be deposited using a molecular beam epitaxy process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. Therefore, the stack 214 is also referred to as an epitaxial stack 214. As described above, in at least some examples, the sacrificial layer 216 includes an epitaxially grown silicon germanium layer, and the channel layer 218 includes an epitaxially grown silicon layer. In some embodiments, the sacrificial layer 216 and the channel layer 218 are substantially free of dopants (e.g., having an extrinsic dopant concentration of about 0 cm-3 to about 1×10 17 cm-3), wherein, for example, no intentional doping is performed during the epitaxial growth process of the stack 214. In the N-type field effect transistor region, the top surface of the semiconductor substrate 202 is a (100) crystal plane, and therefore each film layer in the stack 214 in the N-type field effect transistor region has a (100) top surface. In the P-type field effect transistor region, the top surface of the second semiconductor substrate 204 is a (110) crystal plane, so each film layer of the stack 214 in the P-type field effect transistor region has a (110) top surface.

[0028] 1 and 10 , the method 100 includes block 116, wherein a fin structure 222 is formed by patterning the stack 214 and the top of the hybrid substrate 205. In the illustrated embodiment, the fin structure 222N is formed in the N-type field effect transistor region by patterning the stack 214 and the top of the first semiconductor substrate 202, and the fin structure 222P is formed in the P-type field effect transistor region by patterning the stack 214, the second semiconductor substrate 204, and the top of the first semiconductor substrate 202.

[0029] To pattern the stack 214, a hard mask (not shown) may be deposited over the stack 214 to form an etch mask. The hard mask may be a single layer or multiple layers. For example, the hard mask may include a pad oxide layer and a pad nitride layer located on the pad oxide layer. The fin structure 222 may be patterned from the stack 214 and the hybrid substrate 205 using a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods.

[0030] In some embodiments, a double or multiple patterning process can be used to define fin structures with, for example, finer pitch patterns than those achieved using a single, direct lithography process. For example, in one embodiment, a material layer is formed above a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can be used as a mask to etch the top of the stack 214 and hybrid substrate 205 to pattern the fin structures 222. The patterned top of the hybrid substrate 205 is also designated as fin base 212B. In the N-type field-effect transistor region, fin base 212B comprises the top of the first semiconductor substrate 202. In the P-type field-effect transistor region, fin base 212B comprises the top of the second semiconductor substrate 204 and the top of the first semiconductor substrate 202. Each fin structure 222 (including the patterned stack 214 and fin base 212B) extends vertically along the Z direction and longitudinally along the X direction. In some cases, each fin structure 222 has a width measured along the Y direction between about 6 nm and about 80 nm, and a spacing between opposing sidewalls of two adjacent fin structures 222 is between about 6 nm and about 115 nm measured along the Y direction.

[0031] Continuing with FIG. 10 , isolation features 224 may be formed adjacent to the fin structures 222. In some embodiments, isolation features 224 may be formed in trenches between adjacent fin structures 222 to isolate the fin structures 222 from each other. Isolation features 224 may also be referred to as shallow trench isolation (STI) features. For example, in some embodiments, a dielectric layer is first deposited on the hybrid substrate 205 to fill the trenches. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited using a chemical vapor deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition (FCVD) process, a spin-on coating process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized using, for example, a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back using a dry etch process, a wet etch process, and / or a combination thereof to form isolation features 224. After the recessed etching, the fin structure 222 rises above the isolation features 224. The recessed top surface of the isolation features 224 can be flush with or lower than the bottom surface of the patterned stack 214.

[0032] Referring to Figures 1 and 11 , method 100 includes block 118 , in which a dummy gate stack 230 is formed on the channel region of the fin structure 222 . Figure 11 illustrates a schematic cross-sectional view taken along line segments AA and BB of Figure 10 , respectively. In some embodiments, a gate replacement process (or gate-last process) is employed, wherein the dummy gate stack 230 serves as a placeholder for various processes before being removed and replaced by a functional gate structure. Other processes and configurations are possible. The dummy gate stack 230 is formed on the fin structure 222 , and the fin structure 222 is divided into a channel region located below the dummy gate stack 230 and a source / drain region located outside the dummy gate stack 230 . The channel region is adjacent to the source / drain region, with each channel region disposed between two source / drain regions along the X-direction.

[0033] Forming the dummy gate stack 230 may include depositing and patterning film layers of the dummy gate stack 230. Referring to FIG. 11 , a dummy dielectric layer 226, a dummy electrode layer 228, and a top gate hard mask layer 232 may be blanket deposited on the workpiece 200. In some embodiments, the dummy dielectric layer 226 may be formed on the fin structure 222 using a chemical vapor deposition process, an atomic layer deposition process, an oxygen plasma oxidation process, or other suitable processes. In some cases, the dummy dielectric layer 226 may include silicon oxide. Thereafter, a dummy electrode layer 228 may be deposited on the dummy dielectric layer 226 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable processes. In some cases, the dummy electrode layer 228 may include polysilicon. For patterning purposes, the top gate hard mask layer 232 may be deposited on the dummy electrode layer 228 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable processes. The top gate hard mask layer 232, the dummy electrode layer 228, and the dummy dielectric layer 226 may then be patterned to form the dummy gate stack 230, as shown in FIG11 . For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the top gate hard mask layer 232 may include a silicon oxide layer 234 and a silicon nitride layer 236 on the silicon oxide layer 234.

[0034] Referring to Figures 1 and 12 , method 100 includes block 120 , where a gate spacer layer 238 is deposited on the dummy gate stack 230 . In some embodiments, the gate spacer layer 238 is conformally deposited on the workpiece 200 , including on the top surface and sidewalls of the dummy gate stack 230 . The term "conformally" may be used herein to describe a film layer having a substantially uniform thickness across various regions. The gate spacer layer 238 may be a single layer or multiple layers. At least one layer of the gate spacer layer 238 may include silicon carbonitride, silicon oxycarbide (SiOC), silicon oxycarbonitride, or silicon nitride. The gate spacer layer 238 may be deposited on the dummy gate stack 230 using a process such as chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atomic layer deposition, or other suitable process. In one embodiment, the gate spacer layer 238 includes a first layer and a second layer disposed on the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride. In some cases, the gate spacer layer 238 has a thickness along the X-direction between approximately 3 nm and approximately 8 nm.

[0035] 1 and 13 , the method 100 includes block 122, wherein the source / drain region of the fin structure 222 is recessed to form a source / drain trench 240. In some embodiments, the source / drain region not covered by the dummy gate stack 230 and the gate spacer layer 238 is etched by dry etching or a suitable etching process to form the source / drain trench 240. For example, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, and / or hexafluoroethane (C 2 F 6)), a chlorine-containing gas (e.g., chlorine, trichloromethane (CHCl 3), tetrachloromethane (CCl 4), and / or boron trichloride (BCl 3)), a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or tribromomethane (CHBr 3)), an iodine-containing gas, other suitable gases, plasma, and / or combinations thereof. In some embodiments represented in FIG. 13 , the source / drain regions of the fin structure 222 are recessed to expose the sidewalls of the sacrificial layer 216 and the channel layer 218. In some embodiments, the source / drain trenches 240 extend below the stack 214 into the hybrid substrate 205. As shown in FIG. 13 , the first semiconductor substrate 202 is exposed in the source / drain trenches 240 in the N-type field-effect transistor region, while the second semiconductor substrate 204 is exposed in the source / drain trenches 240 in the P-type field-effect transistor region. The first semiconductor substrate 202 in the P-type field-effect transistor region remains covered by the second semiconductor substrate 204.

[0036] Referring to Figures 1, 14, and 15, method 100 includes block 124, in which inner spacer features 244 are formed. The operations of block 124 may include selectively and partially removing the sacrificial layer 216 to form inner spacer recesses 242, depositing inner spacer material on the workpiece 200, and etching back the inner spacer material to form inner spacer features 244 in the inner spacer recesses 242. The sacrificial layer 216 exposed in the source / drain trenches 240 (as shown in Figure 14) is selectively and partially etched back to form the inner spacer recesses 242. Due to limited etching contrast, the end portions of the channel layer 218 exposed through the inner spacer recesses 242 may also suffer some etching loss, resulting in the end portions of the channel layer 218 being moderately etched and becoming thinner than the center portion of the channel layer 218 measured along the Z direction. In embodiments where the channel layer 218 comprises silicon and the sacrificial layer 216 comprises silicon germanium, the sacrificial layer 216 may be selectively etched back using a selective wet etch process or a selective dry etch process. The selective and partial etch back of the sacrificial layer 216 may include a silicon germanium oxidation process followed by silicon germanium oxide removal. In this embodiment, the silicon germanium oxidation process may include the use of ozone. In some other embodiments, the selective dry etch process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etch process may include etching with an ammonia-hydrogen peroxide (APM) mixture.

[0037] After forming the inner spacer recesses 242, an inner spacer material is deposited on the workpiece 200, including on the inner spacer recesses 242. The inner spacer material may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), or other suitable metal oxides. Although not explicitly shown, the inner spacer material may be a single layer or multiple layers. In some embodiments, the inner spacer material can be deposited using chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sub-atmospheric pressure CVD, atomic layer deposition (ALD), or other suitable methods. The inner spacer material is deposited in the inner spacer recess 242 and on the sidewalls of the channel layer 218 exposed in the source / drain trench 240. Then, referring to FIG. 15 , the deposited inner spacer material is etched back to remove the inner spacer material from the sidewalls of the channel layer 218, thereby forming an inner spacer feature 244 in the inner spacer recess 242. At block 124, the inner spacer material can also be removed from the top surface and / or sidewalls of the top gate hard mask layer 232 and the gate spacer layer 238. In some embodiments, the etch-back operation performed at block 124 may include using hydrogen fluoride, fluorine (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride, or other fluorine-based etchants. As shown in FIG. 15 , each interspacer feature 244 is in direct contact with the recessed sacrificial layer 216 and is disposed between two adjacent channel layers 218. In some cases, each interspacer feature 244 has a thickness measured along the X-direction between approximately 3 nm and approximately 5 nm.

[0038] Referring to Figures 1 and 16 , method 100 includes block 126 , where a cleaning process 300 is performed. Cleaning process 300 may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using Standard Clean 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Clean 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), a sulfuric acid-hydrogen peroxide mixture (SPM), and / or hydrofluoric acid to remove oxides. The dry cleaning process may include a helium (He) and hydrogen treatment at a temperature between approximately 250°C and approximately 550°C and a pressure between approximately 75 mTorr and approximately 155 mTorr. The hydrogen treatment converts silicon on the surface into silane (SiH 4), which can be pumped out for removal. In some embodiments, the cleaning process is configured to selectively remove or trim a portion of the channel layer without substantially removing the inner spacer features 244. The cleaning process 300 can remove surface oxides and debris to ensure a clean semiconductor surface that facilitates the growth of the pedestal epitaxial layer at block 128.

[0039] 1 and 17 , method 100 includes block 128 , wherein a pedestal epitaxial layer 246 is deposited in the bottom of each source / drain trench 240 . In the illustrated embodiment, the pedestal epitaxial layer 246 formed in the N-type field effect transistor region is labeled as pedestal epitaxial layer 246N, and the pedestal epitaxial layer 246 formed in the P-type field effect transistor region is labeled as pedestal epitaxial layer 246P. The pedestal epitaxial layer 246N has the same crystalline structure as the semiconductor substrate 202 . That is, the top surface of the pedestal epitaxial layer 246N has a (100) crystal plane. The pedestal epitaxial layer 246P has the same crystalline structure as the semiconductor substrate 204 . That is, the top surface of the pedestal epitaxial layer 246P has a (110) crystal plane. In some embodiments, the pedestal epitaxial layer 246 comprises the same material as the channel layer 218 , such as silicon. Specifically, the pedestal epitaxial layer 246 is formed of undoped silicon. In some embodiments, the pedestal epitaxial layer 246 comprises the same material as the sacrificial layer 216, such as silicon germanium, where the germanium composition of the pedestal epitaxial layer 246 is the same as or different from the germanium composition of the sacrificial layer 216. Specifically, the pedestal epitaxial layer 246 is formed of undoped silicon germanium. In various embodiments, the pedestal epitaxial layer 246 is undoped, for example, without intentional doping during the epitaxial growth process. The undoped pedestal epitaxial layer 246 provides a high-resistance path at the bottom of the source / drain trench 240, thereby suppressing leakage current into the substrate.

[0040] Suitable epitaxial deposition processes at block 128 include vapor phase epitaxy, molecular beam epitaxy, selective chemical vapor deposition, and / or other suitable processes. Various deposition parameters can be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trenches 240, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, power supply, RF bias, DC bias, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the pedestal epitaxial layer 246, the workpiece 200 is exposed to a deposition mixture comprising dichlorosilane (DCS) (SiH2Cl2) and / or silane (containing silicon precursors), hydrogen (carrier precursor), and hydrochloric acid (containing etchant precursors). In some embodiments, the selective chemical vapor deposition process is performed at a deposition temperature of approximately 600°C to approximately 750°C. In some embodiments, the selective chemical vapor deposition process is performed at a deposition pressure of approximately 10 Torr to approximately 100 Torr. In some embodiments, the selective chemical vapor deposition process is configured as a bottom-up deposition process, such that the pedestal epitaxial layer 246 grows from the exposed semiconductor surface at the bottom of the source / drain trench 240, rather than from the exposed end of the channel layer 218. The growth of the pedestal epitaxial layer 246 is time-controlled, allowing the top surface of the pedestal epitaxial layer 246 to be fine-tuned to be flush with, below, or above the bottom surface of the bottommost sacrificial layer 216, depending on device performance requirements. If the top surface of the pedestal epitaxial layer 246 is below the bottom surface of the bottommost sacrificial layer 216, the pedestal epitaxial layer 246 may not be in physical contact with the bottommost inner spacer feature 244. Conversely, the pedestal epitaxial layer 246 may be in physical contact with the bottommost inner spacer feature 244.

[0041] 1 , 18 , and 19 , method 100 includes block 130 , in which a dielectric film 250 is formed in the bottom of the source / drain trench 240 and on the pedestal epitaxial layer 246 . The operations of block 130 may include depositing a dielectric material 248 on the workpiece 200 and etching back the dielectric material 248 to form the dielectric film 250 in the bottom of the source / drain trench 240 . The dielectric material 248 is deposited on the workpiece 200 , including on the sidewalls and bottom surfaces of the source / drain trench 240 and on the sidewalls and top surfaces of the dummy gate stack 230 , as shown in FIG. 18 . In some embodiments, dielectric material 248 may include a metal oxide or metal nitride, such as lanthanum oxide, aluminum oxide, zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (Zr2Al3O9), titanium oxide, tantalum oxide, zirconium oxide, hafnium oxide, yttrium oxide, aluminum oxynitride (AlON), tantalum carbonitride (TaCN), other suitable materials, or combinations thereof. In some embodiments, dielectric material 248 may include silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. In some embodiments, dielectric material 248 may be deposited using a directional deposition process, such as plasma-assisted atomic layer deposition (PEALD) with radio frequency plasma processing, or other suitable methods. During the directional plasma treatment, the horizontal portion of the dielectric material 248 receives more plasma bombardment than the vertical portion, resulting in different etch selectivities between the horizontal and vertical portions. This allows the dielectric material 248 to be etched back with the horizontal portion remaining at the bottom of the source / drain trench 240. Alternatively, the directional deposition process can form the dielectric material 248 with a thicker horizontal portion (e.g., on the bottom of the source / drain trench 240) and a thinner vertical portion (e.g., on the sidewalls of the dummy gate stack 230), also resulting in the horizontal portion remaining after etching back the dielectric material 248. In some embodiments, the horizontal portion of the dielectric material 248 has a thickness ranging from approximately 4.5 nm to approximately 10.5 nm, while the vertical portion of the dielectric material 248 has a thinner thickness ranging from approximately 3.5 nm to approximately 5.5 nm.

[0042] Referring to FIG. 19 , the deposited dielectric material 248 is then etched back to remove the thinner vertical portions from the sidewalls of the dummy gate stack 230 . In some embodiments, the etch-back operation performed in block 130 may include using hydrogen fluoride, fluorine, hydrogen, ammonia, nitrogen trifluoride, or other fluorine-based etchants. Due to the loading effect, the horizontal portion of the top of the dummy gate stack 230 may also be removed, while the horizontal portion of the bottom of the source / drain trench 240 is thinned, but remains as a dielectric film 250 covering the pedestal epitaxial layer 246 . In some embodiments, the dielectric film 250 has a thickness (measured along the Z direction) in a range from approximately 1 nm to approximately 5 nm. The top surface of the dielectric film 250 may be above the bottom surface of the bottommost sacrificial layer 216 , but below the top surface of the bottommost sacrificial layer 216 . The bottommost inner spacer feature 244 may have a height measured in the Z direction of about 5 nm to about 7 nm, such that the dielectric film 250 is in physical contact with the bottommost inner spacer feature 244, while the top portion of the bottommost inner spacer feature 244 is located above the top surface of the dielectric film 250. In the embodiment shown, the top surface of the dielectric film 250 may have a flat profile. Alternatively, the top surface of the dielectric film 250 may have a concave profile or a convex profile.

[0043] Referring to Figures 1 and 20, method 100 includes block 132, wherein the channel layer 218 in the P-type field-effect transistor region is laterally etched back. Etching back the channel layer 218 in the P-type field-effect transistor region results in a channel length in the P-type field-effect transistor region that is shorter than the channel length in the N-type field-effect transistor region. Etching back the channel layer 218 in the P-type field-effect transistor region pushes the junction back closer to the gate structure in the P-type field-effect transistor region, which is beneficial to the performance of the P-type field-effect transistor. In some embodiments, a photoresist layer is formed over the N-type field-effect transistor region, exposing the P-type field-effect transistor region. The etch back operation performed in block 132 may include using hydrogen fluoride, fluorine gas, hydrogen gas, ammonia, nitrogen trifluoride, or other fluorine-based etchants. In the illustrated embodiment, the end portion of the channel layer 218 vertically stacked between the inner spacer features 244 is removed from the P-type field-effect transistor region. In some embodiments, the operation at block 132 is optional, and method 100 may proceed to block 134 without performing the operation at block 132 .

[0044] 1 and 21 , method 100 includes block 134 , wherein source / drain features 256 are selectively formed epitaxially from the exposed sidewalls of the channel layer 218 , while the sidewalls of the sacrificial layer 216 remain covered by the inner spacer features 244 . Suitable epitaxial processes for block 134 include vapor phase epitaxy, ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, and / or other suitable processes. In the illustrated embodiment, the source / drain features 256 formed in the N-type field effect transistor region are labeled as source / drain features 256N, while the source / drain features 256 formed in the P-type field effect transistor region are labeled as source / drain features 256P. The source / drain features 256N share the same crystalline structure as the semiconductor substrate 202 and the channel layer 218 in the N-type field effect transistor region. That is, the top surface of the source / drain component 256N has a (100) crystal plane. The source / drain component 256P has the same crystal structure as the second semiconductor substrate 204 and the channel layer 218 in the P-type field effect transistor region. That is, the top surface of the source / drain component 256P has a (110) crystal plane.

[0045] The source / drain feature 256N and the source / drain feature 256P can be formed separately. For example, the source / drain feature 256N can be epitaxially grown in the source / drain trench 240 in the N-type FET region, while the source / drain trench 240 in the P-type FET region is covered by a photoresist layer to prevent epitaxial growth in the P-type FET region. After forming the source / drain feature 256N, the source / drain feature 256P can be epitaxially grown in the source / drain trench 240 in the P-type FET region, while the N-type FET region is covered by a photoresist layer to prevent epitaxial growth in the N-type FET region. Alternatively, the source / drain feature 256P can be epitaxially grown before the source / drain feature 256N.

[0046] In the N-type field-effect transistor region, the source / drain features 256N may include silicon, silicon phosphide (SiP), silicon arsenide (SiAs), silicon carbide, silicon phosphocarbide (SiCP), silicon carbon arsenide (SiCAs), or other suitable semiconductor materials. The source / drain features 256N may be doped with dopants such as arsenic or phosphorus. In one example, the arsenic or phosphorus doped source / drain features 256N have a molar concentration of approximately 5×10 20 cm -3 to approximately 4×10 21 cm -3. When the source / drain features 256N include carbon, the atomic percentage of carbon may be in a range of approximately 10% to approximately 20%. In some embodiments, the source / drain features 256N include the same semiconductor material as the pedestal epitaxial layer 246N, but with a higher dopant concentration. For example, both the source / drain features 256N and the pedestal epitaxial layer 246N may include silicon, with the source / drain features 256N doped with phosphorus, while the pedestal epitaxial layer 246N is substantially free of dopants.

[0047] In the P-type field-effect transistor region, the source / drain feature 256P may include silicon germanium, silicon tin (SiSn), or other suitable semiconductor materials. The source / drain feature 256P may be doped with a dopant, such as germanium or boron. In one example, the source / drain feature 256P is doped with boron and includes silicon germanium boron (SiGeB), silicon tin boron (SiSnB), or other suitable semiconductor materials having a boron molar concentration of approximately 4×10 20 cm -3 to approximately 2×10 21 cm -3. When the source / drain feature 256P includes germanium, the atomic percentage of germanium may range from approximately 10% to approximately 60%. In some embodiments, the source / drain feature 256P includes the same semiconductor material as the pedestal epitaxial layer 246P, but with a higher dopant concentration. For example, both the source / drain feature 256P and the pedestal epitaxial layer 246P may comprise silicon germanium, with the source / drain feature 256P doped with boron and the pedestal epitaxial layer 246P being substantially free of dopants. If the channel layer 218 in the P-type field effect transistor region is laterally recessed in block 132, the source / drain feature 256P may have a lateral protrusion extending to a position directly beneath the gate spacer layer 238 (or even directly beneath the dummy gate stack 230), which is vertically stacked through the inner spacer feature 244, as shown in FIG. Furthermore, due to the additional protrusion, the volume of the source / drain feature 256P may be larger than the volume of the source / drain feature 256N.

[0048] FIG22 illustrates a schematic cross-sectional view taken along line segments CC and DD in FIG21 . In both the N-type field-effect transistor (NFET) region and the P-type field-effect transistor (PFET) region, the gate spacer layer 238 formed in block 120 is also deposited on the sidewalls of the fin structure 222N and the fin structure 222P in the source / drain regions, respectively. The portion of the gate spacer layer 238 in the source / drain regions is also referred to as a fin spacer layer 238'. After recessing the fin structure 222N and the fin structure 222P and epitaxially growing the pedestal epitaxial layer 246N and the pedestal epitaxial layer 246P, the fin spacer layer 238' is located on the sidewalls of the pedestal epitaxial layer 246N and the pedestal epitaxial layer 246P. The fin spacer layer 238' limits the epitaxial growth of the pedestal epitaxial layer 246N and the pedestal epitaxial layer 246P in the Y direction. Etching back fin structures 222N and fin structures 222P also etch back isolation features 224. Fin spacer layer 238′ protects the portion of isolation features 224 directly below it from etching loss, while other portions of isolation features 224 are etched back. The bottom surfaces of pedestal epitaxial layers 246N and 246P may be located above the recessed top surfaces of isolation features 224. The bottom surface of second semiconductor substrate 204 may also be located above the recessed top surfaces of isolation features 224.

[0049] Continuing with FIG. 22 , to clarify the spatial relationship, the channel layer 218 and the sacrificial layer 216 overlap in the channel region, as represented by the dashed box. In some embodiments, the top surface of the dielectric film 250 may be above the bottom surface of the bottommost sacrificial layer 216 and below the top surface of the bottommost sacrificial layer 216. In some embodiments, the bottom surface of the dielectric film 250 may be flush with the bottom surface of the bottommost sacrificial layer 216. In some embodiments, the thickness of the dielectric film 250 after epitaxial growth of the source / drain features 256N and the source / drain features 256P may range from approximately 0.5 nm to approximately 6.5 nm. In the N-type field effect transistor region, the top surface of the source / drain features 256N may be grown above the top surface of the fin structure 222N (e.g., the top surface of the topmost channel layer 218). In some embodiments, the top surface of the source / drain feature 256N extends above the top surface of the fin structure 222N by a distance Hn ranging from approximately 1 nm to approximately 11 nm. In some embodiments, the width Wn of the source / drain feature 256N measured in the Y direction may be in a range from approximately 33 nm to approximately 42 nm. In the P-type field-effect transistor region, the top surface of the source / drain feature 256P may be grown above the top surface of the fin structure 222P (e.g., the top surface of the topmost channel layer 218). In some embodiments, the top surface of the source / drain feature 256P extends above the top surface of the fin structure 222P by a distance Hp ranging from approximately 1 nm to approximately 11 nm. In some embodiments, the width Wp of the source / drain feature 256P measured in the Y direction may be in a range from approximately 33 nm to approximately 42 nm.

[0050] Referring to Figures 1 and 23, method 100 includes block 136, wherein the workpiece 200 is annealed in an annealing process 400. In some embodiments, annealing process 400 may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. Annealing process 400 may include a peak annealing temperature between approximately 900°C and approximately 1000°C. In these embodiments, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Annealing process 400 may achieve a desired electron contribution of a P-type dopant in a semiconductor body (e.g., silicon germanium or germanium). Annealing process 400 may create vacancies that facilitate movement of the P-type dopant from interstitial sites to alternative lattice sites and reduce damage or defects in the crystal lattice of the semiconductor body.

[0051] 1 and 24-26 , the method 100 includes block 138 , where subsequent processes are performed. The subsequent processes may include, for example, depositing a contact etch stop layer (CESL) 258 on the workpiece 200 (shown in FIG. 24 ), depositing an interlayer dielectric (ILD) layer 260 on the CESL 258 (shown in FIG. 24 ), removing the dummy gate stack 230 (shown in FIG. 25 ), selectively removing the sacrificial layer 216 in the channel region to release the channel layer 218 for use as a channel member (shown in FIG. 25 ), and forming a gate structure 266 on the channel region (shown in FIG. 26 ).

[0052] Continuing with FIG. 24 , a contact etch stop layer 258 is formed before forming an interlayer dielectric layer 260. In some examples, the contact etch stop layer 258 comprises silicon nitride, silicon oxynitride, and / or other materials known in the art. The contact etch stop layer 258 can be formed by atomic layer deposition, plasma-assisted chemical vapor deposition, and / or other suitable deposition processes. Then, the interlayer dielectric layer 260 is deposited on the contact etch stop layer 258. In some embodiments, the interlayer dielectric layer 260 includes a material such as tetraethoxysilane (TEOS) oxide, undoped silicate glass (USG), or doped silica oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). The interlayer dielectric layer 260 can be deposited using a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 260, the workpiece 200 can be annealed to improve the integrity of the interlayer dielectric layer 260. As shown in FIG. 24 , the contact etch stop layer 258 is disposed directly on the top surface of the source / drain feature 256. After depositing the contact etch stop layer 258 and the interlayer dielectric layer 260, the workpiece 200 can be planarized by a planarization process to expose the dummy gate stack 230. For example, the planarization process can include a chemical mechanical planarization process. After the chemical mechanical planarization process, the distance along the Z direction from the top surface of the dummy gate stack 230 to the top surface of the topmost channel layer 218 can be measured between 5 nm and 50 nm.

[0053] The exposure of the dummy gate stack 230 allows the dummy gate stack 230 to be removed and releases the channel layer 218, as shown in FIG. 25 . In some embodiments, the removal of the dummy gate stack 230 results in a gate trench 262 in the channel region. Removing the dummy gate stack 230 may include one or more etching processes that are selective to the material of the dummy gate stack 230. For example, the dummy gate stack 230 may be removed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 230. After removing the dummy gate stack 230, the sidewalls of the channel layer 218 and the sacrificial layer 216 in the channel region are exposed in the gate trench 262. After removing the dummy gate stack 230, the method 100 may include selectively removing the sacrificial layer 216 between the channel layer 218 in the channel region. Selectively removing the sacrificial layer 216 releases the channel layer 218 to form a channel member (also referenced as 218). Selectively removing the sacrificial layer 216 also leaves spaces 264 between the channel elements. The selective removal of the sacrificial layer 216 can be performed by selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Examples of selective wet etching processes may include etching with an ammonia-hydrogen peroxide mixture.

[0054] Referring to FIG. 26 , method 100 may include a subsequent operation to form a gate structure 266 surrounding each channel member. In some embodiments, gate structure 266 is formed within gate trench 262 and in space 264 left by removing sacrificial layer 216. In this regard, gate structure 266 surrounds each channel member. Gate structure 266 includes a gate dielectric layer 268 and a gate electrode layer 270 on gate dielectric layer 268. In some embodiments, although not explicitly shown in the figures, gate dielectric layer 268 includes an interfacial layer and a high-k gate dielectric layer. High-k dielectric materials, as used and described herein, include dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (~3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate (HfSiO), or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The high-k gate dielectric layer may include hafnium oxide. Alternatively, the high-k gate dielectric layer may include other high-k dielectric materials, such as titanium oxide, hafnium zirconium oxide (HfZrOx), tantalum oxide, hafnium silicon oxide (HfSiO4), zirconium oxide, zirconium silicon oxide (ZrSiO2), lanthanum oxide, aluminum oxide, zirconium oxide, yttrium oxide, strontium titanate (STO) (SrTiO3), barium titanate (BTO) (BaTiO3), barium zirconate (BZO) (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfLaO), and lanthanum silicon oxide (LaSiO). The high-k gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0055] The gate electrode layer 270 of the gate structure 266 may include a single layer or alternatively a multi-layer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the gate electrode layer 270 may include titanium nitride, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride, tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer 270 can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process can be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 266. The gate structure 266 includes a portion interposed between channel members in the channel region.

[0056] Continuing with FIG. 26 , when the operations of block 138 are completed, transistors 280 are substantially formed, specifically one or more N-type transistors (N-type FETs) 280N in the N-type FET region and one or more P-type transistors (P-type FETs) 280P in the P-type FET region. Transistor 280 includes channel members stacked vertically along the Z-direction. Each channel member is surrounded by a respective gate structure 266. The channel members extend along the X-direction or are sandwiched between two source / drain features 256. Beneath the source / drain features 256 are dielectric film 250 and pedestal epitaxial layer 246. The dielectric film 250 and pedestal epitaxial layer 246 exhibit high resistivity, thereby providing a high-resistance path from the source / drain features 256 to the substrate, thereby suppressing leakage current into the substrate. Specifically, in the N-type field effect transistor region, the channel component, the base epitaxial layer 246N, and the source / drain component 256N all carry the same (100) crystal structure as the semiconductor substrate 202; in the P-type field effect transistor region, the channel component, the base epitaxial layer 246P, and the source / drain component 256P all carry the same (110) crystal structure as the semiconductor substrate 204. The channel component with the (110) crystal structure provides higher carrier mobility for the P-type transistor, while the source / drain component 256P with the (110) crystal structure alleviates the loss of compressive strain caused by the dielectric film 250 inserted under the source / drain component 256P. Therefore, the AC and DC performance of the transistors in the N-type field effect transistor region and the P-type field effect transistor region are optimized without sacrificing the DC performance of the P-type transistor in the P-type field effect transistor region.

[0057] In an exemplary aspect, the present disclosure is directed to a method for forming a semiconductor device. The method for forming a semiconductor device includes: bonding a first semiconductor substrate to a second semiconductor substrate, the first semiconductor substrate having a (110) orientation, and the second semiconductor substrate having a (100) orientation; forming a stack on the first semiconductor substrate, the stack including a plurality of channel layers and a plurality of sacrificial layers arranged alternately; patterning the stack to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack on the channel region of the fin-shaped structure; depositing a gate spacer layer on the dummy gate stack; and etching the source / drain region. The invention relates to a method for forming a source / drain trench to expose the sidewalls of the channel layer and the sacrificial layer; partially etching the sacrificial layer to form a plurality of inner spacer grooves; forming a plurality of inner spacer components in the inner spacer grooves; forming a dielectric film in the source / drain trench; epitaxially growing an epitaxial component on the dielectric film, the epitaxial component contacting the channel layer, the epitaxial component having a (110) direction; after forming the epitaxial component, removing the dummy gate stack; releasing the channel layer in the channel region to serve as a plurality of channel components; and forming a gate structure surrounding each of the channel components.

[0058] In some embodiments, the method of forming a semiconductor device further includes depositing a pedestal epitaxial layer in the source / drain trench before depositing the dielectric film. In some embodiments, the pedestal epitaxial layer does not contain dopants. In some embodiments, the pedestal epitaxial layer has a (110) orientation. In some embodiments, the channel layer in the stack has a (110) orientation. In some embodiments, the sacrificial layer in the stack has a (110) orientation. In some embodiments, the epitaxial component is doped with a P-type dopant. In some embodiments, the epitaxial component includes silicon germanium. In some embodiments, forming the dielectric film includes: depositing a dielectric layer on the bottom surface and sidewall surfaces of the source / drain trench; and removing the dielectric layer from the sidewall surfaces of the source / drain trench. In some embodiments, the fin structure includes a first semiconductor substrate and a top portion of a second semiconductor substrate.

[0059] In another exemplary aspect, the present disclosure is directed to a method for forming a semiconductor device. The method includes: forming a hybrid substrate having a first region and a second region, the first region having a top surface of a (100) crystal plane and the second region having a top surface of a (110) crystal plane; patterning the second region to form a fin-shaped base; forming a plurality of channel components on the fin-shaped base; forming a plurality of inner spacer components alternately arranged with the channel components; depositing a dielectric material layer on the inner spacer components and on the top surface of the fin-shaped base; etching back the dielectric material layer to form a dielectric film; depositing an epitaxial component on the dielectric film, the epitaxial component contacting the channel component, the epitaxial component having a top surface of a (110) crystal plane; and forming a gate structure surrounding each of the channel components.

[0060] In some embodiments, the method for forming a semiconductor device further includes depositing a base epitaxial layer on the top surface of the fin-shaped base before depositing the dielectric material layer, the base epitaxial layer having a top surface with a (110) crystal plane. In some embodiments, forming a hybrid substrate includes: bonding a first semiconductor substrate to a second semiconductor substrate, the first semiconductor substrate having a top surface with a (110) crystal plane, and the second semiconductor substrate having a top surface with a (100) crystal plane; removing the first semiconductor substrate from the first region; thickening the second semiconductor substrate in the first region; and planarizing the first semiconductor substrate and the second semiconductor substrate. In some embodiments, the dielectric film is in physical contact with the bottommost of the inner spacer components. In some embodiments, the method for forming a semiconductor device further includes laterally etching back the channel component after etching back the dielectric material layer. In some embodiments, the epitaxial component includes a lateral protrusion vertically stacked between two adjacent inner spacer components.

[0061] In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes: a fin-shaped base protruding from a semiconductor substrate, the top surface of the fin-shaped base being a (110) crystal plane; a plurality of channel members disposed on the top surface of the fin-shaped base; a plurality of inner spacer components interlaced with the channel members; a gate structure surrounding each of the channel members; a source / drain component in contact with the channel members and the inner spacer components, the top surface of the source / drain component being a (110) crystal plane; and a dielectric film directly below the source / drain component and above the top surface of the fin-shaped base.

[0062] In some embodiments, the semiconductor device further includes an undoped epitaxial layer directly below the dielectric film and above the top surface of the fin base, wherein the top surface of the undoped epitaxial layer is a (110) crystal plane. In some embodiments, the fin base includes a semiconductor layer disposed on top of a semiconductor substrate, wherein the top of the semiconductor substrate has a top surface with a (110) crystal plane. In some embodiments, the source / drain component is doped with a P-type dopant.

[0063] The above summarizes the features of several embodiments to help those skilled in the art better understand the concepts of the present disclosure. Those skilled in the art will readily appreciate that other processes and structures can be easily designed or modified based on the present disclosure to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that these and other similarly effective structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations are possible without departing from the spirit and scope of the present disclosure.

[0064] 100: Method 102: Box 104: Box 106: Box 108: Box 110: Box 112: Box 114: Box 116: Box 118: Box 120: Box 122: Box 124: Box 126: Box 128: Box 130: Box 132: Box 134: Box 136: Box 138: Box 200:Workpiece 202: first semiconductor substrate 204: second semiconductor substrate 205: Mixed base 206: Patterned Mask 208: District 1 210: Second District 212: Groove 212B: Fin base 214: Stack 216: Sacrificial layer 218: Channel layer 222: Fin-like structure 222N: Fin-shaped structure 222P: Fin-shaped structure 224: Isolation components 226: dummy dielectric layer 228: dummy electrode layer 230:Dummy Gate Stack 232: Top gate hard mask layer 234: Silicon oxide layer 236: Silicon nitride layer 238: Gate spacer layer 238': fin spacer layer 240: Source / Drain Trench 242: Inner spacer groove 244: Inner spacer component 246: base epitaxial layer 246N: base epitaxial layer 246P: base epitaxial layer 248: Dielectric Materials 250: Dielectric film 256: Source / Drain Components 256N: Source / Drain components 256P: Source / Drain components 258: Touch etch stop layer 260: interlayer dielectric layer 262: Gate trench 264: Space 266: Gate structure 268: Gate dielectric layer 270: Gate electrode layer 280: Transistor 280N: Transistor 280P: Transistor 300: Cleaning process 400: Annealing process AA: Line segment BB: Line segment CC: Line segment DD: Line segment Hn: Spacing Hp: Spacing Wn: width Wp: width

Claims

1. A method for forming a semiconductor device, comprising: A first semiconductor substrate is bonded to a second semiconductor substrate, the first semiconductor substrate having a (110) orientation and the second semiconductor substrate having a (100) orientation; a stack is formed on the first semiconductor substrate, the stack including a plurality of channel layers and a plurality of sacrificial layers alternately disposed; the stack is patterned to form a fin structure, the fin structure including a channel region and a source / drain region; a dummy gate stack is formed on the channel region of the fin structure; a gate spacer layer is deposited on the dummy gate stack; the source / drain region is etched to form a source / drain trench, exposing the sidewalls of the channel layers and the sacrificial layers; the sacrificial layers are partially etched to form a plurality of inner spacer grooves; a plurality of inner spacer components are formed in the inner spacer grooves; a dielectric film is formed in the source / drain trench; An epitaxial component is grown on the dielectric film, the epitaxial component is in contact with the channel layers, and the epitaxial component has a (110) orientation; after the epitaxial component is formed, the dummy gate stack is removed; the channel layers are released in the channel region as a plurality of channel members; and a gate structure is formed surrounding each of the channel members.

2. The method of forming the semiconductor device as claimed in claim 1 further includes: Before depositing the dielectric film, a substrate epitaxial layer is deposited in the source / drain trench, wherein the substrate epitaxial layer is free of dopants and wherein the substrate epitaxial layer has a (110) orientation.

3. A method of forming a semiconductor device as claimed in claim 1, wherein the channel layers in the stack have a (110) orientation.

4. A method for forming a semiconductor device as claimed in claim 1, wherein the epitaxial component is doped with a P-type dopant.

5. A method for forming a semiconductor device according to any one of claims 1 to 4, wherein forming the dielectric film comprises: A dielectric layer is deposited on the bottom and sidewall surfaces of the source / drain trench; And the dielectric layer is removed from the sidewall surface of the source / drain trench.

6. A method of forming a semiconductor device as claimed in claim 1, wherein the fin structure includes the top of the first semiconductor substrate and the second semiconductor substrate.

7. A method for forming a semiconductor device, comprising: A hybrid substrate is formed having a first region and a second region, the first region having a top surface with a (100) crystal plane and the second region having a top surface with a (110) crystal plane; the second region is patterned to form a fin-shaped substrate; a plurality of channel members are formed on the fin-shaped substrate; a plurality of inner spacer members are formed and interleaved with the channel members; a dielectric material layer is deposited on the inner spacer members and the top surface of the fin-shaped substrate; the dielectric material layer is etched back to form a dielectric film; an epitaxial member is deposited on the dielectric film, the epitaxial member being in contact with the channel members, the epitaxial member having a top surface with a (110) crystal plane; and a gate structure is formed surrounding each of the channel members.

8. The method of forming the semiconductor device as described in claim 7 further includes: Before depositing the dielectric material layer, a substrate epitaxial layer is deposited on the top surface of the fin substrate, the substrate epitaxial layer having a (110) crystal plane on the top surface.

9. A method for forming a semiconductor device as claimed in claim 7, wherein forming the hybrid substrate comprises: A first semiconductor substrate is bonded to a second semiconductor substrate, the first semiconductor substrate having a top surface of a (110) crystal plane and the second semiconductor substrate having a top surface of a (100) crystal plane; the first semiconductor substrate is removed from the first region; the second semiconductor substrate in the first region is thickened; And planarize the first semiconductor substrate and the second semiconductor substrate.

10. A method of forming a semiconductor device as claimed in claim 7, wherein the dielectric film is in physical contact with the bottommost of the inner spacer components.

11. The method of forming a semiconductor device as described in claim 7 further includes: After the dielectric material layer is etched back, the channel components are etched laterally.

12. A method of forming a semiconductor device as claimed in claim 11, wherein the epitaxial member includes a lateral protrusion that is vertically stacked between adjacent inner spacer members.

13. A semiconductor device, comprising: A fin-shaped base protrudes from a semiconductor substrate, and the top surface of the fin-shaped base is a (110) crystal plane; A plurality of channel members are disposed on the top surface of the finned base; a plurality of inner spacer members are disposed alternately with the channel members; a gate structure surrounds each of the channel members; a source / drain member is in contact with the channel members and the inner spacer members, the top surface of the source / drain member being a (110) crystal plane; and a dielectric film is disposed directly below the source / drain member and above the top surface of the finned base, wherein the top surface of the dielectric film is located above the top surface of the semiconductor substrate.

14. The semiconductor device of claim 13 further includes: An undoped epitaxial layer is located directly below the dielectric film and above the top surface of the fin-shaped substrate. The top surface of the undoped epitaxial layer is a (110) crystal plane.

15. The semiconductor device of claim 13, wherein the fin-shaped base includes a semiconductor layer disposed on top of the semiconductor substrate, wherein the top of the semiconductor substrate has a top surface of a (110) crystal plane.

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