Image receiving device and image receiving method

Abstract

The image receiving device includes a first-in-first-out (FIFO) memory, a processor circuit, and a FIFO multiplexer circuit. The FIFO memory includes a plurality of FIFO buffers. The processor circuit sets a plurality of first pipeline parameters based on device information of a plurality of image sensors and the data capacity of the plurality of FIFO buffers. The FIFO multiplexer circuit configures the correspondence between the plurality of image sensors and the plurality of FIFO buffers according to the plurality of first pipeline parameters, so that each of the plurality of image sensors transmits image data to a corresponding buffer in the plurality of FIFO buffers.

Description

[Technical Field]

[0001] This case relates to an image receiving apparatus, and in particular to an image receiving apparatus and image receiving method with adaptable hardware resources. [Previous Technology]

[0002] In the prior art, image processing systems allocate multiple buffers and / or multiple memory channels to multiple image connection interfaces in a fixed order. However, if the buffers and / or memory channels allocated to a specific image connection interface do not meet the specifications required by the image sensor connected to that specific image connection interface, the image data generated by the image sensor will not meet expectations. For example, if the image sensor has a high image resolution, but the data capacity of the buffer allocated to the image sensor is insufficient to temporarily store the image data generated by the image sensor; or, the image sensor is shooting in a special scene mode, but the memory channel allocated to the image sensor does not support that special scene mode. All of these situations will cause the image processing system to fail to meet the shooting requirements of the image sensor, resulting in reduced system versatility. [Summary of the Invention]

[0003] In some embodiments, one of the objectives of this invention is to provide an image receiving apparatus and its image receiving method with adaptable hardware resource configuration to improve the shortcomings of the prior art.

[0004] In some embodiments, the image receiving device includes a first-in-first-out (FIFO) memory, a processor circuit, and a FIFO multiplexer circuit. The FIFO memory includes a plurality of FIFO buffers. The processor circuit sets a plurality of first pipeline parameters based on device information of a plurality of image sensors and the data capacity of the plurality of FIFO buffers. The FIFO multiplexer circuit configures the correspondence between the plurality of image sensors and the plurality of FIFO buffers based on the plurality of first pipeline parameters, so that each of the plurality of image sensors transmits image data to a corresponding one of the plurality of FIFO buffers.

[0005] In some embodiments, the image receiving apparatus includes the following operations: setting a plurality of first pipeline parameters by a processor circuit based on device information of a plurality of image sensors and data capacity of a plurality of first-in-first-out buffers; and configuring the correspondence between the plurality of image sensors and the plurality of first-in-first-out buffers by a first-in-first-out multiplexer circuit based on the plurality of first pipeline parameters, so that each of the plurality of image sensors transmits image data to a corresponding one of the plurality of first-in-first-out buffers.

[0006] Regarding the features, implementation and effects of this case, the preferred embodiments are described in detail below with reference to the drawings.

Implementation Method

[0008] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this document. Similarly, this document is not limited to the various embodiments shown in this specification.

[0009] The terms "coupled" or "connected" as used herein can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or two or more components operating or acting on each other. As used herein, the term "circuit" can be a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0010] FIG1 is a schematic diagram of an image processing system 100 according to some embodiments of the present invention. The image processing system 100 includes an image receiving device 110, an image processing circuit 120, and a memory 130. In some embodiments, a plurality of image sensors 101-104 are sensing devices that can convert optical signals into electrical signals (e.g., a plurality of image data D1-D4). The image receiving device 110 is coupled to the plurality of image sensors 101-104 to receive the plurality of image data D1-D4. In detail, the image receiving device 110 can adaptively allocate hardware buffers in the image receiving device 110 to the plurality of image sensors 101-104 according to the device requirements of the plurality of image sensors 101-104, so as to make more efficient use of limited hardware resources. The image receiving device 110 can temporarily store the plurality of image data D1-D4 in its internal buffer and transfer the plurality of image data D1-D4 to the memory 130. Thus, the image processing circuit 120 can retrieve the image data D1 to D4 from the memory 130 for subsequent image processing (e.g., high dynamic range image processing as described later). In some embodiments, the memory 130 may be, but is not limited to, dynamic random access memory.

[0011] In some embodiments, the image receiving device 110 includes a register circuit 111, a first-in-first-out (FIFO) multiplexer circuit 112, a FIFO memory 113, a channel multiplexer circuit 114, a direct memory access controller circuit 115, and a processor circuit 116. In some embodiments, after the image processing system 100 is powered on, the processor circuit 116 can initialize and configure a plurality of image sensors 101-104 via an inter-integrated circuit (I2C) bus and obtain device information DI for the plurality of image sensors 101-104. In some embodiments, the device information DI can indicate the image resolution, scene mode, etc. of each of the plurality of image sensors 101-104. The processor circuit 116 can perform multiple operations as shown in Figures 3 and 4 below based on the device information DI and the parameters C1 and C2 in the temporary storage circuit 111, thereby setting multiple pipeline parameters P11 to P14 and multiple pipeline parameters P21 to P24. In some embodiments, multiple image sensors 101 to 104 can transmit image data D1 to D4 to the first-in-first-out multiplexer circuit 112 via the mobile industry processor interface (MIPI).

[0012] The first-in-first-out (FIFO) memory 113 includes multiple FIFO buffers (e.g., multiple FIFO buffers 113A-113D in FIG. 2), which can be used to temporarily store multiple image data D1-D4. In some embodiments, parameter C1 in the register circuit 111 can be used to indicate the data capacity and priority order of the multiple FIFO buffers 113A-113D, so that the processor circuit 116 can set multiple pipeline parameters P11-P14 according to the data capacity, priority order, and the aforementioned device information DI. The FIFO multiplexer circuit 112 can configure the correspondence between the multiple image sensors 101-104 and the multiple FIFO buffers 113A-113D according to the multiple pipeline parameters P11-P14. For example, based on pipeline parameter P11, the FIFO multiplexer circuit 112 can assign the FIFO buffer 113A to the image sensor 101, so that the image sensor 101 can transmit image data D1 to the FIFO buffer 113A via the FIFO multiplexer circuit 112. Similarly, the correspondence between the multiple pipeline parameters P12-P14 and the multiple FIFO buffers 113B-113D should be understood. In some embodiments, the FIFO memory 113 may be, but is not limited to, asynchronous FIFO memory.

[0013] Similarly, the direct memory access controller circuit 115 includes multiple channel groups (e.g., multiple channel groups CG1 to CG4 in FIG. 2), and each of these channel groups includes multiple access channels (e.g., channels 0 to 2 in FIG. 2). In some embodiments, parameter C2 in the register circuit 111 can be used to indicate the priority order of the multiple channel groups and the priority order of the multiple access channels of each channel group, so that the processor circuit 116 can set multiple pipeline parameters P21 to P24 according to the priority order of the above two and the device information DI. The channel multiplexer circuit 114 can configure the correspondence between multiple first-in-first-out buffers 113A to 113D and multiple access channels according to the multiple pipeline parameters P21 to P24. For example, according to pipeline parameter P21, channel multiplexer circuit 114 can assign channels 0 and 1 in channel group CG1 to FIFO buffer 113D, so that FIFO buffer 113D can transfer image data D4 to memory 130 and / or image processing circuit 120 via channels 0 and 1 in channel group CG1. Similarly, the correspondence between multiple pipeline parameters P22-P24 and multiple channel groups CG2-CG4 should be understood. In some embodiments, each of FIFO multiplexer circuit 112 and channel multiplexer circuit 114 can connect the corresponding sensor and the corresponding access channel by establishing virtual channels, but this is not limited thereto.

[0014] Figure 2 is an operational schematic diagram of the FIFO multiplexer circuit 112 and channel multiplexer circuit 114 in Figure 1, drawn according to some embodiments of the present invention. As previously described, the FIFO memory 113 includes a plurality of FIFO buffers 113A to 113D, and the direct memory access controller circuit 115 includes a plurality of channel groups CG1 to CG4, each of which includes a plurality of channels (i.e., channels 0 to 2 in the figure). Through the FIFO multiplexer circuit 112, each of the plurality of FIFO buffers 113A to 113D is assigned to a corresponding one of the plurality of image sensors 101 to 104 to receive a corresponding one of the plurality of image data D1 to D4. Similarly, through the channel multiplexer circuit 114, each of the multiple channel groups CG1 to CG4 is assigned to a corresponding one of the multiple first-in-first-out buffers 113A to 113D to transfer a corresponding one of the multiple image data D1 to D4 to the memory 130 and / or the image processing circuit 120. Detailed operation of FIG2 will be explained with reference to FIG3 and FIG4.

[0015] Figure 3 is an operation flowchart of the processor circuit 116 and the first-in-first-out multiplexer circuit 112 of Figure 1, which are configured to allocate first-in-first-out buffers according to some embodiments of the present invention. In some embodiments, the processor circuit 116 may set multiple pipeline parameters P11 to P14 by executing multiple processes of Figure 3, so that the first-in-first-out multiplexer circuit 112 can configure the correspondence between multiple image sensors 101 to 104 and multiple first-in-first-out buffers 113A to 113D according to the multiple pipeline parameters P11 to P14.

[0016] In operation S310, an image resolution corresponding to an image sensor is obtained based on device information, and it is confirmed whether the image resolution is greater than a predetermined resolution. If yes, operation S320 is executed; if no, operation S330 is executed. In operation S320, according to the priority order of the plurality of first-in-first-out (FIFO) buffers, the buffer with the highest priority is selected from at least one buffer that has not yet been allocated among the plurality of FIFO buffers, and the selected buffer is allocated to the corresponding image sensor, wherein each of the at least one buffer has a first data capacity. In operation S330, according to the priority order of the plurality of FIFO buffers, the buffer with the highest priority is selected from at least one buffer that has not yet been allocated among the plurality of FIFO buffers, and the selected buffer is allocated to the corresponding image sensor, wherein each of the at least one buffer has a second data capacity, and the first data capacity is higher than the second data capacity. In operation S340, the corresponding first pipeline parameters are set according to the allocated FIFO buffer.

[0017] For example, the processor circuit 116 can determine, based on the device information DI of the image sensor 101, that the image resolution of the image sensor 101 is greater than a predetermined resolution (e.g., 5M, i.e., 2560×1920). Under this condition, the processor circuit 116 can select a buffer with a first data capacity (which is at least sufficient to temporarily store image data greater than or equal to the predetermined resolution) from a plurality of first-in-first-out buffers 113A to 113D according to parameter C1, and allocate this buffer to the image sensor 101. For example, assuming that the plurality of first-in-first-out buffers 113A to 113D have not yet been allocated, the data capacity of each of the plurality of first-in-first-out buffers 113A to 113B is 4k bytes (which may be the aforementioned first data capacity, but this invention is not limited to this), and the data capacity of each of the plurality of first-in-first-out buffers 113C to 113D is 2k bytes (which may be the aforementioned second data capacity, but this invention is not limited to this). Since the image resolution of the image sensor 101 is greater than a predetermined resolution, the processor circuit 116 selects buffers 113A and 113B with larger first data capacity from a plurality of first-in-first-out buffers 113A to 113D according to parameter C1, and selects the first-in-first-out buffer 113A with the highest priority from the two buffers according to priority order. In this way, the processor circuit 116 can set the pipeline parameter P11 according to the above allocation result, so that the first-in-first-out multiplexer circuit 112 can allocate the first-in-first-out buffer 113A to the image sensor 101 according to the pipeline parameter P11.

[0018] In some embodiments, parameter C1 can be used to indicate the priority order of the plurality of first-in-first-out (FIFO) buffers 113A to 113D. For example, each of the plurality of FIFO buffers 113A to 113D can be configured with a sequence number. The larger the value of the sequence number, the lower its priority level. In one example, the sequence numbers of the plurality of FIFO buffers 113A to 113D can be represented as shown in the following table: First-in-first-out buffer Sequence number 113A 0 113B 1 113C 2 113D 3 Therefore, in the above example, the first-in-first-out buffer with the first data capacity includes first-in-first-out buffer 113A and first-in-first-out buffer 113B, but first-in-first-out buffer 113A has a higher priority, so the processor circuit 116 preferentially allocates first-in-first-out buffer 113A to the image sensor 101.

[0019] Similarly, the processor circuit 116 can confirm, based on the device information DI of the image sensor 102, that the image resolution of the image sensor 102 is not greater than a predetermined resolution. Under this condition, the processor circuit 116 can select a buffer with a second data capacity from a plurality of first-in-first-out buffers 113A to 113D according to parameter C1, and allocate this buffer to the image sensor 102. For example, since the image resolution of the image sensor 102 is not greater than the predetermined resolution, the processor circuit 116 selects first-in-first-out buffers 113C and 113D with smaller second data capacities from a plurality of first-in-first-out buffers 113A to 113D according to parameter C1, and selects the first-in-first-out buffer 113C with the highest priority from the two buffers according to priority order. Thus, the processor circuit 116 can set the pipeline parameter P13 according to the above allocation result, so that the FIFO multiplexer circuit 112 can allocate the FIFO buffer 113C to the image sensor 102 according to the pipeline parameter P13. Similarly, the processor circuit 116 can set all the pipeline parameters P11 to P14, so that the FIFO multiplexer circuit 112 can configure the correspondence between the multiple image sensors 101 to 104 and the multiple FIFO buffers 113A to 113D according to the multiple pipeline parameters P11 to P14.

[0020] Figure 4 is an operation flowchart of the processor circuit 116 and the channel multiplexer circuit 114 of Figure 1, which are configured to allocate channel groups according to some embodiments of the present invention. In some embodiments, the processor circuit 116 may set multiple pipeline parameters P21 to P24 by performing multiple operations of Figure 4, so that the channel multiplexer circuit 114 may configure the correspondence between multiple access channels in multiple channel groups CG1 to CG4 and multiple first-in-first-out buffers 113A to 113D according to the multiple pipeline parameters P21 to P24.

[0021] In operation S410, a scene mode corresponding to an image sensor is obtained based on device information, and it is confirmed whether the scene mode is a predetermined mode. If yes, operation S420 is executed; if no, operation S430 is executed. In operation S420, it is confirmed whether the image processing corresponding to the predetermined mode uses three frames. If yes, operation S440 is executed; if no, operation S450 is executed. In operation S430, a corresponding channel group with the highest priority is selected from at least one unassigned group among the plurality of channel groups, and a specific channel with the highest priority is selected from at least one unassigned channel among the plurality of access channels of the corresponding group. In operation S440, a corresponding channel group with the lowest priority is selected from the plurality of channel groups. In operation S450, a corresponding channel group with the second lowest priority is selected from the plurality of channel groups. In operation S460, the corresponding second pipeline parameters are set according to the selected corresponding channel group and / or specific channel.

[0022] In some embodiments, the predetermined mode is a real-time high dynamic range (HDR) mode, but this invention is not limited thereto. For example, the processor circuit 116 can confirm that the scene mode of the image sensor 101 is not a real-time HDR mode based on the device information DI of the image sensor 101. Under this condition, the processor circuit 116 can select the channel group with the highest priority from at least one unassigned channel group among multiple channel groups CG1 to CG4 according to parameter C2, select the channel with the highest priority from at least one unassigned channel in the channel group, and set the channel with the highest priority as the specific channel. For example, assuming that none of the multiple channel groups CG1 to CG4 have been assigned, since the scene mode of the image sensor 101 is not a real-time HDR mode, the processor circuit 116 can select the channel group CG4 with the highest priority from the multiple channel groups CG1 to CG4 according to parameter C2, and select the channel 1 with the highest priority from the unassigned channels 0 and 1 in the channel group CG4 as the specific channel (i.e., operation S430). In this way, the processor circuit 116 can set the pipeline parameter P24 according to the above configuration result (i.e., operation S460), so that the channel multiplexer circuit 114 can assign channel 1 in the channel group CG4 to the first-in-first-out buffer 113A (which is assigned to the image sensor 101) according to the pipeline parameter P24.

[0023] In some embodiments, parameter C2 can be used to indicate the priority order of multiple channel groups CG1 to CG4 and the priority order of multiple channels 0 to 2 within the multiple channel groups CG1 to CG4. For example, each of the multiple channel groups CG1 to CG4 can be configured with a first priority number. The larger the value of the first priority number, the lower the priority level of the corresponding channel group. Similarly, each of the multiple channels 0 to 2 can be configured with a second priority number. The larger the value of the second priority number, the lower the priority level of the corresponding access channel. In one example, the aforementioned multiple first priority numbers and multiple second priority numbers can be represented as shown in the following table: Channel Group First sequence number aisle Second sequence number CG1 2 0 14 1 13 CG2 3 0 16 1 15 2 15 CG3 1 0 12 1 11 2 10 CG4 0 0 1 1 0

[0024] In some embodiments, if the priority of a channel is higher (i.e., the second sequence number is lower), the priority of the channel group to which the channel belongs is higher (i.e., the first sequence number is lower). In the above example, the processor circuit 116 selects the channel group CG4 with the highest priority from multiple channel groups CG1 to CG4, selects the channel 1 with the highest priority from the channel group CG4, and allocates the channel 1 to the first-in-first-out buffer 113A assigned to the image sensor 101 via the channel multiplexer circuit 114. In some embodiments, after the image processing system 100 is powered on, the processor circuit 116 can initialize and configure the first-in-first-out memory 113 and the direct memory access controller 115 during the initialization of multiple image sensors 101-104, thereby obtaining information (e.g., data capacity and priority order) of each first-in-first-out buffer via the first-in-first-out multiplexer circuit 112 to set parameter C1, and obtaining information (e.g., priority order of the channel group and priority order of its internal access channels) of each channel group via the channel multiplexer circuit 114 to set parameter C2.

[0025] In some embodiments, the image processing corresponding to the real-time HDR mode typically involves multiple frames (e.g., frames with short exposures and frames with long exposures). The direct memory access controller circuit 115 can use a pre-set access channel to directly transmit the aforementioned frames to the image processing circuit 120 without passing through the memory 130 (as shown in the signal path SP of FIG1). Therefore, in some embodiments, the priority of multiple channel groups CG1 to CG4 can be set by the aforementioned first sequence number, and the priority of multiple channel groups CG1 to CG2 supporting the real-time HDR mode can be set as the last two priorities (i.e., the aforementioned lowest or second lowest priority), thereby pre-reserving these channel groups CG1 to CG2. Further, the number of channels in the multiple channel groups CG1 to CG2 is also set according to the number of frames involved in the image processing corresponding to the real-time HDR mode. For example, if the number of frames involved in the image processing corresponding to the real-time HDR mode is 2, the channel group CG1 with two channels can be assigned to the corresponding sensor operating in the real-time HDR mode. Alternatively, if the image processing for the real-time HDR mode involves 3 frames, a channel group CG2 with 3 channels can be assigned to the corresponding sensor operating in that real-time HDR mode. In this example, a channel group CG1 with 2 channels is set to have the second lowest priority, and a channel group CG2 with 3 channels is set to have the lowest priority, but this is not a limitation. In different embodiments, a channel group CG1 with 2 channels may also be set to have the lowest priority, and a channel group CG2 with 3 channels may also be set to have the second lowest priority. In some embodiments, the processor circuit 116 can determine whether the scene mode is a real-time HDR mode based on device information DI, and can determine whether the real-time HDR mode is an HDR mode using three frames based on device information DI.

[0026] For example, the processor circuit 116 confirms that the scene mode of the image sensor 103 is real-time HDR mode based on the device information DI of the image sensor 101, and confirms that the image processing corresponding to the real-time HDR mode does not use three frames. Under this condition, the processor circuit 116 can select the channel group CG1 with the second lowest priority from at least one of the multiple channel groups CG1 to CG4 that has not yet been assigned according to parameter C2 (i.e., operation S450), and set the pipeline parameter P21 accordingly (i.e., operation S460). Thus, as shown in FIG2, the channel multiplexer circuit 114 can assign channel 0 and channel 1 of the channel group CG1 with the lowest priority to the first-in-first-out buffer 113A according to the pipeline parameter P21, so as to transmit multiple frames respectively.

[0027] Similarly, if the processor circuit 116 confirms that the scene mode of the image sensor 103 is real-time HDR mode based on the device information DI of the image sensor 101, and confirms that the image processing corresponding to the real-time HDR mode uses three frames, then the processor circuit 116 can select the channel group CG2 with the lowest priority from at least one of the multiple channel groups CG1 to CG4 that has not yet been assigned according to parameter C2 (i.e., operation S440), and set the pipeline parameter P22 accordingly (i.e., operation S460). In this way, the channel multiplexer circuit 114 can allocate channels 0 to 2 of the channel group CG2 with the lowest priority to the first-in-first-out buffer 113B according to the pipeline parameter P22, so as to transmit multiple frames respectively.

[0028] Similarly, the above-described operations of allocating multiple first-in-first-out (FIFO) buffers 113A-113D and multiple channel groups CG1-CG4 should be understood. Specifically, taking the example of FIG2, if the image resolution of the image sensor 101 is greater than a predetermined resolution, the processor circuit 116 can select the FIFO buffer 113A with the highest priority from among the multiple FIFO buffers 113A and 113B with a first data capacity from the multiple FIFO buffers 113A-113D, and allocate the FIFO buffer 113A to the image sensor 101 via the FIFO multiplexer circuit 112. Next, since the scene mode of the image sensor 101 is not a predetermined mode (e.g., a real-time HDR mode), the processor circuit 116 can select the channel group CG4 with the highest priority from among the multiple channel groups CG1-CG4, and allocate the channel 1 with the highest priority in the channel group CG4 to the FIFO buffer 113A via the channel multiplexer circuit 114.

[0029] Since the image resolution of the image sensor 102 is less than the predetermined resolution, the processor circuit 116 can select the first-in-first-out buffer 113C with the highest priority from the multiple first-in-first-out buffers 113C and 113D with the second data capacity among the multiple first-in-first-out buffers 113A to 113D, and allocate the first-in-first-out buffer 113C to the image sensor 102 via the first-in-first-out multiplexer circuit 112. Next, since the scene mode of the image sensor 102 is not the predetermined mode, the processor circuit 116 can select the channel group CG4 with the highest priority from the multiple channel groups CG1 to CG4, and allocate the second-highest priority channel 0 (the highest priority channel 1 has been allocated) in the channel group CG4 to the first-in-first-out buffer 113C via the channel multiplexer circuit 114.

[0030] Since the image resolution of the image sensor 103 is less than a predetermined resolution, the processor circuit 116 can select the unallocated first-in-first-out buffer 113D from the multiple first-in-first-out buffers 113C and 113D with a second data capacity among the multiple first-in-first-out buffers 113A to 113D, and allocate the first-in-first-out buffer 113D to the image sensor 103 via the first-in-first-out multiplexer circuit 112. Next, since the scene mode of the image sensor 103 is a predetermined mode and its image processing does not use three frames, the processor circuit 116 can select the channel group CG1 with the second lowest priority from the multiple channel groups CG1 to CG4, and allocate multiple channels 0 and 1 of the channel group CG1 to the first-in-first-out buffer 113D via the channel multiplexer circuit 114.

[0031] Since the image resolution of the image sensor 104 is greater than the predetermined resolution, the processor circuit 116 can select the unallocated first-in-first-out buffer 113A from the plurality of first-in-first-out buffers 113A and 113B with a first data capacity among the plurality of first-in-first-out buffers 113A to 113D, and allocate the first-in-first-out buffer 113A to the image sensor 104 via the first-in-first-out multiplexer circuit 112. Next, since the scene mode of the image sensor 104 is not the predetermined mode, the processor circuit 116 can select channel group CG3 from the remaining plurality of channel groups CG2 to CG3 (since all channels in the channel group CG4 with the highest priority have been allocated), and allocate the channel 2 with the highest priority in channel group CG3 to the first-in-first-out buffer 113B via the channel multiplexer circuit 114.

[0032] In other examples, if the scene mode of the image sensor 104 is a predetermined mode and its image processing uses three frames, the processor circuit 116 can select the channel group CG2 with the lowest priority from multiple channel groups CG1 to CG4, and allocate multiple channels 0 to 2 in the channel group CG3 to the first-in-first-out buffer 113B via the channel multiplexer circuit 114.

[0033] In some embodiments, the multiple operations of Figures 3 and 4 above can be implemented via software or a driver, and the processor circuit 116 can execute the multiple operations of Figures 3 and 4 above by executing the instruction set of the software or the driver. On the other hand, the aforementioned settings for the predetermined mode, number of sensors, number of channels, and predetermined resolution are merely examples, and this application is not limited thereto.

[0034] In some related technologies, the processor circuit allocates the first-in-first-out (FIFO) buffer and the direct memory access controller (DMA) channel to the corresponding image sensor in a fixed order. For example, the first FIFO buffer is always assigned to the first image sensor, and the first channel (or the first group of channels) of the DMA is always assigned to the first FIFO buffer. This fixed configuration may result in some image sensors using buffers with insufficient specifications (e.g., a high-resolution image sensor is assigned to a low-data-capacity buffer, or an image sensor using HDR mode is assigned to a DMA channel that does not support HDR mode), thus failing to meet the requirements of the shooting scenario. Compared to the above-mentioned technologies, in some embodiments of this case, through the multiple operations shown in Figures 3 and 4, the processor circuit 116 can adaptively configure the correspondence between the multiple first-in-first-out buffers 113A-113D and the multiple image sensors 101-104, as well as the correspondence between the multiple first-in-first-out buffers 113A-113D and the multiple channel groups CG1-CG4, based on the device information DI, the data capacity of the multiple first-in-first-out buffers 113A-113D (indicated by parameter C1), the priority order of the multiple channel groups CG1-CG4, and the priority order of the multiple channels 0-2 (indicated by parameter C2). This satisfies the application requirements of different scenarios and improves the resource utilization of the system.

[0035] Figure 5 is a flowchart of an image receiving method 500 according to this invention. In operation S510, a processor circuit sets a plurality of first pipeline parameters based on device information of a plurality of image sensors and data capacity of a plurality of first-in-first-out buffers. In operation S520, a first-in-first-out multiplexer circuit configures the correspondence between the plurality of image sensors and the plurality of first-in-first-out buffers according to the plurality of first pipeline parameters, so that each of the plurality of image sensors transmits image data to a corresponding one of the plurality of first-in-first-out buffers.

[0036] The various operations in the image receiving method 500 can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The various operations in the image receiving method 500 are merely examples and are not limited to being executed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this application, the various operations in the image receiving method 500 may be appropriately added, replaced, omitted, or executed in a different order. Alternatively, the various operations in the image receiving method 500 may be executed simultaneously or partially simultaneously.

[0037] In summary, the image receiving apparatus and image receiving method provided in some embodiments of this case can utilize the device information of the image sensor to adaptively configure the correspondence between multiple image sensors and multiple first-in-first-out buffers, as well as the correspondence between multiple image sensors and multiple first-in-first-out buffers, so as to improve the overall resource utilization and be applicable to more scenario requirements.

[0038] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make variations to the technical features of this case based on the explicit or implicit content of this case. All such variations may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification. [Simplified Explanation of the Diagram]

[0007] [Figure 1] is a schematic diagram of an image processing system according to some embodiments of the present invention; [Figure 2] is an operational schematic diagram of the first-in-first-out multiplexer circuit and the channel multiplexer circuit in Figure 1 according to some embodiments of the present invention; [Figure 3] is an operational flowchart of the processor circuit and the first-in-first-out multiplexer circuit in Figure 1 allocating a first-in-first-out buffer according to some embodiments of the present invention; [Figure 4] is an operational flowchart of the processor circuit and the channel multiplexer circuit in Figure 1 allocating a channel group according to some embodiments of the present invention; and [Figure 5] is a flowchart of an image receiving method according to the present invention.

Claims

1. An image receiving device, comprising: a first-in-first-out (FIFO) memory including a plurality of FIFO buffers; a processor circuit for setting a plurality of first pipeline parameters based on device information of a plurality of image sensors and the data capacity of the plurality of FIFO buffers; and a FIFO multiplexer circuit for configuring a correspondence between the plurality of image sensors and the plurality of FIFO buffers based on the plurality of first pipeline parameters, such that each of the plurality of image sensors transmits image data to a corresponding one of the plurality of FIFO buffers.

2. The image receiving apparatus of claim 1, wherein the apparatus information includes an image resolution of a corresponding image sensor among the plurality of image sensors, and if the image resolution is greater than a predetermined resolution, the first-in-first-out multiplexer circuit allocates a first buffer with a first data capacity among the plurality of first-in-first-out buffers to the corresponding image sensor according to a corresponding parameter among the plurality of first pipeline parameters.

3. The image receiving apparatus of claim 2, wherein the processor circuit further sets the plurality of first pipeline parameters according to the priority order of the plurality of first-in-first-out buffers, and if a plurality of second buffers that have not yet been allocated among the plurality of first-in-first-out buffers have the first data capacity, the first-in-first-out multiplexer circuit configures the one with the highest priority among the plurality of second buffers as the first buffer.

4. The image receiving apparatus of claim 2, wherein if the image resolution is less than the predetermined resolution, the first-in-first-out multiplexer circuit allocates a second buffer with a second data capacity from the plurality of first-in-first-out buffers to the corresponding image sensor, and the first data capacity is greater than the second data capacity.

5. The image receiving apparatus of claim 4, wherein the processor circuit further sets the plurality of first pipeline parameters according to the priority order of the plurality of first-in-first-out buffers, and if a plurality of third buffers that have not yet been allocated among the plurality of first-in-first-out buffers have the second data capacity, the first-in-first-out multiplexer circuit configures the one with the highest priority among the plurality of third buffers as the second buffer.

6. The image receiving apparatus of claim 1 further comprises: a direct memory access controller circuit including a plurality of channel groups, wherein each of the plurality of channel groups includes a plurality of access channels, and the processor circuit further sets a plurality of second pipeline parameters according to device information of a plurality of image sensors; a channel multiplexer circuit configuring the correspondence between the plurality of access channels and the plurality of first-in-first-out buffers according to the plurality of second pipeline parameters, so that each of the plurality of first-in-first-out buffers transmits the image data to a memory via a corresponding channel of the plurality of access channels.

7. The image receiving device of claim 6, wherein the device information includes a scene mode of the corresponding image sensor, and the processor circuit determines whether the scene mode is a predetermined mode in order to set a corresponding parameter among the plurality of second pipeline parameters.

8. The image receiving apparatus of claim 7, wherein the processor circuit further sets the plurality of second pipeline parameters according to the priority order of the plurality of channel groups and the priority order of the plurality of access channels, and if the scene mode is not the predetermined mode, the processor circuit selects a corresponding channel group with the highest priority from at least one group that has not yet been allocated in the plurality of channel groups, selects one with the highest priority from at least one channel that has not yet been allocated in the plurality of access channels of the corresponding channel group as a specific channel, and allocates the specific channel to one of the corresponding image sensors in the plurality of first-in-first-out buffers via the channel multiplexer circuit.

9. The image receiving device of claim 8, wherein if the scene mode is the predetermined mode, the processor circuit further confirms whether an image processing corresponding to the predetermined mode uses three image frames to set the plurality of second pipeline parameters.

10. The image receiving apparatus of claim 9, wherein the processor circuit further sets the plurality of second pipeline parameters according to the priority order of the plurality of channel groups, and if the image processing uses three image frames, the processor circuit selects a corresponding channel group with the lowest priority from the plurality of channel groups, and allocates the plurality of channels in the corresponding channel group to one of the plurality of first-in-first-out buffers allocated to the corresponding image sensor via the channel multiplexer circuit.

11. The image receiving apparatus of claim 9, wherein the processor circuit further sets the plurality of second pipeline parameters according to the priority order of the plurality of channel groups, and if the image processing uses two image frames, the processor circuit selects a corresponding channel group with a lower priority from the plurality of channel groups, and allocates the plurality of channels in the corresponding channel group to one of the plurality of first-in-first-out buffers allocated to the corresponding image sensor via the channel multiplexer circuit.

12. The image receiving device as claimed in claim 7, wherein the predetermined mode is an instantaneous high dynamic range mode.

13. An image receiving method, comprising: setting a plurality of first pipeline parameters by means of a processor circuit based on device information of a plurality of image sensors and data capacity of a plurality of first-in-first-out buffers; and configuring a correspondence between the plurality of image sensors and the plurality of first-in-first-out buffers by means of a first-in-first-out multiplexer circuit based on the plurality of first pipeline parameters, such that each of the plurality of image sensors transmits image data to a corresponding one of the plurality of first-in-first-out buffers.

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