Electronic device

Abstract

An electronic device includes a substrate, a plurality of transistors disposed on the substrate, a light-emitting unit disposed on at least one of the plurality of transistors, a first insulating layer disposed on the light-emitting unit, and an optical unit. The first insulating layer has a first opening and a second opening, and the optical unit is disposed in the first opening. In a top view of the electronic device, the first opening overlaps at least a portion of the light-emitting unit, and the second opening overlaps at least a portion of at least one of the plurality of transistors.

Description

[Technical Field]

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device including a hole structure. [Previous Technology]

[0002] As the types or number of films on the circuit layers in electronic devices increase, the inspection and / or repair steps of electronic components (e.g., transistors) in the circuit layers may be affected by the films on the circuit layers, potentially leading to problems in effectively repairing the electronic components. Furthermore, some components (e.g., alignment elements) disposed in the electronic device may be obscured by the films on the circuit layers and lose their functionality. Therefore, how to solve the above problems remains an important issue in the art. [Summary of the Invention]

[0003] One of the purposes of this disclosure is to provide an electronic device including a hole structure, wherein the hole structure can be used to assist in the performance of a specific process or reduce the influence of a film layer on a circuit layer on a specific component.

[0004] In some embodiments, this disclosure provides an electronic device including a substrate, a plurality of transistors disposed on the substrate, a light-emitting unit disposed on at least one of the plurality of transistors, a first insulating layer disposed on the light-emitting unit, and an optical unit. The first insulating layer has a first opening and a second opening, and the optical unit is disposed in the first opening. In a top view of the electronic device, the first opening overlaps at least a portion of the light-emitting unit, and the second opening overlaps at least a portion of at least one of the plurality of transistors.

Implementation Method

[0006] This disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that, in order to facilitate the reader's understanding and for the sake of brevity, many of the drawings in this disclosure only show a portion of the device, and certain elements in the drawings are not drawn to scale. Furthermore, the number and size of each element in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0007] Certain terms will be used throughout this specification and the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names.

[0008] In the following description and the scope of the patent application, the words "containing" and "including" are open-ended terms, and therefore should be interpreted as "containing but not limited to...".

[0009] It should be understood that when an element or film is referred to as being "placed" on or "connected" to another element or film, it can be directly on or directly connected to the other element or film, or there may be an inserted element or film between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or film, there may be no inserted element or film between them. When an element or film is referred to as being "electrically connected" to another element or film, it can be interpreted as a direct electrical connection or an indirect electrical connection. The electrical connection or coupling described in this disclosure can refer to a direct connection or an indirect connection. In the case of a direct electrical connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect electrical connection, there may be a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited to these.

[0010] Although the terms "first," "second," "third," etc., can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by "first," "second," "third," etc., according to the order in which the components are declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0011] In this disclosure, the thickness, length and width can be measured by using an optical microscope, and the thickness or width can be measured by cross-sectional images in an electron microscope, but are not limited thereto.

[0012] In addition, there may be a certain degree of error between any two values ​​or directions used for comparison. The terms "approximately", "substantially", or "roughly" are generally interpreted as being within ±10% of the given value, or within ±5%, ±3%, ±2%, ±1%, or ±0.5% of the given value.

[0013] In addition, the terms “given range is from the first value to the second value” and “given range falls within the range of the first value to the second value” indicate that the given range includes the first value, the second value and other values ​​in between.

[0014] If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0016] It should be understood that the technical features of several different embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure.

[0017] The electronic devices disclosed herein may include, but are not limited to, light-emitting devices, display devices, sensing devices, backlight devices, antenna devices, splicing devices, or other suitable electronic devices. The electronic devices disclosed herein may be bendable, flexible, or stretchable. Display devices may include non-self-emissive display devices or self-emissive display devices. Non-self-emissive display devices include, for example, liquid crystal displays, but are not limited to, them. Self-emissive display devices include, for example, light-emitting diode displays, but are not limited to, them. Display devices may be used, for example, in notebook computers, public displays, splicing displays, automotive displays, touch displays, televisions, monitors, smartphones, tablets, light source modules, lighting equipment, or, for example, electronic devices used in the aforementioned products, but are not limited to, them. Sensing devices may include biosensors, touch sensors, fingerprint sensors, other suitable sensors, or combinations of sensors of the above types. Antenna devices may include, for example, liquid crystal antenna devices, but are not limited to, them. Splicing devices may include, for example, display splicing devices or antenna splicing devices, but are not limited to, them. The electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may include electronic units, which may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. Diodes may include light-emitting diodes (LEDs) or photodiodes. LEDs may include, for example, organic light-emitting diodes (OLEDs), quantum dot LEDs (QLEDs or QDLEDs), or in-organic light-emitting diodes. In-organic LEDs may include, for example, mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. The electronic device may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (e.g., augmented reality or virtual reality), automotive devices (e.g., automotive windshields), or splicing devices. The following description uses electronic devices, including display devices, as examples to illustrate the content of this disclosure, but this disclosure is not limited thereto. The electronic devices disclosed herein can be various combinations of the aforementioned devices, such as a combination of a display device and other devices, but are not limited thereto.

[0018] Please refer to FIG1, which is a partial cross-sectional schematic diagram of an electronic device according to a first embodiment of the present disclosure. The electronic device ED disclosed herein may include a light-emitting device for emitting light. In one embodiment, the electronic device ED may include a display device DD for displaying a screen or image, but is not limited thereto. In some embodiments, the electronic device ED may include a combination of the display device DD and other types of devices. As shown in FIG1, the electronic device ED may include a substrate SB, a circuit layer CL disposed on the substrate SB, an electronic unit (e.g., a light-emitting unit LU) disposed on the circuit layer CL, and an optical unit LCU disposed on the light-emitting unit LU, but is not limited thereto. It should be noted that the structure of the electronic device ED is not limited to that shown in FIG1, and may also include other components and / or film layers. The structure of each film layer or component of the electronic device ED is described in detail below.

[0019] The substrate SB can be used to support components and films located thereon. The substrate SB may comprise a rigid material or a flexible material. Rigid materials include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof. Flexible materials include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof. In some embodiments, the substrate SB may comprise a multilayer structure, not limited to that shown in FIG1.

[0020] The circuit layer CL may include various wires, circuits, and electronic units applicable to the electronic device ED. The electronic units may include any suitable active and / or passive components. The circuit layer CL may include any suitable structure formed by stacking conductive and insulating layers, wherein the conductive layers can be used to form the aforementioned wires, circuits, or electronic units. According to this embodiment, the circuit layer CL may include a plurality of transistors, capacitors, nodes, and / or signal feed lines, such as the transistor T1 shown in FIG1. ​​It should be noted that FIG1 only exemplarily shows the structure of one transistor T1 and does not show the structures of other transistors, but the structures of other transistors can be referenced to the structure of transistor T1, but are not limited thereto. In other words, the electronic device ED includes a plurality of transistors disposed on the substrate SB. The plurality of transistors in the circuit layer CL may serve as driving units, switching units, sensing driving units, or other suitable electronic units. For example, the transistor T1 shown in FIG1 may be electrically connected to the light-emitting unit LU in the electronic device ED to drive the light-emitting unit LU, that is, the transistor T1 may serve as the driving unit of the light-emitting unit LU, but is not limited thereto. The transistors (e.g., transistor T1) in the circuit layer CL may include, but are not limited to, thin-film transistors (TFTs). Specifically, as shown in FIG1, the circuit layer CL may include a buffer layer BF, a semiconductor SM disposed on the buffer layer BF, a conductive layer M1 disposed on the semiconductor SM, and a conductive layer M2 disposed on the conductive layer M1. The conductive layer M1 may form the gate electrode GE of transistor T1, while the conductive layer M2 may form the source electrode and drain electrode DE of transistor T1. In one embodiment, the circuit layer CL may further include a conductive layer M0 disposed between the buffer layer BF and the substrate SB. The gate electrode GE of transistor T1 may correspond to the channel region of semiconductor SM, while the source electrode and drain electrode DE of transistor T1 may be electrically connected to the source region and drain region of semiconductor SM, respectively. It should be noted that the source electrode and the channel region, source region, and drain region of semiconductor SM are not shown in FIG1; they are labeled in FIG3. The conductive layers M1 and M2 may comprise any suitable conductive material, such as a metal, but are not limited thereto. The semiconductor SM may comprise any suitable semiconductor material. For example, the material of the semiconductor SM in this embodiment may comprise metal oxides (e.g., indium gallium zinc oxide (IGZO)), a-IGZO (amorphous IGZO), crystalline IGZO, spinel-type IGZO crystal structures, CAAC-IGZO hybrid thin films (C-Axis Aligned Crystal IGZO), nc-IGZO (nanocrystalline IGZO, intermediate between single-crystal IGZO and amorphous IGZO), native crystalline IGZO thin films (a morphology in which amorphous and nanocrystalline phases coexist), polycrystalline spinel-type IGZO, but is not limited thereto.In other embodiments, the material of the semiconductor SM may include low-temperature polysilicon (LTPS) or amorphous silicon (a-Si), but is not limited thereto. In other embodiments, the semiconductor SM material of some transistors may be metal oxide materials, and the semiconductor SM material of some transistors may be low-temperature polysilicon. Although the transistor T1 shown in FIG1 is a top-gate thin-film transistor, this embodiment is not limited thereto. In some embodiments, the transistor T1 may include a bottom-gate thin-film transistor, a dual-gate or double-gate thin-film transistor, a multi-gate thin-film transistor, or other types of thin-film transistors. The plurality of transistors in the electronic device ED may be the same or different types of transistors. As shown in FIG1, the electronic device ED may also include an insulating layer IN2 disposed between the gate electrode GE (or conductive layer M1) and the semiconductor SM. The insulating layer IN2 may serve as the gate insulating layer in the transistor T1. It should be noted that although the insulating layer IN2 shown in Figure 1 is a patterned film layer, this embodiment is not limited thereto. In some embodiments, the insulating layer IN2 may be a continuous film layer disposed on the semiconductor SM and the buffer layer BF. The electronic device ED may also include an insulating layer IN3 disposed between the conductive layer M1 and the conductive layer M2 and an insulating layer IN4 disposed on the conductive layer M2. The insulating layers IN2, IN3, and IN4 may comprise any suitable insulating material.

[0021] In some embodiments, the transistor T1 may further include a semiconductor OL disposed on the substrate SB. In other words, the transistor T1 may include two semiconductor layers (i.e., semiconductor SM and semiconductor OL). Semiconductor OL may be disposed between semiconductor SM and substrate SB. For example, semiconductor OL may be directly disposed on buffer layer BF, but is not limited thereto. In the top view direction (i.e., direction Z) of the electronic device ED, semiconductor SM may at least partially overlap semiconductor OL. In some embodiments, the electronic device ED may further include an insulating layer IN1, wherein insulating layer IN1 is disposed between semiconductor SM and semiconductor OL. Specifically, insulating layer IN1 may be directly disposed on the upper surface of semiconductor OL and directly contact semiconductor OL. Semiconductor SM may be electrically connected to semiconductor OL. In this case, the source electrode (not shown in FIG. 1) and / or drain electrode DE of transistor T1 may be electrically connected to semiconductor SM and semiconductor OL. For example, semiconductor SM may be electrically connected to semiconductor OL by filling a through-hole through buffer layer BF and insulating layer IN1 with conductive layer M2 or conductive layer M1 (e.g., conductive layer M2 in FIG. 1) to contact semiconductor OL, but is not limited thereto. In other embodiments, the semiconductor SM may be electrically connected to the semiconductor OL through other conductive layers. In some embodiments, the semiconductor SM may be electrically connected to the semiconductor OL through multiple conductive layers. The insulating layer IN1 may include a metal oxide material, such as aluminum oxide, but is not limited thereto. The insulating layer IN1 may serve as an etching stopping layer and / or an oxygen-resistant layer, thereby protecting the semiconductor OL. The material of the semiconductor OL may include, but is not limited to, indium zinc oxide (In-Zn-O), indium gallium zinc tin oxide (In-Ga-Zn-Sn-O), indium gallium tin oxide (In-Ga-Sn-O), or indium tin zinc oxide (In-Sn-Zn-O). The crystal structure of the semiconductor OL may differ from that of the semiconductor SM. For example, the semiconductor OL may include a polycrystalline oxide material, but is not limited thereto. The atomic percentage content of indium in the material of the semiconductor OL may be greater than the atomic percentage content of zinc, and the atomic percentage content of zinc may be greater than the atomic percentage content of gallium. The atomic percentage content of indium and gallium in the semiconductor SM material can be greater than that in the semiconductor OL material. The atomic percentage content of oxides in the semiconductor OL material can be greater than that in the semiconductor SM material. In this embodiment, the carrier mobility of the semiconductor OL can be greater than that of the semiconductor SM.In this case, by including a semiconductor OL electrically connected to the semiconductor SM in the transistor T1, the overall carrier mobility of the semiconductor in the transistor T1 can be improved. For example, after providing the semiconductor OL, the carrier mobility of the semiconductor (including the semiconductor SM and the semiconductor OL) of the transistor can be greater than 50 cm² / Vs, but is not limited thereto. This improves the performance of the transistor T1, and consequently improves the performance of the electronic device ED. In this embodiment, the semiconductor SM can have a thickness H1, and the semiconductor OL can have a thickness H2, wherein the thickness H2 can be less than the thickness H1. Thicknesses H1 and H2 are shown in FIG3, but not in FIG1. ​​The comparison of the thickness H1 of the semiconductor SM and the thickness H2 of the semiconductor OL can be performed in the portion where the semiconductor SM and the semiconductor OL overlap. Specifically, it can be first determined that the semiconductor SM overlaps a portion of the semiconductor OL, and the maximum thickness of that portion of the semiconductor SM is defined as thickness H1. Similarly, it can be first determined that the semiconductor OL overlaps a portion of the semiconductor SM, and the maximum thickness of that portion of the semiconductor OL is defined as thickness H2. In other embodiments, thicknesses H1 and H2 may be defined in other suitable ways and are not limited to the above. It should be noted that the inclusion of semiconductor OL in the transistor T1 described above is not limited to all transistors applied to circuit layer CL. For example, in some embodiments, a portion of the transistors may include semiconductor OL, while another portion may not.

[0022] In some embodiments, the circuit layer CL may further include capacitor elements, which may be formed by different conductive layers and insulating layers in the circuit layer CL. For example, as shown in FIG1, the circuit layer CL may include capacitor elements CP1 and CP2, which may be formed by conductive layers M1 and M2 and an insulating layer IN3 sandwiched between conductive layers M1 and M2, but are not limited thereto. In other embodiments, capacitor elements CP1 and CP2 may be formed by other conductive layers. Capacitor elements CP1 and CP2 can be used to stabilize the voltage when the electronic device ED displays the screen, thereby improving the display effect of the electronic device ED, but are not limited thereto.

[0023] In some embodiments, the circuit layer CL may further include a wiring structure WS, wherein the wiring structure WS may be formed by a conductive layer in the circuit layer CL. Specifically, the electronic device ED may include an active region DA and a peripheral region NDA. The active region DA may be an area in the electronic device ED that serves a primary function (such as displaying an image, emitting light, or being operable by a user). In this embodiment, the active region DA may be defined as the smallest rectangular or smallest area shape surrounded by the outer edge of the outermost light-emitting unit LU (e.g., the outer edge of the light-emitting layer LEL of the light-emitting unit LU), but is not limited thereto. In other embodiments, the shape, position, or extent of the active region DA may be defined by any suitable method. The peripheral region NDA may be defined as other areas in the electronic device ED besides the active region DA, such as a non-display area or a non-light-emitting area. As shown in FIG1, the wiring structure WS may be disposed within the peripheral region NDA. In this embodiment, the wiring structure WS may be formed by conductive layers M0, M1, M2, and M3. Specifically, the electronic device ED may further include a conductive layer M0, wherein the conductive layer M0 may be directly disposed on the surface of the substrate SB and may extend on the surface of the substrate SB to be electrically connected to external electronic components (not shown in FIG1). The conductive layer M1 may be electrically connected to the conductive layer M0 through a via passing through the buffer layer BF. The electronic device ED may further include an insulating layer INS disposed between insulating layers IN3 and IN4, and the conductive layer M2 may be electrically connected to the conductive layer M1 through a via passing through the insulating layers INS and IN3. The electronic device ED may further include a conductive layer M3, wherein the conductive layer M3 may be disposed on the insulating layer I2 and may be electrically connected to the conductive layer M2. The conductive layers (e.g., conductive layers M2 and M3) in the wiring structure WS may extend within the active region DA and / or peripheral region NDA of the electronic device ED and be electrically connected to any suitable electronic component (e.g., transistor T1, but not limited thereto) in the electronic device ED. In some embodiments, the conductive layer M3 may be disposed at other suitable locations in the electronic device ED. Thus, the electronic components in the electronic device ED can be electrically connected to external electronic components through the wiring structure WS. The materials of conductive layers M0 and M3 can refer to those of conductive layers M1 and M2 described above. The insulating layer INS can include any suitable insulating material. It should be noted that the wiring structure WS shown in Figure 1 is merely exemplary and this disclosure is not intended to limit it. In other embodiments, the conductive layers in the wiring structure WS can be connected in any manner, allowing electronic components in the electronic device ED to be electrically connected to external electronic components.

[0024] Although FIG. 1 only shows the transistor T1 disposed in the active region DA, the circuit layer CL may include transistors disposed in the peripheral region NDA. That is, the transistors in the circuit layer CL may be disposed in the active region DA and / or the peripheral region NDA of the electronic device ED. Furthermore, the structure of the circuit layer CL shown in FIG. 1 is merely exemplary and this disclosure is not limited thereto. The circuit layer CL may also include other suitable components or films depending on the design of the electronic device ED.

[0025] According to this embodiment, as shown in FIG1, the electronic device ED may further include an insulating layer IN5, wherein the insulating layer IN5 may be disposed on the circuit layer CL and may cover the components in the circuit layer CL, such as transistor T1, capacitor element CP1, capacitor element CP2, etc., but is not limited thereto. The upper surface of the insulating layer IN5 (or the surface away from the circuit layer CL) may be a flat surface to facilitate the placement of other components and / or film layers thereon. In this case, the insulating layer IN5 may serve as a planarization layer. The insulating layer IN5 may include any suitable insulating material.

[0026] The electronic unit may be disposed on the insulating layer IN5. In one embodiment, the electronic unit may include a light-emitting unit LU as a light source for the electronic device ED. The light-emitting unit LU may include a light-emitting diode, but is not limited thereto. In this embodiment, the electronic device ED may include an organic light-emitting diode display device, and the light-emitting unit LU may include an organic light-emitting diode, but is not limited thereto. For example, as shown in FIG1, the light-emitting unit LU may include an electrode E1, an electrode E2, and a light-emitting layer LEL disposed between the electrodes E1 and E2. The electrode E1 may be disposed on the insulating layer IN5, the light-emitting layer LEL may be disposed on the electrode E1, and the electrode E2 may be disposed on the light-emitting layer LEL. One of the electrodes E1 and E2 may be an anode, and the other may be a cathode. For example, the electrode E1 may be an anode, and the electrode E2 may be a cathode, but is not limited thereto. The electrode E1 may include any suitable conductive material, such as a metallic material or a transparent conductive material, but is not limited thereto. The electrode E2 may include any suitable conductive material, such as a transparent conductive material, but is not limited thereto. The electronic device ED may further include an insulating layer IN6 disposed on an insulating layer IN5, wherein the insulating layer IN6 may include an opening OP that partially covers the electrode E1 and exposes a portion of the electrode E1. A portion of the light-emitting layer LEL may be disposed within the opening OP of the insulating layer IN6. Specifically, a light-emitting unit LU may consist of a portion of the electrode E1 exposed by the opening OP, a portion of the light-emitting layer LEL disposed within the opening OP, and a corresponding portion of the electrode E2 disposed within the opening OP. In this case, the range of a light-emitting unit LU may be defined, for example, by the range of the portion of the light-emitting layer LEL disposed within the opening OP, but is not limited thereto. Therefore, the insulating layer IN6 may serve as a pixel defining layer and include a plurality of openings OP. Although only one light-emitting unit LU is shown in FIG1, the electronic device ED may include a plurality of light-emitting units LU, each disposed in one of the plurality of openings OP of the insulating layer IN6. The electrode E1 may be electrically connected to a transistor T1 (e.g., the drain electrode DE of the transistor T1), thereby electrically connecting the light-emitting unit LU to the transistor T1. In other words, the light-emitting unit LU can be disposed on at least one transistor (e.g., transistor T1) and electrically connected to that transistor. It should be noted that although only one light-emitting unit LU is shown in FIG1, the electronic device ED may include a plurality of light-emitting units LU, and each of these light-emitting units LU may be disposed on at least one transistor and electrically connected to that transistor.

[0027] In some embodiments, the electronic device ED may further include an insulating layer IL1, an insulating layer OIL, and an insulating layer IL2 disposed on the light-emitting unit LU. Specifically, the insulating layers IL1, OIL, and IL2 may be disposed on the electrode E2. The insulating layers IL1, OIL, and IL2 may serve as encapsulation layers for encapsulating the components, the light-emitting unit LU, and the film layers between themselves and the substrate SB. Furthermore, the insulating layer IL2 may have a flat upper surface to facilitate the placement of other components and film layers thereon. In this embodiment, the insulating layers IL1 and IL2 may comprise any suitable transparent inorganic material, while the insulating layer OIL may comprise any suitable transparent organic material. In other words, the aforementioned encapsulation layer may be formed by alternating stacks of inorganic and organic insulating layers.

[0028] In some embodiments, as shown in FIG1, the electronic device ED may further include an insulating layer I1 disposed between insulating layer IN5 and insulating layer IL1, and an insulating layer I2 disposed on insulating layer IL2. Insulating layer I1 and insulating layer I2 may include any suitable insulating material. Insulating layer I2 may isolate the optical unit LCU from the packaging layer (including insulating layer IL1, insulating layer OIL and insulating layer IL2) and the components or film layers below it. In this case, the conductive layer M3 in the above-described wiring structure WS may be electrically connected to the conductive layer M2, for example, through through holes passing through insulating layer I2, insulating layer IL2, insulating layer IL1, insulating layer I1, insulating layer IN5 and insulating layer IN4, but is not limited thereto.

[0029] In some embodiments, the electronic device ED may further include a barrier structure DW1 disposed on the insulating layer IN5. The barrier structure DW1 may be formed by patterning the insulating layer IN6. Specifically, the insulating layer IN6 with a protruding shape after patterning may serve as the barrier structure DW1, wherein the barrier structure DW1 can be used to reduce the possibility of moisture and / or oxygen intruding into the electronic device ED, thereby achieving the effect of protecting the electronic components inside the electronic device ED. The electrode E1, the light-emitting layer LEL, and the insulating layer IL1 may extend on the barrier structure DW1, but are not limited thereto. The barrier structure DW1 may be disposed in the peripheral area NDA of the electronic device ED.

[0030] In some embodiments, a portion of the light-emitting layer LEL disposed in one of the openings OP of the insulating layer IN6 may include a via V1, wherein the via V1 exposes a portion of the electrode E1, and the electrode E2 may fill the via V1 and contact the exposed portion of the electrode E1. Furthermore, the portion of the electrode E1 exposed by the via V1 may be electrically connected to the conductive layer M2 in the circuit layer CL, and through the conductive layer M2 to the semiconductor SM, and then through the semiconductor SM to the semiconductor OL, but is not limited thereto. Through the above design, electrodes E1 and E2 can be electrically connected to a voltage source through the conductive layer M2, the semiconductor SM, and the semiconductor OL, thereby reducing the impedance of the electrodes (i.e., electrodes E1 and E2) in the light-emitting unit LU, thereby improving the performance of the light-emitting unit LU. It should be noted that the portion of the light-emitting layer LEL including the via V1 may not be used as the light-emitting area in the light-emitting unit LU. In some embodiments, the portion of the electrode E1 exposed by the via V1 may be electrically connected to a voltage source in other suitable ways, and is not limited to the methods described above.

[0031] In this embodiment, the optical unit LCU may be disposed on the insulating layer I2. The optical unit LCU may include any suitable material that can change the wavelength or color of the light passing through the optical unit LCU, or can change the emission angle of the light. The optical unit LCU may include quantum dots, fluorescent materials, phosphorescent materials, scattering particles, other suitable materials, or combinations of the above materials. For example, the optical unit LCU in this embodiment may include quantum dots QD, but is not limited thereto. The optical unit LCU may be disposed corresponding to the light-emitting unit LU. Specifically, the electronic device ED also includes an insulating layer INL disposed on the light-emitting unit LU, wherein the insulating layer INL may include a first opening OP1, and the optical unit LCU may be disposed in the first opening OP1. In other words, in this embodiment, the optical unit LCU may be formed by disposing quantum dots QD in the first opening OP1 of the insulating layer INL, but is not limited thereto. The first opening OP1 may penetrate the insulating layer INL and may expose a film layer (e.g., insulating layer I2, but not limited thereto) located below the insulating layer INL. The insulating layer INL may include any suitable light-shielding material, such as black resin, gray resin, scattering particles, other suitable materials, or combinations thereof. The phrase "optical unit LCU corresponds to light-emitting unit LU" may refer to the optical unit LCU overlapping at least a portion of the light-emitting unit LU in the top view of the electronic device ED. Here, "optical unit LCU overlapping at least a portion of light-emitting unit LU" may mean that the optical unit LCU overlaps at least a portion of the light-emitting layer LEL of the light-emitting unit LU, but is not limited thereto. In this case, the first opening OP1 of the insulating layer INL may overlap at least a portion of the light-emitting unit LU in the top view of the electronic device ED. The optical unit LCU can be used to change the wavelength or color of the light emitted by its corresponding light-emitting unit LU, or to change the emission angle of the light emitted by its corresponding light-emitting unit LU. It should be noted that although only one optical unit LCU is shown in Figure 1, the electronic device ED may include a plurality of optical units LCU, and each optical unit LCU may be disposed in a first opening OP1 of the insulating layer INL and correspond to one of the light-emitting units LU. In this case, the insulating layer INL may include a plurality of first openings OP1, which may overlap at least a portion of one of the light-emitting units LU in the top view of the electronic device ED. The plurality of optical units LCU in the electronic device ED may change the light to have different wavelengths or colors or different emission angles, but are not limited thereto.For example, as shown in Figure 2, the electronic device ED may include optical units LCU1, LCU2, and LCU3. The light passing through optical units LCU1, LCU2, and LCU3 will be red, green, and blue light, respectively, and may be mixed to produce white light, but this is not a limitation. Figure 1 only shows an exemplary structure in which optical unit LCU1 is disposed within the first opening OP1. In some embodiments, as shown in Figure 1, the electronic device ED may also include a dummy optical unit DCU disposed in the peripheral region NDA, wherein the dummy optical unit DCU may not correspond to a light-emitting unit LU. The dummy optical unit DCU may, for example, be disposed in the peripheral region NDA adjacent to the active region DA, but this is not a limitation.

[0032] According to this disclosure, the insulating layer INL may include a second opening OP2 in addition to the first opening OP1 described above, wherein the second opening OP2 may not contain an optical unit LCU. Specifically, the insulating layer INL may have a plurality of openings, wherein a portion of these openings may be the first opening OP1 described above, in which an optical unit LCU may be disposed, and another portion of these openings may be openings OPE, in which no optical unit LCU may be disposed, and the second opening OP2 may be one of the openings OPE. The second opening OP2 (or opening OPE) may penetrate the insulating layer INL and may expose the film layer located below the insulating layer INL. According to this disclosure, the second opening OP2 of the insulating layer INL may overlap at least a portion of at least one transistor in the circuit layer CL in the top view of the electronic device ED. The above-mentioned "the second opening OP2 overlaps at least a portion of the transistor" may include an embodiment in which the second opening OP2 overlaps at least one of the source electrode (or source electrode) and drain electrode (or drain electrode) in the transistor in the top view of the electronic device ED. For example, as shown in FIG1, the insulating layer INL may include a second opening OP2 overlapping the transistor T1, but is not limited thereto. In this case, the second opening OP2 may overlap at least one of the source electrode (not shown) and drain electrode DE of the transistor T1 in the top view of the electronic device ED, or may overlap both the source electrode and drain electrode DE of the transistor T1 simultaneously. The second opening OP2 may also overlap the gate electrode GE, semiconductor SM and / or semiconductor OL (if any) of the transistor T1, but is not limited thereto. In other words, the electronic device ED disclosed herein may include a plurality of transistors disposed on a substrate SB, a light-emitting unit LU disposed on at least one of the transistors (e.g., transistor T1), and an insulating layer INL disposed on the light-emitting unit LU, wherein the insulating layer INL may include a first opening OP1 overlapping at least a portion of the light-emitting unit LU and a second opening OP2 overlapping at least a portion of the at least one transistor (e.g., transistor T1). It should be noted that the "opening OPE overlapping at least a portion of the transistor" described in this disclosure can include cases where at least one of the opening OPEs overlaps at least a portion of the transistor. Specifically, in some embodiments, the insulating layer INL may include a plurality of opening OPEs in which no optical unit LCU is disposed, wherein a portion of the openings of these opening OPEs (e.g., the second opening OP2) may overlap at least a portion of at least one transistor, while other portions of the openings of these opening OPEs (e.g., another opening OPE shown in FIG. 1) may not overlap with the transistor. In this embodiment, at least a portion of each transistor in the circuit layer CL (i.e., at least one of the source electrode and drain electrode) may overlap at least one opening OPE (e.g., the second opening OP2) of the insulating layer INL in the top view direction of the electronic device ED, but this is not a limitation.In some embodiments, the opening OPE may overlap at least a portion of other electronic components in the top view of the electronic device ED, depending on the design of the electronic device ED. The definition of the range of the source electrode and drain electrode in the transistor will be described in detail below.

[0033] In some embodiments, the electronic device ED may further include insulating layers IN7, IN8, and IN9 disposed on the insulating layer INL. Insulating layers IN7, IN8, and IN9 may extend on the insulating layer INL and may fill the second opening OP2 (or opening OPE). In other words, a portion of insulating layers IN7, IN8, and IN9 may be disposed in the second opening OP2 (or opening OPE). Insulating layers IN7 and IN9 may be inorganic layers and include any suitable transparent inorganic material. Insulating layer IN8 may be an organic layer and include any suitable transparent organic material or a material with a low refractive index. In this embodiment, the material of insulating layer IN8 may have a lower refractive index compared to other organic layers in the electronic device ED (e.g., insulating layer OIL, but not limited thereto). This can improve the light emission effect of the electronic device ED and / or reduce interference caused by external ambient light incident on the electronic device ED. In some embodiments, the electronic device ED may further include a barrier structure DW2 disposed on the insulating layer IN7. The barrier structure DW2 can be formed by patterning the insulating layer IN8. Specifically, the insulating layer IN8, after being patterned, has a protruding shape and can serve as the barrier structure DW2, which can reduce the possibility of moisture and / or oxygen intruding into the electronic device ED. The insulating layer IN9 can extend on the barrier structure DW2, but is not limited thereto. The barrier structure DW2 can be disposed in the peripheral area NDA of the electronic device ED.

[0034] According to this embodiment, the electronic device ED may further include a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 disposed on an optical unit LCU (or insulating layer INL), wherein the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can respectively allow light of a specific color to pass through. The first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may, for example, include color filters, but are not limited thereto. In this embodiment, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can respectively allow red light, green light, and blue light to pass through, but are not limited thereto. In other words, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may respectively include a red color filter layer, a green color filter layer, and a blue color filter layer. In this embodiment, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be stacked to form a filter layer structure CFL. For example, as shown in Figure 1, a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 can be sequentially disposed on the insulating layer IN9 to form a filter layer structure CFL. The arrangement order of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 in the filter layer structure CFL is merely exemplary and is not limited to this embodiment. The filter layer structure CFL can extend on the insulating layer INL and can be filled into the second opening OP2 (or opening OPE) of the insulating layer INL. Specifically, as shown in Figure 1, the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be filled into the second opening OP2 (or opening OPE) of the insulating layer INL, that is, a portion of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 can be disposed in the second opening OP2 (or opening OPE). Furthermore, in this embodiment, a portion of the filter layer structure CFL corresponding to an optical unit LCU may only include filter layers with the same color as the light emitted after passing through the optical unit LCU. The phrase "the filter layer structure CFL corresponds to a portion of an optical unit LCU" here refers to the filter layer structure CFL overlapping a portion of the optical unit LCU in the top view of the electronic device ED. For example, as shown in Figure 1, the light passing through the optical unit LCU1 is red light, and the portion of the filter layer structure CFL corresponding to the optical unit LCU1 may only include a red color filter layer, i.e., the first filter layer CF1. Specifically, the optical unit LCU1 can be made to correspond only to the first filter layer CF1 in the filter layer structure CFL by removing the second filter layer CF2 and the third filter layer CF3 from the portion of the filter layer structure CFL corresponding to the optical unit LCU1 (e.g., through a patterning process of the second filter layer CF2 and the third filter layer CF3). In this case, after removing a portion of the second filter layer CF2 and the third filter layer CF3, an opening corresponding to the optical unit LCU1 can be formed.In short, taking the structure shown in Figure 1 as an example, the electronic device ED may include a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 disposed on the insulating layer INL. A portion of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may be disposed in the second opening OP2. In the top view direction of the electronic device ED, the first filter layer CF1 may overlap with the optical unit LCU1, while the second filter layer CF2 and the third filter layer CF3 may not overlap with the optical unit LCU1. Similarly, when light passes through the optical unit LCU2 shown in Figure 1 and emits green light, the portion of the filter layer structure CFL corresponding to the optical unit LCU2 may only include the second filter layer CF2, meaning the first filter layer CF1 and the third filter layer CF3 do not correspond to the optical unit LCU2. Conversely, when light passes through the optical unit LCU3 shown in Figure 1 and emits blue light, the portion of the filter layer structure CFL corresponding to the optical unit LCU3 may only include the third filter layer CF3, meaning the first filter layer CF1 and the second filter layer CF2 do not correspond to the optical unit LCU3. It should be noted that a portion of the filter layer structure CFL corresponding to the dummy optical unit DCU located in the peripheral region NDA may include the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3; that is, this portion of the filter layer may not be removed.

[0035] According to this embodiment, the electronic device ED may further include a protective layer disposed on the filter layer structure CFL. The protective layer may refer to a combination of film layers located on the filter layer structure CFL, or it may include a structure formed by stacking film layers on the filter layer structure CFL. As shown in FIG1, the protective layer of the electronic device ED in this embodiment may include an optical layer OC, an adhesive layer AD, a cover layer CO, and an anti-reflective layer AR, but is not limited thereto. The optical layer OC may be disposed on the filter layer structure CFL, and the adhesive layer AD may be disposed on the optical layer OC. The optical layer OC may include any suitable element or film layer that can improve the light emission effect of the electronic device ED. The adhesive layer AD may include any suitable transparent adhesive material. The cover layer CO may be attached to the optical layer OC through the adhesive layer AD. The cover layer CO provides protection for the film layer or element located thereunder. The cover layer CO may include, for example, glass, but is not limited thereto. The anti-reflective layer AR may be disposed on the cover layer CO, thereby improving the light emission effect of the electronic device ED. A portion of the protective layer may be filled into the second opening OP2 (or opening OPE) of the insulating layer INL. For example, as shown in FIG1, a portion of the optical layer OC in the protective layer may be filled into the second opening OP2 (or opening OPE). It should be noted that the protective layer shown in FIG1 is merely exemplary and this disclosure is not limited thereto. In other embodiments, the protective layer may include other suitable elements or layers depending on the design of the electronic device ED. Furthermore, although not shown in FIG1, in some embodiments, the electronic device ED may also include a touch layer, wherein the touch layer may be disposed at any suitable location in the electronic device ED.

[0036] Please refer to Figures 2 and 3. Figure 2 is a partial top view of the electronic device according to the second embodiment of this disclosure, and Figure 3 is a cross-sectional view of the transistor of the electronic device according to the second embodiment of this disclosure. To simplify the drawings, Figure 2 only shows a partial structure of the insulating layer INL. Specifically, Figure 2 shows the arrangement of an optical unit LCU1, an optical unit LCU2, and an optical unit LCU3 within an opening in the insulating layer INL. As described above, the insulating layer INL can be patterned to form a plurality of openings, which can be divided into first openings OP1 in which optical units LCU are disposed and openings OPE in which no optical units LCU are disposed. Therefore, in the partial top view of the insulating layer INL shown in Figure 2, the insulating layer INL may include three first openings OP1, in which optical units LCU1, LCU2, and LCU3 are disposed respectively, while other openings in the insulating layer INL that do not have optical units LCU may be openings OPE. The opening OPE may include a second opening OP2, which, in the top view of the electronic device ED, may overlap at least a portion of the transistor in the circuit layer CL. For example, FIG2 shows the case where the second opening OP2 overlaps the transistor T1 in the top view of the electronic device ED. In this case, a portion of the structure shown in FIG1 may correspond to the cross-sectional structure along tangent A-A' of the top view structure shown in FIG2. It should be noted that, although not shown in FIG2, the electronic device ED may include another transistor, and another opening OPE may overlap at least a portion of that other transistor in the top view of the electronic device ED. In some embodiments, a portion of the opening OPE may not overlap the transistor. The pattern of the insulating layer INL shown in FIG2 is merely exemplary and is not limited to this embodiment. In other embodiments, the insulating layer INL may have any suitable pattern depending on the design of the electronic device ED (e.g., the placement of the optical unit LCU or the transistor), thereby forming a first opening OP1 for placing the optical unit LCU and an opening OPE (e.g., including the second opening OP2) that may overlap at least a portion of the transistor.

[0037] Figure 3 shows a cross-sectional structure of a transistor (e.g., transistor T1) in an electronic device ED. Specifically, the structure shown in Figure 3 can be a cross-sectional structure of the structure shown in Figure 2 along tangent B-B'. As shown in Figure 3, transistor T1 may include a semiconductor SM, a gate electrode GE, a source electrode SE, and a drain electrode DE, but is not limited thereto. In some embodiments, transistor T1 may also include a semiconductor OL electrically connected to the semiconductor SM. The gate electrode GE may be formed by a conductive layer M1, while the source electrode SE and drain electrode DE may be formed by a conductive layer M2, but are not limited thereto. In this embodiment, the electronic device ED may also include a plurality of data lines and a plurality of scan lines (not shown), wherein one of the plurality of scan lines may be electrically connected to the gate electrode GE, or both the scan line and the gate electrode GE may be formed by patterning the conductive layer M1. One of the plurality of data lines may be electrically connected to the source electrode SE, or both the data line and the source electrode SE may be formed by patterning the conductive layer M2. These scan lines can extend in one direction, which can be the extension direction of the conductive layer M1 used to form the gate electrode GE of transistor T1. For example, in this embodiment, the extension direction of the conductive layer M1 used to form the gate electrode GE of transistor T1 can be parallel to direction X, that is, the extension direction of the scan lines can be parallel to direction X, but is not limited thereto. These data lines can extend in another direction that is not parallel to the extension direction of the scan lines. According to this embodiment, the ranges of the gate electrode GE, source electrode SE, and drain electrode DE in transistor T1 can be defined in a cross-sectional view of transistor T1. Specifically, the gate electrode GE, source electrode SE, and drain electrode DE of transistor T1 can be defined in a cross-sectional view of transistor T1 perpendicular to the extension direction of the scan lines (i.e., direction Y). The following uses the structure shown in FIG3 as an example to illustrate how the ranges of the gate electrode GE, source electrode SE, and drain electrode DE of transistor T1 are defined, where FIG3 shows a cross-sectional view of transistor T1 perpendicular to the extension direction of the scan lines (i.e., direction Y).

[0038] According to this embodiment, the gate electrode GE of the transistor T1 may have a range RG in a cross-sectional view of the transistor T1, wherein the range RG of the gate electrode GE can be defined by the range R1 of the portion of the conductive layer M1 overlapping the semiconductor SM. Specifically, in a cross-sectional view of the transistor T1 perpendicular to the extension direction of the scan line, the range R1 of the portion of the conductive layer M1 overlapping the semiconductor SM can be identified first, and the width DG of the range R1 can be measured. The width DG can be the maximum width of the range R1 measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). Then, the range RG of the gate electrode GE can be defined by extending the range R1 to its left and right sides by 0.25 times the width of the range R1 (i.e., the width DG). In other words, in the cross-sectional view of the transistor T1, the left and right sides of the range RG can protrude from the left and right sides of the range R1 by a distance of 0.25 times the width DG of the range R1, respectively. In this case, the range RG can have a width D3, which is 1.5 times the width DG (i.e., D3 = 1.5 * DG). The width D3 can be the maximum width of the range RG measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). The width D3 can also be regarded as the width of the gate electrode GE. The range RG of the gate electrode GE of transistor T1 can be defined in the above way.

[0039] According to this embodiment, the source electrode SE of transistor T1 may have a range RS in a cross-sectional view of transistor T1, wherein the range RS of the source electrode SE can be defined by the range R3 of the portion where the conductive layer M2 contacts the source region SR of the semiconductor SM. Specifically, in a cross-sectional view of transistor T1 perpendicular to the extension direction of the scan line, the range R3 of the overlapping portion of the conductive layer M2 and the source region SR of the semiconductor SM can be identified first, and the width DS of the range R3 can be measured. The width DS can be the maximum width of the range R3 measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). Specifically, the width DS can be the width measured on the side where the conductive layer M2 contacts the source region SR of the semiconductor SM. Then, the range RS of the source electrode SE can be defined by extending the range R3 to the left and right sides by 0.25 times the width of the range R3 (i.e., the width DS). In other words, in the cross-sectional view of transistor T1, the left and right sides of range RS can protrude from the left and right sides of range R3 by a distance of 0.25 times the width DS of range R3, respectively. In this case, range RS can have a width D4, which is 1.5 times the width DS (i.e., D4 = 1.5 * DS). Width D4 can be the maximum width of range RS measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). Width D4 can also be regarded as the width of the source electrode SE. The range RS of the source electrode SE of transistor T1 can be defined in the above manner.

[0040] According to this embodiment, the drain electrode DE of transistor T1 may have a range RD in a cross-sectional view of transistor T1, wherein the range RD of drain electrode DE can be defined by the range R2 of the portion where conductive layer M2 contacts the drain region DR of semiconductor SM. Specifically, in a cross-sectional view of transistor T1 perpendicular to the extension direction of the scan line, the range R2 of the overlapping portion of conductive layer M2 and drain region DR of semiconductor SM can be identified first, and the width DRD of range R2 can be measured. The width DRD can be the maximum width of range R2 measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). Specifically, the width DRD can be the width measured on the side where conductive layer M2 contacts drain region DR of semiconductor SM. Then, the range RD of drain electrode DE can be defined by extending range R2 to the left and right sides by 0.25 times the width of range R2 (i.e., the width DRD). In other words, in the cross-sectional view of transistor T1, the left and right sides of range RD can protrude from the left and right sides of range R2 by a distance of 0.25 times the width DRD of range R2, respectively. In this case, range RD can have a width D2, which is 1.5 times the width DRD (i.e., D2 = 1.5 * DRD). Width D2 can be the maximum width of range RD measured in a direction perpendicular to the extension direction of the scan line (i.e., direction Y). Width D2 can also be regarded as the width of the drain electrode DE. The range RD of the drain electrode DE of transistor T1 can be defined in the above manner.

[0041] After defining the ranges of the gate electrode GE, source electrode SE, and drain electrode DE of transistor T1, the aforementioned "the second opening OP2 overlaps with at least one of the drain electrode DE and source electrode SE in transistor T1" can refer to, in a top view of the electronic device ED, or in a cross-sectional view of the electronic device ED (e.g., a cross-sectional view perpendicular to the extension direction of the scan line), the projection of the second opening OP2 on the substrate SB can overlap with at least one of the projections of the drain electrode DE range RD on the substrate SB and the source electrode SE range RS on the substrate SB, or in other words, the range of the projection of the second opening OP2 on the substrate SB can cover at least one of the projections of the range RD on the substrate SB and the projections of the range RS on the substrate SB. It should be noted that the above definition of the gate electrode GE, source electrode SE, and drain electrode DE of transistor T1 can be applied to other transistors in circuit layer CL. In this disclosure, when describing other openings (e.g., openings OPE) of the insulating layer INL overlapping at least a portion of the transistor or describing one element overlapping another element, the definition of "overlap" is as above and will not be repeated here.

[0042] According to this embodiment, as shown in FIG2, the second opening OP2 may have a width D1, wherein the width D1 may be the width of the second opening OP2 measured in a direction parallel to the extension direction of the scan line (i.e., parallel to direction X). That is, the extension direction of the width D1 may be perpendicular to direction X, for example, parallel to direction Y, but is not limited thereto. Specifically, in the top view of the insulating layer INL (e.g., FIG2), the width D1 may be defined as the maximum width of the second opening OP2 measured in a direction parallel to the extension direction of the scan line, but is not limited thereto. In this case, the width D1 of the second opening OP2, the width D2 of the drain electrode DE of the transistor T1, the width D3 of the gate electrode GE of the transistor T1, and the width D4 of the source electrode SE of the transistor T1 may be widths measured in the same direction (i.e., parallel to direction X). According to this embodiment, the width D1 of the second opening OP2 can range from 15 micrometers (μm) to 45 μm (i.e., 15 μm ≤ D1 ≤ 45 μm), but is not limited thereto. In some embodiments, the width D1 of the second opening OP2 can range from 20 μm to 40 μm (i.e., 20 μm ≤ D1 ≤ 40 μm). The definition and range of the widths of other openings OPE in the insulating layer INL can refer to the width D1 of the second opening OP2 described above. When the width D1 of the second opening OP2 is less than 15 μm, the size of the second opening OP2 may be too small, thereby increasing the difficulty of overlapping with the transistor T1. When the width of the second opening OP2 is greater than 45 μm, the size of the second opening OP2 may be too large, thereby reducing the light-shielding effect of the insulating layer INL.

[0043] In some embodiments, the second opening OP2 shown in FIG2 may overlap with the gate electrode GE of transistor T1, and the width D1 of the second opening OP2 may be greater than the width D3 of the gate electrode GE of transistor T1 (i.e., D1 > D3). In some embodiments, the second opening OP2 shown in FIG2 may overlap with the source electrode SE of transistor T1, and the width D1 of the second opening OP2 may be greater than the width D4 of the source electrode SE of transistor T1 (i.e., D1 > D4). In some embodiments, the second opening OP2 shown in FIG2 may overlap with the drain electrode DE of transistor T1, and the width D1 of the second opening OP2 may be greater than the width D2 of the drain electrode DE of transistor T1 (i.e., D1 > D2). In some embodiments, the width D1 of the second opening OP2 may be greater than the sum of the widths D2, D3, and D4 (i.e., D1 > D2 + D3 + D4). In this case, the second opening OP2 may, for example, overlap simultaneously with the gate electrode GE, the source electrode SE, and the drain electrode DE of transistor T1. It should be noted that the relationship between the width D1 of the second opening OP2 and the width D3 of the gate electrode GE, the width D2 of the drain electrode DE, and the width D4 of the source electrode SE of the transistor T1 overlapping the second opening OP2 can be applied to other openings of the insulating layer INL (such as opening OPE, but not limited thereto) and the widths of the gate electrode, drain electrode, and source electrode of the transistor overlapping the opening.

[0044] Referring back to FIG1, according to this embodiment, the second opening OP2 of the insulating layer INL may have a depth DH, wherein the depth DH may be defined as the maximum vertical distance between the upper and lower surfaces of the portion of the insulating layer INL adjacent to the second opening OP2, but is not limited thereto. In some embodiments, the thickness DH may range from 4 μm to 13 μm (i.e., 4 μm ≤ DH ≤ 13 μm). In some embodiments, the thickness DH may range from 6 μm to 10 μm (i.e., 6 μm ≤ DH ≤ 10 μm).

[0045] In some embodiments, the electronic device ED may include a conductive layer ML disposed on the buffer layer BF and an insulating layer INO disposed on the conductive layer ML, but is not limited thereto. The conductive layer ML may form a capacitor cell with the conductive layer M1 or the conductive layer M2, but is not limited thereto. The insulating layer INO may include any suitable insulating material. In some embodiments, the electronic device ED may not include the insulating layer INO and the conductive layer ML. Furthermore, as shown in FIG3, in this embodiment, the semiconductor SM may be electrically connected to the semiconductor OL through a contact CT. The contact CT may be formed from any suitable conductive layer in the circuit layer CL. The features of other film layers and elements shown in FIG3 can be referred to above, and will not be repeated here.

[0046] Please refer to FIG4, which is a partial top view of an electronic device according to the third embodiment of the present disclosure. Specifically, FIG4 shows, for example, a top view of a driving circuit DI for a sub-pixel SPX. In detail, in this embodiment, an optical unit LCU, a filter layer corresponding to the optical unit LCU (one of a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3), at least one light-emitting unit LU, and a driving circuit DI (including at least one transistor) for driving the at least one light-emitting unit can be regarded as a sub-pixel SPX. In this case, the aforementioned optical units LCU1, LCU2, and LCU3 can respectively form a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX, and the three sub-pixels can form a pixel. The driving circuit DI shown in FIG4 can be the driving circuit DI for any one of the red sub-pixel SPX, the green sub-pixel SPX, and the blue sub-pixel SPX. In this embodiment, as shown in FIG4, the driving circuit DI of a sub-pixel SPX may include, for example, three transistors: a switching transistor TW, a driving transistor TD, and a sensing transistor TS, but this is not a limitation. The switching transistor TW may include a gate electrode G1, a source electrode S1, and a drain electrode DE1; the driving transistor TD may include a gate electrode G2, a source electrode S2, and a drain electrode DE2; and the sensing transistor TS may include a gate electrode G3, a source electrode S3, and a drain electrode DE3. It should be noted that the number of transistors included in the driving circuit DI shown in FIG4 is merely exemplary, and this embodiment is not limited thereto. In other embodiments, depending on the design of the driving circuit DI, the driving circuit DI may include any suitable number of transistors.

[0047] The following are several examples illustrating the overlap between the opening OPE of the insulating layer INL and the transistor.

[0048] In some embodiments, an opening OPE in the insulating layer INL (which may be the second opening OP2 described above, but is not limited thereto) may overlap at least a portion of a transistor in the top view of the electronic device ED. For example, as shown in FIG4, an opening OPE in the insulating layer INL may overlap the gate electrode G2, source electrode S2, and drain electrode DE2 of the driving transistor TD, i.e., overlap the driving transistor TD. In some embodiments, an opening OPE in the insulating layer INL may overlap at least one of the source electrode S2 and drain electrode DE2 of the driving transistor TD. It should be noted that FIG4 only shows a portion of the insulating layer INL by way of example, and the insulating layer INL may include other openings OPE overlapping at least a portion of the switching transistor TW and / or the sensing transistor TS.

[0049] In some embodiments, an opening OPE in the insulating layer INL (which may be the second opening OP2 described above, but is not limited thereto) may overlap at least a portion of a plurality of transistors in the top view of the electronic device ED. For example, an opening OPE in the insulating layer INL may simultaneously overlap the gate electrode G2, source electrode S2, and drain electrode DE2 of the driving transistor TD, the gate electrode G1, source electrode S1, and drain electrode DE1 of the switching transistor TW, and the gate electrode G3, source electrode S3, and drain electrode DE3 of the sensing transistor TS, but is not limited thereto. In some embodiments, an opening OPE in the insulating layer INL may overlap at least a portion of any two of the switching transistor TW, the driving transistor TD, and the sensing transistor TS. In some embodiments, an opening OPE in the insulating layer INL may overlap a plurality of transistors in a plurality of driving circuits DI.

[0050] In some embodiments, a transistor may overlap with multiple openings OPE in the top view of the electronic device ED. Here, "a transistor overlapping with multiple openings OPE" may include, for example, embodiments where the source electrode SE (or drain electrode DE) of the transistor overlaps with multiple openings OPE, and embodiments where the source electrode SE and drain electrode DE of the transistor overlap with different openings OPE. For example, in a drive circuit DI, the source electrode S1 and drain electrode DE1 of a switching transistor TW may overlap with different openings OPE, the source electrode S2 and drain electrode DE2 of a driving transistor TD may overlap with different openings OPE, and the source electrode S3 and drain electrode DE3 of a sensing transistor TS may overlap with different openings OPE, but this is not a limitation.

[0051] The overlapping manner of the opening OPE in the insulating layer INL and the transistor described above can be applied to the various embodiments and variations disclosed herein. It should be noted that different openings OPE in the insulating layer INL can overlap the transistor in different ways.

[0052] Please refer to FIG5, which is a partial top view of an electronic device according to the fourth embodiment of the present disclosure. One of the main differences between the structure shown in FIG5 and the structure shown in FIG4 is that the driving transistor TD, the switching transistor TW, and the sensing transistor TS shown in FIG5 each further include a semiconductor OL. According to this embodiment, the opening OPE of the insulating layer INL can overlap with the semiconductor OL of the transistor in the top view direction of the electronic device ED. In some embodiments, one opening OPE of the insulating layer INL (which may be the second opening OP2 mentioned above, but is not limited thereto) can overlap with the semiconductor OL of one transistor in the top view direction of the electronic device ED. For example, as shown in FIG5, one opening OPE of the insulating layer INL can overlap with the semiconductor OL of the driving transistor TD. In some embodiments, one opening OPE of the insulating layer INL (which may be the second opening OP2 mentioned above, but is not limited thereto) can overlap with the semiconductor OL of multiple transistors in the top view direction of the electronic device ED. For example, one opening OPE of the insulating layer INL can simultaneously overlap with the semiconductor OL of the driving transistor TD, the semiconductor OL of the switching transistor TW, and the semiconductor OL of the sensing transistor TS. In some embodiments, an opening OPE in the insulating layer INL may simultaneously overlap with the semiconductor OLs of multiple transistors in multiple driving circuits DI. In some embodiments, the semiconductor OL of a transistor may overlap with multiple opening OPEs in the top view of the electronic device ED. For example, the semiconductor OL of the driving transistor TD, the semiconductor OL of the switching transistor TW, and the semiconductor OL of the sensing transistor TS may each overlap with more than one opening OPE, but this is not a limitation. The above-described overlap method of the opening OPE of the insulating layer INL with the semiconductor OL of the transistor can be applied to various embodiments and variations of this disclosure. It should be noted that different opening OPEs may overlap with the semiconductor OLs in different ways.

[0053] Please refer to FIG6, which is a partial top view of an electronic device according to the fifth embodiment of the present disclosure. Specifically, FIG6 shows the arrangement of a plurality of pixels PX in the electronic device ED. In this embodiment, each pixel PX may be composed of three sub-pixels (i.e., the sub-pixels SPX mentioned above), and the three sub-pixels may respectively include optical unit LCU1, optical unit LCU2, and optical unit LCU3, but are not limited thereto. In other embodiments, the number of sub-pixels (or optical units LCU) included in each pixel PX may be determined according to the design of the electronic device ED. In this embodiment, the range of a pixel PX may be defined as follows. First, in a horizontal direction (e.g., direction X), two adjacent optical units LCUs of the same color located in two adjacent pixels PX can be identified. Here, "two adjacent optical units LCUs" may refer to two optical units LCUs excluding other optical units LCUs between them. For example, in Figure 6, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX2, which is adjacent to pixel PX1 and located to the left of pixel PX1, can be two adjacent optical units LCUs of the same color. Similarly, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3, which is adjacent to pixel PX1 and located to the right of pixel PX1, can also be two adjacent optical units LCUs of the same color. After confirming the above-mentioned "two adjacent optical units LCUs of the same color", a virtual straight line passing through the midpoint of the two optical units LCU can be defined. Specifically, taking pixel PX1 as an example, the optical unit LCU2 in pixel PX1 can define a virtual straight line VL1 with another optical unit LCU2 located to its left (i.e., the optical unit LCU2 in pixel PX2), wherein the virtual straight line VL1 can extend along a vertical direction (e.g., direction Y) perpendicular to the horizontal direction and pass through the midpoint of the optical units LCU2 in pixel PX1 and the optical units LCU2 in pixel PX2. In this scenario, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX2 can have a horizontal distance F1. The distances from the virtual line VL1 to the optical unit LCU2 in pixel PX1 and from the virtual line VL1 to the optical unit LCU2 in pixel PX2 can both be half of the distance F1. Similarly, the optical unit LCU2 in pixel PX1 can also define a virtual line VL2 with another optical unit LCU2 located to its right (i.e., the optical unit LCU2 in pixel PX3). The virtual line VL2 can extend vertically and pass through the midpoint between the optical units LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3.In this scenario, the optical unit LCU2 in pixel PX1 and the optical unit LCU2 in pixel PX3 can have a horizontal distance F2, while the distances from the virtual line VL2 to the optical unit LCU2 in pixel PX1 and from the virtual line VL2 to the optical unit LCU2 in pixel PX3 can both be half of the distance F2. In other words, a pixel PX can define a virtual line with two other pixels PX located to its left and right. The distances F1 and F2 can be the same or different, and this embodiment is not limited to this. Furthermore, in the vertical direction, the two optical units LCUs with the minimum vertical distance located in two adjacent pixels PX can be identified first. For example, in Figure 6, the optical unit LCU2 of pixel PX1 and the optical unit LCU3 of pixel PX4, which is adjacent to and above pixel PX1, can be the optical units LCUs with the minimum vertical distance located in two adjacent pixels PX. Similarly, the optical unit LCU3 of pixel PX1 and the optical unit LCU2 of pixel PX5, which is adjacent to and below pixel PX1, can also be optical units LCUs located in two adjacent pixels PX with minimum vertical distance. After confirming the above-mentioned "two optical units LCUs located in two adjacent pixels PX with minimum vertical distance", a virtual straight line passing through the midpoint of the two optical units LCU can be defined. Specifically, taking pixel PX1 as an example, the optical unit LCU2 in pixel PX1 and the optical unit LCU3 in pixel PX4, which is above pixel PX1, can define a virtual straight line HL1, where the virtual straight line HL1 can extend horizontally and pass through the midpoint of the optical unit LCU2 in pixel PX1 and the optical unit LCU3 in pixel PX4. In this scenario, the optical unit LCU2 in pixel PX1 and the optical unit LCU3 in pixel PX4 can have a vertical distance K1, and the distances from the virtual line HL1 to the optical unit LCU2 in pixel PX1 and from the virtual line HL1 to the optical unit LCU3 in pixel PX4 can both be half of distance K1. Similarly, the optical unit LCU3 in pixel PX1 can also define a virtual line HL2 with the optical unit LCU2 in pixel PX5 located below pixel PX1, where the virtual line HL2 can extend horizontally and pass through the midpoint between the optical units LCU3 in pixel PX1 and LCU2 in pixel PX5. In this scenario, the optical unit LCU3 in pixel PX1 and the optical unit LCU2 in pixel PX5 can have a vertical distance K2, and the distances from the virtual line HL2 to the optical unit LCU3 in pixel PX1 and from the virtual line HL2 to the optical unit LCU2 in pixel PX5 can both be half of distance K2. In other words, a pixel PX can define a virtual straight line with two other pixels PX located above and below it.Distances K1 and K2 may be the same or different, and this embodiment is not limited thereto. According to this embodiment, after defining two virtual lines VL1 and VL2 and two virtual lines HL1 and HL2 based on a pixel PX, the region of pixel PX can be defined as the region enclosed by the two virtual lines VL1 and VL2 and the two virtual lines HL1 and HL2, but is not limited thereto. For example, in Figure 6, the region of pixel PX1 can be the region enclosed by virtual lines VL1, VL2, HL1, and HL2. Thus, the range of the region of pixel PX can be defined. It should be noted that the above definition of the region of pixel PX is merely exemplary, and this disclosure is not limited thereto. In other embodiments, the region of pixel PX can be defined in any suitable manner according to the arrangement of the pixels PX and / or the setting position of the optical unit LCU.

[0054] In this embodiment, the region of a pixel PX may include a first region A1 and a second region A2, wherein the first region A1 corresponds to an optical unit LCU, while the second region A2 does not correspond to an optical unit LCU. In other words, the first region A1 can be defined as the part of the region of a pixel PX that corresponds to the optical unit LCU, while the second region A2 can be defined as another part of the region of a pixel PX that does not correspond to the optical unit LCU, that is, the second region A2 can be any part of the region of a pixel PX other than the first region A1. The first region A1 may include three parts, corresponding to optical units LCU1, LCU2 and LCU3 in the pixel PX respectively, but is not limited thereto. According to this embodiment, in the top view direction of the electronic device ED, the number of transistors overlapping with the first region A1 in the circuit layer CL may be less than the number of transistors overlapping with the second region A2. The phrase "transistor overlapping with first region A1 (or second region A2)" here refers to at least a portion of the transistor (e.g., at least one of the source electrode and drain electrode) overlapping first region A1 (or second region A2). For example, in the top view of an electronic device ED, the circuit layer CL may include X1 transistors overlapping first region A1 of a pixel PX and Y1 transistors overlapping second region A2 of the same pixel PX, where X1 may be less than Y1. The aforementioned relationship between the number of transistors overlapping first region A1 and second region A2 can be applied to each pixel PX. Furthermore, as described above, the insulating layer INL may include a first opening OP1 in which an optical unit LCU is disposed and an opening OPE in which no optical unit LCU is disposed. In this case, the first opening OP1 may correspond to first region A1, and the opening OPE may correspond to second region A2. Specifically, the first region A1 of a pixel PX may correspond to three first openings OP1, respectively used to dispose of optical units LCU1, LCU2, and LCU3. In some embodiments, the second region A2 of a pixel PX may correspond to one opening OPE. In this case, in the top view of the electronic device ED, the total number of transistors overlapping the three first openings OP1 corresponding to the first region A1 of a pixel PX may be less than the number of transistors overlapping the opening OPE corresponding to the second region A2 of the pixel PX. In some embodiments, the second region A2 of a pixel PX may correspond to a plurality of openings OPE. In this case, in the top view of the electronic device ED, the total number of transistors overlapping the three first openings OP1 corresponding to the first region A1 of a pixel PX may be less than the total number of transistors overlapping the plurality of openings OPE corresponding to the second region A2 of the pixel PX.In some embodiments, the total area of ​​the semiconductor (e.g., semiconductor SM) of the transistor overlapping the three first openings OP1 corresponding to the first region A1 of a pixel PX may be smaller than the total area of ​​the semiconductor (e.g., semiconductor SM) of the transistor overlapping the plurality of openings OPE corresponding to the second region A2 of the pixel PX. The features of this embodiment can be applied to other embodiments and variations disclosed herein.

[0055] Please refer to Figures 7 and 8. Figure 7 is a partial top view of an electronic device according to a sixth embodiment of the present disclosure, and Figure 8 is a partial top view of an electronic device according to a variation of the sixth embodiment of the present disclosure. Specifically, Figures 7 and 8 show top views of a driving circuit DI for a sub-pixel SPX. The structure of the driving circuit DI shown in Figures 7 and 8 can be referred to Figures 4 and 5 and the related content above, and will not be repeated here. According to this embodiment, in the driving circuit DI of a sub-pixel SPX, the number of transistors superimposed on the first opening OP1 in which an optical unit LCU is disposed may be less than the number of transistors superimposed on the opening OPE in which no optical unit LCU is disposed. Specifically, in the top view direction of the electronic device ED, the plurality of transistors in the driving circuit DI of a sub-pixel SPX may include a first portion of transistors superimposed on the first opening OP1 and a second portion of transistors superimposed on the opening OPE, wherein the number of the first portion of transistors of the plurality of transistors may be different from the number of the second portion of transistors of these transistors. In one embodiment, the number of the first portion of transistors of these transistors may be less than the number of the second portion of transistors of these transistors. In some embodiments, as shown in FIG7, different numbers of transistors in the driving circuit DI of a sub-pixel SPX may overlap a first opening OP1 and an opening OPE. In this case, the plurality of transistors in the driving circuit DI of the sub-pixel SPX may include a first portion of transistors overlapping the first opening OP1 and a second portion of transistors overlapping the opening OPE, wherein the number of the first portion of transistors is less than the number of the second portion of transistors. For example, in FIG7, the first portion of transistors may include one transistor (i.e., sensing transistor TS) overlapping the first opening OP1, while the second portion of transistors may include two transistors (i.e., driving transistor TD and switching transistor TW) overlapping the opening OPE, but this is not a limitation. The opening OPE here may be the second opening OP2 mentioned above. In other words, in this embodiment, the first opening OP1 may overlap the first portion of transistors among the plurality of transistors, and the second opening OP2 may overlap the second portion of transistors among these transistors, and the number of the first portion of transistors and the number of the second portion of transistors may be different. For example, the number of first-part transistors in a transistor may be less than the number of second-part transistors in a transistor. In some embodiments, as shown in FIG8, a plurality of transistors in the driving circuit DI of a sub-pixel SPX may overlap a first opening OP1 and a plurality of openings OPE. In this case, the plurality of transistors in the driving circuit DI of the sub-pixel SPX may include first-part transistors overlapping the first opening OP1 and second-part transistors overlapping the openings OPE, wherein the number of first-part transistors in these transistors is less than the number of second-part transistors in these transistors.The phrase "transistor including a second portion of transistor overlapping the openings OPE" here can refer to a second portion of transistor overlapping a region corresponding to the openings OPE. For example, in FIG8, the first portion of transistor may include one transistor (i.e., sensing transistor TS) overlapping the first opening OP1, while the second portion of transistor may include two transistors (i.e., driving transistor TD and switching transistor TW) overlapping a plurality of openings OPE (e.g., five in FIG8, but not limited thereto), but not limited thereto. It should be noted that the number of transistors in the driving circuit DI of a sub-pixel SPX can be determined according to the design of the driving circuit DI, and is not limited to the above. In some embodiments, the driving circuit DI of a sub-pixel SPX may include X1 transistors, which include Y1 transistors (i.e., the first portion of transistors) overlapping the first opening OP1 and Z1 transistors (i.e., the second portion of transistors) overlapping at least one opening OPE, wherein X1 is the sum of Y1 and Z1, and Y1 may be less than Z1. The features of this embodiment can be applied to other embodiments and variations disclosed herein.

[0056] Please refer to FIG9, which is a partial cross-sectional schematic diagram of an electronic device according to the seventh embodiment of the present disclosure. Specifically, FIG9 shows a portion of the electronic device ED shown in FIG1, including an insulating layer INL and the underlying film layer and components. In detail, the structure shown in FIG9 can be, for example, the structure formed after the insulating layer INL and the optical unit LCU are provided during the manufacturing process of the electronic device ED. According to this embodiment, since the insulating layer INL includes an opening OPE in addition to the first opening OP1 of the optical unit LCU, a special process can be performed on the components or film layer under the insulating layer INL through the opening OPE after the insulating layer INL and the optical unit LCU are provided.

[0057] In some embodiments, since the opening OPE can overlap at least a portion of the transistor in the circuit layer CL in the top view of the electronic device ED, the position of a specific transistor can be marked through the opening OPE after the insulating layer INL and the optical unit LCU are set. For example, when a defective transistor is found in the transistor detection step, the position of the defective transistor can be marked to facilitate the subsequent repair process of the defective transistor. In this embodiment, the position of the transistor can be marked, for example, by laser dot positioning, but is not limited thereto. Specifically, as shown in FIG9, if a defective transistor T1 is detected in the transistor detection step, laser light can be emitted through the laser light emitter LR1, wherein the laser light can overlap the opening OP2 (or opening OPE) of the transistor T1 and leave a mark at any suitable position corresponding to the transistor T1 (e.g., on the surface of the insulating layer I2 of the transistor T1, but is not limited thereto). In other embodiments, the position of the transistor can be marked by computer coordinate positioning, ink color positioning or other suitable methods. Furthermore, after marking the defective transistor, a repair process can be performed on the defective transistor through the opening OPE. For example, as shown in Figure 9, after marking the position of transistor T1 in the above manner, laser light can be emitted through laser light emitter LR2, wherein the laser light can pass through the opening OP2 and be directed to transistor T1 to repair transistor T1.

[0058] In some embodiments, the opening process can also be performed on the film layer or component under the insulating layer INL through the opening OPE. For example, as shown in FIG9, the laser emitter LR3 can emit laser light, wherein the laser light can pass through the opening OPE and form a perforation V1 in the light-emitting layer LEL. The characteristic description of the perforation V1 can be referred to above, and will not be repeated here. In other words, the perforation V1 can overlap or at least partially overlap the opening OPE of the insulating layer INL in the top view of the electronic device ED. FIG1 also shows the characteristic of the perforation V1 overlapping the opening OPE. Since the laser light used to form the perforation V1 can bypass the insulating layer INL (or pass through the material of the insulating layer INL), the possibility of the material of the insulating layer INL being vaporized at high temperature and contaminating due to laser light irradiation can be reduced. It should be noted that the opening OPE is not limited to forming the above-mentioned perforation V1, but can also be used to perform the opening process of other film layers. In this case, the perforation structure formed through the opening OPE can overlap or at least partially overlap the opening OPE in the top view of the electronic device ED. In some embodiments, the electronic device ED may include a video wall display device and may form a glass via (TGV) through an opening OPE, thereby electrically connecting different electronic devices ED.

[0059] In existing electronic devices, when marking the location of defective transistors, repairing defective transistors, or forming perforations in the film layer under the optical unit after setting up an optical unit, the laser light used in the above processes is affected by the barrier structure when passing through the barrier structure of the optical unit. For example, the laser light may be blocked or absorbed by the material of the barrier structure, thereby increasing the difficulty of the above processes. Alternatively, the barrier structure may affect the difficulty of observing the location marking of the transistor. On the other hand, since the insulating layer INL of the electronic device ED disclosed herein may include an open OPE without an optical unit LCU, and the above processes can be performed through the open OPE, the influence of the insulating layer INL material on the above processes can be reduced. For example, the possibility of laser light being blocked or absorbed by the insulating layer INL material can be reduced. In this way, the process yield of the electronic device ED can be improved. It should be noted that the open OPE can also be used for other suitable processes and is not limited to the above processes.

[0060] Furthermore, although not shown in FIG9, in this embodiment, the semiconductor OL can be disposed in the peripheral region NDA and the active region DA. In the top view of the electronic device ED, the number of openings in the insulating layer INL overlapped by the semiconductor OL in the peripheral region NDA is different from the number of openings in the insulating layer INL overlapped by the semiconductor OL in the active region DA. The openings in the insulating layer INL here may include a first opening OP1 in which an optical unit LCU is disposed and an opening OPE in which no optical unit LCU is disposed. Specifically, the number of openings in the insulating layer INL overlapped by the semiconductor OL in the peripheral region NDA may be less than the number of openings in the insulating layer INL overlapped by the semiconductor OL in the active region DA, but is not limited thereto.

[0061] Please refer to FIG10, which is a partial cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present disclosure. According to this embodiment, the electronic device ED may further include a photosensor OD, wherein the photosensor OD may be disposed between an insulating layer INL and a substrate SB. For example, as shown in FIG10, the photosensor OD may be disposed on an insulating layer IN5 and located between an insulating layer IN5 and an insulating layer OIL, but is not limited thereto. In other embodiments, the photosensor OD may be disposed at any suitable location between the insulating layer INL and the substrate SB. According to this embodiment, in the top view of the electronic device ED, at least a portion of the photosensor OD may overlap with at least one opening OPE of the insulating layer INL that is not provided with an optical unit LCU. For example, as shown in FIG10, in the top view of the electronic device ED, one of the openings OPE of the insulating layer INL (e.g., the second opening OP2, but not limited thereto) may overlap with at least a portion of the photosensor OD. In other embodiments, the photosensor OD may overlap with a plurality of openings OPE. The photosensor OD may include any suitable photosensing element capable of receiving visible or non-visible light. The photosensitive element OD in this embodiment may include, for example, an organic photodiode (OPD), but is not limited thereto. In some embodiments, the photosensitive element OD may be formed within the electronic device ED through an opening OPE in the insulating layer INL, for example, an organic photodiode element may be formed within the electronic device ED through the opening OPE, but is not limited thereto. In some embodiments, the photosensitive element OD may first be formed outside the electronic device ED, and then transferred into the electronic device ED through the opening OPE. The photosensitive element OD may be electrically connected to the circuit layer CL, for example, electrically connected to a transistor in the circuit layer CL, thereby driving the photosensitive element OD through the transistor. In this embodiment, the photosensitive element OD may serve as a fingerprint sensing element, for example, but is not limited thereto. For example, as shown in FIG10, light L1 emitting a self-emissive unit LU may be reflected by an object OB (e.g., a user's finger) and received by the photosensitive element OD after passing through the opening OP2, thereby achieving the function of fingerprint recognition. In other embodiments, the photosensitive element OD may include other suitable sensing elements depending on the design of the electronic device ED.

[0062] According to this embodiment, the portions of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 disposed within the opening OPE overlapping at least a portion of the photosensor OD may each include a filter opening. Specifically, as shown in FIG10, the second opening OP2 of the insulating layer INL may overlap at least a portion of the photosensor OD in the top view direction of the electronic device ED, and the portion of the first filter layer CF1 disposed within the second opening OP2 may include the first filter opening OF1, the portion of the second filter layer CF2 disposed within the second opening OP2 may include the second filter opening OF2, and the portion of the third filter layer CF3 disposed within the second opening OP2 may include the third filter opening OF3. The first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 may at least partially overlap each other in the top view direction of the electronic device ED. Furthermore, the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3 may overlap at least a portion of the photosensor OD in the top view direction of the electronic device ED. In short, taking the structure shown in Figure 10 as an example, the electronic device ED may include a first filter layer CF1 and a second filter layer CF2 disposed on the insulating layer INL. A portion of the first filter layer CF1 is disposed in the second opening OP2 and has a first filter opening OF1, and a portion of the second filter layer CF2 is disposed in the second opening OP2 and has a second filter opening OF2. In the top view of the electronic device ED, the first filter layer CF1 may overlap with the optical unit LCU1, while the second filter layer CF2 may not overlap with the optical unit LCU1. The optical layer OC may be filled with the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3, but is not limited thereto. By providing filter openings in the above-mentioned filter layers, the influence of these filter layers on the function of the photosensor OD can be reduced. Specifically, by forming first filter openings OF1, second filter openings OF2, and third filter openings OF3 overlapping at least a portion of the photosensor OD in the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3, light (e.g., light L1) can pass through the first filter openings OF1, the second filter openings OF2, and the third filter openings OF3 into the photosensor OD without being blocked or absorbed by the first filter layer CF1, the second filter layer CF2, and / or the third filter layer CF3. This reduces the possibility that the photosensor OD may be unable to receive light signals, thus affecting its function. In some embodiments, as shown in FIG10, insulating layers IN7, IN8, and IN9 may each include an opening corresponding to the first filter opening OF1, the second filter opening OF2, and the third filter opening OF3, and the optical layer OC may fill these openings.

[0063] It should be noted that the electronic device ED may also include other types of sensors overlapping the opening OPE, and is not limited to the light sensor OD described above. For example, the electronic device ED may include a piezoelectric sensor, a haptic feedback device, a sound sensing element, a charge-coupled device (CCD), an antenna element, or other suitable elements, wherein at least a portion of these elements or devices may overlap at least one of the opening OPE.

[0064] In some embodiments, one opening OPE of the insulating layer INL may simultaneously overlap with multiple elements, such as simultaneously overlapping with a transistor and a photosensor OD. For example, as shown in FIG10, a second opening OP2 of the insulating layer INL may simultaneously overlap with the photosensor OD and the transistor T1 in the top view of the electronic device ED. In some embodiments, one opening OPE of the insulating layer INL may overlap with one of the transistor and the photosensor OD, while another opening OPE of the insulating layer INL may overlap with the other of the transistor and the photosensor OD. For example, referring back to FIG2, in the top view of the electronic device ED, one opening OPE of the insulating layer INL (e.g., the second opening OP2) may overlap with the transistor T1, while another opening OPE of the insulating layer INL (e.g., the third opening OP3) may overlap with at least a portion of the photosensor OD.

[0065] Please refer to FIG11, which is a partial cross-sectional schematic diagram of an electronic device according to the ninth embodiment of the present disclosure. According to this embodiment, the electronic device ED may further include a pattern layer PPL disposed on a substrate SB. The pattern layer PPL may be disposed, for example, in a circuit layer CL, but is not limited thereto. The pattern layer PPL may be formed through a conductive layer in the circuit layer CL, but is not limited thereto. For example, as shown in FIG11, the pattern layer PPL may be formed by conductive layers M1 and / or conductive layers M2. The pattern layer PPL may be formed by one or more conductive layers. In this case, the pattern layer PPL may share the same material as the conductive layers M1 and / or conductive layers M2 or be formed by the same process, thereby reducing manufacturing costs. In the top view direction of the electronic device ED, at least a portion of the pattern layer PPL may overlap at least one opening OPE of the insulating layer INL. In other words, the pattern layer PPL may be disposed corresponding to the opening OPE. In some embodiments, the pattern layer PPL may serve as an alignment element. Specifically, in the manufacturing process of electronic devices (EDs), the pattern layer (PPL) can assist in positioning the film layer or components, thereby reducing misalignment. For example, when using a small-area mask in the manufacturing process of an electronic device ED, the pattern layer (PPL) can assist in positioning the mask, thereby reducing mask misalignment, but this is not a limitation. In some embodiments, the pattern layer (PPL) may include a code pattern, through which the user can obtain specific information, including but not limited to position information on the electronic device ED. For example, as shown in Figure 11, the user can use a stylus TU to read the code (i.e., the pattern layer (PPL)) through the opening (OPE), thereby obtaining the position information on the electronic device ED corresponding to the stylus TU, but this is not a limitation. In detail, the stylus TU can emit a light signal, which can reach the pattern layer (PPL) through the opening (OPE), thereby obtaining the pattern information of the pattern layer (PPL) (or code). Here, the "light signal of the stylus TU" can include visible light signals and non-visible light signals (e.g., infrared light signals, but not limited to these). An electronic device (ED) may include, for example, a plurality of patterned layers (PPLs) disposed at different locations within the ED. Each PPL can serve as a pattern to provide information about its location, and each PPL can overlap at least one opening (OPE) of an insulating layer (INL). In some embodiments, the PPL can simultaneously serve as a alignment element and a pattern. For example, the PPL can serve as an alignment element during the manufacturing process of the ED and as a pattern in subsequent use of the ED. According to this embodiment, since the PPL can overlap the opening (OPE), the influence of the insulating layer (INL) on the function of the PPL can be reduced. Specifically, when the PPL serves as an alignment element, overlapping the PPL with the opening (OPE) reduces the likelihood that the location of the PPL cannot be determined.Alternatively, when the pattern layer PPL is used as a graphic code, overlapping the pattern layer PPL with the opening OPE can reduce the possibility of the graphic code being unreadable due to the absorption of the light signal emitted by the stylus TU by the insulating layer INL.

[0066] According to this embodiment, as shown in FIG11, the portions of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 disposed within the opening OPE overlapping at least a portion of the pattern layer PPL can be removed. In this case, the pattern layer PPL may not overlap the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 in the top view direction of the electronic device ED. Through the above design, the influence of the filter layers on the function of the pattern layer PPL can be reduced. For example, by removing the portion of the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 overlapping the pattern layer PPL, the possibility of the light signal emitted by the stylus TU being blocked or absorbed by the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3, resulting in failure to read the pattern code, can be reduced.

[0067] It should be noted that, although not shown in FIG11, the patterned layer PPL may be formed of other materials, and the patterned layer PPL is not limited to being disposed in the circuit layer CL. For example, in some embodiments, the patterned layer PPL may be disposed in one of the openings OPE of the insulating layer INL, and the patterned layer PPL may include a filter material that allows infrared light to pass through, a fluorescent material, a quantum dot material, or other suitable material.

[0068] Please refer to FIG12, and also to FIG1. ​​FIG12 is a schematic flowchart of a method for manufacturing an electronic device according to the first embodiment of this disclosure. According to this embodiment, the method M100 for manufacturing the electronic device ED may include the following steps:

[0069] S100: A substrate is provided, and a circuit layer is disposed on the substrate;

[0070] S101: Forming light-emitting units on the circuit layer;

[0071] S102: Form an encapsulation layer on the light-emitting unit;

[0072] S103: Perform the inspection procedure;

[0073] S104: An insulating layer is formed on the encapsulation layer, and a plurality of openings are formed in the insulating layer;

[0074] S105: An optical unit is provided in a portion of a plurality of openings in the insulating layer;

[0075] S106: Perform a laser process;

[0076] S107: A functional layer is formed on the insulating layer and the optical unit;

[0077] S108: A filter layer is formed on the functional layer;

[0078] S109: An optical layer is formed on the filter layer to form an electronic panel, and a cutting process is performed;

[0079] S110: Forming a capping layer on the optical layer; and

[0080] S111: An optical film is formed on the coating layer.

[0081] The following details each step of the manufacturing method M100 for the electronic device ED.

[0082] According to this embodiment, the manufacturing method M100 of the electronic device ED first includes step S100: providing a substrate SB and forming a circuit layer CL on the substrate SB. Specifically, after providing the substrate SB, a structure formed by stacking conductive and insulating layers can be formed on the substrate SB, thereby forming components in the circuit layer CL, such as transistors. The detailed structure of the substrate SB and the circuit layer CL can be referred to FIG1 and the relevant content above, and will not be described again.

[0083] Next, the manufacturing method M100 may include step S101: forming a light-emitting unit LU on the circuit layer CL. For example, as shown in FIG1, an encapsulation layer (i.e., an insulating layer IN5) may be formed on the circuit layer CL first, and an electrode E1, a light-emitting layer LEL, and an electrode E2 may be sequentially disposed on the encapsulation layer to form the light-emitting unit LU, but this is not a limitation. It should be noted that after the electrode E1 is disposed, an insulating layer IN6 may be disposed on the electrode E1 first, and then the light-emitting layer LEL may be disposed, but this is not a limitation.

[0084] Next, the manufacturing method M100 may include step S102: forming an encapsulation layer on the light-emitting unit LU. According to this embodiment, the encapsulation layer may include the structure shown in FIG1, which is formed by stacking insulating layer IL1, insulating layer OIL and insulating layer IL2. For example, the encapsulation layer may be formed by sequentially providing insulating layer IL1, insulating layer OIL and insulating layer IL2 on electrode E2.

[0085] Next, the manufacturing method M100 may include step S103: performing an inspection procedure. Specifically, after the encapsulation layer is set, an inspection procedure may be performed on specific components (e.g., light-emitting unit LU, transistor, etc.) in the formed structure.

[0086] Next, the manufacturing method M100 may include step S104: forming an insulating layer INL on the encapsulation layer and forming a plurality of openings in the insulating layer INL. Specifically, as shown in FIG1, an insulating layer INL may be formed on the encapsulation layer, and a plurality of openings (including a first opening OP1 and an opening OPE) may be formed in the insulating layer INL.

[0087] Next, the manufacturing method M100 may include step S105: setting an optical unit LCU in a portion of a plurality of openings in the insulating layer INL. Specifically, as shown in FIG1, each of the optical units LCU (including the aforementioned optical units LCU1, LCU2, and LCU3) can be set in one opening in the plurality of openings forming the insulating layer INL. The opening in which the optical unit LCU is set may be the aforementioned first opening OP1, while the opening in which the optical unit LCU is not set may be the aforementioned opening OPE.

[0088] Next, the manufacturing method M100 may include step S106: performing a laser process. Specifically, after setting the optical unit LCU, a laser process may be performed on the film layer or element below the insulating layer INL through the aperture OPE. In some embodiments, the laser process includes repairing defective transistors with laser light through the aperture OPE. In some embodiments, the laser process includes creating an aperture in a specific film layer (e.g., the light-emitting layer LEL, but not limited thereto) with laser light through the aperture OPE.

[0089] Next, the manufacturing method M100 may include step S107: forming a functional layer on the insulating layer and the optical unit. The functional layer here may be the insulating layer IN8 shown in FIG. 1. As described above, the insulating layer IN8 may include, but is not limited to, a material with a refractive index lower than that of other organic layers in the electronic device ED. In some embodiments, the insulating layer IN8 may also include hollow particles filled in the organic material layer.

[0090] Next, the manufacturing method M100 may include step S108: forming a filter layer on the functional layer. Specifically, after sequentially setting insulating layers IN7, IN8, and IN9, a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 may be set on insulating layer IN9 to form a filter layer structure CFL. It should be noted that the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may be patterned so that the portion of the filter layer structure CFL corresponding to an optical unit LCU may only include a filter layer with the same color as the light after passing through the optical unit LCU.

[0091] Next, the manufacturing method M100 may include step S109: forming an optical layer OC on the filter layer and performing a cutting process. Specifically, after forming the filter layer structure CFL, the optical layer OC can be set on the filter layer structure CF. Afterwards, a cutting process can be performed on the formed structure to divide the formed structure into a plurality of electronic panels.

[0092] Next, the manufacturing method M100 may include step S110: forming a cover layer CO on the optical layer OC, and step S111: forming an optical film on the cover layer CO. Specifically, after setting the optical layer OC and cutting out a plurality of electronic panels, an adhesive layer AD may be set on the optical layer OC of one electronic panel, and a cover layer CO may be set on the adhesive layer AD, thereby attaching the cover layer CO to the electronic panel. Afterwards, an optical film, such as an anti-reflective layer AR as shown in FIG1, may be set on the cover layer CO to form an electronic device ED, thereby improving the light emission effect of the electronic device ED.

[0093] It should be noted that the manufacturing method M100 of the electronic device ED may also include other suitable steps, and is not limited to the steps described above.

[0094] Please refer to Figures 13 and 14. Figure 13 is a partial cross-sectional schematic diagram of an electronic device according to the tenth embodiment of this disclosure, and Figure 14 is a flowchart illustrating a method for manufacturing the electronic device according to the tenth embodiment of this disclosure. According to this embodiment, the method M200 for manufacturing the electronic device ED may include the following steps:

[0095] S200: A first substrate is provided, and a circuit layer is disposed on the first substrate;

[0096] S201: Forming light-emitting units on the circuit layer;

[0097] S202: Form an encapsulation layer on the light-emitting unit;

[0098] S203: Perform the inspection procedure;

[0099] S204: An insulating layer is formed on the encapsulation layer, and a plurality of openings are formed in the insulating layer;

[0100] S205: An optical unit is provided in a portion of a plurality of openings in the insulating layer;

[0101] S206: Perform a laser process;

[0102] S207: Provide a second substrate and provide a filter layer on the second substrate;

[0103] S208: Set a functional layer on the filter layer;

[0104] S209: A sealing layer and a filler layer are formed on the first substrate;

[0105] S210: Align and bond the first substrate and the second substrate;

[0106] S211: Perform the cutting process; and

[0107] S212: An optical film is disposed on the second substrate.

[0108] The following details each step of the manufacturing method M200 for the electronic device ED.

[0109] According to this embodiment, the manufacturing method M200 of the electronic device ED may include a two-substrate process. Specifically, steps S200 to S206 in the manufacturing method M200 may be the process of the first substrate structure SS1 shown in FIG. 13, while steps S207 to S208 in the manufacturing method M200 may be the process of the second substrate structure SS2 shown in FIG. 13. After forming the first substrate structure SS1 and the second substrate structure SS2, the first substrate structure SS1 and the second substrate structure SS2 may be bonded together to form the electronic device ED.

[0110] The fabrication process of the first substrate structure SS1 may first include step S200: providing a first substrate SB and setting a circuit layer CL on the first substrate SB. Specifically, as shown in FIG13, the first substrate SB may be the substrate SB of FIG1, and the circuit layer CL may be set on the first substrate SB. The detailed structure of the first substrate SB and the circuit layer CL can be referred to above, and therefore will not be repeated here.

[0111] Next, the fabrication process of the first substrate structure SS1 may include steps S201 to S206, the details of which can be referred to the contents of steps S101 to S106 above, and will not be repeated here. After completing step S206, the first substrate structure SS1 can be formed. The structural features of the first substrate structure SS1 can be referred to the partial structure of the electronic device ED shown in FIG1, and will not be repeated here.

[0112] The fabrication process of the second substrate structure SS2 may first include step S207: providing a second substrate SB1 and forming a filter layer on the second substrate SB1. Specifically, as shown in FIG13, the second substrate SB1 may be provided first, and a first filter layer CF1, a second filter layer CF2, and a third filter layer CF3 may be formed on the second substrate SB1 to form a filter layer structure CFL. It should be noted that the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 may be patterned respectively, so that after the second substrate structure SS2 is subsequently bonded to the first substrate structure SS1, the portion of the filter layer structure CFL corresponding to an optical unit LCU may only include a filter layer with the same color as the light after passing through the optical unit LCU. FIG13, for example, shows the structure where the portion of the first filter layer CF1 and the third filter layer CF3 corresponding to the optical unit LCU is removed, and the second filter layer CF2 corresponds to the optical unit LCU. In this case, the optical unit LCU shown in FIG13 may be optical unit LCU2.

[0113] Next, the fabrication process of the second substrate structure SS2 may include step S208: forming a functional layer FC on the filter layer. Specifically, after forming a filter layer structure CFL on the second substrate SB1, a functional layer FC may be formed on the filter layer structure CFL. In this embodiment, the functional layer FC may refer to, for example, the insulating layer IN8 shown in FIG1, but is not limited thereto. After forming the functional layer FC, the second substrate structure SS2 can be formed.

[0114] It should be noted that the fabrication processes of the first substrate structure SS1 and the second substrate structure SS2 described above can be performed in any order or simultaneously, and this embodiment is not limited thereto. In addition, the first substrate structure SS1 and the second substrate structure SS2 may also include other suitable elements or films, and are not limited to the structure shown in FIG13.

[0115] After forming the first substrate structure SS1 and the second substrate structure SS2, the manufacturing method M200 of the electronic device ED may include step S209: forming a sealing layer SL and a filling layer FL on the first substrate. Specifically, as shown in FIG13, after forming the first substrate structure SS1, the sealing layer SL may be first formed on the first substrate structure SS1. The sealing layer SL may have an annular structure, for example, surrounding the edge of the first substrate structure SS1, but is not limited thereto. After forming the sealing layer SL, the filling layer FL may be formed on the first substrate structure SS1 corresponding to the area enclosed by the sealing layer SL and cover the elements and / or film layers of the first substrate structure SS1. The filling layer FL may include any suitable transparent material. In another embodiment, the sealing layer SL may also be formed on the second substrate structure SS2 before the filling layer FL is formed on the second substrate structure SS2 corresponding to the area enclosed by the sealing layer SL.

[0116] Next, the manufacturing method M200 of the electronic device ED may include step S210: aligning and bonding the first substrate and the second substrate. Specifically, as shown in FIG13, after the sealing layer SL and the filling layer FL are provided, the second substrate structure SS2 can be flipped and aligned and bonded with the first substrate structure SS1, so that the first substrate SB and the second substrate SB1 can be located on opposite sides, and the components and / or film layers in the electronic device ED can be located between the first substrate SB and the second substrate SB1.

[0117] Next, the manufacturing method M200 of the electronic device ED may include step S211: performing a cutting process. Specifically, after aligning and bonding the first substrate structure SS1 and the second substrate structure SS2, a cutting process may be performed on the formed structure to divide it into a plurality of electronic panels.

[0118] Next, the manufacturing method M200 of the electronic device ED may include step S212: forming an optical film on the side of the second substrate SB1 opposite to the filter layer structure CFL. Specifically, although not shown in the figure, after forming an electronic panel through a cutting process, an optical film, such as the anti-reflection layer AR shown in FIG1, can be formed on the second substrate SB1 of an electronic panel to form the electronic device ED, thereby improving the light emission effect of the electronic device ED.

[0119] It should be noted that the manufacturing method M200 of the electronic device ED may also include other suitable steps, and is not limited to the steps described above.

[0120] In summary, this disclosure provides an electronic device comprising an insulating layer disposed on a light-emitting unit, wherein the insulating layer includes a plurality of openings. Optical units may be disposed in a portion of these openings, while other portions of these openings may not contain optical units and may overlap with specific components (e.g., transistors, photosensors, etc.) in the electronic device from a top-view perspective. With the above design, specific processes can be performed on components or films under the insulating layer through the openings without optical units, thereby improving the process yield of the electronic device. The above description is merely an embodiment of this disclosure; all equivalent variations and modifications made within the scope of the claims of this disclosure shall fall within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a partial cross-sectional view of an electronic device according to a first embodiment of the present disclosure. Figure 2 is a partial top view of an electronic device according to a second embodiment of the present disclosure. Figure 3 is a cross-sectional view of the transistor in the electronic device according to a second embodiment of the present disclosure. Figure 4 is a partial top view of an electronic device according to a third embodiment of the present disclosure. Figure 5 is a partial top view of an electronic device according to a fourth embodiment of the present disclosure. Figure 6 is a partial top view of an electronic device according to a fifth embodiment of the present disclosure. Figure 7 is a partial top view of an electronic device according to a sixth embodiment of the present disclosure. Figure 8 is a partial top view of an electronic device according to a variation of the sixth embodiment of the present disclosure. Figure 9 is a partial cross-sectional view of an electronic device according to a seventh embodiment of the present disclosure. Figure 10 is a partial cross-sectional view of an electronic device according to an eighth embodiment of the present disclosure. Figure 11 is a partial cross-sectional view of an electronic device according to a ninth embodiment of the present disclosure. Figure 12 is a flowchart illustrating a method for manufacturing an electronic device according to a first embodiment of the present disclosure. Figure 13 is a partial cross-sectional view of an electronic device according to a tenth embodiment of the present disclosure. Figure 14 is a flowchart illustrating a method for manufacturing an electronic device according to a tenth embodiment of the present disclosure.

Claims

1. An electronic device comprising: One substrate; A plurality of transistors are disposed on the substrate; A light-emitting unit is disposed on at least one of the plurality of transistors; A first insulating layer is disposed on the light-emitting unit and has a first opening and a second opening; An optical unit is disposed in the first opening; wherein, in a top view of the electronic device, the first opening overlaps at least a portion of the light-emitting unit, and the second opening overlaps at least a portion of at least one of the plurality of transistors; wherein the first opening overlaps a first portion of the plurality of transistors, the second opening overlaps a second portion of the plurality of transistors, and the number of the first portion of the plurality of transistors is different from the number of the second portion of the plurality of transistors.

2. The electronic device according to claim 1, wherein the second opening overlaps a gate electrode of one of at least one of the plurality of transistors, and the width of the second opening is greater than the width of the gate electrode.

3. The electronic device according to claim 1, wherein the second opening overlaps a source electrode of one of the at least one of the plurality of transistors, and the width of the second opening is greater than the width of the source electrode.

4. The electronic device according to claim 1, wherein the second opening overlaps a drain electrode of one of at least one of the plurality of transistors, and the width of the second opening is greater than the width of the drain electrode.

5. The electronic device according to claim 1, wherein one of the at least one of the plurality of transistors includes a first semiconductor and a second semiconductor, the second semiconductor being disposed between the first semiconductor and the substrate.

6. The electronic device according to claim 5 further includes a second insulating layer disposed between the first semiconductor and the second semiconductor, the second insulating layer being in direct contact with the second semiconductor.

7. The electronic device according to claim 6, wherein the second insulating layer comprises a metal oxide material.

8. The electronic device according to claim 5, wherein one of the at least one of the plurality of transistors includes a source electrode and a drain electrode, one of the source electrode and the drain electrode being electrically connected to the first semiconductor and the second semiconductor.

9. The electronic device according to claim 5, wherein the thickness of the second semiconductor is less than the thickness of the first semiconductor.

10. The electronic device according to claim 1 further includes a third insulating layer disposed on the first insulating layer, a portion of the third insulating layer being disposed in the second opening.

11. The electronic device according to claim 1 further includes a first filter layer disposed on the first insulating layer, a portion of the first filter layer being disposed in the second opening, and the first filter layer overlapping the optical unit in the top view direction of the electronic device.

12. The electronic device according to claim 11 further includes a second filter layer disposed on the first insulating layer, a portion of the second filter layer being disposed in the second opening, and the second filter layer not overlapping the optical unit in the top view direction of the electronic device.

13. The electronic device according to claim 1 further includes a photosensor disposed between the first insulating layer and the substrate, wherein, in the top view of the electronic device, the second opening overlaps at least a portion of the photosensor.

14. The electronic device according to claim 13 further includes a first filter layer disposed on the first insulating layer, a portion of the first filter layer being disposed in the second opening and having a first filter opening, wherein the first filter layer overlaps the optical unit in the top view direction of the electronic device.

15. The electronic device according to claim 14 further includes a second filter layer disposed on the first insulating layer, a portion of the second filter layer being disposed in the second opening and having a second filter opening, wherein, in the top view of the electronic device, the second filter layer does not overlap the optical unit.

16. The electronic device according to claim 1 further includes a photosensor disposed between the first insulating layer and the substrate, the first insulating layer including a third opening that overlaps at least a portion of the photosensor in the top view of the electronic device.

17. The electronic device according to claim 1, wherein the number of the first portion of transistors in the plurality of transistors is less than the number of the second portion of transistors in the plurality of transistors.

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