Multipliers, multiply-accumulate circuits, arithmetic circuits, processors, and computing devices

Abstract

This invention relates to multipliers, multiply-accumulate circuits, arithmetic circuits, processors, and computing devices. An arithmetic circuit includes an input processing circuit and a multiply-accumulate circuit. The input processing circuit receives a first number and, if the first number is signed, outputs the first number as a first multiplier for feeding into the multiply-accumulate circuit by inverting the sign bit of the first number; if the first number is unsigned, it directly outputs the first number as a first multiplier for feeding into the multiply-accumulate circuit. The input processing circuit also receives a pre-known second number and directly outputs the second number as a second multiplier for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit. The multiplication subcircuit includes a multiplier for performing a multiplication operation between the first and second multipliers and providing an unsigned output. The accumulation subcircuit receives the output of the multiplication subcircuit and accumulates it.

Description

Technical Field

[0001] The present invention is based on and claims priority to a Chinese patent application with Chinese application number 202311056807.2 and application date August 22, 2023. The disclosed content of the Chinese patent application is hereby introduced into the present invention as a whole.

[0002] The present invention relates to the field of data processing technology, and more particularly to a multiplier, a multiplication-accumulation circuit, an arithmetic circuit, and a processor and a computing device comprising such a multiplier or multiplication-accumulation circuit or arithmetic circuit. Prior Art

[0003] Multiply and Accumulate (MAC) circuits are used to perform multiply-accumulate operations such as vector multiplication, matrix multiplication, and vector-matrix multiplication. They are crucial computational subsystems in processors such as auxiliary processors, digital signal processors, central processing units (CPUs), special-purpose instruction processors (DSPs), and neural network processors. The rapid development of artificial intelligence (AI) has highlighted the crucial role of neural network processors, making them the cornerstone of intelligent computing technology. The convolutional unit (CLU) is the core unit of a neural network processor. Its implementation relies on the CMU circuits, which perform CMU operations on the activation data and weight data. Therefore, the design of CMU circuits is crucial for both the CLU and the neural network processor. Summary of the Invention

[0004] According to a first aspect of the present invention, a multiplier is provided for performing a multiplication operation between a first multiplier and a second multiplier, wherein the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned number or a signed number. The multiplier includes: a partial product generation circuit configured to receive the first and second multipliers and output their partial products; and a partial product summation circuit, wherein an input terminal of the partial product summation circuit is coupled to an output terminal of the partial product generation circuit and the partial product summation circuit is configured to receive and sum the partial products output by the partial product generation circuit. The partial product generation circuit includes a first partial product generation unit configured to output the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit is configured to: if the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; and if the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier.

[0005] In some embodiments, the first partial product generating unit is configured to: receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number; output a partial product of the highest bit of the second multiplier and the first multiplier when the sign flag indicates that the second multiplier is an unsigned number; and output a negated result of the partial product of the highest bit of the second multiplier and the first multiplier when the sign flag indicates that the second multiplier is a signed number.

[0006] In some embodiments, the first partial product generating unit includes: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; and an XOR gate group configured to receive the AND operation result of the AND gate group and the sign flag and perform an XOR operation on them, wherein the XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

[0007] In some embodiments, the first partial product generating unit includes: an inverted-AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND-NON operation on them; and an exclusive-OR gate group configured to receive the NAND operation result of the inverted-AND gate group and the sign flag and perform an exclusive-OR operation on them, wherein the exclusive-OR operation result of the exclusive-OR gate group is provided as the output of the first partial product generating unit.

[0008] In some embodiments, the first partial product generating unit includes: an XOR gate configured to receive the highest bit of the second multiplier and the sign flag and perform an XOR operation on them; and a multiplexer group, each multiplexer in the multiplexer group being configured to receive the sign flag as a first input, receive the XOR operation result of the XOR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generating unit.

[0009] In some embodiments, the first partial product generating unit includes: an exclusive-OR gate configured to receive the highest bit of the second multiplier and the sign flag and perform an exclusive-OR operation on them; and an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group being configured to receive the sign flag as a first input, receive the exclusive-OR operation result of the exclusive-OR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the inverting multiplexer group is provided as the output of the first partial product generating unit.

[0010] In some embodiments, the first partial product generating unit includes: an AND gate group, configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; and a multiplexer group, configured to receive the AND operation result of the AND gate group as a first input, receive the inverted result of the AND operation result of the AND gate group as a second input, receive the sign flag as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generating unit.

[0011] In some embodiments, the multiplier has a dual output terminal, and the partial product summation circuit includes: a partial product compression circuit, the input terminal of the partial product compression circuit being coupled to the output terminal of the partial product generation circuit, the partial product compression circuit being configured to receive the partial products output by the partial product generation circuit and compress and sum them to output the sum digits and carries of the compressed summation results of the partial products. In some embodiments, the multiplier has a single output terminal, and the partial product summation circuit includes: a partial product compression circuit, the input terminal of the partial product compression circuit being coupled to the output terminal of the partial product generation circuit, the partial product compression circuit being configured to receive the partial products output by the partial product generation circuit and compress and sum them to output the sum digits and carries of the compressed summation results of the partial products; and a final addition circuit, the input terminal of the final addition circuit being coupled to the output terminal of the partial product compression circuit, the final addition circuit being configured to receive the sum digits and carries output by the partial product compression circuit and sum them.

[0012] In some embodiments, the partial product generation circuit further includes a second partial product generation unit for outputting a partial product of a modified second multiplier and the first multiplier, wherein the modified second multiplier is obtained by removing the highest bit of the second multiplier and is an unsigned number, and the second partial product generation unit includes a multiplier for performing an unsigned-unsigned multiplication operation.

[0013] In some embodiments, the partial product generation circuit further includes a plurality of second partial product generation units, each of the plurality of second partial product generation units being configured to output a partial product of a corresponding bit of the second multiplier except for the highest bit and the first multiplier.

[0014] In some embodiments, each of the plurality of second partial product generating units includes an AND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform an AND operation thereon, wherein the AND operation result of the AND gate group is provided as the output of the second partial product generating unit. In some embodiments, each of the plurality of second partial product generating units includes an INVERT-AND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform an AND-NON operation thereon, wherein the NOR operation result of the INVERT-AND gate group is provided as the output of the second partial product generating unit.

[0015] In some embodiments, the output of the partial product summation circuit is coupled to the input of an additional adding circuit, wherein the additional adding circuit is configured to add the output of the partial product summation circuit to a constant when the second multiplier is a signed number, wherein the constant is , where w is the bit width of the second multiplier.

[0016] According to a second aspect of the present invention, a multiply-accumulate circuit is provided for performing a plurality of multiply-accumulate operations on a first number and a second number, the second number being known in advance. The multiply-accumulate circuit includes at least one multiply-accumulate unit. The multiply-accumulate unit includes: a multiplication subcircuit, the multiplication subcircuit including a multiplier for performing a multiplication operation on a first multiplier and a second multiplier, the first multiplier being obtained from the first number and being an unsigned number, and the second multiplier being obtained from the second number and being a known unsigned number or a signed number, the multiplier being configured to provide an output that is an unsigned number; and an accumulation subcircuit, the accumulation subcircuit having an input coupled to an output of the multiplication subcircuit, the accumulation subcircuit being configured to receive and accumulate the output of the multiplication subcircuit.

[0017] In some embodiments, the multiplier of the multiplication subcircuit is the multiplier according to any embodiment of the first aspect of the present invention.

[0018] In some embodiments, the multiplication subcircuit includes a plurality of the multipliers, each of the multipliers being configured to receive a corresponding pair of first multipliers and second multipliers and to product the corresponding pair of first multipliers and second multipliers.

[0019] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, a first adder, a second adder, and a register group; the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees; the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees; the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the first adder; the output end of the first adder is coupled to the corresponding input end of the second adder; the output end of the second adder is coupled to the input end of the register group; and the output end of the register group is coupled to the corresponding input end of the second adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0020] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, a full adder, an adder, and a register group. The output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the full adder, the output end of the full adder is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0021] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, an adder, and a register group; the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees; the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees; the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the adder; the output end of the adder is coupled to the input end of the register group; and the output end of the register group is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, wherein n is a positive integer, i=1, 2, ..., n-1.

[0022] In some embodiments, the accumulation subcircuit includes: a full adder module having one or more stages of full adders, an adder, and a register group; the output of the multiplication subcircuit is coupled to the corresponding input of the full adder module, the output of the full adder module is coupled to the corresponding input of the adder, the output of the adder is coupled to the input of the register group, and the output of the register group is coupled to the corresponding input of the full adder module.

[0023] In some embodiments, the at least one multiplication-accumulation unit includes two or more of the multiplication-accumulation units, and the multiplication-accumulation circuit also includes a summing unit, the input end of the summing unit is coupled to the output end of the two or more of the multiplication-accumulation units, and the summing unit is configured to receive the outputs of the two or more of the multiplication-accumulation units and sum them.

[0024] In some embodiments, the summation unit includes s-level compression trees and an adder, the output end of each of the two or more multiplication and accumulation units is coupled to the corresponding input end of the 1st-level compression tree in the s-level compression trees, the output end of the i-th-level compression tree in the s-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree in the s-level compression trees, and the output end of the s-th-level compression tree in the s-level compression trees is coupled to the corresponding input end of the adder, wherein s is a non-negative integer, i=1, 2,…, s-1.

[0025] In some embodiments, the summing unit further includes an additional register group, an input end of the additional register group is coupled to an output end of the adder, and an output end of the additional register group is coupled to a corresponding input end of the first-level compression tree in the s-level compression tree.

[0026] In some embodiments, the multiplication-accumulation circuit further includes a control element arranged between the output end of each of the two or more multiplication-accumulation units and the corresponding input end of the summation unit, wherein the control element is configured to receive a control signal and the output of the corresponding multiplication-accumulation unit and control whether to provide the output of the corresponding multiplication-accumulation unit to the summation unit at the output end of the control element according to the control signal.

[0027] In some embodiments, the input end of the multiplication subcircuit is also coupled to the output end of the input processing circuit, and the input processing circuit is configured to receive the first number and the second number and: when the first number is a signed number, output the first number as a first multiplier for feeding into the multiplier by inverting the sign bit of the first number, and output the second number as a second multiplier for feeding into the multiplier; and when the first number is an unsigned number, output the first number as the first multiplier for feeding into the multiplier, and output the second number as the second multiplier for feeding into the multiplier.

[0028] In some embodiments, the input processing circuit includes: an exclusive-OR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an exclusive-OR operation thereon, wherein the exclusive-OR operation result of the exclusive-OR gate is provided as the most significant bit of the first number output by the input processing circuit. In some embodiments, the input processing circuit includes: a multiplexer configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input based on the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

[0029] In some embodiments, the input of the multiplication subcircuit is further coupled to the output of an input processing circuit, the input processing circuit being configured to receive the first number and the second number. The input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiply-accumulate circuit further includes a shifter coupled to the output of the multiplication subcircuit, the shifter being configured to perform a shift operation corresponding to the split. In some embodiments, the input processing circuit is further configured to split the second number according to the bit width of the multiplier. In some embodiments, the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

[0030] In some embodiments, the output of the accumulation subcircuit is coupled to the input of an output processing circuit, and the output processing circuit is configured to perform at least one of the following: subtracting the output of the accumulation subcircuit from a first constant, where the first constant is the sum of all the second numbers in the plurality of pairs of first and second numbers that are paired with the first number as a signed number after being left shifted by (z-1), where z is the bit width of the first number; or adding the output of the accumulation subcircuit to a second constant, where the second constant is , where w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all second numbers in the plurality of pairs of first and second numbers.

[0031] According to a third aspect of the present invention, an arithmetic circuit is provided, comprising: the multiply-accumulate circuit according to any embodiment of the second aspect of the present invention; and an input processing circuit, wherein the output of the input processing circuit is coupled to the input of the multiply-accumulate circuit. The input processing circuit is configured to receive a first number and a second number and: if the first number is a signed number, output the first number as a first multiplier to be fed into the multiplier by inverting the sign bit of the first number, and output the second number as a second multiplier to be fed into the multiplier; and if the first number is an unsigned number, output the first number as the first multiplier to be fed into the multiplier, and output the second number as the second multiplier to be fed into the multiplier.

[0032] In some embodiments, the input processing circuit includes: an exclusive-OR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an exclusive-OR operation thereon, wherein the exclusive-OR operation result of the exclusive-OR gate is provided as the most significant bit of the first number output by the input processing circuit. In some embodiments, the input processing circuit includes: a multiplexer configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input based on the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

[0033] In some embodiments, the input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiply-accumulate circuit further includes a shifter coupled to the output of the multiplication subcircuit, the shifter configured to perform a shift operation corresponding to the split. In some embodiments, the input processing circuit is further configured to split the second number according to the bit width of the multiplier. In some embodiments, the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

[0034] In some embodiments, the arithmetic circuit further includes an output processing circuit, and the output terminal of the multiplication and accumulation circuit is coupled to the input terminal of the output processing circuit. The output processing circuit is configured to perform at least one of the following: subtracting the output of the multiplication and accumulation circuit from a first constant, the first constant being the sum of all the second numbers in the plurality of pairs of first and second numbers that are paired with the first number as a signed number after being shifted left by (z-1), where z is the bit width of the first number; or adding the output of the multiplication and accumulation circuit to a second constant, the second constant being , where w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all second numbers in the plurality of pairs of first and second numbers.

[0035] According to a fourth aspect of the present invention, there is provided an arithmetic circuit, comprising: a multiplier according to any embodiment of the first aspect of the present invention; and an additional adding circuit, wherein an output terminal of the multiplier is coupled to an input terminal of the additional adding circuit, and the additional adding circuit is configured to add an output of the partial product summation circuit to a constant when the second multiplier is a signed number, the constant being , where w is the bit width of the second multiplier.

[0036] According to a fifth aspect of the present invention, there is provided a processor, comprising the multiplier according to any embodiment of the first aspect of the present invention, the multiplication-accumulation circuit according to any embodiment of the second aspect of the present invention, or the arithmetic circuit according to any embodiment of the third party aspect and the fourth aspect of the present invention.

[0037] According to a sixth aspect of the present invention, there is provided a computing device comprising the processor according to the fifth aspect of the present invention.

[0038] Other features and advantages of the present invention will become more apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. Simple diagram description

[0039] The drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0040] The present invention may be more clearly understood from the following detailed description with reference to the accompanying drawings, wherein: Figures 1 to 3 respectively show circuit diagrams of multiplication and accumulation circuits according to some comparative examples of the present invention; Figures 4 and 5 respectively show a schematic block diagram of an operation circuit according to some embodiments of the present invention; Figures 6 to 9 respectively show example circuit diagrams of input processing circuits for implementing the arithmetic circuits of Figures 4 and 5 according to some embodiments of the present invention; Figures 10 to 17 respectively show example circuit diagrams of multiplication and accumulation circuits for implementing the arithmetic circuits of Figures 4 and 5 according to some embodiments of the present invention; Figure 18 shows a schematic block diagram of a multiplication and accumulation circuit for implementing the arithmetic circuits of Figures 4 and 5 according to some embodiments of the present invention; Figures 19 to 22 respectively show example circuit diagrams for implementing the multiplication and accumulation circuit of Figure 18 according to some embodiments of the present invention; Figure 23 shows a schematic block diagram of a multiplier according to some embodiments of the present invention; Figures 24 to 27 respectively show example circuit diagrams for implementing the multiplier of Figure 23 according to some embodiments of the present invention; Figures 28 to 30 respectively show example circuit diagrams for implementing a first partial product generating unit of the multiplier of Figure 23 according to some embodiments of the present invention; FIG31 shows a schematic block diagram of an arithmetic circuit including the multiplier of FIG23 and an additional adding circuit according to some embodiments of the present invention. Implementation Method

[0041] Note that in the following embodiments, the same reference numerals are sometimes used across different figures to denote the same components or components having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0043] Various exemplary embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, digital operation expressions and numerical values ​​described in these embodiments do not limit the scope of the present invention.

[0044] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention, its application, or use. That is, the structures and methods described herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present invention. However, those skilled in the art will understand that these are merely exemplary, not exhaustive, ways in which the present invention may be implemented. Furthermore, the drawings are not necessarily drawn to scale; some features may be exaggerated to illustrate details of specific components.

[0045] In addition, technologies, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the technologies, methods and equipment should be considered part of the specification.

[0046] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0047] FIG1 shows a multiply-accumulate circuit 10, which includes a multiplier 11, an adder 12, and a temporary register 13. Assuming that multiply-accumulate circuit 10 is to calculate the multiply-accumulate of x logarithms (a1·b1+a2·b2+...ax·bx, where x is a positive integer), then in each of x cycles, a corresponding pair of logarithms ak and bk (k=1, 2, ..., x) in the x logarithms is fed as a multiplier into multiplier 11 to calculate the product ak·bk of these logarithms. The product ak·bk is then accumulated via adder 12 and temporary register 13. For example, if the x logarithms are fed sequentially from 1 to x, then at the end of the first cycle, the result stored in register 13 is a 1·b 1, at the end of the second cycle, the result stored in register 13 is a 1·b 1+a 2·b 2, and so on, until the end of the xth cycle, the result stored in register 13 is a 1·b 1+a 2·b 2+…ax·bx.

[0048] However, the multiply-accumulate circuit 10 is not compatible with multiply-accumulate operations on different data types, including signed and unsigned numbers. For signed numbers, the highest bit (MSB) is used to indicate the sign and is called the sign bit. A sign bit of 0 indicates a positive number, while a sign bit of 1 indicates a negative number. For unsigned numbers, the MSB is used only to indicate the value. For example, suppose ak = 0b10101010 and bk = 0b01010101: If both ak and bk are signed numbers, the decimal representation of ak·bk is (-86 × 85) = -7310; if both ak and bk are unsigned numbers, the decimal representation of ak·bk is (170 × 85) = 14450. It can be seen that if the multiplication-accumulation circuit 10 itself is designed to perform multiplication-accumulation operations on signed numbers, then once an unsigned number is input into the multiplication-accumulation circuit 10, an erroneous operation result will be obtained; and if the multiplication-accumulation circuit 10 itself is designed to perform multiplication-accumulation operations on unsigned numbers, then once a signed number is input into the multiplication-accumulation circuit 10, an erroneous operation result will be obtained.

[0049] To make the same multiply-accumulate circuit compatible with multiply-accumulate operations on different data types, sign extension can be performed on ak and bk before feeding them into the multiply-accumulate circuit. Specifically, the sign bit is extended for signed numbers (i.e., the sign bit is added to the upper bits), and zero extension is performed for unsigned numbers (i.e., the sign bit is added to the upper bits). For example, for the signed number 0101, one bit is extended to 00101, and four bits are extended to 00000101; for the signed number 1010, one bit is extended to 11010, and four bits are extended to 11111010; for the unsigned number 0101, one bit is extended to 00101, and four bits are extended to 00000101; for the unsigned number 1010, one bit is extended to 01010, and four bits are extended to 0000101. The specific number of extended bits can be determined by the designed bit width of the multiplier, or conversely, the multiplier can be designed based on the specific number of extended bits. The key to sign extension is that it only expands the data bit width without changing the data size. Before sign extension, ak and bk could be signed or unsigned numbers, but after sign extension, ak and bk are both signed numbers. Figure 2 shows a multiply-accumulate circuit 20. This circuit includes a multiplier 21 that supports signed-by-signed multiplication and provides a signed output, an adder 22, and a register 23. This circuit performs a multiply-accumulate operation on the sign-extended ak and bk. While the multiply-accumulate circuit 20 is compatible with multiply-accumulate operations on different data types, the sign extension increases the data width, requiring more resources for the correspondingly designed multiplier 21. Furthermore, the multiplier 21 performing signed-by-signed multiplication and providing a signed output complicates the subsequent data path (not only the adder 22 and register 23 in the multiply-accumulate circuit 20, but also potentially other circuits coupled to the output of the multiply-accumulate circuit 20), increasing design difficulty, circuit area, and power consumption.

[0050] Alternatively, the product-accumulation operation sum of a signed number ak (assuming bit width z) and a signed number bk (assuming bit width w) can be unified into an unsigned operation using the following mathematical derivation.

[0051] make (equivalent to The sign bit of (equivalent to (the sign bit of

[0052] can be extracted as a constant term. The multiplication and accumulation circuit 30 shown in FIG3 can be used for processing. As shown in FIG3, the multiplication and accumulation circuit 30 includes a multiplier 31 that supports multiplication of unsigned numbers by unsigned numbers and provides unsigned output, an adder 32, and a register 33. It also includes an adder 34 and a subtractor 35. The multiplier 31 is used to calculate , adder 34 is used to calculate , subtractor 35 is used to calculate ,Adder 32 and register 33 are used for accumulation.

[0053] Similarly, the multiplication-accumulation operation sum of a signed number ak (assuming the bit width is z) and an unsigned number bk (assuming the bit width is w) can be unified into an unsigned number operation through the following mathematical derivation.

[0054] make (equivalent to (the sign bit of

[0055] The same can be done with the multiplication and accumulation circuit 30, but a first control element 361 is required to set the input at the first input of the adder 34 to 0, and the second input of the adder 34 can receive Such a first control element 361 can be realized, for example, by an AND gate, the first input of which can receive an input desired to be processed by the adder 34 ( or as will be described later ,) and the second input terminal can receive the control signal Sc1, and the output terminal can be coupled to the first input terminal of the adder 34. For the AND gate, setting Sc1=0 prohibits the first input terminal of the adder 34 from receiving the input at the first input terminal of the AND gate, and setting Sc1=1 allows the first input terminal of the adder 34 to receive the input at the first input terminal of the AND gate.

[0056] Similarly, the product-addition operation sum of the unsigned number ak (assuming the bit width is z) and the signed number bk (assuming the bit width is w) can be unified into an unsigned number operation through the following mathematical derivation.

[0057] make (equivalent to (the sign bit of

[0058] The same can be done with the multiplication and accumulation circuit 30, but a second control element 362 is required to set the input at the second input of the adder 34 to 0, and the first input of the adder 34 can receive Such a second control element 362 can also be realized by, for example, an AND gate, the first input of which can receive an input desired to be processed by the adder 34 ( or ,) and the second input terminal can receive the control signal Sc2, and the output terminal can be coupled to the second input terminal of the adder 34. For the AND gate, by setting Sc2=0, the second input terminal of the adder 34 is prohibited from receiving the input at the first input terminal of the AND gate, and by setting Sc2=1, the second input terminal of the adder 34 is allowed to receive the input at the first input terminal of the AND gate.

[0059] For the multiplication and accumulation operation of unsigned number ak (assuming bit width is z) and unsigned number bk (assuming bit width is w) The same process can be performed using the multiply-accumulate circuit 30 , where the first control element 361 and the second control element 362 are configured to prohibit the first input terminal and the second input terminal of the adder 34 from receiving the input at the first input terminal of the AND gate.

[0060] Thus, the multiply-accumulate circuit 30 is compatible with multiply-accumulate operations on different data types. Because sign bit extension is not required, the multiplier 31 of the multiply-accumulate circuit 30 consumes fewer resources than the multiplier 21 of the multiply-accumulate circuit 20. However, the multiply-accumulate circuit 30 has significantly more circuit elements than the multiply-accumulate circuit 20. On one hand, the multiply-accumulate circuit 30 includes an additional adder 34 and control elements 361 and 362 to process the additional accumulation terms. This consumes significant adder resources, and the introduction of control elements 361 and 362 also complicates the control logic. On the other hand, although the multiplier 31 supports unsigned multiplication by unsigned numbers and provides an unsigned output, the multiplication-accumulation circuit 30 also includes a subtractor 35, which still provides a signed output. This makes the data path after the subtractor 35 (not only the adder 32 and register 33 in the multiplication-accumulation circuit 30, but also other circuits coupled to the output end of the multiplication-accumulation circuit 30) complicated, increasing the design difficulty, circuit area, and power consumption.

[0061] The inventors of the present invention have noted that in some application scenarios involving multiplication-accumulation operations on two sets of data, one of the sets of data can be known in advance. For example, in the convolution calculation unit of a neural network processor, a multiplication-accumulation circuit is required to perform multiplication-accumulation operations on the starting data and weight data. For non-limiting purposes, the starting data can be image data, such as an image captured by a camera in real time, which is to be used by the neural network model onboard the neural network processor for object detection, while the weight data is derived from the weight parameters of the neural network model. Since the weight parameters of a trained neural network model are fixed, the weight data is known in advance. In contrast, the starting data is unknown in advance and cannot be determined until processing is required. This characteristic can be exploited to optimize the calculation circuit.

[0062] Specifically, the product-addition operation sum of the previously unknown ak (assuming the bit width is z) and the previously known bk (assuming the bit width is w) can be unified into the following operation through the following mathematical derivation.

[0063] When ak is an unsigned number and bk is a signed or unsigned number,

[0064] Therefore, the multiply-accumulate circuit is used to calculate That's it.

[0065] When ak is a signed number and bk is a signed or unsigned number,

[0066] make (equivalent to inverting the sign bit of ak),

[0067] Since bk is known in advance, ( ) can be extracted as a constant term. Therefore, we only need to use the multiplication and accumulation circuit to calculate That's it.

[0068] To this end, the present invention provides an arithmetic circuit capable of performing multiple multiplication-accumulation operations on pairs of a first number and a pre-known second number using the aforementioned arithmetic principles. The arithmetic circuits according to various embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that actual arithmetic circuits may include additional components, which are not shown in the drawings and are not discussed herein to avoid obscuring the key points of the present invention.

[0069] Figure 4 illustrates an arithmetic circuit 1000 according to some embodiments of the present invention, configured to perform multiple multiplication-accumulation operations on a first number ak and a second number bk, where the second number bk is known in advance. Assuming the bit width of the first number ak is z and the bit width of the second number bk is w, this is for illustrative purposes only and is not intended to limit the possibility that the first number ak and the second number bk have the same or different bit widths. In practice, the present invention is applicable to both the case where the first number ak and the second number bk have the same or different bit widths. In many practical situations, the first number ak and the second number bk have the same bit width.

[0070] As shown in FIG4 , the arithmetic circuit 1000 includes a multiply-accumulate circuit 100 and an input processing circuit 200. The input terminal of the input processing circuit 200 can provide an input terminal IN of the arithmetic circuit 1000. The output terminal of the input processing circuit 200 is coupled to the input terminal of the multiply-accumulate circuit 100. The output terminal of the multiply-accumulate circuit 100 can provide an output terminal OUT of the arithmetic circuit 1000.

[0071] FIG5 shows another example 1000′ of the operation circuit 1000, which further includes an output processing circuit 300 compared to the operation circuit 1000. The output terminal of the multiplication and accumulation circuit 100 is coupled to the input terminal of the output processing circuit 300. The output terminal of the output processing circuit 300 can provide the output terminal OUT of the operation circuit 1000′. The output processing circuit 300 is used to process the constant term extracted in the above mathematical derivation. Specifically, the output processing circuit 300 can be configured to subtract the output of the multiplication and accumulation circuit 100 from a first constant, which is the sum of all the second numbers bk paired with the first number ak as a signed number in the multiple pairs of first numbers ak and second numbers bk after being shifted left by (z-1) bits ( ). In some cases, the computation circuit 1000 of Figure 4 is sufficient, and there's no need for a dedicated output processing circuit 300 to handle these constant terms. For example, in the convolutional computation unit of a neural network processor, in addition to performing a multiplication-accumulation operation on the activation data and weight data, the result of this multiplication-accumulation operation also needs to be added to a bias term. In the convolutional computation unit, the addition of the bias term is already handled by dedicated hardware, so the constant term can be integrated with the bias term in advance, eliminating the need for additional hardware processing.

[0072] The input processing circuit 200 can be configured to receive a first number ak and a second number bk. If the first number ak is a signed number, the input processing circuit 200 can also be configured to invert the sign bit of the first number ak to output the first number ak as a first multiplier for feeding into the multiplier-accumulator circuit 100, and to output the second number bk as a second multiplier for feeding into the multiplier-accumulator circuit 100. If the first number ak is unsigned, the input processing circuit 200 can also be configured to output the first number ak as a first multiplier for feeding into the multiplier-accumulator circuit 100, and to output the second number bk as a second multiplier for feeding into the multiplier-accumulator circuit 100. In other words, the input processing circuit 200 does not perform any transformation on the known second number bk, regardless of whether the second number bk is signed or unsigned. As for the unknown first number ak, the input processing circuit 200 only performs a transformation on the signed first number ak by inverting the sign bit, and does not perform any transformation on the unsigned first number ak.

[0073] Any suitable circuit may be designed to selectively perform a sign-inverting transformation on the first number ak according to the data type of the first number ak.

[0074] In some embodiments, the input processing circuit 200 may include an XOR gate configured to receive the most significant bit of the first number ak and a sign flag indicating whether the first number ak is unsigned or signed, and perform an XOR operation on them. The XOR operation result of the XOR gate is provided as the most significant bit of the first number Ak output by the input processing circuit 200. Figure 6 shows an example 200A of the input processing circuit 200, which includes an XOR gate. The XOR gate receives the most significant bit of the first number ak (z-1) and a sign flag (Flag1) indicating whether the first number ak is unsigned or signed, and performs an XOR operation on them. Flag1 = 0 indicates that the first number ak is unsigned, and the output of the XOR gate is ak(z-1). Flag1 = 1 indicates that the first number ak is signed, and the output of the XOR gate is the inverse of ak(z-1). The output of the XOR gate is concatenated with the remaining bits of the first number ak (ak(z-2):0) except the most significant bit ak(z-1) to form Ak. In addition, the input processing circuit 200 does not perform any transformation on the second number bk, and thus can directly output bk.

[0075] Alternatively, in other embodiments, the input processing circuit 200 may also include a multiplexer configured to receive the most significant bit of the first number ak as a first input, receive the inverted result of the most significant bit of the first number ak as a second input, receive a sign flag indicating whether the first number ak is unsigned or signed as a selection signal, and output the first input or the second input based on the selection signal. The output of the multiplexer may be provided as the most significant bit of the first number Ak output by the input processing circuit 200. The inverted result of the most significant bit of the first number ak may be obtained by receiving the most significant bit of the first number ak and performing a NOT operation on it using an inverting gate. Figure 7 shows an example 200B of the input processing circuit 200, which includes a multiplexer MUX and an inverting gate NOT. The NOT gate NOT is used to obtain the inverted result of the most significant bit ak(z-1) of the first number ak. The multiplexer MUX receives the most significant bit ak(z-1) of the first number ak as a first input, the inverted result of the most significant bit ak(z-1) of the first number ak as a second input, and a sign flag Flag1 indicating whether the first number ak is unsigned or signed as a selection signal. The multiplexer MUX outputs either the first input or the second input based on the selection signal. A selection signal Flag1 = 0 indicates that the first number ak is unsigned. In this case, the output of the multiplexer MUX is the first input, ak(z-1). A selection signal Flag1 = 1 indicates that the first number ak is signed. In this case, the output of the multiplexer MUX is the inverted result of the second input, ak(z-1). The output of the multiplexer MUX is concatenated with the remaining bits ak(z-2):0 of ​​the first number ak, excluding the most significant bit ak(z-1). Ak is formed by concatenating the output of the multiplexer MUX with the remaining bits ak(z-2):0 of ​​the first number ak, excluding the most significant bit ak(z-1). Furthermore, the input processing circuit 200 does not perform any transformation on the second number bk, thus directly outputting bk.

[0076] The multiply-accumulate circuit 100 can be designed to adapt to the bit widths of the first number ak and the second number bk. Conversely, the first number ak and the second number bk can also be split based on the designed bit width of the multiply-accumulate circuit 100, particularly its multiplier. Taking the example of a first number ak and a second number bk with a bit width of 2r and a multiplier with a designed bit width of r, the operational principle of the splitting is explained as follows.

[0077] akh is the most significant r bits of the first number ak, akl is the least significant r bits of the first number ak, bkh is the most significant r bits of the second number bk, and bkl is the least significant r bits of the second number bk. Thus, a large-bitwidth 2r multiplication operation can be equivalent to four small-bitwidth r multiplication operations. "," " is a shift operation, representing left shift of 2r bits and left shift of r bits, which can be performed by a shifter.

[0078] Therefore, in some embodiments, the input processing circuit 200 may be further configured to split the first number ak according to the bit width of the multiplier of the multiply-accumulate circuit 100, and the multiply-accumulate circuit 100 may further include a shifter coupled to the output of the multiplication sub-circuit 111, the shifter configured to perform a shift operation corresponding to the split. Furthermore, for a pre-known second number bk, its splitting may also be performed by the input processing circuit 200. Specifically, the input processing circuit 200 may be further configured to split the second number bk according to the bit width of the multiplier of the multiply-accumulate circuit 100. FIG8 illustrates an example 200C of the input processing circuit 200, which, compared to example 200A, further splits Ak into Akh (the high-order portion of Ak) and Akl (the low-order portion of Ak), and also splits bk into bkh (the high-order portion of bk) and bkl (the low-order portion of bk). Note that the splitting shown here is for illustrative purposes only and is not limiting. For example, each of Ak and bk can be split into more parts, each with the same or different bit widths. However, since the second number bk is known in advance, its splitting can be pre-processed (e.g., by software such as a compiler). Therefore, the input processing circuit 200 can alternatively be configured to receive the second number bk pre-split according to the bit width of the multiplier. Figure 9 shows an example 200D of the input processing circuit 200. Compared to example 200C, this example does not split bk and instead directly receives the pre-split bkh and bkl. Therefore, compared to example 200C, example 200D has a lower hardware cost because the corresponding circuit components used to split bk are eliminated. It will be understood that although Figures 8 and 9 illustrate the transformation followed by splitting, splitting followed by transformation is also feasible.

[0079] After the input processing circuit 200 processes the first and second numbers, the multiply-accumulate circuit 100 performs a multiply-accumulate operation on the first number, which is an unsigned number, and the pre-known second number. Referring back to Figures 4 and 5, the multiply-accumulate circuit 100 may include at least one multiply-accumulate unit 110. The multiply-accumulate unit 110 includes a multiplication sub-circuit 111 and an accumulation sub-circuit 112. The multiplication sub-circuit 111 may include a multiplier for performing a multiplication operation on the first multiplier and the second multiplier. The first multiplier is obtained from the first number (e.g., processed by the input processing circuit 200) and is an unsigned number. The second multiplier is obtained from the second number (e.g., processed by the input processing circuit 200) and is a pre-known unsigned number or a signed number. The multiplier of the multiplication sub-circuit 111 supports both unsigned-by-unsigned and unsigned-by-signed multiplications and is configured to provide an unsigned output. The input of the accumulation sub-circuit 112 is coupled to the output of the multiplication sub-circuit 111. The accumulation sub-circuit 112 is configured to receive the output of the multiplication sub-circuit 111 and accumulate it.

[0080] In some embodiments, the multiplication subcircuit 111 may include one or more multipliers, each of which is configured to receive a corresponding pair of first and second multipliers and calculate the product of the corresponding pair of first and second multipliers. The multipliers in the multiplication subcircuit 111 may have a single output terminal or a dual output terminal, depending on specific needs. When the multiplication subcircuit 111 includes multiple multipliers, parallel computing can be implemented.

[0081] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, a first adder, a second adder, and a register group. The output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the first adder, the output end of the first adder is coupled to the corresponding input end of the second adder, the output end of the second adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the second adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0082] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, a full adder, an adder, and a register group. The output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the full adder, the output end of the full adder is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0083] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, an adder, and a register group. The output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, wherein n is a positive integer, i=1, 2, ..., n-1.

[0084] Each level of the n-level compression tree can include a single compression tree or multiple compression trees in parallel. Common compression trees include 4:2 compression trees, 3:2 compression trees, and other compression trees with two outputs, as well as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees with three outputs. The compression tree used in the accumulation subcircuit 112 can be an existing or later-developed compression tree with any number of inputs and outputs, or a compression tree module with any number of inputs and outputs implemented by combining multiple existing compression trees, as long as it can compress the output result of the multiplication subcircuit 111.

[0085] In other embodiments, the compression tree may alternatively be implemented as a full adder or a combination of a full adder and a half adder. For example, in some embodiments, the accumulation subcircuit 112 may include a full adder module having one or more full adder stages, an adder, and a register set. The output of the multiplication subcircuit 111 is coupled to the corresponding input of the full adder module, the output of the full adder module is coupled to the corresponding input of the adder, the output of the adder is coupled to the input of the register set, and the output of the register set is coupled to the corresponding input of the full adder module.

[0086] The number of registers included in a register group may depend on the register bit width and the bit width of the input data. Similarly to the register group, the number of circuit elements in the various circuit element groups mentioned elsewhere herein (including AND gate groups, NAND gate groups, NAND gate groups, XOR gate groups, multiplexer groups, inverting multiplexer groups, etc.) may also depend on the circuit design bit width.

[0087] For non-limiting illustrative purposes, FIG. 10 to FIG. 17 respectively illustrate exemplary circuit diagrams of a multiplication-accumulation circuit 100 for implementing the arithmetic circuits 1000 and 1000′ of FIG. 4 and FIG. 5 according to some embodiments of the present invention.

[0088] As shown in FIG10 , the multiplication-accumulation circuit 100A includes a multiplication-accumulation unit 110, which includes a multiplication sub-circuit 111 and an accumulation sub-circuit 112. In the example of FIG10 , the multiplication sub-circuit 111 includes a multiplier 1110 with a single output terminal. Assuming that the multiplication-accumulation circuit 100 is used for the multiplication-accumulation of x-logarithms (a 1·b 1 + a 2·b 2 + ... ax·bx, where x is a positive integer), where ak (k=1, 2, ..., x) has been processed into Ak by, for example, the input processing circuit 200A of FIG6 , then in each of x cycles, the corresponding pair of numbers Ak and bk in the x-logarithm can be fed into the multiplier 1110 as the first and second multipliers, respectively. The multiplier 1110 calculates the product Ak·bk of these pairs and provides an unsigned output. Ak·bk is then accumulated via the accumulation sub-circuit 112. Accumulation sub-circuit 112 includes an adder ADD and a register bank 1121. A first input of adder ADD is coupled to the output of multiplier 1110, a second input is coupled to the output of register bank 1121, and an output of adder ADD is coupled to an input of register bank 1121. Assuming that the logarithms of x to be calculated by product-accumulation circuit 100A are fed sequentially from 1 to x to multiplier 1110, then at the end of the first cycle, the result stored in register bank 1121 is A 1·b 1. At the end of the second cycle, the result stored in register bank 1121 is (A 1·b 1 + A 2·b 2). This continues until the end of the xth cycle, when the result stored in register bank 1121 is (A 1·b 1 + A 2·b 2 + ... A x·bx).

[0089] Compared to the multiply-accumulate circuit 20 of Figure 2 , the multiplier 1110 of the multiply-accumulate circuit 100A of Figure 10 provides an unsigned output, simplifying the subsequent data path and reducing design difficulty, circuit area, and power consumption. Compared to the multiply-accumulate circuit 30 of Figure 3 , the multiply-accumulate circuit 100A of Figure 10 has a reduced component count (one adder, one subtractor, and two control elements are eliminated), eliminating the need for complex control logic. Furthermore, the subsequent data paths of multiplier 1110 are all unsigned, reducing design difficulty, circuit area, and power consumption.

[0090] Figure 11 shows a multiply-accumulate circuit 100B. Compared to the multiply-accumulate circuit 100A of Figure 10 , the difference lies in that the multiplier 1110 has a dual output instead of a single output, and accordingly, the adder ADD is transformed into a full adder (FA). A multiplier typically consists of three parts: a partial product generating part, a partial accumulation and addition part, and a final addition part. Compared to a multiplier with a single output, a multiplier with a dual output can reduce the final addition part, meaning one adder can be eliminated. Therefore, using a multiplier with a dual output can reduce power consumption compared to a multiplier with a single output. Furthermore, replacing the adder ADD with a full adder FA also reduces power consumption.

[0091] FIG12 shows a multiply-accumulate circuit 100C. Compared to the multiply-accumulate circuit 100A of FIG10 , it differs in that the multiplication subcircuit 111 includes m parallel multipliers 1110 1, 1110 2, ..., 1110 m (m is a positive integer greater than 1). Accordingly, the accumulation subcircuit 112 further includes a 2m:2 compression tree 1120 and an adder ADD0. The outputs of the multipliers 1110 1, 1110 2, ..., 1110 m are coupled to the corresponding inputs of the compression tree 1120, the output of the compression tree 1120 is coupled to the corresponding input of the adder ADD0, and the output of the adder ADD0 is coupled to the input of the adder ADD0. If designing a 2m:2 compression tree is inconvenient, a combination of existing compression trees can be used to achieve compression from m inputs to two outputs. By designing multipliers in parallel, the multiply-accumulate circuit 100C can perform m logarithmic multiply-accumulates per cycle. Compared to the x cycles required by the multiply-accumulate circuit 100A in FIG10 , the multiply-accumulate circuit 100C only requires (x / m) cycles, thus improving computational efficiency. The number m of parallel multipliers can be flexibly configured according to actual needs.

[0092] In contrast, the multiplication-accumulation circuit 20 of Figure 2 is difficult to implement parallel computation of multipliers 21 because multipliers 21 provide signed outputs, which complicates the design of the compression tree. Consequently, the computational efficiency of the multiplication-accumulation circuit 20 is low. While the multiplication-accumulation circuit 30 of Figure 3 provides unsigned outputs, making it relatively easy to design a compression tree to facilitate parallel computation, it also requires the addition of multiple adders 34 and related control elements 361 and 362 to accommodate the multiple multipliers 31. This significantly increases the number of circuit components, resulting in increased circuit area and power consumption.

[0093] FIG13 shows a multiply-accumulate circuit 100D. Compared to the multiply-accumulate circuit 100C of FIG12 , this circuit differs in that adder ADD0 is replaced with a full adder FA. The outputs of the compression tree 1120 are coupled to corresponding inputs of the full adder FA, which in turn is coupled to corresponding inputs of the adder ADD. The outputs of the temporary register group 1121 are instead coupled to corresponding inputs of the full adder FA. By replacing adder ADD0 with the full adder FA, the multiply-accumulate circuit 100D saves resources and reduces power consumption.

[0094] FIG14 shows a multiply-accumulate circuit 100E. Compared to the multiply-accumulate circuit 100D of FIG13 , the circuit 100E omits the full adder FA. The outputs of the compression tree 1120 are coupled to corresponding inputs of the adder ADD, while the outputs of the register group 1121 are coupled to corresponding inputs of the compression tree 1120.

[0095] FIG15 illustrates an example arrangement of a compression tree 1120 that can be used in each of FIG12 through FIG14 . As shown in FIG15 , compression tree 1120 comprises two stages of compression trees, where the first stage of the compression tree comprises two parallel compression trees 1120 1 , and the second stage of the compression tree comprises a single compression tree 1120 2 . FIG15 is equivalent to implementing an 8:2 compression tree using a combination of three 4:2 compression trees. The compression tree in FIG15 can have a simpler design than the compression trees in FIG12 through FIG14 . From another perspective, while FIG15 and FIG12 through FIG14 employ the same compression tree, the former can accommodate a larger multiplier size, further improving circuit processing performance.

[0096] FIG16 shows a multiply-accumulate circuit 100F, which differs from the multiply-accumulate circuit 100E of FIG14 in that the compression tree 1120 is replaced by a full adder module 1120′ having multiple stages of full adders FA.

[0097] Figure 17 shows a multiply-accumulate circuit 100G. Compared to the multiply-accumulate circuit 100E of Figure 14 , it differs in that shifters 11231 and 11232 are further provided between the outputs of the compression tree 1120 and the corresponding inputs of the full adder FA. For example, assuming that Ak and bk are processed by the input processing circuit 200 of Figures 8 and 9 , the shifting configuration of shifters 11231 and 11232 can implement a shift operation corresponding to the splitting performed by the input processing circuit 200. Therefore, the multiply-accumulate circuit 100G is capable of supporting mixed-bit multiply-accumulate operations. Alternatively, a corresponding shifter can be provided between each output of each multiplier 1110 and the corresponding input of the compression tree 1120. However, this obviously requires a much larger number of shifters, resulting in an unnecessary increase in circuit area and power consumption.

[0098] It can be understood that the aforementioned multiplication-accumulation circuits can be enhanced to support mixed-bit multiplication-accumulation operations by adding shifters. For example, in FIG10 , a shifter can be added between the output of the multiplier 1110 and the input of the adder ADD; in FIG11 , a shifter can be added between each output of the multiplier 1110 and the corresponding input of the full adder FA; in FIG12 , a shifter can be added between each output of each multiplier 1110 and the corresponding input of the compression tree 1120, or between each output of the compression tree 1120 and the corresponding input of the adder ADD0, or between the output of the adder ADD0 and the input of the adder ADD0. 13 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the compression tree 1120, or a shifter may be added between each output end of the compression tree 1120 and the corresponding input end of the full adder FA; in FIG14 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the compression tree 1120; in FIG16 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the full adder module 1120′.

[0099] FIG18 illustrates a multiplication-accumulation circuit 100′ that can be used to implement the multiplication-accumulation circuit 100 of the arithmetic circuit 1000 of FIG4 and FIG5 according to some embodiments of the present invention. The multiplication-accumulation circuit 100′ includes two or more multiplication-accumulation units 110 1, 110 2, ..., 110 j (j is a positive integer greater than 1) and a summation unit 120. The output of each of the multiplication-accumulation units 110 1, 110 2, ..., 110 j is coupled to a corresponding input of the summation unit 120. The input of each of the multiplication-accumulation units 110 1, 110 2, ..., 110 j can provide an input IN of the multiplication-accumulation circuit 100′, while the output of the summation unit 120 can provide an output OUT of the multiplication-accumulation circuit 100′.

[0100] Each of the multiplication and accumulation units 1101, 1102, ... 110j includes a multiplication subcircuit 1111, 1112, ... 110j and an accumulation subcircuit 1121, 1122, ... 112j. The summation unit 120 is configured to receive and sum the outputs of the multiplication and accumulation units 1101, 1102, ... 110j.

[0101] Each of the multiply-accumulate units 110 1, 110 2, ..., 110 j is similar to the multiply-accumulate unit 110 of the aforementioned multiply-accumulate circuit 100. Therefore, the previous description of the multiply-accumulate unit 110 and its various embodiments also apply here and will not be repeated here. It will be appreciated that the multiply-accumulate units 110 1, 110 2, ..., 110 j may have the same design or different designs.

[0102] Compared to the multiplication-accumulation circuit 100 having only one multiplication-accumulation unit 110, the multiplication-accumulation circuit 100' has multiple parallel multiplication-accumulation units 1101, 1102, ... 110j. Each multiplication-accumulation unit takes on a part of the accumulation function, so that each multiplication-accumulation unit can be kept at an appropriate scale, avoiding the difficulty of timing convergence caused by the circuit scale of a single multiplication-accumulation unit being too large, facilitating the reduction of glitch power consumption and optimizing circuit speed.

[0103] The summation unit 120 may include s levels of compressed trees and adders. The output of each of the multiplication-accumulation units 110 1, 110 2, ..., 110 j is coupled to the corresponding input of the first-level compressed tree in the s-level compressed trees, the output of the i-th-level compressed tree in the s-level compressed trees is coupled to the corresponding input of the (i+1)-th-level compressed tree in the s-level compressed trees, and the output of the s-th-level compressed tree in the s-level compressed trees is coupled to the corresponding input of the adder. Here, s is a non-negative integer, i=1, 2, ..., s-1. It should be understood that when s=0, the summation unit 120 includes only an adder and no compressed trees. For example, when j is 2, the summation unit 120 may include only an adder. Each level of compressed trees may include one compressed tree or multiple compressed trees in parallel. Similar to the above, the compressed trees here may alternatively be implemented as full adders or a combination of full adders and half adders.

[0104] In addition, in some embodiments, the summing unit 120 may further include an additional register group, the input of which is coupled to the output of the adder, and the output of which is coupled to the corresponding input of the first-level compression tree in the s-level compression tree. It should be understood that when s=0, the summing unit 120 includes only the adder. In this case, the summing unit 120 may further include a second adder and an additional register group, the input of which is coupled to the output of the second adder, and the output of the additional register group and the output of the adder are coupled to the corresponding inputs of the second adder. Due to the introduction of the additional register group, the summing unit 120 also has an accumulation function. This means that the accumulation subcircuit of each of the multiplication and accumulation units 110 1, 110 2, ... 110 j does not need to perform full accumulation, thereby reducing the bit width requirement of the register group of the accumulation subcircuit, so that the registers in the register group of the accumulation subcircuit can have a smaller number of bits, thereby having lower area and power consumption.

[0105] Since the summing unit 120 must continuously flip (flipping means the circuit switches from 0 to 1 or from 1 to 0) throughout the entire operation process of the multiplication-accumulation units 110 1, 110 2, ..., 110 j) to perform the summing operation, the dynamic power consumption of the multiplication-accumulation circuit 100 ′ is high. Therefore, in some embodiments, the multiplication-accumulation circuit 100 ′ further includes a control element disposed between the output of each of the multiplication-accumulation units 110 1, 110 2, ..., 110 j and the corresponding input of the summing unit 120. The control element may be configured to receive a control signal and the output of the corresponding multiplication-accumulation unit and, based on the control signal, control whether the output of the corresponding multiplication-accumulation unit is provided to the summing unit 120 at the output of the control element. For example, the control element may include at least one of the following: an AND gate, an NAND gate, a multiplexer, or an inverting multiplexer.

[0106] The control signal can be configured to cause the control element to not provide the output of the corresponding multiplication and accumulation unit to the summing unit 120 at its output terminal before the corresponding multiplication and accumulation unit completes each round of accumulation, and to provide the output of the corresponding multiplication and accumulation unit to the summing unit 120 at its output terminal after the corresponding multiplication and accumulation unit completes each round of accumulation and before starting the next round of accumulation. Note that "each round of accumulation" here refers to the accumulation performed from the time the registers of each multiplication and accumulation unit are cleared of stored results in preparation for accumulation to the time the registers are cleared of stored results in preparation for accumulation, and does not refer to each time the registers are updated with stored results.

[0107] Under the control of the control element, summing unit 120 does not receive the outputs of each multiplication-accumulation unit until each multiplication-accumulation unit completes its current round of accumulation, and thus does not perform a summation operation. In other words, under the control of the control element, the input received by summing unit 120 is always zero until each multiplication-accumulation unit completes its current round of accumulation. Only after each multiplication-accumulation unit completes its current round of accumulation does summing unit 120, under the control of the control element, receive and sum the outputs of each multiplication-accumulation unit. In other words, during the entire operation of multiplication-accumulation units 110 1, 110 2, ..., 110 j, each multiplication-accumulation unit continuously flips, but summing unit 120 does not flip. Only after the operation of multiplication-accumulation units 110 1, 110 2, ..., 110 j completes does summing unit 120 flip for one cycle for summing. Due to the isolation of the control element, the flipping frequency of summing unit 120 is much lower than that of multiplication-accumulation units 110 1, 110 2, ..., 110 j. The multiply-accumulate units 110 1, 110 2, ..., 110 j can be considered as the active region of the multiply-accumulate circuit 100 ′, while the summation unit 120 can be considered as the quiet region of the multiply-accumulate circuit 100 ′. By dividing the active region into the quiet region, the multiply-accumulate circuit 100 ′ achieves reduced power consumption.

[0108] For non-limiting illustrative purposes, FIG. 19 to FIG. 22 respectively illustrate exemplary circuit diagrams for implementing the multiplication-accumulation circuit 100 ′ of FIG. 18 according to some embodiments of the present invention.

[0109] FIG19 shows a multiply-accumulate circuit 100H. Compared to the multiply-accumulate circuit 100G in FIG17 , it differs in that the number of multiply-accumulate units has been increased from one to j, and a summation unit 120 is added to sum the outputs from the j multiply-accumulate units 110 1, ..., 110 j. Summation unit 120 includes a first-level compression tree 1210 and an adder 1200. When j = 2, compression tree 1210 can be omitted. By designing the multiply-accumulate units 110 1, ..., 110 j in parallel, each multiply-accumulate unit in the multiply-accumulate circuit 100H can perform m logarithmic multiply-accumulates per cycle. Compared to the (x / m) cycles required for the multiply-accumulate circuit 100G in FIG17 , the multiply-accumulate circuit 100H in FIG19 only requires (x / jm+1) cycles, resulting in improved computational efficiency. The number j of parallel multiply-accumulate units can be flexibly configured according to actual needs. In addition, compared with the multiplication-accumulation circuit 100G which uses a single accumulation sub-circuit for accumulation, the multiplication-accumulation circuit 100H uses multiple accumulation sub-circuits for accumulation, which can avoid the difficulty of timing convergence caused by the circuit scale of one accumulation sub-circuit being too large.

[0110] Referring to FIG. 20 , it shows that summing unit 120 is provided with two levels of compressed trees before adder 1200. The first-level compressed tree includes two parallel compressed trees 1210 1 and 1210 2, and the second-level compressed tree includes a compressed tree 1220. The outputs of the multiplication-accumulation units 110 1, ..., 110 j can be coupled to the respective inputs of the first-level compressed trees 1210 1 and 1210 2. The outputs of the first-level compressed trees 1210 1 and 1210 2 can be coupled to the respective inputs of the second-level compressed tree 1220. The output of the second-level compressed tree 1220 can be coupled to adder 1200. The output of adder 1200 can provide both the output of summing unit 120 and the output of the multiplication-accumulation circuit. FIG. 20 is equivalent to implementing an 8:2 compressed tree using a combination of three 4:2 compressed trees. The compression tree of the summing unit 120 of FIG20 can have a simpler design than the compression tree of the summing unit 120 of FIG19 . From another perspective, when the summing unit 120 of FIG20 and the summing unit 120 of FIG19 use the same compression tree, the former can accommodate a larger multiplication-accumulation unit size, thereby further improving circuit processing performance.

[0111] FIG21 shows a multiply-accumulate circuit 100I. Compared to the multiply-accumulate circuit 100H of FIG19 , it differs in that the summing unit 120 further includes an additional register group 1201. The input of the additional register group 1201 is coupled to the output of the adder 1200, and the output of the additional register group 1201 is coupled to the corresponding input of the first-stage compression tree 1210. The introduction of the additional register group 1201 provides summing unit 120 with an accumulation function. This eliminates the need for the accumulation subcircuit of each of the multiply-accumulate units 110 1, ..., 110 j to perform full accumulation. This reduces the bit width requirement for the register group of the accumulation subcircuit, allowing the registers in the register group of the accumulation subcircuit to have a smaller number of bits, thereby reducing area and power consumption.

[0112] FIG22 shows a multiply-accumulate circuit 100J. Compared to the multiply-accumulate circuit 100I of FIG21 , this circuit differs in that control elements 113 1 , 113 j are further provided between the output terminals of the multiply-accumulate units 110 1 , 110 j and the corresponding input terminals of the summing unit 120. The control elements 113 1 , 113 j receive the outputs of the corresponding multiply-accumulate units 110 1 , 110 j and control signals Sc 1 , Sc j as inputs and are configured to control whether the outputs of the corresponding multiply-accumulate units 110 1 , 110 j are provided to the summing unit 120 at the output terminals of the control elements 113 1 , 113 j based on the control signals Sc 1 , Sc j. Each of the control elements 113 1 , 113 j may include at least one of the following: an AND gate, an NAND gate, a multiplexer, or an inverting multiplexer. For example, each of the control elements 113 1 , ... 113 j may include an AND gate group, an NAND gate group, a multiplexer group, or an inverting multiplexer group. The number of elements in the AND gate group, NAND gate group, multiplexer group, or inverting multiplexer group may depend on the data bit width. For example, when each of the control elements 113 1 , ... 113 j includes an AND gate group, when the control signal Sc 1 , ... Sc j is 0, the output of the register group of the corresponding multiply-accumulate unit may not be provided at the output terminal (instead, the output terminal may output 0), and when the control signal Sc 1 , ... Sc j is 1, the output of the register group of the corresponding multiply-accumulate unit may be provided at the output terminal. When the control elements 113 1, ... 113 j each include a multiplexer group, the control signal Sc 1, ... Sc j can serve as a selection signal, 0 can serve as a first input, and the output of the register group of the corresponding multiplication and accumulation unit can serve as a second input. Thus, the multiplexer group can provide the first input of 0 at its output end (i.e., not provide the second input as the output of the register group of the corresponding multiplication and accumulation unit at its output end) when the control signal Sc 1, ... Sc j = 0, and provide the second input as the output of the register group of the corresponding multiplication and accumulation unit at its output end when the control signal Sc 1, ... Sc j = 1. The situations when the control elements 113 1, ... 113 j each include an anti-AND gate group and the situations when the control elements 113 1, ... 113 j each include an inverting multiplexer group are similar to the situations when the control elements 113 1, ... 113 j each include an AND gate group and the situations when the control elements 113 1, ... 113 j each include a multiplexer group, but inverted outputs are provided, which can be corrected within the summing unit 120 by adjusting the configuration of the summing unit 120 (for example, adding an anti-gate or an inverter, etc.).

[0113] For example, assume that the multiply-accumulate circuit 100J is to implement a multiply-accumulate of 1024 logarithms (A 1·b 1+A 2·b 2+...A 1024·b 1024), the multiplication-accumulation circuit 100J includes 4 multiplication-accumulation units (j=4), and the multiplication subcircuit of each multiplication-accumulation unit includes 4 multipliers (m=4). Then, a typical multiplication-accumulation operation process can be performed as follows: 16 multipliers calculate in parallel to output 16 multiplication operation results in each cycle; 4 accumulation subcircuits accumulate in parallel, and the temporary register group in each accumulation subcircuit is configured to output and clear the stored results every 8 cycles (meaning that one round of accumulation includes 8 cycles). Therefore, under the control of the corresponding control element, the output provided to the summation unit by each multiplication-accumulation unit includes 32 logarithmic multiplication-accumulation results, that is, the summation unit will receive 128 logarithmic multiplication-accumulation results every 8 cycles; in order to complete the multiplication-accumulation of 1024 logarithms, the compression tree, adder and additional temporary register group in the summation unit only need to be flipped 8 times, thereby achieving reduced power consumption.

[0114] As mentioned above, since the unknown first number ak can be processed as an unsigned number Ak, the multiplier of the multiply-accumulate circuits 100 and 100' only needs to support the multiplication of the unsigned number Ak with the known number bk (whether signed or unsigned). The multiplication operation mul for the unsigned number Ak (assuming a bit width of z) and the known number bk (assuming a bit width of w) can be unified as follows through the following mathematical derivation.

[0115] When bk is an unsigned number,

[0116] Among them, bk(w-1) is the most significant bit of bk, and bk[(w-2):0] is the rest of the bits of bk except the most significant bit bk(w-1). " is a shift operation, which means shifting left by (w-1) bits.

[0117] When bk is a signed number,

[0118] in, Is the bitwise negation operator. It can be extracted as a constant term. Therefore, the operation process of the unsigned number Ak and the pre-known unsigned number bk is similar to the operation process of the unsigned number Ak and the pre-known signed number bk. When calculating the partial product of Ak and the other bits bk[(w-2):0] of bk except the highest bit bk(w-1), ) are the same, the difference lies in finding the partial product of Ak and the most significant bit of bk [bk(w-1)], because for a signed number bk, its most significant bit is the sign bit and does not represent a value.

[0119] Based on the above-mentioned operational principles, the present invention provides a multiplier that can be used to perform a multiplication operation between a first multiplier and a second multiplier, wherein the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned number or a signed number. Such a multiplier may include a partial product generation circuit and a partial product summation circuit. The partial product generation circuit is configured to receive the first multiplier and the second multiplier and output their partial products. The input terminal of the partial product summation circuit is coupled to the output terminal of the partial product generation circuit. The partial product summation circuit is configured to receive the partial products output by the partial product generation circuit and sum them. In particular, the partial product generation circuit may include a first partial product generation unit for outputting the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit is configured to: if the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; and if the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier. For example, the first partial product generation unit may be configured to: receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number; if the sign flag indicates that the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; and if the sign flag indicates that the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit may also determine whether the second multiplier is an unsigned number or a signed number using other methods.

[0120] FIG23 illustrates a multiplier 1110 according to some embodiments of the present invention. As shown in FIG23 , the multiplier 1110 includes a partial product generation circuit 510 and a partial product summation circuit 520. The input of the partial product generation circuit 510 may provide an input terminal IN of the multiplier 1110. The input of the partial product summation circuit 520 is coupled to the output terminal of the partial product generation circuit 510. The output terminal of the partial product summation circuit 520 may provide an output terminal OUT of the multiplier 1110.

[0121] The partial product generation circuit 510 is configured to receive a first unsigned multiplier and a pre-known second multiplier and output their partial products. The partial product generation circuit 510 may include a first partial product generation unit 511 for outputting the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit 511 may receive the most significant bit of the second multiplier and the first multiplier, as well as a sign flag indicating whether the second multiplier is unsigned or signed. If the received sign flag indicates that the second multiplier is unsigned, the first partial product generation unit 511 is configured to output the partial product of the most significant bit of the second multiplier and the first multiplier. If the received sign flag indicates that the second multiplier is signed, the first partial product generation unit 511 is further configured to output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier.

[0122] In some embodiments, the first partial product generating unit 511 includes: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; and an XOR gate group configured to receive the AND operation result of the AND gate group and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation on them. The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit 511.

[0123] In some embodiments, the first partial product generating unit 511 includes: an NOR gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform a NOR operation on them; and an XOR gate group configured to receive the NOR operation result of the NOR gate group and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation on them. The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit 511.

[0124] In some embodiments, the first partial product generation unit 511 includes: an exclusive-OR gate configured to receive the highest bit of the second multiplier and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an exclusive-OR operation thereon; and a multiplexer group, each multiplexer in the multiplexer group configured to receive the sign flag as a first input, receive the exclusive-OR operation result of the exclusive-OR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input based on the selection signal. The output of the multiplexer group is provided as the output of the first partial product generation unit 511.

[0125] In some embodiments, the first partial product generation unit 511 includes: an exclusive-OR gate configured to receive the highest bit of the second multiplier and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an exclusive-OR operation on them; and an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group configured to receive the sign flag as a first input, receive the exclusive-OR operation result of the exclusive-OR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input based on the selection signal. The output of the inverting multiplexer group is provided as the output of the first partial product generation unit 511.

[0126] In some embodiments, the first partial product generation unit 511 includes: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; a multiplexer group configured to receive the AND operation result of the AND gate group as a first input, receive the inverted result of the AND operation result of the AND gate group as a second input, receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number as a selection signal, and output the first input or the second input based on the selection signal. The output of the multiplexer group is provided as the output of the first partial product generation unit 511. An inverting gate group can be used to receive the AND operation result of the AND gate group and perform a NOT operation on it to obtain the inverted result of the AND operation result of the AND gate group. Furthermore, the AND gate group can be replaced by an inverting AND gate group. Additionally or alternatively, the multiplexer group can be replaced by an inverting multiplexer group.

[0127] The partial product generation circuit 510 may further include a second partial product generation unit 512 for outputting a partial product of the first multiplier and bits other than the most significant bit of the second multiplier.

[0128] In some embodiments, the second partial product generation unit 512 may be configured to output a partial product of a modified second multiplier (bk[(w-2):0]) and the first multiplier (Ak). The modified second multiplier (bk[(w-2):0]) is obtained by removing the most significant bit (bk(w-1)) of the second multiplier (bk) and is an unsigned number. In such embodiments, the second partial product generation unit 512 may include a multiplier configured to perform an unsigned-to-unsigned multiplication operation.

[0129] Instead of generating partial products from bk[(w-2):0] as a whole, bk[(w-2):0] can be split into multiple parts to generate partial products separately, each part comprising one or more bits from bk[(w-2):0]. For example, the second partial product generation unit 512 may include multiple second partial product generation units, each of which is configured to output a partial product of corresponding bits of the second multiplier (bk) other than the most significant bit (bk(w-1)) and the first multiplier (Ak). In some embodiments, each second partial product generation unit may include an AND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform an AND operation on them. The AND operation result of the AND gate group is provided as the output of each second partial product generation unit. In other embodiments, each second partial product generation unit may also include an INVERT-AND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform an AND-NOT-AND operation on them. The NOR-AND operation result of the INVERT-AND gate group is provided as the output of each second partial product generation unit.

[0130] Continuing with FIG. 23 , the partial product summation circuit 520 is configured to receive and sum the partial products output by the partial product generation circuit 510. If the multiplier 1110 is configured with dual output terminals, the partial product summation circuit 520 may include a partial product compression circuit 521. The input terminal of the partial product compression circuit 521 is coupled to the output terminal of the partial product generation circuit 510. The partial product compression circuit 521 is configured to receive the partial products output by the partial product generation circuit 510 and compress and sum them to output the sum and carry of the compressed sum of the partial products. If the multiplier 1110 is configured with a single output terminal, the partial product summation circuit 520 may further include a final addition circuit 522 in addition to the partial product compression circuit 521. The input terminal of the final addition circuit 522 is coupled to the output terminal of the partial product compression circuit 521. The final addition circuit 522 is configured to receive and sum the sum and carry output by the partial product compression circuit 521.

[0131] For non-limiting illustrative purposes, FIG. 24 to FIG. 27 respectively illustrate example circuit diagrams for implementing the multiplier 1110 of FIG. 23 according to some embodiments of the present invention.

[0132] As shown in FIG24 , multiplier 1110A has two output terminals and includes a partial product generation circuit 510 and a partial product summation circuit 520. Partial product generation circuit 510 includes a first partial product generation unit 511 and multiple second partial product generation units 512 0, ..., 512 w-3, and 512 w-2. First partial product generation unit 511 includes an AND gate group and an XOR gate group. The AND gate group receives the AND operation result of the AND gate group and the most significant bit bk(w-1) of the second multiplier bk and performs an XOR operation on them. The XOR gate group receives the XOR operation result of the AND gate group and a sign flag Flag2 indicating whether the second multiplier is unsigned or signed and performs an XOR operation on them. The XOR operation result of the XOR gate group is provided as the output of the first partial product generation unit 511. Each of the second partial product generating units 512 0, ..., 512 w-3, and 512 w-2 includes an AND gate set that receives the first multiplier Ak and a corresponding one of the second multipliers bk (bk 0, ..., bk( w-3), and bk( w-2)) and performs an AND operation on them. The AND operation result is provided as the output of the second partial product generating unit. The partial product summation circuit 520 may include a compression tree as a partial product compression circuit 521. The outputs of the first partial product generating unit 511 and the plurality of second partial product generating units 512 0, ..., 512 w-3, and 512 w-2 are respectively coupled to corresponding inputs of the partial product compression circuit 521, and the two outputs of the partial product compression circuit 521 provide the two outputs of the multiplier 1110A. In FIG24 , the partial product compression circuit 521 is shown as a single w:2 compression tree, which may also employ a combination of multiple compression trees (e.g., a cascade of multiple levels of compression trees, where each level of compression tree may include one compression tree or multiple compression trees in parallel), or may alternatively be implemented as a full adder or a combination of a full adder and a half adder.

[0133] FIG25 shows a multiplier 1110B, which differs from the multiplier 1110A in FIG24 in that the partial product summation circuit 520 further includes an adder as a final adding circuit 522, so that the multiplier 1110B has a single output terminal.

[0134] FIG26 shows a multiplier 1110C, which differs from the multiplier 1110A in FIG24 in that the AND gate group in the partial product generation circuit 510 is replaced with a NAND gate group. This results in the output of the partial product generation circuit 510 of the multiplier 1110C being inverted relative to the output of the partial product generation circuit 510 of the multiplier 1110A. Accordingly, the partial product compression circuit 521′ of the multiplier 1110C needs to be adjusted accordingly compared to the partial product compression circuit 521 of the multiplier 1110A to internally correct the inverted output of the partial product generation circuit 510 of the multiplier 1110C. This adjustment can be achieved, for example, but not limited to, by incorporating a NAND gate or an inverter into the partial product compression circuit 521′.

[0135] FIG27 shows a multiplier 1110D, which differs from the multiplier 1110C in FIG26 in that the partial product summation circuit 520 further includes an adder as a final adding circuit 522, so that the multiplier 1110D has a single output terminal.

[0136] For non-limiting illustrative purposes, FIG. 28 to FIG. 30 also respectively illustrate example circuit diagrams for implementing the first partial product generating unit 511 of the multiplier 1110 of FIG. 23 according to some embodiments of the present invention.

[0137] As shown in Figure 28, the first partial product generation unit 511A includes an exclusive OR gate (XOR) configured to receive the highest-order bit (bk(w-1)) of the second multiplier bk and a sign flag (Flag2) indicating whether the second multiplier is unsigned or signed, and perform an exclusive OR operation on them. The first partial product generation unit 511A also includes a multiplexer group (MUX). Each multiplexer group (MUX) is configured to receive the sign flag (Flag2) as a first input (q0), receive the exclusive OR operation result of the exclusive OR gate (XOR) as a second input (q1), receive the corresponding bit (Ak0, ..., Ak(z-2), Ak(z-1)) of the first multiplier Ak as a selection signal, and output either the first input (q0) or the second input (q1) based on the selection signal. Specifically, when the selection signal is 0, the multiplexer group (MUX) outputs the first input (q0), and when the selection signal is 1, the multiplexer group (MUX) outputs the second input (q1). The output of the multiplexer group (MUX) is provided as the output of the first partial product generation unit 511A. The first partial product generating unit 511A of FIG. 28 may have fewer logic gates than the first partial product generating unit 511 of FIG. 24 and FIG. 25 .

[0138] FIG29 illustrates a first partial product generating unit 511B, which differs from the first partial product generating unit 511A in FIG28 in that the multiplexer group MUX is replaced with an inverting multiplexer group MUXI. This results in the output of the first partial product generating unit 511B being inverted relative to the output of the first partial product generating unit 511A. Accordingly, the partial product compression circuit 521 of the multiplier 1110 also requires corresponding adjustments to internally correct the inverted output of the first partial product generating unit 511B. This adjustment can be achieved, for example but not limited to, by incorporating an anti-gate or inverter into the partial product compression circuit 521. The first partial product generating unit 511B in FIG29 can have fewer logic gates than the first partial product generating unit 511 in FIG26 and FIG27.

[0139] Figure 30 shows a first partial product generation unit 511C, which includes an AND gate group, a NOT gate group, and a multiplexer group (MUX). The AND gate group is configured to receive the highest bit (bk(w-1)) of the second multiplier bk and the first multiplier Ak and perform an AND operation on them. The NOT gate group is configured to receive the AND operation result of the AND gate group and perform a NOT operation (inversion) on them. The multiplexer group (MUX) is configured to receive the AND operation result of the AND gate group as a first input, the NOT operation result of the NOT gate group as a second input, and a sign flag (Flag2) indicating whether the second multiplier bk is unsigned or signed as a selection signal. The output of the multiplexer group (MUX) is provided as the output of the first partial product generation unit 511. Similarly, the AND gate group can also be replaced with an INVERTED AND gate group. Additionally or alternatively, the multiplexer group can also be replaced with an INVERTED multiplexer group. Accordingly, the partial product compression circuit 521 of the multiplier 1110 may make corresponding adjustments as appropriate.

[0140] In addition, regarding the constant term of precipitation In some embodiments, referring to FIG. 31 , the output of the partial product summation circuit 520 of the multiplier 1110 is coupled to the input of the additional adding circuit 600. The additional adding circuit 600 may be configured to add the output of the partial product summation circuit 520 to a constant when the second multiplier bk is a signed number. The constant is , where w is the bit width of the second multiplier bk. In some embodiments, the multiplier 1110 may further include an additional adding circuit 600. In other embodiments, the additional adding circuit 600 may not be used, and the constant term may be With the constant term mentioned above ( ) are processed together. For example, in some embodiments, the output processing circuit 300 shown in FIG5 may be configured to perform at least one of the following: subtracting the output of the accumulation subcircuit 112 from a first constant, the first constant being the sum of all the second numbers bk paired with the first number ak as a signed number in the plurality of pairs of first numbers ak and second numbers bk after being left-shifted by (z-1) bits ( ), where z is the bit width of the first number ak; or adding the output of the accumulation subcircuit 112 to a second constant, wherein the second constant is , where w is the bit width of the second multiplier bk, and y is the number of second multipliers bk obtained as signed numbers from all the second numbers bk of the plurality of pairs of first numbers ak and second numbers bk. In some cases, it is not necessary to provide a dedicated output processing circuit 300 or an additional adding circuit 600 to process these constant terms. For example, in the convolutional computing unit of a neural network processor, in addition to performing multiplication and accumulation operations on the startup data and weight data, the result of the multiplication and accumulation operation also needs to be added to the bias term. In the convolutional computing unit, the addition of the bias term itself is handled by dedicated hardware, so the above constant term and( ) can be integrated with the bias term in advance without paying additional hardware costs for processing.

[0141] In another aspect, the present invention provides a processor, which may include the multiplier according to any of the aforementioned embodiments, the multiplication-accumulation circuit according to any of the aforementioned embodiments, or the arithmetic circuit according to any of the aforementioned embodiments. For example, such a processor may be an auxiliary processor, a digital signal processor, a central processing unit, a dedicated instruction processor, a neural network processor, or other processors. If such a processor is a neural network processor, its convolution calculation unit may include the multiplier according to any of the aforementioned embodiments, the multiplication-accumulation circuit according to any of the aforementioned embodiments, or the arithmetic circuit according to any of the aforementioned embodiments.

[0142] In yet another aspect, the present invention provides a computing device, which may include a processor according to any of the aforementioned embodiments. Examples of computing devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic testing equipment, cellular communication infrastructure such as base stations, and the like. Examples of computing devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, telephones, televisions, computer monitors, computers, modems, PDAs, laptops, tablets, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automobile electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer / dryer combinations, peripheral devices, clocks, and the like. Furthermore, computing devices may include incomplete products.

[0143] The terms "left," "right," "front," "back," "top," "bottom," "upper," "lower," "higher," "lower," and the like, if used in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. For example, when the device in the figures is turned over, features described as "above" other features could then be described as "below" the other features. The device can also be otherwise oriented (rotated 90 degrees or at other orientations), and relative spatial relationships would be interpreted accordingly.

[0144] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly attached," "directly connected," "directly coupled," or "directly contacting" another element, there are no intervening elements. In the specification and claims, when a feature is positioned "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or is located above or below the adjacent feature.

[0145] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present invention is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0146] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for variations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0147] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0148] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or elements, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or elements and / or their combinations.

[0149] In addition, when used in this disclosure, the words "herein," "above," "below," "hereunder," "above," and words of similar meaning shall refer to the disclosure as a whole and not to any particular portions of the disclosure. Furthermore, unless expressly stated otherwise or understood otherwise in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0150] In the present invention, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing something" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0151] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0152] Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all of the above-described embodiments of the invention may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this description and the drawings should be regarded as illustrative rather than restrictive. Indeed, the novel devices, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0153] The various embodiments of the present invention may be described in a progressive manner, with reference to the common and similar parts between the various embodiments. Each embodiment will focus on the differences from the other embodiments. In the present invention, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with such embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0154] Although certain specific embodiments of the present invention have been described in detail through examples, those skilled in the art will appreciate that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The various embodiments of the present invention may be combined in any manner without departing from the spirit and scope of the present invention. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

[0155] 10: Multiply-accumulate circuit 11: Multiplier 12: Adder 13: Register 20: Multiply-accumulate circuit 21: Multiplier 22: Adder 23: Register 30: Multiplication and accumulation circuit 31: Multiplier 32: Adder 33: register 34: Adder 35: Subtractor 361, 362: Related control elements Sc1, Sc2: control signal 1000, 1000': Operational circuit 100, 100': Multiply-accumulate circuit 100A~100J: Multiplication and accumulation circuit 110: Multiplication and accumulation unit 111: Multiplication subcircuit 1110: Multiplier 1110A~1110D: Multiplier 112: Accumulation subcircuit 1120:Compressed Tree 1120 1, 1120 2: compression tree 1121: register group 1120': Full adder module 11231, 11232: shifter 113: Control element 120:Summation unit 1200: Adder 1201: Additional register group 1210, 1220: compression tree 200: Input processing circuit 200A~200D: Input processing circuit 300: output processing circuit 510: Partial product generation circuit 511: First partial product generating unit 511A~511C: First partial product generation unit 512: Second partial product generating unit 520: Partial product summation circuit 521, 521': Partial product compression circuit 522: Final adding circuit 600: Additional adding circuit Flag1, Flag2: symbol flags FA: Full Adder ADD, ADD0: adder AND: and gate group NAND: NAND gate group NOT: Reverse brake (group) XOR: Exclusive OR gate (group) MUX: Multiplexer (group) MUXI: Inverting Multiplexer Group r, w, z: bit width

Claims

1. A multiplier for performing multiplication of a first multiplier and a second multiplier, wherein the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned or signed number, the multiplier comprising: A partial product generation circuit is configured to receive the first multiplier and the second multiplier and output their partial product; The system also includes a partial product summation circuit, the input of which is coupled to the output of the partial product generation circuit. The partial product summation circuit is configured to receive and sum the partial products output by the partial product generation circuit. The partial product generation circuit includes a first partial product generation unit for outputting the partial product obtained by multiplying the most significant digit of the second multiplier by the first multiplier. The first partial product generation unit is configured to: output the partial product obtained by multiplying the most significant digit of the second multiplier by the first multiplier when the second multiplier is unsigned; and output the inverted result of the partial product obtained by multiplying the most significant digit of the second multiplier by the first multiplier when the second multiplier is signed.

2. The multiplier according to claim 1, wherein, The first partial product generating unit is configured to: receive a sign flag indicating whether the second multiplier is an unsigned or signed number; output the partial product obtained by multiplying the most significant bit of the second multiplier with the first multiplier if the sign flag indicates that the second multiplier is an unsigned number; and output the inverted result of the partial product obtained by multiplying the most significant bit of the second multiplier with the first multiplier if the sign flag indicates that the second multiplier is a signed number.

3. The multiplier according to claim 2, wherein, The first partial product generation unit includes: a gate group configured to receive the most significant bit of the second multiplier and the first multiplier and perform a bitwise AND operation on them; and an XOR gate group configured to receive the bitwise AND operation result of the gate group and the sign flag bit and perform an XOR operation on them, wherein the XOR operation result of the XOR gate group is provided as the output of the first partial product generation unit.

4. The multiplier according to claim 2, wherein, The first partial product generating unit includes: an inverse gate group configured to receive the most significant bit of the second multiplier and the first multiplier and perform a NAND operation on them; and an XOR gate group configured to receive the NAND operation result of the inverse gate group and the sign flag bit and perform an XOR operation on them, wherein the XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

5. The multiplier according to claim 2, wherein, The first partial product generating unit includes: an XOR gate configured to receive the most significant bit of the second multiplier and the sign flag bit and perform an XOR operation thereon; and a multiplexer group, each multiplexer in the multiplexer group being configured to receive the sign flag bit as a first input, receive the XOR operation result of the XOR gate as a second input, receive a corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generating unit.

6. The multiplier according to claim 2, wherein, The first partial product generating unit includes: an XOR gate configured to receive the most significant bit of the second multiplier and the sign flag bit and perform an XOR operation on them; and an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group being configured to receive the sign flag bit as a first input, receive the XOR operation result of the XOR gate as a second input, receive a corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the inverting multiplexer group is provided as the output of the first partial product generating unit.

7. The multiplier according to claim 2, wherein, The first partial product generation unit includes: a gate group configured to receive the most significant bit of the second multiplier and the first multiplier and perform an AND operation on them; and a multiplexer group configured to receive the AND operation result of the gate group as a first input, receive the inverted result of the AND operation result of the gate group as a second input, receive the sign flag bit as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generation unit.

8. The multiplier according to any one of claims 1 to 7, wherein, The partial product generation circuit further includes a second partial product generation unit for outputting a partial product obtained by multiplying a modified second multiplier by a first multiplier, wherein the modified second multiplier is obtained by removing the most significant bit of the second multiplier and is an unsigned number, and the second partial product generation unit includes a multiplier for performing unsigned number multiplication operations.

9. The multiplier according to any one of claims 1 to 7, wherein, The partial product generation circuit further includes a plurality of second partial product generation units, each of which is used to output the partial product obtained by multiplying the corresponding bit of the second multiplier (excluding the highest bit) with the first multiplier.

10. The multiplier according to claim 9, wherein, Each of the plurality of second partial product generating units includes one of the following: a gate group configured to receive a corresponding bit of the second multiplier (excluding the most significant bit) and the first multiplier and perform an AND operation on them, wherein the AND operation result of the gate group is provided as the output of the second partial product generating unit; or an inverse gate group configured to receive a corresponding bit of the second multiplier (excluding the most significant bit) and the first multiplier and perform a NAND operation on them, wherein the NAND operation result of the inverse gate group is provided as the output of the second partial product generating unit.

11. The multiplier according to claim 1, wherein, The output of the partial product summing circuit is coupled to the input of an additional adder circuit, which is configured to add the output of the partial product summing circuit to a constant when the second multiplier is a signed number, wherein the constant is, where z is the bit width of the first multiplier and w is the bit width of the second multiplier.

12. A multiply-accumulate circuit for performing multiply-accumulate operations on multiple pairs of first and second numbers, the second number being known in advance, the multiply-accumulate circuit comprising at least one multiply-accumulate unit, the multiply-accumulate unit comprising: A multiplication subcircuit, comprising a multiplier for performing a multiplication operation of a first multiplier and a second multiplier, the first multiplier being obtained from a first number and being an unsigned number, and the second multiplier being obtained from a second number and being a previously known unsigned or signed number, the multiplier being configured to provide an output as an unsigned number, wherein the multiplier is a multiplier according to any one of claims 1 to 11; and an accumulation subcircuit, the input of the accumulation subcircuit being coupled to the output of the multiplication subcircuit, the accumulation subcircuit being configured to receive the output of the multiplication subcircuit and accumulate it.

13. The multiply-accumulate circuit according to claim 12, wherein, The multiplication subcircuit includes a plurality of said multipliers, each said multiplier being configured to receive a corresponding pair of first multipliers and second multipliers and to multiply the corresponding pair of first multipliers and second multipliers.

14. The multiply-accumulate circuit according to claim 13, wherein, The accumulator sub-circuit includes one of the following: an n-level compressed tree, a first adder, a second adder, and a register group. The output of the multiplication sub-circuit is coupled to the corresponding input of the first-level compressed tree in the n-level compressed tree. The output of the i-th level compressed tree in the n-level compressed tree is coupled to the corresponding input of the (i+1)-th level compressed tree in the n-level compressed tree. The output of the n-th level compressed tree in the n-level compressed tree is coupled to the corresponding input of the first adder. The output of the first adder is coupled to the corresponding input of the second adder. The output of the second adder is coupled to the input of the register group. The output of the register group... The multiplication sub-circuit is coupled to the corresponding input of the second adder, where n is a positive integer, i = 1, 2, ..., n-1; or an n-level compressed tree, a full adder, an adder and a register group, the output of the multiplication sub-circuit is coupled to the corresponding input of the first level of the n-level compressed tree, the output of the i-th level of the n-level compressed tree is coupled to the corresponding input of the (i+1)-th level of the n-level compressed tree, the output of the n-th level of the n-level compressed tree is coupled to the corresponding input of the full adder, and the output of the full adder is coupled to the corresponding input of the adder. The output of the multiplier is coupled to the input of the register group, and the output of the register group is coupled to the corresponding input of the full adder, where n is a positive integer, i = 1, 2, ..., n-1; or an n-level compressed tree, an adder, and a register group, the output of the multiplier sub-circuit is coupled to the corresponding input of the first level of the n-level compressed tree, the output of the i-th level of the n-level compressed tree is coupled to the corresponding input of the (i+1)-th level of the n-level compressed tree, and the output of the n-th level of the n-level compressed tree is coupled to the corresponding input of the adder, the adder... The output terminal of the multiplier is coupled to the input terminal of the register group, and the output terminal of the register group is coupled to the corresponding input terminal of the first level of the compressed tree in the n-level compressed tree, where n is a positive integer and i = 1, 2, ..., n-1; or a full adder module, adder and register group having one or more levels of full adders, the output terminal of the multiplier sub-circuit is coupled to the corresponding input terminal of the full adder module, the output terminal of the full adder module is coupled to the corresponding input terminal of the adder, the output terminal of the adder is coupled to the input terminal of the register group, and the output terminal of the register group is coupled to the corresponding input terminal of the full adder module.

15. The multiply-accumulate circuit according to any one of claims 12 to 14, wherein, The at least one multiply-accumulate unit includes two or more of the multiply-accumulate units, and the multiply-accumulate circuit further includes a summing unit, the input of which is coupled to the output of the two or more multiply-accumulate units, and the summing unit is configured to receive the output of the two or more multiply-accumulate units and sum them.

16. The multiply-accumulate circuit according to claim 15, wherein, The summation unit includes an s-level compressed tree and an adder. The output of each of the two or more multiply-accumulate units is coupled to the corresponding input of the first-level compressed tree in the s-level compressed tree. The output of the i-th level compressed tree in the s-level compressed tree is coupled to the corresponding input of the (i+1)-th level compressed tree in the s-level compressed tree. The output of the s-th level compressed tree in the s-level compressed tree is coupled to the corresponding input of the adder, where s is a non-negative integer and i = 1, 2, ..., s-1.

17. The multiply-accumulate circuit according to claim 16, wherein, The summation unit further includes an additional register group, the input of which is coupled to the output of the adder, and the output of which is coupled to the corresponding input of the first-level compression tree in the s-level compression tree.

18. The multiply-accumulate circuit according to claim 15, wherein, The multiply-accumulate circuit further includes a control element disposed between the output of each of the two or more multiply-accumulate units and the corresponding input of the summing unit. The control element is configured to receive a control signal and the output of the corresponding multiply-accumulate unit and, based on the control signal, control whether to provide the output of the corresponding multiply-accumulate unit to the summing unit at the output of the control element.

19. The multiply-accumulate circuit according to claim 12, wherein, The input terminal of the multiplication sub-circuit is also coupled to the output terminal of the input processing circuit, which is configured to receive the first number and the second number and: when the first number is a signed number, output the first number as a first multiplier for feeding into the multiplier by inverting the sign bit of the first number, and output the second number as a second multiplier for feeding into the multiplier; and when the first number is an unsigned number, output the first number as a first multiplier for feeding into the multiplier, and output the second number as a second multiplier for feeding into the multiplier.

20. The multiply-accumulate circuit according to claim 19, wherein, The input processing circuit includes one of the following: an XOR gate, configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is unsigned or signed, and perform an XOR operation on them, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit; or a multiplexer, configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is unsigned or signed as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

21. The multiply-accumulate circuit according to claim 12, wherein, The input terminal of the multiplication sub-circuit is also coupled to the output terminal of the input processing circuit, which is configured to receive the first number and the second number. The input processing circuit is also configured to split the first number according to the bit width of the multiplier. The multiply-accumulate circuit further includes a shifter coupled to the output terminal of the multiplication sub-circuit, which is configured to perform a shift operation corresponding to the split.

22. The multiply-accumulate circuit according to claim 21, wherein: The input processing circuit is further configured to split the second number according to the bit width of the multiplier; or the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

23. The multiply-accumulate circuit according to claim 12, wherein, The output of the accumulator subcircuit is coupled to the input of an output processing circuit configured to perform at least one of the following: subtracting the output of the accumulator subcircuit from a first constant, the first constant being the sum of all second numbers paired with the first number as a signed number in the plurality of pairs of first and second numbers after left shifting by (z-1) bits, where z is the bit width of the first number; or adding the output of the accumulator subcircuit to a second constant, the second constant being, where z is the bit width of the first multiplier, w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all the second numbers in the plurality of pairs of first and second numbers.

24. An operational circuit, comprising: Multiply-accumulate circuit according to any one of claims 12 to 23; The system also includes an input processing circuit, the output of which is coupled to the input of the multiply-accumulate circuit. The input processing circuit is configured to receive the first number and the second number and: if the first number is a signed number, output the first number as a first multiplier for feeding into the multiplier by inverting the sign bit of the first number, and output the second number as a second multiplier for feeding into the multiplier; and if the first number is an unsigned number, output the first number as a first multiplier for feeding into the multiplier, and output the second number as a second multiplier for feeding into the multiplier.

25. The operational circuit according to claim 24, wherein, The input processing circuit includes one of the following: an XOR gate, configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is unsigned or signed, and perform an XOR operation on them, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit; or a multiplexer, configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is unsigned or signed as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

26. The operational circuit according to claim 24, wherein, The input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiply-accumulate circuit further includes a shifter coupled to the output of the multiplication sub-circuit, the shifter being configured to perform a shift operation corresponding to the split.

27. The operational circuit according to claim 26, wherein, The input processing circuit is further configured to split the second number according to the bit width of the multiplier; or the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

28. The operational circuit according to claim 24 further includes: An output processing circuit, wherein the output of the multiply-accumulate circuit is coupled to the input of the output processing circuit, the output processing circuit being configured to perform at least one of the following: subtracting the output of the multiply-accumulate circuit from a first constant, the first constant being the sum of all second numbers paired with the first number as a signed number in the plurality of pairs of first and second numbers after left shifting (z-1) bits, where z is the bit width of the first number; or adding the output of the multiply-accumulate circuit to a second constant, the second constant being, where z is the bit width of the first multiplier, w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all the second numbers in the plurality of pairs of first and second numbers.

29. An operational circuit, comprising: A multiplier according to any one of claims 1 to 11; And an additional adder circuit, wherein the output of the multiplier is coupled to the input of the additional adder circuit, the additional adder circuit being configured to add the output of the partial product summing circuit to a constant when the second multiplier is a signed number, the constant being, where z is the bit width of the first multiplier and w is the bit width of the second multiplier.

30. A processor comprising a multiplier according to any one of claims 1 to 11, a multiply-accumulate circuit according to any one of claims 12 to 23, or an arithmetic circuit according to any one of claims 24 to 29.

31. A computing device comprising the processor as described in claim 30.

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