Semiconductor device and methods of forming same

Abstract

An integrated circuit includes a semiconductor substrate, a first recess in the semiconductor substrate, and a transistor. The transistor includes a plurality of stacked channels. The bottom of the recess is lower than all the channels. The transistor includes a source / drain region, the source / drain region including a bottom epitaxial structure located in the recess. The bottom epitaxial structure includes a first semiconductor layer contacting the bottom of the first recess and having a top surface lower than all the channels, and a semiconductor material different from the semiconductor substrate. The source / drain region includes a second semiconductor layer located on the bottom epitaxial structure, the second semiconductor layer having a bottom surface lower than all the channels and a top surface higher than all the channels.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor technology, and in particular to semiconductor devices and methods of forming the same. [Previous Technology]

[0002] Electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices, have an ever-increasing demand for computing power. Integrated circuits provide this computing power to these electronic devices. One way to increase the computing power of integrated circuits is to increase the number of transistors and other integrated circuit components that can be contained in a given area of ​​a semiconductor substrate.

[0003] Nanostructure transistors can help improve computing power because they can be very small and have improved functionality compared to conventional transistors. Nanostructure transistors can include multiple semiconductor nanostructures (e.g., nanowires, nanosheets, etc.) that serve as the channel region of the transistor. [Summary of the Invention]

[0004] This disclosure provides a method for forming a semiconductor device, comprising: forming a plurality of stacked first channels of a first transistor above a semiconductor substrate; forming a concave first groove in a semiconductor substrate; forming a first source / drain bottom epitaxial structure of a first source / drain region of the first transistor in the first groove, wherein the first source / drain bottom epitaxial structure includes a first semiconductor layer contacting the bottom of the first groove and having a semiconductor material different from that of the semiconductor substrate; forming a second semiconductor layer of the first source / drain region on the first source / drain bottom epitaxial structure, wherein the top surface of the second semiconductor layer is higher than all the first channels; and forming a first gate metal surrounding the first channels.

[0005] This disclosure provides a semiconductor device, comprising: a semiconductor substrate; a first trench located in the semiconductor substrate; and a first transistor including: a plurality of stacked first channels, the bottom of the first trench being lower than all the first channels; and a first source / drain region including: a first semiconductor layer, the first semiconductor layer contacting the bottom of the first trench and having a concave top surface lower than all the first channels and a semiconductor material different from the semiconductor substrate; and a second semiconductor layer having a bottom surface and a top surface, the bottom surface being lower than all the first channels and the top surface being higher than all the first channels.

[0006] This disclosure provides a semiconductor device, comprising: a semiconductor substrate; a first trench located in the semiconductor substrate; and a first transistor having a first conductivity type and including: a plurality of stacked first channels; a first gate metal surrounding the first channels; and a first source / drain region including: a first semiconductor layer located on the bottom of the first trench and having a top surface located below the bottom of the first gate metal and having a semiconductor material whose conductor material is different from that of the semiconductor substrate; and a dielectric isolation region having a bottom surface located on the top surface of the first semiconductor layer and lower than the bottom of the first gate metal.

Implementation Method

[0008] In the following description, numerous thicknesses and materials of various layers and structures within an integrated circuit die are described. Specific dimensions and materials are given by way of example of various embodiments. Based on this disclosure, those skilled in the art will recognize that other dimensions and materials may be used in many cases without departing from the scope of this disclosure.

[0009] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments disclosed herein. Of course, the above are merely examples and are not intended to limit the embodiments disclosed herein. For example, if the description mentions that a first element is formed on top of a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments disclosed herein may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0010] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," "higher," etc., may be used to facilitate the description of the relationship between one or more features or components in the diagram and another feature or component(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0011] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of this disclosure. However, those skilled in the art will understand that this disclosure may be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of the embodiments of this disclosure.

[0012] Unless the context otherwise requires, throughout the specification and subsequent requests, the word “including” and its variations, such as “including” and “contains”, shall be interpreted in an open and inclusive sense, meaning “including but not limited to”.

[0013] Using ordinal numbers such as first, second and third does not necessarily imply the order of sorting, but may simply distinguish the steps or structure of multiple examples.

[0014] Throughout this specification, references to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the referred embodiment is incorporated into at least some of the embodiments. Therefore, the phrases "in one embodiment," "in one embodiment," or "in some embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

[0015] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless otherwise expressly stated. It should also be noted that the term “or” is generally used in its meaning as including “and / or” unless otherwise expressly stated.

[0016] Embodiments of this disclosure provide an integrated circuit with a nanostructured transistor. Each nanostructured transistor includes multiple stacked channels. The stacked channels extend between source / drain regions. Embodiments of this disclosure provide source / drain regions with a bottom epitaxial structure that extends below the lowest channel. The bottom epitaxial structure includes a semiconductor material with a different composition than the other higher portions of the source / drain regions. Furthermore, N-channel transistors and P-channel transistors can have different types of bottom epitaxial structures with different numbers of layers and different layer shapes. As a result, stress or strain can be selectively applied to the source / drain regions and channels to improve the DC performance of the transistor. This leads to transistors with improved characteristics, integrated circuits with improved characteristics, and electronic devices with improved characteristics. In addition, the functionality and reliability of the transistor are improved, thereby increasing wafer yield and reducing scrap wafers.

[0017] Figure 1 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 includes a substrate 102. This integrated circuit also includes two transistors 104a and 104b. As will be described in more detail below, transistors 104a and 104b include bottom source / drain epitaxial structures whose composition and characteristics are selected to improve transistor performance.

[0018] The diagrams include some diagrammatic designations with the suffix "a" or "b". For example, transistors 104a and 104b, channels 106a and 106b (described below), and gate metals 108a and 108b, etc. In some cases, the suffix "a" or "b" may be omitted in the following description when a specific structure is not mentioned. For example, in some cases, transistors 104a and 104b may be collectively referred to as transistor 104.

[0019] Transistors 104a and 104b may correspond to transistors surrounding the gate. The gate surrounding the transistor structure can be patterned by any suitable method. For example, one or more optical lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine optical lithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the gate surrounding the structure. Furthermore, the gate surrounding transistors 104a and 104b may each include multiple semiconductor nanostructures corresponding to the channel regions of transistors 104a and 104b. The nanostructures may include nanosheets, nanowires, or other types of nanostructures.

[0020] In some embodiments, substrate 102 includes a single-crystalline semiconductor layer on at least its surface portion. Substrate 102 may include single-crystalline semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the example processes described herein, substrate 102 includes Si, but other semiconductor materials may be used without departing from the scope of this disclosure.

[0021] Each transistor 104 includes a plurality of channels 106. The channels 106 are stacked along the vertical direction or the Z-direction. In the example of Figure 1, each transistor 104 has three stacked channels 106. However, in practice, without departing from the scope of this disclosure, there may be only two stacked channels 106 or there may be more than three stacked channels 106. The channels 106 correspond to the channel regions of the transistor 104. More specifically, transistor 104a includes three channels 106a and transistor 104b includes three channels 106b.

[0022] Channel 106 may comprise one or more layers of Si, SiGe, or other semiconductor materials. Other semiconductor materials may be used for channel 106 without departing from the scope of this disclosure. In the non-limiting example described herein, channel 106 is silicon. The vertical thickness of channel 106 may be between 3 nm and 10 nm. Semiconductor channels 106 may be spaced 3 nm to 15 nm apart from each other. Other thicknesses and materials may be used for channel 106 without departing from the scope of this disclosure.

[0023] Each transistor 104 includes a gate metal 108. The gate metal 108 surrounds the channel 106. The gate metal 108 corresponds to a gate electrode, or may correspond to one of the metals forming the gate electrode of the transistor 108. The gate metal 108 may include one or more of titanium nitride, tungsten, tantalum, tantalum nitride, aluminum tantalum nitride, ruthenium, cobalt, aluminum, titanium, or other suitable conductive materials. The length of the gate metal 108 in the X direction may be between 5 nm and 150 nm. Other materials and thicknesses may be used for the gate metal 108 without departing from the scope of this disclosure. In some embodiments, the gate metal 108a of transistor 104a includes a different material or a different layer than the gate metal 108b of transistor 104b. Differences in composition or materials can be selected to impart a desired work function to the different transistors 104a and 104b.

[0024] Transistor 104a includes a source / drain region 110a. Each source / drain region 110a is in contact with each of the channels 106a. Each channel 106a extends along the X direction between the source / drain regions 110a. The source / drain regions 110a comprise one or more semiconductor materials. The source / drain regions 110a may be doped with P-type dopants, such as boron or other P-type dopants. As will be explained in more detail below, the source / drain regions 110a of transistor 104a comprise a variety of different semiconductor materials.

[0025] In some embodiments, the source / drain region 110a of transistor 104a includes a source / drain bottom epitaxial structure 118a. The bottom epitaxial structure 118a is formed in a concave recess or trench in substrate 102. The concave recess extends below the lowest channel 106a and below the lowest portion of gate metal 108a. The bottom epitaxial structure 118a includes one or more semiconductor materials. The semiconductor material can initially be epitaxially grown from the substrate. Different materials for the bottom epitaxial structure can help apply beneficial strain to the source / drain region 110a and channel 106a.

[0026] In some embodiments, the bottom epitaxial structure 118a includes an epitaxial semiconductor layer 119a. The epitaxial semiconductor layer 119a is in direct contact with the substrate 102. The first epitaxial semiconductor layer 119a is epitaxially grown from the substrate 102. The semiconductor layer 119a has a bottom surface shaped like a groove in the substrate 102. The semiconductor layer 119a has a concave top surface.

[0027] In some embodiments, the substrate 102 comprises silicon and the epitaxial semiconductor layer 119a comprises silicon germanium, including a germanium concentration between 25% and 35%, but other concentrations may be used without departing from the scope of this disclosure. In some embodiments, the first epitaxial semiconductor layer 119a is in-situ doped with P-type dopant atoms during the epitaxial growth process. The P-type dopant atoms may include boron or other dopant types.

[0028] In some embodiments, the bottom epitaxial structure 118a includes an epitaxial semiconductor layer 121a. The epitaxial semiconductor layer 121a is in direct contact with the epitaxial semiconductor layer 119a and a portion of the substrate 102 above the epitaxial semiconductor layer 118a. A second epitaxial semiconductor layer 121a is epitaxially grown from the semiconductor layer 119a. The semiconductor layer 121a has a bottom surface with a groove shape along the substrate 102. The semiconductor layer 121a has a concave top surface.

[0029] In some embodiments, the epitaxial semiconductor layer 121a comprises a different semiconductor material than that of semiconductor layer 119a but the same semiconductor material as that of substrate 102. In an example where substrate 102 comprises silicon and semiconductor layer 119a comprises silicon-germanium, semiconductor layer 121a comprises silicon. The difference in crystal structure of semiconductor layer 121a can help to apply beneficial strain or stress to source / drain regions 110a and channel 106a. In some embodiments, epitaxial semiconductor layer 121a is in-situ doped with P-type dopant atoms during the epitaxial growth process. P-type dopant atoms may include boron or other dopant species.

[0030] In some embodiments, the bottom epitaxial structure 118a includes an epitaxial semiconductor layer 122a. The epitaxial semiconductor layer 122a is located on the epitaxial semiconductor layer 121a. The epitaxial semiconductor layer 122a may contact a portion of the lowest inner spacer 114 (described further below). In some embodiments, the top surface of the epitaxial semiconductor layer 122a is convex because its central portion is higher than its lateral end portions.

[0031] In some embodiments, semiconductor layer 122a comprises a semiconductor material different from that of semiconductor layer 121a. In an example where epitaxial semiconductor layer 119a comprises silicon germanium and semiconductor layer 121a comprises silicon, semiconductor layer 122a comprises silicon germanium. In some embodiments, semiconductor layer 121a may comprise SiB (boron-doped silicon). The germanium concentration of semiconductor layer 122a is less than 25%, but other concentrations may be used without departing from the scope of this disclosure. Mismatch in semiconductor materials can help apply beneficial strain or stress to channel regions 110a and channel 106a. Semiconductor layer 122a may be doped with p-type dopant atoms, such as boron or other suitable dopant species. More specifically, each semiconductor material may comprise a crystalline structure in which the atoms have a specific spacing. When two different semiconductor materials are bonded to each other at the boundary, the spacing mismatch between atoms may result in compressive or tensile strain. This strain can lead to a beneficial improvement in electron or hole mobility.

[0032] In some embodiments, the source / drain region 110a includes an epitaxial semiconductor layer 113a in direct contact with the channel 106a. Therefore, the semiconductor layer 113a can be epitaxially grown from the channel 106a. In some embodiments, the epitaxial semiconductor layer 113a is grown in the same epitaxial growth process as the semiconductor layer 121a. Therefore, the semiconductor layer 113a may include silicon in situ doped with p-type dopant atoms, but other materials and processes may be used without departing from the scope of this disclosure.

[0033] In some embodiments, the source / drain region 110a includes an epitaxial semiconductor layer 115a in direct contact with the semiconductor layer 113a. Therefore, the epitaxial semiconductor layer 115a can be epitaxially grown from the epitaxial semiconductor layer 113a. In some embodiments, the epitaxial semiconductor layer 115a is grown in the same epitaxial growth process as the semiconductor layer 122a. Therefore, the semiconductor layer 115a can include silicon germanium with a germanium concentration of less than 25% and in-situ doped with P-type dopant atoms, but other materials and processes can be used without departing from the scope of this disclosure. Both the source / drain layers 115a are protruded in a convex manner.

[0034] The source / drain region 110a may include a semiconductor layer 112a. The semiconductor layer 112a corresponds to a bulk source / drain region that fills the remaining area of ​​the source / drain trench and has a total height higher than the highest channel 106a. The semiconductor layer 112a includes a semiconductor material different from the source / drain layers 115a and 122a. In examples where semiconductor layers 115a and 122a include silicon-germanium with a germanium concentration of less than 25%, semiconductor layer 112a may include silicon-germanium with a concentration greater than 25% and be in-situ doped with a P-type dopant. Other processes and materials may be used without departing from the scope of this disclosure.

[0035] Although the source / drain region 110a of transistor 104a in Figure 1 is illustrated as having a specific set of semiconductor layers, in practice, the source / drain region 110a may have other structures and compositions without departing from the scope of this disclosure. For example, some embodiments further described below illustrate processes that result in a structure of source / drain region 110a different from that shown in Figure 1. These other structures of source / drain region 110a may be used for transistor 104a in Figure 1 without departing from the scope of this disclosure. In some embodiments, the source / drain region 110a comprises silicon germanium. Silicon germanium may have a germanium concentration between 25% and 35%, but other materials and concentrations may be utilized without departing from the scope of this disclosure.

[0036] Transistor 104b includes a source / drain region 110b. Each source / drain region 110b is in contact with each of the channels 106b. Each channel 106b extends between the source / drain regions 110b. The source / drain regions 110b comprise one or more semiconductor materials. The source / drain regions 110b may be doped with N-type dopant materials, such as phosphorus, arsenic, or other N-type dopants. As will be described in more detail below, the source / drain regions 110b of transistor 104b may comprise a variety of different semiconductor materials.

[0037] In some embodiments, the source / drain region 110b of transistor 104b includes a bottom epitaxial structure 118b formed in a concave groove in substrate 102. The concave groove extends below the lowest channel 106b and below the lowest portion of gate metal 108b. The bottom epitaxial structure 118b includes one or more semiconductor materials. The semiconductor material can initially be epitaxially grown from the substrate. Different materials for the bottom epitaxial structure can help apply beneficial strain to the source / drain region 110b and channel 106b.

[0038] In some embodiments, the bottom epitaxial structure 118b includes an epitaxial semiconductor layer 119b. The epitaxial semiconductor layer 119b is in direct contact with the substrate 102. In fact, the first epitaxial semiconductor layer 119b is epitaxially grown from the substrate 102. The semiconductor layer 119b has a bottom surface shaped along a groove in the substrate 102. The semiconductor layer 119b has a substantially flat top surface, or a slightly concave top surface.

[0039] In some embodiments, the substrate 102 comprises silicon and the epitaxial semiconductor layer 119b comprises silicon germanium, including a germanium concentration between 25% and 35%, but other concentrations may be used without departing from the scope of this disclosure. In some embodiments, the first epitaxial semiconductor layer 119b has the same composition as the semiconductor layer 119b and may be formed in the same epitaxial growth process.

[0040] In some embodiments, the source / drain region 110b includes a dielectric isolation structure 120b located on the top surface of the source / drain epitaxial structure 118b. The dielectric isolation structure 120b may be positioned below the lowest channel 106b of the transistor 104b.

[0041] In some embodiments, the dielectric isolation structure 120b may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials. The dielectric isolation structure 120b may have a thickness between 1 nm and 15 nm. This thickness is sufficient to ensure substantially no leakage current, but not so thick as to adversely affect the potential thickness of the source / drain regions to be formed thereon. Other thicknesses and materials may be used for the dielectric isolation structure 120b without departing from this disclosure.

[0042] The presence of the dielectric isolation structure 120b ensures that leakage current does not flow from the source / drain region 110b into the semiconductor substrate 102. This can significantly improve the efficiency of the transistor 104b by substantially eliminating leakage current. This reduces power consumption and heat generation. Although not shown, in some embodiments, the transistor 104a may also include a dielectric isolation structure, although such a structure may be less advantageous for p-type transistors than for n-type transistors.

[0043] In some embodiments, the source / drain region 110b includes an epitaxial semiconductor layer 115b in direct contact with the channel 106b. Therefore, the semiconductor layer 115b can be epitaxially grown from the channel 106b. The semiconductor layer 115a may include silicon in situ doped with N-type dopant atoms, but other materials and processes may be used without departing from the scope of this disclosure. In some embodiments, the semiconductor layer 115b may be doped with arsenic or phosphorus. The semiconductor layer 115b protrudes complexly from the channel 106b.

[0044] The source / drain region 110b may include a semiconductor layer 112b. The semiconductor layer 112b corresponds to a bulk source / drain region that fills the remaining area of ​​the source / drain trench and has a total height exceeding that of the highest channel 106b. In some embodiments, the semiconductor layer 112b comprises silicon doped with an N-type dopant. In one example, the semiconductor layer 112b is doped with phosphorus, while the semiconductor layer 115b is doped with arsenic.

[0045] Transistor 104 includes a gate dielectric composed of an interface dielectric layer 107 and a high-k dielectric layer 109. The gate dielectric is located between gate metal 108 and channel 106. The gate dielectric surrounds channel 106. Gate metal 108 surrounds gate dielectric.

[0046] The interface gate dielectric layer 107 is a low-k gate dielectric layer. The interface gate dielectric layer 107 is in contact with the channel 106. The high-k dielectric layer 109 is in contact with the low-k gate dielectric layer 107 and the gate metal 108. The interface gate dielectric layer 107 is located between the channel 106 and the high-k dielectric layer 109.

[0047] The interface gate dielectric layer 107 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface gate dielectric layer 107 may include a dielectric material with a relatively low dielectric constant (low-k) relative to a high-k dielectric material, such as hafnium oxide, or other high-k dielectric materials that can be used as gate dielectrics for transistors.

[0048] The high-k gate dielectric layer 109 comprises one or more dielectric materials, such as HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO₂-Al₂O₃) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The thickness of the high-k dielectric layer 109 is from about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 109 without departing from the scope of this disclosure. The high-k gate dielectric layer 109 may include a first layer and a second layer, the first layer including HfO2 having dipole doping including La and Mg, and the second layer including a high-k ZrO layer having crystallization.

[0049] Transistor 104 includes an inner spacer 114. The inner spacer 114 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k materials, or other dielectric materials without departing from the scope of this disclosure. The inner spacer 114 physically separates the gate metal 108a from the source / drain region 110. This prevents short circuits between the gate metal 108a and the source / drain region 110. The inner spacer 114 may have a thickness between 2 nm and 10 nm. Other materials, dimensions, and structures may be used for the inner spacer 114 without departing from the scope of this disclosure. The inner spacer 114 may have a thickness between 2 nm and 10 nm.

[0050] Transistor 104 includes source / drain contacts 111. Each source / drain contact 111 is located on and electrically connected to a corresponding source / drain region 110. Electrical signals can be applied to the source / drain region 110 via the source / drain contacts 111. The source / drain contacts 111 may include conductive materials such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. The source / drain contacts may have a width between 5 nm and 50 nm.

[0051] Transistor 104 may include silicon 127. Silicon 127 is formed on top of source / drain region 110. Source / drain contact 111 is positioned to contact the silicon. Silicon facilitates good electrical connection between source / drain contact 111 and source / drain region 110. Silicon may include titanium silicon, aluminum silicon, nickel silicon, tungsten silicon, or other suitable silicon. Source / drain contact 111 may have a width between 5 nm and 50 nm.

[0052] Transistor 104 includes a pair of dielectric layers 124 and 125. Dielectric layers 124 and 125 can together serve as a gate spacer layer located between the gate electrode 108 and the source / drain contact 111. Dielectric layer 124 can correspond to a contact etch stop layer and can be positioned to contact the gate metal 108. Dielectric layer 124 can include SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials. Dielectric layer 125 can correspond to a gate spacer layer and can include silicon oxide or another suitable dielectric material.

[0053] Transistor 104 can be operated by applying a voltage to the source / drain region 110a and the gate metal 108. The voltage can be applied to the source / drain region 110 via the source / drain contact 111. The voltage can be applied to the gate metal 108 via the gate contact (not shown in Figure 1). The voltage can be selected to turn on or off transistor 104. When transistor 104 is on, current can flow through each channel 106 between the source / drain regions 110. When transistor 104 is off, current does not flow through the channels 106.

[0054] Figures 2A-2I are cross-sectional views of the integrated circuit 100 at various stages of the process for forming the transistor 104 according to some embodiments. Figures 2A-2D do not separately show the regions of the P-type transistor and the N-type transistor. The process steps shown in Figures 2A-2D can be used to form both the P-type and N-type transistors. Figures 2E-2I each show the individual locations of the P-type and N-type transistors.

[0055] In Figure 2A, a stack 138 of semiconductor layers has been formed on the substrate 102. Although not clearly visible in the view of Figure 2A, the stack 130 of semiconductor layers can be patterned as fins extending along the X direction. A plurality of transistors 104 can be formed in each fin.

[0056] The semiconductor stack includes multiple semiconductor layers 139 interleaved with each other and multiple sacrificial semiconductor layers 141. The semiconductor layers 139 will be patterned to form a stack of channels 106. The semiconductor layers 141 will be patterned to form sacrificial semiconductor nanostructures 142 between the channels 106. The sacrificial semiconductor nanostructures 142 will eventually be removed and gate metal 108 will be formed in their places.

[0057] In one embodiment, semiconductor layer 139 comprises silicon or other materials described with respect to the channels in Figure 1, but other semiconductor materials may be used without departing from the scope of this disclosure. In one embodiment, sacrificial semiconductor layer 141 comprises a semiconductor material different from the semiconductor material of layer 139. This allows sacrificial semiconductor layer 141 to be selectively etched relative to semiconductor layer 139. In the example where semiconductor layer 139 comprises silicon, sacrificial semiconductor layer 141 may comprise silicon germanium.

[0058] The integrated circuit 100 includes a plurality of dummy gate structures 140 on a stack 138. The positions of the dummy gate structures 140 correspond to the positions where a channel stack 106 will be formed below the patterned stack 138, as shown in Figure 2B. The dummy gate structures 140 are placed at the positions where the gate electrodes of the transistor 104 will be placed.

[0059] Each of the dummy gate structures 140 includes a polycrystalline silicon layer 144. The polycrystalline silicon layer 144 can be deposited by epitaxial growth, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, or atomic layer deposition (ALD) process. Other thicknesses and deposition processes can be used to deposit the polycrystalline silicon layer 144 without departing from the scope of this disclosure.

[0060] Spacer layer 124 has been deposited on polycrystalline silicon layer 144 and dielectric layers 146 and 148. The spacer layer may include silicon nitride, SiOCN, or other suitable dielectric layers. Spacer layer 124 may be deposited by CVD, PVD, ALD, or other suitable processes. Spacer layer 124 may have a thickness between 2 nm and 10 nm. Spacer layer 124 may have other materials, deposition processes, and thicknesses without departing from the scope of this disclosure.

[0061] In Figure 2B, trench 150 has been formed in stack 138. A pseudo-gate structure 140 is used as a pattern for forming trench 150. Trench 150 may correspond to a source / drain trench, as source / drain regions 110 will be formed therein. The formation of trench 150 defines a stack of individual channels 106 from semiconductor layer 139. The formation of trench 150 also defines a stack of sacrificial semiconductor nanostructures 142. Trench 150 extends into substrate 102 below the lowest sacrificial semiconductor nanostructure 142. As will be explained in more detail below, source / drain epitaxial structures 118 will be formed at the bottom of trench 150.

[0062] In Figure 2C, an etching step has been performed to etch the sacrificial semiconductor nanostructure 142. The etching process removes the outer portion of the sacrificial semiconductor nanostructure 142 without completely removing it. The etching process can be performed using isotropic etching, which selectively etches the material of the sacrificial semiconductor nanostructure 142 relative to the materials of the semiconductor channel 106 and the substrate 102. The isotropic etching process may include a timed etching process. The duration of the etching process is selected to remove only a portion of the sacrificial semiconductor nanostructure 142 without completely removing it.

[0063] In Figure 2D, dielectric spacers 114 have been deposited between exposed portions of the semiconductor channel 106. Specifically, dielectric spacers 114 are formed at locations where the sacrificial semiconductor nanostructure 142 has been etched. Dielectric spacers 114 can be deposited using an ALD process, a CVD process, or other suitable processes. In one example, dielectric spacer 114 comprises silicon nitride. Other materials and deposition processes may be used for dielectric spacers 114 without departing from the scope of this disclosure.

[0064] Figure 2E shows the positions of transistors 104a (e.g., P-type) and 104b (e.g., N-type). In Figure 2E, an epitaxial semiconductor layer 119 of the source / drain epitaxial structure 118 has been formed on the bottom of the trench 150 at transistors 104a and 104b. The epitaxial semiconductor layer 119 can be formed from substrate 102 through an epitaxial growth process. In an example where substrate 102 comprises silicon, semiconductor layer 119 may comprise silicon germanium at a concentration of less than 25%. In some embodiments, epitaxial semiconductor layer 119 may comprise an intrinsic semiconductor material (undoped).

[0065] In the process stage shown in Figure 2E, the top surface of the semiconductor layer 119 is substantially flush with or slightly higher than the bottom surface of the lowest sacrificial semiconductor nanostructure 142. The top surface of the semiconductor layer 119 is higher than the bottom surface of the lowest inner spacer 114.

[0066] In Figure 2F, according to some embodiments, a mask 152 has been formed in the trench 150 of the transistor 104b. The mask 152 is not present at the transistor 104a. The mask 152 may include a conductive material, such as titanium, aluminum, tungsten, or other conductive materials. The mask 152 may include a dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon oxycarbonate, silicon carbonitride, or other suitable dielectric materials. The mask 152 may be deposited using ALD, PVD, CVD, or other processes. The mask 152 may be patterned using an optical lithography process.

[0067] In some embodiments, an initial etching process has been performed at transistor 104a to etch the top surface of semiconductor layer 119a. After the initial etching, the top surface of semiconductor layer 119a is slightly recessed and lower than the lowest surface of the lowest inner spacer 114. Because mask 152 is present at transistor 104b, semiconductor layer 119b is not recessed.

[0068] In Figure 2G, according to some embodiments, a further etching process is performed at transistor 104a. This further etching process can be achieved via an isotropic etching process, which selectively etches the semiconductor material of semiconductor layer 119 relative to other exposed material. The result is that the top surface of semiconductor layer 119 is recessed by a dimension D1 below the bottom surface of the lowest sacrificial semiconductor nanostructure 142. Dimension D1 can be between 5 nm and 10 nm, but other values ​​can be used without departing from the scope of this disclosure. Furthermore, the etching process results in a highly concave top surface of semiconductor layer 119a.

[0069] Another result of the etching process is that channel 106a is slightly recessed inward. Although the etching process etches the semiconductor material of semiconductor layer 119 at a higher rate than the semiconductor material of channel 106, some etching of semiconductor channel 106 still occurs. It can be seen that channel 106a has a lateral recess size D2 relative to the outer edge of inner spacer 114 and dielectric layer 124. Size D2 can have a value between 1 nm and 3 nm, but other values ​​can be used without departing from the scope of this disclosure. Since there is a mask 152 at transistor 104b, no recess occurs at transistor 104b in Figure 2G.

[0070] In Figure 2H, a series of epitaxial growth processes have been performed at transistor 104a. The first epitaxial growth process forms a semiconductor layer 121a on the semiconductor layer 119a of the source / drain epitaxial structure 118a. The second epitaxial semiconductor layer 121a is in direct contact with the first epitaxial semiconductor layer 119a and a portion of the substrate 102 above the first epitaxial semiconductor layer 119a. In fact, the second epitaxial semiconductor layer 121a is epitaxially grown from the semiconductor layer 119a. The semiconductor layer 121a has a bottom surface with a groove shape along the substrate 102. The semiconductor layer 121a has a concave top surface.

[0071] In some embodiments, the epitaxial semiconductor layer 121a comprises a different semiconductor material than that of the semiconductor layer 119a but the same semiconductor material as the substrate 102. In an example where the substrate 102 comprises silicon and the semiconductor layer 119a comprises silicon-germanium, the semiconductor layer 121a comprises silicon. The difference in the crystal structure of the semiconductor layer 121a can help to apply beneficial strain or stress to the source / drain region 110a and the channel 106a. In some embodiments, the epitaxial semiconductor layer 121a is in-situ doped with P-type dopant atoms during the epitaxial growth process. The P-type dopant atoms may include boron or other dopant species.

[0072] In some embodiments, the epitaxial growth process of the semiconductor layer 121a forming the source / drain bottom epitaxial structure 118a also results in the formation of the source / drain layer 113a. The semiconductor layer 113a is epitaxially grown from the channel 106a. The semiconductor layer 113a may include silicon in situ doped with p-type dopant atoms, but may utilize other materials and processes without departing from the scope of this disclosure. The semiconductor layer 113a is grown from a groove formed in the channel 106a.

[0073] In some embodiments, an epitaxial semiconductor layer 122a of the source / drain bottom epitaxial structure 118a is grown using a different epitaxial growth process. The epitaxial semiconductor layer 122a is located on the epitaxial semiconductor layer 121a. The epitaxial semiconductor layer 122a may contact a portion of the lowest inner spacer 114. In some embodiments, the top surface of the epitaxial semiconductor layer 122a is convex because its central portion is higher than its lateral ends.

[0074] In some embodiments, semiconductor layer 122a comprises a semiconductor material different from that of semiconductor layer 121a. In an example where semiconductor layer 119a comprises silicon germanium and epitaxial semiconductor layer 121a comprises silicon, semiconductor layer 122a comprises silicon germanium. The germanium concentration of semiconductor layer 122a is less than 25%, but other concentrations may be used without departing from the scope of this disclosure. The mismatch of semiconductor materials can help to apply beneficial strain or stress to channel region 110a and channel 106a. Semiconductor layer 122a may be doped with p-type dopant atoms, such as boron or other suitable dopant species.

[0075] In some embodiments, semiconductor layer 115a is grown in the same epitaxial growth process as semiconductor layer 122a. Therefore, semiconductor layer 115a has the same material as semiconductor layer 122a. Epitaxial semiconductor layer 115a is epitaxially grown from epitaxial semiconductor layer 113a.

[0076] Subsequent epitaxial growth processes can be performed to form semiconductor layer 112a. Semiconductor layer 112a corresponds to a bulk source / drain region, which fills the remaining area of ​​the source / drain trench and has a total height higher than the highest channel 106a. Semiconductor layer 112a comprises a semiconductor material different from that of source / drain layers 115a and 122a. In examples where semiconductor layers 115a and 122a comprise silicon-germanium with a germanium concentration of less than 25%, semiconductor layer 112a may comprise silicon-germanium with a concentration greater than 25% and is in-situ doped with P-type dopant. Other processes and materials can be used without departing from the scope of this disclosure.

[0077] In Figure 2H, the formation of the source / drain region 110a is complete. Due to the presence of the mask 152, no epitaxial growth occurs at the transistor 104b.

[0078] In Figure 2I, according to some embodiments, the mask 152 has been removed from the transistor 104b. After the mask 152 is removed, a dielectric isolation structure 120b has been formed on the top surface of the epitaxial semiconductor region semiconductor layer 119b of the source / drain bottom epitaxial structure 118b. The dielectric isolation structure 120b can be deposited by CVD, ALD, PVD or other processes and subsequently patterned.

[0079] In some embodiments, the dielectric isolation structure 120b may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials. The dielectric isolation structure 120b may have a thickness between 1 nm and 15 nm. This thickness is sufficient to ensure substantially no leakage current, but not so thick as to adversely affect the potential thickness of the source / drain regions to be formed thereon. Other thicknesses and materials may be used for the dielectric isolation structure 120b without departing from this disclosure.

[0080] The presence of the dielectric isolation structure 120b ensures that leakage current does not flow from the source / drain region 110b into the semiconductor substrate 102. This can significantly improve the efficiency of the transistor 104b by substantially eliminating leakage current. This reduces power consumption and heat generation.

[0081] In Figure 2I, an epitaxial growth process has been performed to form an epitaxial semiconductor layer 115b of the source / drain region 110b. The semiconductor layer 115b can be epitaxially grown from channel 106b. The semiconductor layer 115a may include silicon in situ doped with N-type dopant atoms, but other materials and processes may be used without departing from the scope of this disclosure. In some embodiments, the semiconductor layer 115b may be doped with arsenic or phosphorus. The semiconductor layer 115b protrudes complexly from channel 106b.

[0082] In Figure 2I, an epitaxial growth process has been performed to form a semiconductor layer 112b of source / drain regions 110b. Semiconductor layer 112b can be epitaxially grown from semiconductor layer 115b. Semiconductor layer 112b corresponds to a bulk source / drain region that fills the remaining area of ​​the source / drain trench and has a total height exceeding that of the highest channel 106b. In some embodiments, semiconductor layer 112b comprises silicon doped with an N-type dopant. In one example, semiconductor layer 112b is doped with phosphorus, while semiconductor layer 115b is doped with arsenic.

[0083] Figures 3A-3E are cross-sectional views of integrated circuit 100 at various process stages according to some embodiments. In Figure 3A, the integrated circuit 100 is substantially the same as the process stage shown in Figure 2E.

[0084] In Figure 3B, an initial etching process has been performed at transistors 104a and 104b to etch the top surface of semiconductor layer 119. After the initial etching, the top surface of semiconductor layer 119 is slightly recessed and lower than the lowest surface of the lowest inner spacer 114. The top surface of semiconductor layer 119 is dimension D3 lower than the bottom surface of the lowest sacrificial semiconductor nanostructure 142. Dimension D3 can have a value between 1 nm and 5 nm, but other dimensions may be used without departing from the scope of this disclosure.

[0085] In Figure 3C, according to some embodiments, a mask 152 has been formed in the trench 150 of the transistor 104b. The mask 152 is not present at the transistor 104a. The mask 152 may include a conductive material, such as titanium, aluminum, tungsten, or other conductive materials. The mask 152 may include a dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon oxycarbonate, silicon carbonitride, or other suitable dielectric materials. The mask 152 may be deposited by ALD, PVD, CVD, or other processes. The mask 152 may be patterned using an optical lithography process.

[0086] In Figure 3C, according to some embodiments, a further etching process is performed at transistor 104a. This further etching process can be achieved via an isotropic etching process, which selectively etches the semiconductor material of semiconductor layer 119a relative to other exposed material. The result is that the top surface of semiconductor layer 119a is recessed by a dimension D1 below the bottom surface of the lowest sacrificial semiconductor nanostructure 142. Dimension D1 can be between 5 nm and 10 nm, but other values ​​can be used without departing from the scope of this disclosure. Furthermore, the etching process results in a highly recessed top surface of semiconductor layer 119a.

[0087] Another result of the etching process is that channel 106a is slightly recessed inward. Although the etching process etches the semiconductor material of semiconductor layer 119 at a higher rate than the semiconductor material of channel 106, some etching of semiconductor channel 106 still occurs. It can be seen that channel 106a has a lateral recess size D2 relative to the outer edge of inner spacer 114 and dielectric layer 124. Size D2 can have a value between 1 nm and 3 nm, but other values ​​can be used without departing from the scope of this disclosure. Since there is a mask 152 at transistor 104b, no recess occurs at transistor 104b in Figure 3C.

[0088] In the 3D diagram, a series of epitaxial growth processes have been performed at transistor 104a. This series of epitaxial growth processes forms semiconductor layers 121a, 122a, 113a, 115a, and 112a, substantially as described with respect to diagram 2H. In the 3D diagram, the formation of the source / drain region 110a is complete. Due to the presence of the mask 152, no epitaxial growth occurs at transistor 104b.

[0089] In Figure 3E, according to some embodiments, the mask 152 has been removed from the transistor 104b. After removing the mask 152, semiconductor layers 112b and 115b are formed, substantially as described with respect to Figure 2I, to form the dielectric isolation structure 120b and the source / drain region 110b. One difference from the structure in Figure 2I is that the top surface of the semiconductor layer 119b is lower than the lowest surface of the lowest inner spacer 114. Additionally, the bottom surface of the isolation structure 120b is lower than the lowest surface of the lowest inner spacer 114, while the top surface of the isolation structure 120b is higher than the lower surface of the lowest inner spacer 114. In Figure 3D, the formation of the source / drain region 110b is complete.

[0090] Figures 4A-4E are cross-sectional views of integrated circuit 100 at various process stages according to some embodiments. In Figure 4A, the integrated circuit 100 is substantially at the same process stage as shown in Figure 3B.

[0091] In Figure 4B, according to some embodiments, an etching process has been performed at the two transistors 104. Further etching can be achieved via an isotropic etching process, which selectively etches the semiconductor material of the semiconductor layer 119 relative to other exposed material. This results in the top surface of the semiconductor layer 119 being recessed below the bottom surface of the lowest sacrificial semiconductor nanostructure 142. Furthermore, the etching process causes a high degree of recess in the top surface of the semiconductor layer 119a. Although not shown in Figure 4B, in some embodiments, the channels 106 of the two transistors 104 can be recessed inwards, as shown by channel 106a in Figure 3C.

[0092] In Figure 4B, according to some embodiments, a dielectric isolation structure 120 has been formed on the semiconductor layer 119 at the two transistors 104. The material, deposition process, and thickness of the dielectric isolation structure 120 can be substantially the same as previously described. One difference is that, due to the highly recessed top surface of the semiconductor layer 119, the dielectric isolation structure 120 is also recessed in Figure 4B.

[0093] In Figure 4C, according to some embodiments, a mask 152 has been formed in the trench 150 of the transistor 104b. The mask 152 is not present at the transistor 104a. Figure 4C shows a groove in the channel 106a. This can be achieved through an additional isotropic etching process. Alternatively, as previously described, the etching process described with respect to Figure 4B can result in the formation of grooves in the channels 1068 of both transistors 104.

[0094] In Figure 4D, a series of epitaxial growth processes have been performed at transistor 104a. This series of epitaxial growth processes forms semiconductor layers 113a, 115a, and 112a, substantially as described in Figure 2H. In Figure 4D, the formation of the source / drain region 110a is complete. Due to the presence of the mask 152, no epitaxial growth occurs at transistor 104b.

[0095] In Figure 4E, according to some embodiments, the mask 152 has been removed from the transistor 104b. After removing the mask 152, the semiconductor layers 112b and 115b of the source / drain regions 110b are formed substantially as described with respect to Figure 2I. One difference from the structure in Figure 2I is that the bottom surface of the semiconductor layer 112b convexes according to the shape of the dielectric isolation structure 120b. The bottom surface of the semiconductor layer 112a also convexes in the same manner.

[0096] Figure 5 is a flowchart of a method 500 for forming an integrated circuit according to some embodiments. Method 500 may utilize the processes, structures, and components described with respect to Figures 1-4E. At step 502, the method 500 includes forming a plurality of stacked first channels of a first transistor over a semiconductor substrate. An example of a semiconductor substrate is semiconductor substrate 102 of Figure 1. An example of a first transistor is first transistor 104a of Figure 1. An example of a first channel is first channel 106a of Figure 1. At step 504, the method 500 includes forming a recessed first groove in the semiconductor substrate. An example of a first groove is the bottom of trench 150 of Figure 2B. At step 506, the method 500 includes forming a first source / drain bottom epitaxial structure of a first source / drain region of the first transistor in the first groove, and the first source / drain bottom epitaxial structure includes a first semiconductor layer that contacts the bottom of the first groove and has a semiconductor material different from that of the semiconductor substrate. An example of a first source / drain region is source / drain region 110a in Figure 1. An example of a source / drain bottom epitaxial structure is source / drain bottom epitaxial structure 118a in Figure 1. An example of a first semiconductor layer is semiconductor layer 119a in Figure 1. At step 508, method 500 includes forming a second semiconductor layer on the first source / drain bottom epitaxial structure, the top surface of which is higher than all first channels. An example of a second semiconductor layer is semiconductor layer 112a in Figure 1. At step 510, method 500 includes forming a first gate metal wrapped around the first channels. An example of a first gate metal is gate metal 108a in Figure 1.

[0097] Embodiments of this disclosure provide an integrated circuit with a nanostructured transistor. Each nanostructured transistor includes multiple stacked channels. The stacked channels extend between source / drain regions. Embodiments of this disclosure provide source / drain regions having a bottom epitaxial structure extending below the lowest channel. The bottom epitaxial structure includes a semiconductor material with a different composition than the other higher portions of the source / drain regions. Furthermore, N-type channel transistors and P-type channel transistors can have different types of bottom epitaxial structures with different numbers of layers and different layer shapes. As a result, stress or strain can be selectively applied to the source / drain regions and channels to improve the DC performance of the transistor. This leads to transistors with improved characteristics, integrated circuits with improved characteristics, and electronic devices with improved characteristics. In addition, the functionality and reliability of the transistor are improved, thereby increasing wafer yield and reducing scrap wafers.

[0098] In some embodiments, a method includes forming a plurality of stacked first channels of a first transistor over a semiconductor substrate and forming a recessed first groove in the semiconductor substrate. This method includes forming a first source / drain bottom epitaxial structure of a first source / drain region of the first transistor in the first groove, and including a first semiconductor layer contacting the bottom of the first groove and having a semiconductor material different from the first semiconductor layer. This method includes forming a second semiconductor layer of the first source / drain region on the first source / drain bottom epitaxial structure, the top surface of which is higher than all the first channels, and forming a first gate metal surrounding the first channels.

[0099] In some embodiments, the integrated circuit includes a semiconductor substrate, a first recess in the semiconductor substrate, and a first transistor. The first transistor includes a plurality of stacked first channels, the bottom of the first recess being lower than all the first channels, and a first source / drain. The first source / drain region includes a first semiconductor layer that contacts the bottom of the first recess, and the first semiconductor layer has a concave top surface lower than all the first channels and a semiconductor material different from the semiconductor substrate. The first source / drain region includes a second semiconductor layer that has a bottom surface lower than all the channels and a top surface higher than all the first channels.

[0100] In some embodiments, the integrated circuit includes a semiconductor substrate, a first recess in the semiconductor substrate, and a first transistor of a first conductivity type. The first transistor includes a plurality of stacked first channels, a first gate metal surrounding the first channels, and a first source / drain region. The first source / drain region includes a first semiconductor layer located on the bottom of the first recess and having a top surface below the bottom of the first gate metal and having a semiconductor material different from that of the semiconductor substrate. The first source / drain region includes a dielectric isolation region with its bottom surface located on the top surface of the first semiconductor layer and below the bottom of the first gate metal.

[0101] The components of several embodiments have been summarized above to facilitate a better understanding of the views expressed in the embodiments of this disclosure by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0007] The embodiments disclosed herein can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments disclosed herein. Figure 1 is a cross-sectional view of an integrated circuit according to some embodiments. Figures 2A-2I are cross-sectional views of an integrated circuit at various process stages according to some embodiments. Figures 3A-3E are cross-sectional views of an integrated circuit at various process stages according to some embodiments. Figures 4A-4E are cross-sectional views of an integrated circuit at various process stages according to some embodiments. Figure 5 is a flowchart of a process for forming an integrated circuit according to some embodiments.

Claims

1. A method for forming a semiconductor device, comprising: A plurality of first channels are formed on a semiconductor substrate by stacking a first transistor; A first concave groove is formed in the semiconductor substrate; a first source / drain bottom epitaxial structure of a first source / drain region of the first transistor is formed in the first groove, and the first source / drain bottom epitaxial structure includes a first semiconductor layer contacting a bottom of the first groove and having a semiconductor material different from that of the semiconductor substrate; a second semiconductor layer of the first source / drain region is formed on the first source / drain bottom epitaxial structure, and a top surface of the second semiconductor layer is higher than all the first channels; a first gate metal is formed wrapping around the first channels; and a third semiconductor layer of the first source / drain bottom epitaxial structure is formed on the first semiconductor layer, and the third semiconductor layer has a material different from that of the first semiconductor layer and has a bottom surface lower than that of the first gate metal.

2. The method of forming a semiconductor device as described in claim 1 further includes forming a fourth semiconductor layer in the first groove on the third semiconductor layer to form the first source / drain bottom epitaxial structure.

3. A method of forming a semiconductor device as claimed in claim 2, wherein the fourth semiconductor layer has a convex bottom surface lower than the bottom of the first gate metal and a convex top surface higher than the bottom of the first gate metal.

4. A method for forming a semiconductor device as claimed in claim 2, wherein the first semiconductor layer is silicon germanium having a first germanium concentration, the second semiconductor layer is silicon germanium having a second germanium concentration less than the first germanium concentration, and the fourth semiconductor layer is silicon germanium having a third germanium concentration greater than the second germanium concentration.

5. The method of forming a semiconductor device as described in claim 2 or 3 further includes forming the fifth semiconductor layer of the first source / drain region by growing a fifth semiconductor layer from the first channels using the same epitaxial growth process as the fourth semiconductor layer, wherein the fifth semiconductor layer does not contact the fourth semiconductor layer.

6. A semiconductor device, comprising: A semiconductor substrate; A first trench is located in the semiconductor substrate; The first transistor includes: a plurality of stacked first channels, a bottom of the first trench being lower than all of the first channels; a first gate metal wrapped around the first channels; and a first source / drain region including: a first semiconductor layer contacting the bottom of the first trench and having a concave top surface lower than all of the first channels and a semiconductor material different from the semiconductor substrate; a second semiconductor layer above the first semiconductor layer and having a bottom surface lower than all of the first channels and a top surface higher than all of the first channels; and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer, wherein the third semiconductor has a material different from the first semiconductor layer and has a top surface lower than a bottom of the first gate metal.

7. A semiconductor device, comprising: A semiconductor substrate; A first trench is located in the semiconductor substrate; The first transistor has a first conductivity type and includes: a plurality of stacked first channels; a first gate metal wrapped around the first channels; and a first source / drain region including: a first semiconductor layer located on the bottom of the first trench and having a top surface located below the bottom of the first gate metal and having a semiconductor material different from the semiconductor substrate; a dielectric isolation region having a bottom surface located on the top surface of the first semiconductor layer and lower than a bottom of the first gate metal; and a third semiconductor layer located above the first semiconductor layer, wherein the third semiconductor has a material different from the first semiconductor layer and has a top surface lower than a bottom of the first gate metal.

8. The semiconductor device as claimed in claim 7, wherein the first source / drain region includes a second semiconductor layer that contacts the top surface of the dielectric isolation region and has a top surface higher than all the first channels.

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