Semiconductor structure and method for fabricating the same

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes channel structures perpendicularly spaced from each other, and a gate structure surrounding the channel structures. The semiconductor structure further includes a first porous layer formed on a first sidewall of the gate structure below the channel structures, and a source / drain structure attached to the channel structures. Furthermore, the source / drain structure is laterally separated from the first porous layer by a first air gap.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures and methods of manufacturing the same. Prior Art

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of supporting a growing number of increasingly complex and sophisticated functions. Consequently, the production of low-cost, high-performance, and low-power integrated circuits (ICs) is a continuing trend in the semiconductor industry. To date, these goals have been largely achieved by reducing the size of semiconductor ICs (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, this reduction in component size also increases the complexity of the semiconductor manufacturing process. Therefore, continued advancements in semiconductor ICs and devices require similar advances in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). However, the manufacturing and integration of multi-gate devices can be challenging. Summary of the Invention

[0004] In some embodiments, a semiconductor structure is provided, comprising a plurality of channel structures vertically separated from each other; a gate structure surrounding the plurality of channel structures; a first porous layer formed on a first sidewall of the gate structure below the plurality of channel structures; and a source / drain structure attached to the plurality of channel structures, wherein the source / drain structure is laterally separated from the first porous layer by a first air gap.

[0005] In some embodiments, a semiconductor structure is provided, comprising a base fin structure protruding from a substrate; a plurality of channel structures formed above the base fin structure; a source / drain structure attached to the plurality of channel structures in a first direction; and a gate structure surrounding the plurality of channel structures and longitudinally oriented along a second direction different from the first direction, wherein a bottom air gap exposes a bottom surface of the source / drain structure and a bottom surface of a bottommost one of the plurality of channel structures.

[0006] In some other embodiments, a method for manufacturing a semiconductor structure is provided, which includes alternately stacking a plurality of first semiconductor material layers and a plurality of second semiconductor material layers in a first direction to form a semiconductor stack above a substrate; patterning the semiconductor stack to form a fin structure longitudinally oriented along a second direction perpendicular to the first direction; forming a source / drain trench in the fin structure; recessing a plurality of first semiconductor material layers to form a notch; forming a sacrificial internal spacer in the notch and a sacrificial bottom layer in the bottom area of ​​the source / drain trench; forming a source / drain structure above the sacrificial bottom layer; removing a plurality of first semiconductor material layers to form a gate trench; forming a porous layer on the sidewalls of the sacrificial internal spacer and the sidewalls of the sacrificial bottom layer; removing the sacrificial internal spacer and the sacrificial bottom layer; and forming a gate structure in the gate trench. Simple diagram description

[0007] The following detailed description, combined with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration. 1A, 1B, and 1C illustrate schematic perspective views of intermediate stages in the fabrication of a semiconductor structure according to some embodiments. No. 2A-1, 2B-1, 2C-1, 2D-1, 2E-1, 2F-1, 2G-1, 2H-1, 2I-1, 2J-1, 2K-1, 2L-1, 2M-1, 2A-2 , 2B-2, 2C-2, 2D-2, 2E-2, 2F-2, 2G-2, 2H-2, 2I-2, 2J-2, 2K-2, 2L-2, 2M-2, 2A-3, 2B-3 1C , 2C-3, 2D-3, 2E-3, 2F-3, 2G-3, 2H-3, 2I-3, 2J-3, 2K-3, 2L-3, 2M-3, 2A-4, 2B-4, 2C-4, 2D-4, 2E-4, 2F-4, 2G-4, 2H-4, 2I-4, 2J-4, 2K-4, 2L-4, and 2M-4 respectively show cross-sectional schematic views of intermediate stages of manufacturing the semiconductor structure along lines YSD-YSD', YMG-YMG', X1-X1', and X2-X2' of FIG. 1C , according to some embodiments. FIG. 2F-5 is a schematic enlarged cross-sectional view of the region R 2F shown in FIG. 2F-3 and FIG. 2F-4 according to various embodiments. FIG. 2F-6 is a schematic enlarged cross-sectional view of the region R 2F_B shown in FIG. 2F-3 and FIG. 2F-4 according to various embodiments. Figures 2G-5, 2G-6, and 2G-7 are schematic enlarged cross-sectional views of region R 2G-3 shown in Figure 2G-3 according to various embodiments. FIG. 2H-5 is a schematic enlarged cross-sectional view of region R 2H-3 shown in FIG. 2H-3 according to various embodiments. FIG. 2H-6 is a schematic enlarged cross-sectional view of region R 2H-4 shown in FIG. 2H-4 according to various embodiments. FIG. 2J-5 is a schematic enlarged cross-sectional view of region R 2J-3 shown in FIG. 2J-3 according to various embodiments. FIG. 2J-6 is a schematic enlarged cross-sectional view of the region R 2J-4 shown in FIG. 2J-4 according to various embodiments. FIG. 2K-5 is a schematic enlarged cross-sectional view of the region R 2K-3 shown in FIG. 2K-3 according to various embodiments. FIG. 2K-6 is a schematic enlarged cross-sectional view of the region R 2K-4 shown in FIG. 2K-4 according to various embodiments. FIG. 2L-5 is a schematic enlarged cross-sectional view of region R 2L-3 shown in FIG. 2L-3 according to various embodiments. FIG. 2L-6 is a schematic enlarged cross-sectional view of region R 2L-4 shown in FIG. 2L-4 according to various embodiments. FIG. 2M-5 is a schematic enlarged cross-sectional view of the region R 2M-3 shown in FIG. 2M-3 according to various embodiments. FIG. 2M-6 is a schematic enlarged cross-sectional view of the region R 2M-4 shown in FIG. 2M-4 according to various embodiments. FIG. 2M-7 is a schematic enlarged cross-sectional view of the region R 2M-3W shown in FIG. 2M-3 according to various embodiments. FIG. 2M-8 is a schematic enlarged cross-sectional view of the region R 2M-4W shown in FIG. 2M-4 according to various embodiments. 3A, 3B, 3C, and 3D are schematic cross-sectional views of semiconductor structures according to some embodiments. FIG3E is a schematic enlarged cross-sectional view of the region R3C shown in FIG3C according to various embodiments. Implementation Method

[0008] It should be understood that the following description provides many different embodiments or examples for implementing various components of the disclosed subject matter. Specific examples of various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, component dimensions are not limited to the ranges or values ​​of one embodiment of the present disclosure but may depend on the processing conditions and / or desired properties of the component. Furthermore, the following description of forming a first component above or on a second component includes embodiments in which the first and second components are in direct contact, as well as embodiments in which additional components may be formed between the first and second components, eliminating the need for direct contact. Furthermore, the disclosure may use repeated reference symbols and / or terms throughout the various examples. This repeated reference symbol or term is for simplicity and clarity and is not intended to limit the relationship between the various embodiments and / or the described structures.

[0009] This document describes some variations of some embodiments. Similar reference symbols are used to designate similar elements in the various diagrams and embodiments shown herein. It should be understood that additional operations may be provided before, during, and / or after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.

[0010] The nanostructured transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon field-effect transistors, and gate-all-around (GAA) transistors) can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography with self-aligned processes to create patterns with smaller pitches, for example, patterns with a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the nanostructures can then be patterned using the remaining spacers.

[0011] Embodiments of semiconductor structures and methods for forming the same are provided herein. The semiconductor structure may include a channel structure, a gate structure surrounding the channel structure, and source / drain structures attached to the channel structure. Furthermore, an air gap is formed within the semiconductor structure to electrically and physically separate the gate structure from the source / drain structures. Due to the low dielectric constant (k) of the air gap, the capacitance of the resulting device can be reduced. Furthermore, the air gap can be formed below the source / drain structure to prevent leakage from the bottom of the device.

[0012] Figures 1A to 1C illustrate schematic perspective views of intermediate stages in the fabrication of a semiconductor structure 100 according to some embodiments. Figures 2A-1 to 2M-1, 2A-2 to 2M-2, 2A-3 to 2M-3, and 2A-4 to 2M-4 illustrate schematic cross-sectional views of intermediate stages in the fabrication of the semiconductor structure 100 along lines YSD-YSD' (i.e., in the Y direction), YMG-YMG' (i.e., in the Y direction), X1-X1' (i.e., in the X direction), and X2-X2' (i.e., in the X direction) in Figure 1C, respectively, according to some embodiments. More specifically, according to some embodiments, Figures 2A-1, 2A-2, 2A-3, and 2A-4 show cross-sectional schematic diagrams of intermediate stages of the semiconductor structure 100 in Figure 1C, and Figures 2B-1 to 2M-1, 2B-2 to 2M-2, 2B-3 to 2M-3, and 2B-4 to 2M-4 show cross-sectional schematic diagrams of intermediate stages of subsequent manufacturing of the semiconductor structure 100.

[0013] The semiconductor structure 100 may include a multi-gate device and may be included in a microprocessor, memory, or other integrated circuit device. For example, the semiconductor structure 100 may be part of an integrated circuit chip that includes various passive and / or active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor FETs (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other applicable components, or combinations thereof.

[0014] According to some embodiments, as shown in FIG. 1A , a substrate 102 is formed. The substrate 102 includes a first region 10 and a second region 20. A semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed above the first region 10 and the second region 20 of the substrate 102. The first region 10 and the second region 20 may be formed adjacent to each other, or other device regions may be formed between the first region 10 and the second region 20. In some embodiments, a P-type transistor is formed in the first region 10, and an N-type transistor is formed in the second region 20. To better understand the semiconductor structure 100, an XYZ coordinate reference is provided in the drawings. The X-axis and the Y-axis are generally oriented along lateral (horizontal) directions parallel to the major surface of the substrate 102. The Y-axis is transverse to (e.g., substantially perpendicular to) the X-axis. The Z-axis is generally oriented along a vertical direction perpendicular to the major surface (or XY plane) of the substrate 102.

[0015] The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0016] In some embodiments, first semiconductor material layers 106 and second semiconductor material layers 108 are alternately stacked above substrate 102 to form a semiconductor stack. In some embodiments, first semiconductor material layers 106 and second semiconductor material layers 108 are made of different semiconductor materials. In some embodiments, first semiconductor material layers 106 are made of silicon germanium, while second semiconductor material layers 108 are made of silicon. In some embodiments, the germanium concentration in first semiconductor material layers 106 is in a range from approximately 35 atomic percent to approximately 50 atomic percent.

[0017] It should be noted that although FIG. 1A shows three first semiconductor material layers 106 and three second semiconductor material layers 108, the semiconductor stack may include fewer or more alternating first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack may include 2 to 5 first semiconductor material layers 106 and 2 to 5 second semiconductor material layers 108.

[0018] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed by low-pressure chemical vapor deposition (LPCVD), epitaxial growth, other suitable methods, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0019] According to some embodiments, as shown in FIG. 1B , after a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed as a semiconductor stack above a substrate 102, the semiconductor stack is patterned to form a fin structure 104-1 in the first region 10 and a fin structure 104-2 in the second region 20. Fin structures 104-1 and 104-2 may extend longitudinally in the X-direction. In some embodiments, the patterning process may include forming a mask structure 110 above the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure including a pad oxide layer and a nitride layer formed above the pad oxide layer. The pad oxide layer may be made of silicon oxide, which may be formed by thermal oxidation or chemical vapor deposition, while the nitride layer may be formed of silicon nitride, which may be formed by chemical vapor deposition, such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the fin structures 104-1 and 104-2 include a base fin structure 104B and a semiconductor stack formed above the base fin structure 104B and including a first semiconductor material layer 106 and a second semiconductor material layer 108.

[0020] According to some embodiments, as shown in Figures 1C, 2A-1, 2A-2, 2A-3, and 2A-4, after forming fin structures 104-1 and 104-2, an isolation structure 116 is formed around fin structures 104-1 and 104-2. According to some embodiments, isolation structure 116 is configured to electrically isolate active regions of the semiconductor structure (e.g., fin structures 104-1 and 104-2) and is also referred to as a shallow trench isolation (STI) feature.

[0021] More specifically, an insulating layer may be formed around and covering the fin structures 104-1 and 104-2. The insulating layer may then be recessed to form the isolation structure 116 and the fin structures 104-1 and 104-2 protruding from the top surface of the isolation structure 116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof. Furthermore, before forming the insulating layer, a liner layer (not shown) may be formed and the liner layer and the insulating layer may also be recessed together to form the isolation structure 116. In some embodiments, the liner layer includes multiple dielectric material layers.

[0022] Then, according to some embodiments, as shown in Figures 2B-1, 2B-2, 2B-3, and 2B-4, a dummy gate structure 130 is formed across the fin structures 104-1 and 104-2. The dummy gate structure 130 can be used to define the channel region of the final semiconductor structure 100.

[0023] In some embodiments, the dummy gate structure 130 includes a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, the dummy gate dielectric layer 132 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the dummy gate dielectric layer 132 is formed using thermal oxidation, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or combinations thereof.

[0024] In some embodiments, the dummy gate electrode layer 134 is made of a conductive material, including polycrystalline silicon (poly-Si), polycrystalline silicon-germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed by chemical vapor deposition, physical vapor deposition, or a combination thereof.

[0025] In some embodiments, a hard mask layer 137 is formed over the dummy gate structure 134. In some embodiments, the hard mask layer 137 includes multiple layers, such as an oxide layer 135 and a nitride layer 136. In some embodiments, the oxide layer 135 is silicon oxide, and the nitride layer 136 is silicon nitride.

[0026] The formation of the dummy gate structure 130 may include conformally forming a dielectric material as a dummy gate dielectric layer 132. Subsequently, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 134, and a hard mask layer 137 may be formed over the conductive material. The dielectric material and the conductive material may then be patterned through the hard mask layer 137 to form the dummy gate structure 130.

[0027] According to some embodiments, as shown in Figures 2C-1, 2C-2, 2C-3, and 2C-4, after forming the dummy gate structure 130, a spacer layer 138 is formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structures 104-1 and 104-2. In some embodiments, the spacer layer 138 is made of one or more dielectric materials. The dielectric material may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof.

[0028] According to some embodiments, as shown in Figures 2D-1, 2D-2, 2D-3, and 2D-4, after forming the spacer layer 138, an etching process is performed to form gate spacers 140 and fin spacers 142, as well as source / drain recesses 144 in the fin structures 104-1 and 104-2. The gate spacers 140 can be configured to separate the source / drain structure (to be formed later) from the dummy gate structure 130, and the fin spacers 142 can be configured to limit the growth of the source / drain structure formed therein.

[0029] More specifically, according to some embodiments, the spacer layer 138 is etched to form gate spacers 140 on both sidewalls of the dummy gate structure 130, and to form fin spacers 142 covering the sidewalls of the fin structures 104-1 and 104-2. Furthermore, according to some embodiments, portions of the fin structures 104-1 and 104-2 not covered by the dummy gate structure 130 and the gate spacers 140 are etched to form source / drain recesses 144 during the etching process. The etching process may be an anisotropic etching process, such as a dry plasma etch, and the dummy gate structure 130 and the gate spacers 140 may serve as an etching mask during the etching process. In some embodiments, the isolation structure 116 is also slightly etched during the etching process.

[0030] According to some embodiments, after forming the source / drain recesses 144, the first semiconductor material layer 106 exposed by the source / drain recesses 144 is laterally recessed to form a notch 146. The resulting structure is shown in Figures 2E-1, 2E-2, 2E-3, and 2E-4. In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structures 104-1 and 104-2 from the source / drain recesses 144. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming a notch 146 between adjacent second semiconductor material layers 108.

[0031] In some embodiments, the second semiconductor material layer 108 is also slightly etched during the etching process, resulting in a thinned portion 108T of the second semiconductor material layer 108 exposed in the notch 146 . In some embodiments, the etching process is an isotropic etch, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. In some embodiments, the topmost thinned portion 108T of the second semiconductor material layer 108 is thicker (i.e., in the Z direction) than the other thinned portions 108T of the second semiconductor material layer 108 . In some embodiments, the portion of the base fin structure 104B exposed through the source / drain recess 144 has a stepped shape ST, as shown in FIGS. 2E-3 and 2E-4 .

[0032] Next, according to some embodiments, sacrificial inner spacers 148 are formed in the gaps 146 between the second semiconductor material layer 108, and a bottom sacrificial layer 149 is formed in the bottommost gap 146 and extends to the bottom of the source / drain recess 144. The resulting structure is shown in Figures 2F-1, 2F-2, 2F-3, and 2F-4. The sacrificial inner spacers 148 are configured to form a space for separating the source / drain structure and the gate structure formed in subsequent manufacturing processes. Furthermore, the bottom sacrificial layer 149 is configured to form a space for separating the source / drain structure from the base fin structure 104B.

[0033] As described above, according to some embodiments, because the second semiconductor material layer 108 is also slightly etched when forming the opening 146, the sacrificial inner spacer 148 formed in the opening 146 is thicker than the first semiconductor material layer 106. The shapes of the sacrificial inner spacer 148 and the bottom sacrificial layer 149 can be adjusted according to their application.

[0034] FIG2F-5 shows an enlarged cross-sectional view of the region R2F shown in FIG2F-3 and FIG2F-4, according to various embodiments. That is, the sacrificial inner spacers 148 in the first region 10 and the second region 20 may have substantially the same shape at this stage. More specifically, according to some embodiments, FIG2F-5(a) shows a sacrificial inner spacer 148a having a convex surface extending between the second semiconductor material layers 108. According to some embodiments, FIG2F-5(b) shows a sacrificial inner spacer 148b having a substantially vertical surface extending between the second semiconductor material layers 108. According to some embodiments, FIG2F-5(c) shows a sacrificial inner spacer 148c having a concave surface extending between the second semiconductor material layers 108.

[0035] In some embodiments, the width W148 of the sacrificial inner spacers 148 (e.g., sacrificial inner spacers 148a, 148b, and 148c) ranges from approximately 3 nm to approximately 8 nm. As described above, the sacrificial inner spacers 148 are configured to form a space for separating the subsequently formed source / drain structures and gate structures. Therefore, the sacrificial inner spacers 148 should be wide enough to separate the devices, but not too wide, otherwise the space available for forming the gate structure may be reduced.

[0036] 2F-5 , the second semiconductor material layer 108 has a thinned portion 108T at its edge, and the thinned portion 108T vertically overlaps the sacrificial inner spacer 148. Furthermore, according to some embodiments, the thinned portion 108T has rounded corners.

[0037] FIG2F-6 illustrates an enlarged cross-sectional view of region R2F_B shown in FIG2F-3 and FIG2F-4, according to various embodiments. More specifically, FIG2F-6(a) illustrates a bottom sacrificial layer 149a having a convex top surface, according to some embodiments. FIG2F-6(b) illustrates a bottom sacrificial layer 149b having a substantially flat surface, according to some embodiments. FIG2F-6(c) illustrates a bottom sacrificial layer 149c having a concave top surface, according to some embodiments.

[0038] In some embodiments, the topmost point of the top surface of the bottom sacrificial layer 149 in the source / drain region (i.e., exposed through the source / drain recess 144) is lower than the bottom surface of the topmost second semiconductor material layer 108, so that the connection between the second semiconductor material layer 108 and the subsequently formed source / drain structure will not be damaged by the formation of the bottom sacrificial layer.

[0039] In some embodiments, the topmost point of the top surface of the bottom sacrificial layer 149 in the source / drain region (i.e., exposed through the source / drain recess 144) is higher than the top surface of the pedestal fin structure 104B. This allows the bottom of the subsequently formed source / drain structure to be isolated from the pedestal fin structure 104B, thereby preventing leakage from the bottom of the device. In some embodiments, the height difference H 149 between the topmost point of the top surface of the bottom sacrificial layer 149 in the source / drain region and the top surface of the pedestal fin structure 104B (i.e., the bottom surface of the bottommost first semiconductor material layer 106) in the Z direction is in the range of approximately 3 nm to approximately 5 nm.

[0040] The sacrificial inner spacers 148 (e.g., sacrificial inner spacers 148a, 148b, 148c) and the bottom sacrificial layer 149 (e.g., bottom sacrificial layers 149a, 149b, 149c) can be made of the same material. In some embodiments, the sacrificial inner spacers 148 and the bottom sacrificial layer 149 are both made of a semiconductor material, such as silicon germanium. In some embodiments, the germanium content of the semiconductor material used to form the sacrificial inner spacers 148 and the bottom sacrificial layer 149 is in a range from approximately 15 atomic percent to approximately 25 atomic percent. In some embodiments, the first semiconductor material layer 106, the sacrificial inner spacers 148, and the bottom sacrificial layer 149 are all made of silicon germanium, but the germanium concentration in the first semiconductor material layer 106 is greater than the germanium concentration in the sacrificial inner spacers 148 and the bottom sacrificial layer 149. This allows for etch selectivity among the first semiconductor material layer 106, the sacrificial inner spacers 148, and the bottom sacrificial layer 149 during a subsequent etching process.

[0041] In some embodiments, the sacrificial inner spacers 148 and the bottom sacrificial layer 149 are formed using an epitaxial growth process, such as molecular beam epitaxy, metal organic chemical vapor deposition, vapor phase epitaxy, other applicable epitaxial growth processes, or combinations thereof. More specifically, silicon germanium material may be grown from the sidewalls of the first semiconductor material layer 106 exposed through the source / drain recesses 144 and the top surface of the base fin structure 104B.

[0042] Furthermore, although the second semiconductor material layer 108 and the pedestal fin structure 104B may both be made of silicon, the second semiconductor material layer 108 and the pedestal fin structure 104B may have different surface structures exposed through the source / drain recess 144. In some embodiments, the surface S1 of the pedestal fin structure 104B exposed by the source / drain recess 144 (i.e., the bottom of the source / drain recess 144) has a Si(100) surface, while the sidewall S2 of the second semiconductor material layer 108 has a Si(110) surface. Therefore, the silicon germanium material may be primarily grown on the sidewalls of the first semiconductor material layer 106 and in the bottom of the source / drain recess 144 above the surface S1 of the pedestal fin structure 104B, but not on the sidewall S2 of the second semiconductor material layer 108.

[0043] According to some embodiments, as shown in Figures 2G-1, 2G-2, 2G-3, and 2G-4, after forming the sacrificial inner spacers 148 and the bottom sacrificial layer 149, a recessing process is performed on the first region 10. More specifically, the thinned portion 108T of the second semiconductor material layer 108 in the first region 10 is recessed laterally (i.e., recessed in the X-direction). This allows dopants in the subsequently formed source / drain structures to diffuse into the second semiconductor material layer 108 in the first region 10, thereby improving the performance of the resulting device (e.g., a p-type field-effect transistor). In some embodiments, the sacrificial inner spacers 148 and the gate spacers 140 protrude from the sidewalls of the second semiconductor material layer 108. During the recessing process, the structures in the second region 20 may be protected by a mask structure, which may be removed after the recessing process.

[0044] Figures 2G-5, 2G-6, and 2G-7 illustrate enlarged cross-sectional views of region R 2G-3 shown in Figure 2G-3, according to various embodiments. More specifically, Figure 2G-5(a) illustrates a second semiconductor material layer 108 having a concave sidewall surface that vertically overlaps a sacrificial inner spacer 148a, according to some embodiments. Figure 2G-5(b) illustrates a second semiconductor material layer 108 having a concave sidewall surface that vertically overlaps a sacrificial inner spacer 148b, according to some embodiments. Figure 2G-5(c) illustrates a second semiconductor material layer 108 having a concave sidewall surface that vertically overlaps a sacrificial inner spacer 148c, according to some embodiments. Figure 2G-6(a) illustrates a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps a sacrificial inner spacer 148a, according to some embodiments. Figure 2G-6(b) illustrates a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps a sacrificial inner spacer 148b, according to some embodiments. FIG. 2G-6(c) shows a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps the sacrificial inner spacer 148c, according to some embodiments. FIG. 2G-7(a) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps the sacrificial inner spacer 148a, according to some embodiments. FIG. 2G-7(b) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps the sacrificial inner spacer 148b, according to some embodiments. FIG. 2G-7(c) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps the sacrificial inner spacer 148c, according to some embodiments.

[0045] In some embodiments, the second semiconductor material layer 108 is laterally recessed by a distance D1 ranging from approximately 2 nm to approximately 6 nm. The recessed distance D1 should be large enough to allow for dopant diffusion, but not too large, otherwise it may increase the risk of leakage. In some embodiments, the second semiconductor material layer 108 protrudes from the inner sidewall of the gate spacer 140 by a distance D2 ranging from approximately 3 nm to approximately 5 nm. In some embodiments, distance D1 is greater than distance D2, as shown in FIG. 2G-5. In some embodiments, distance D1 is approximately equal to distance D2, as shown in FIG. 2G-6. In some embodiments, distance D1 is less than distance D2, as shown in FIG. 2G-7.

[0046] According to some embodiments, as shown in Figures 2H-1, 2H-2, 2H-3, and 2H-4, after a recess process, source / drain structures 150-1 and 150-2 are formed in the source / drain recesses 144 in the first region 10 and the second region 20, respectively. Depending on the context, the source / drain structures described herein may be referred to individually or collectively as a source or a drain.

[0047] In some embodiments, source / drain structures 150-1 and 150-2 are formed using a separate epitaxial growth process, such as molecular beam epitaxy, metal organic chemical vapor deposition, vapor phase epitaxy, other applicable epitaxial growth processes, or combinations thereof. In some embodiments, source / drain structures 150-1 and 150-2 are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, source / drain structures 150-1 and 150-2 are in-situ doped during the epitaxial growth process. In some embodiments, source / drain structures 150-1 and 150-2 are doped in one or more implantation processes after the epitaxial growth process.

[0048] In some embodiments, the source / drain structures 150-1 and 150-2 are made of materials having different conductivity types. FIG. 2H-5 illustrates an enlarged cross-sectional view of region R 2H-3 shown in FIG. 2H-3 , according to various embodiments. More specifically, FIG. 2H-5(a) illustrates a source / drain structure 150-1a formed adjacent to sacrificial inner spacer 148a , according to some embodiments. FIG. 2H-5(b) illustrates a source / drain structure 150-1b formed adjacent to sacrificial inner spacer 148b , according to some embodiments. FIG. 2H-5(c) illustrates a source / drain structure 150-1c formed adjacent to sacrificial inner spacer 148c , according to some embodiments. It should be noted that while FIG. 2H-5 illustrates a bottom sacrificial layer 149c , other types of bottom sacrificial layers (e.g., bottom sacrificial layers 149a or 149b shown in FIG. 2F-6 ) may replace bottom sacrificial layer 149c.

[0049] In some embodiments, the source / drain structure 150-1 includes a first source / drain layer 151, a second source / drain layer 152 formed over the first source / drain layer 151, and a third source / drain layer 153 formed over the second source / drain layer 152. In some embodiments, the source / drain structure 150-1 is a source / drain structure for a p-type metal oxide semiconductor transistor. The germanium concentration in the third source / drain layer 153 is greater than the germanium concentration in the second source / drain layer 152, and the germanium concentration in the second source / drain layer 152 is greater than the germanium concentration in the first source / drain layer 151. In some embodiments, the first source / drain layer 151 is made of SiB. In some embodiments, the second source / drain layer 152 is made of SiGeB, and the germanium concentration in the second source / drain layer 152 is greater than 0% but less than 25%. In some embodiments, the third source / drain layer 153 is made of SiGeB, and the germanium concentration in the third source / drain layer 153 is greater than 25%.

[0050] In some embodiments, the first source / drain layer 151 contacts the sidewalls of the second semiconductor material layer 108, the sacrificial inner spacers 148 (e.g., sacrificial inner spacers 148a, 148b, 148c), and the bottom sacrificial layer 149 (e.g., bottom sacrificial layers 149a, 149b, 149c). Furthermore, according to some embodiments, because the second semiconductor material layer 108 is laterally recessed before forming the first source / drain layer 151, the first source / drain layer 151 extends laterally above the sacrificial inner spacers 148. The thickness of the first source / drain layer 151 varies in different regions due to the different growth rates of the epitaxial material formed on different materials. Therefore, according to some embodiments, the first source / drain layer 151 has a wavy sidewall surface, with a thicker portion adjacent to the second semiconductor material layer 108 and a thinner portion adjacent to the sacrificial inner spacers 148.

[0051] In some embodiments, the first source / drain layer 151 includes extended portions vertically (i.e., along the Z direction) sandwiched between the gate spacer 140 and the topmost second semiconductor material layer 108, between two vertically adjacent second semiconductor material layers 108, and between the bottommost second semiconductor material layer 108 and the bottom sacrificial layer 149. Although the second semiconductor material layer 108 shown in FIG. 2H-5 has concave sidewall surfaces, the second semiconductor material layer 108 may have the structures shown in FIG. 2G-6 and FIG. 2G-7. In some embodiments, the first source / drain layer 151 and the second semiconductor material layer 108 have a curved interface. In some embodiments, the first source / drain layer 151 and the second semiconductor material layer 108 have a substantially vertical interface. In some embodiments, the first source / drain layer 151 has a curved (convex) bottom surface. In some other embodiments, the first source / drain layer 151 has a substantially flat or concave bottom surface. In some embodiments, the second source / drain layer 152 is formed above the first source / drain layer 151.

[0052] As shown in FIG. 2H-5 , the first source / drain layer 151 has a width W150-1W measured from the middle portion of the topmost second semiconductor material layer 108 in the X direction (in the Z direction), and a width W150-1N measured from the middle portion of the topmost first semiconductor material layer 106 (or the topmost sacrificial inner spacer 148) in the X direction (in the Z direction). In some embodiments, the width W150-1W is greater than the width W150-1N.

[0053] FIG. 2H-6 illustrates an enlarged cross-sectional view of region R 2H-4 shown in FIG. 2H-4 , according to various embodiments. More specifically, FIG. 2H-6(a) illustrates a source / drain structure 150-2a formed adjacent to sacrificial inner spacer 148a , according to some embodiments. FIG. 2H-6(b) illustrates a source / drain structure 150-2b formed adjacent to sacrificial inner spacer 148b , according to some embodiments. FIG. 2H-6(c) illustrates a source / drain structure 150-2c formed adjacent to sacrificial inner spacer 148c , according to some embodiments. It should be noted that while FIG. 2H-6 illustrates a bottom sacrificial layer 149c , other types of bottom sacrificial layers (e.g., bottom sacrificial layers 149a or 149b shown in FIG. 2F-6 ) may replace bottom sacrificial layer 149c.

[0054] In some embodiments, the source / drain structure 150-2 includes a first source / drain layer 154 and a second source / drain layer 155. In some embodiments, the phosphorus concentration in the second source / drain layer 155 is greater than the phosphorus concentration in the first source / drain layer 154. In some embodiments, the first source / drain layer 154 is made of SiAs or SiP. In some embodiments, the second source / drain layer 155 is made of SiP.

[0055] In some embodiments, the first source / drain layer 154 contacts the sidewalls of the second semiconductor material layer 108, the sacrificial inner spacers 148 (e.g., sacrificial inner spacers 148a, 148b, 148c), and the bottom sacrificial layer 149 (e.g., bottom sacrificial layers 149a, 149b, 149c). Although the second semiconductor material layer 108 shown in FIG. 2H-6 has substantially vertical sidewalls, the second semiconductor material layer 108 may have the structures shown in FIG. 2G-5 and FIG. 2G-7. In some embodiments, the first source / drain layer 154 and the second semiconductor material layer 108 have a curved interface. In some other embodiments, the first source / drain layer 154 and the second semiconductor material layer 108 have a substantially vertical interface. In some embodiments, the first source / drain layer 154 has a curved (convex) bottom surface. In some other embodiments, the first source / drain layer 154 has a substantially flat or concave bottom surface. In some embodiments, the second source / drain layer 155 is formed above the first source / drain layer 154.

[0056] As shown in FIG. 2H-6 , the source / drain structure 150-2 has a width W150-2W measured from the middle portion of the topmost second semiconductor material layer 108 in the X direction (in the Z direction), and a width W150-2N measured from the middle portion of the topmost first semiconductor material layer 106 (or the topmost sacrificial inner spacer 148) in the X direction (in the Z direction). In some embodiments, the width W150-1W of the source / drain structure 150-1 is greater than the width W150-2W of the source / drain structure 150-2. In some embodiments, the width W150-1N of the source / drain structure 150-1 is substantially equal to the width W150-2N of the source / drain structure 150-2.

[0057] According to some embodiments, as shown in Figures 2I-1, 2I-2, 2I-3, and 2I-4, after the source / drain structures 150-1 and 150-2 are formed, a contact etch stop layer (CESL) 160 is conformally formed to cover the source / drain structures 150-1 and 150-2, and an interlayer dielectric (ILD) layer 162 is formed above the CESL 160.

[0058] In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other applicable dielectric materials, or combinations thereof. The dielectric material of the contact etch stop layer 160 can be conformally deposited over the semiconductor structure by chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof.

[0059] The interlayer dielectric layer 162 may include multiple layers made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. The interlayer dielectric layer 162 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process (such as a chemical mechanical polishing or etch-back process) is performed until the dummy gate electrode layer 134 is exposed.

[0060] Next, according to some embodiments, as shown in Figures 2J-1, 2J-2, 2J-3, and 2J-4, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench 166. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form the second semiconductor material layer 108 of the fin structures 104-1 and 104-2, respectively, serving as channel structures 108'-1 and 108'-2 (e.g., nanostructures). According to some embodiments, as shown in Figures 2J-2 and 2J-3, the channel structures 108'-1 and 108'-2 are vertically suspended above the substrate 102 and spaced apart from each other in the Z direction. Furthermore, according to some embodiments, the channel structures 108'-1 and 108'-2 extend laterally in the X direction between the source / drain structures 150-1 and 150-2, respectively.

[0061] The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 134 is made of polysilicon, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) may be used to selectively remove the dummy gate electrode layer 134. Subsequently, the dummy gate dielectric layer 132 is removed using plasma dry etching, dry chemical etching, and / or wet etching. The first semiconductor material layer 106 may be removed by performing a selective wet etching process, such as an ammonia hydroxide-hydrogen peroxide-water mixture (APM) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), tetramethylammonium hydroxide, ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0062] As described above, although the first semiconductor material layer 106, the sacrificial inner spacers 148, and the bottom sacrificial layer 149 are all made of silicon germanium, the germanium concentration of the first semiconductor material layer 106 may be higher than the germanium concentration of the sacrificial inner spacers 148 and the bottom sacrificial layer 149. Therefore, during the etching process used to remove the first semiconductor material layer 106, the first semiconductor material layer 106, the sacrificial inner spacers 148, and the bottom sacrificial layer 149 may have good etch selectivity. In some embodiments, during the etching process used to remove the first semiconductor material layer 106, the sidewalls of the sacrificial inner spacers 148 and the bottom sacrificial layer 149 may be slightly removed.

[0063] FIG. 2J-5 illustrates an enlarged cross-sectional schematic view of region R 2J-3 shown in FIG. 2J-3 , according to various embodiments. More specifically, FIG. 2J-5(a-1) illustrates a sacrificial inner spacer 148a-1 having concave inner sidewalls in the first region 10, according to some embodiments. FIG. 2J-5(a-2) illustrates a sacrificial inner spacer 148a-2 having substantially vertical inner sidewalls in the first region 10, according to some embodiments. FIG. 2J-5(b-1) illustrates a sacrificial inner spacer 148b-1 having concave inner sidewalls in the first region 10, according to some embodiments. FIG. 2J-5(b-2) illustrates a sacrificial inner spacer 148b-2 having substantially vertical inner sidewalls in the first region 10, according to some embodiments. FIG. 2J-5(c-1) illustrates a sacrificial inner spacer 148c-1 having concave inner sidewalls in the first region 10, according to some embodiments. FIG. 2J-5(c-2) shows a sacrificial inner spacer 148c-2 having substantially vertical inner sidewalls in the first region 10, according to some embodiments.

[0064] FIG2J-6 illustrates an enlarged cross-sectional view of region R2J-4 shown in FIG2J-4, according to various embodiments. More specifically, FIG2J-6(a-1) illustrates a sacrificial inner spacer 148a-1 having concave inner sidewalls in the second region 20, according to some embodiments. FIG2J-6(a-2) illustrates a sacrificial inner spacer 148a-2 having substantially vertical inner sidewalls in the second region 20, according to some embodiments. FIG2J-6(b-1) illustrates a sacrificial inner spacer 148b-1 having concave inner sidewalls in the second region 20, according to some embodiments. FIG2J-6(b-2) illustrates a sacrificial inner spacer 148b-2 having substantially vertical inner sidewalls in the second region 20, according to some embodiments. FIG2J-6(c-1) illustrates a sacrificial inner spacer 148c-1 having concave inner sidewalls in the second region 20, according to some embodiments. According to some embodiments, FIG. 2J-6(c-2) shows a sacrificial inner spacer 148c-2 having substantially vertical inner sidewalls in the second region 20.

[0065] According to some embodiments, as shown in Figures 2K-1, 2K-2, 2K-3, and 2K-4, after forming the gate trench 166, a porous layer 170 is formed on the sidewalls of the sacrificial inner spacers 148 in the first region 10 and the second region 20. The porous layer 170 is configured to ensure a space between the gate structure and the source / drain structures 150-1 and 150-2.

[0066] In some embodiments, the porous layer 170 is made of SiO2. In some embodiments, the porous layer 170 has a thickness measured in the X-direction in the range of approximately 0.5 nm to approximately 2 nm. The porous layer 170 should be sufficiently thick, otherwise it may be removed during a subsequent etching process. On the other hand, the porous layer 170 should not be too thick, otherwise the sacrificial inner spacers 148 and the bottom sacrificial layer 149 (described in detail later) may not be completely removed. In some embodiments, the porous layer 170 is formed by a wet process. In some embodiments, the wet process includes spraying a liquid reactant onto the sidewall surfaces of the sacrificial inner spacers 148 and the bottom sacrificial layer 149 exposed in the gate trench 166 to form the porous layer 170, and removing the liquid reactant after forming the porous layer 170. In some embodiments, the porous layer 170 has a curved profile in the cross-sectional schematic diagram.

[0067] FIG. 2K-5 illustrates an enlarged cross-sectional schematic view of region R 2K-3 shown in FIG. 2K-3 , according to various embodiments. More specifically, FIG. 2K-5(a-1) illustrates a porous layer 170a-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148a-1 in the first region 10 , according to some embodiments. FIG. 2K-5(a-2) illustrates a porous layer 170a-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148a-2 in the first region 10 , according to some embodiments. FIG. 2K-5(b-1) illustrates a porous layer 170b-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148b-1 in the first region 10 , according to some embodiments. FIG. 2K-5(b-2) illustrates a porous layer 170b-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148b-2 in the first region 10 , according to some embodiments. According to some embodiments, FIG. 2K-5(c-1) shows a porous layer 170c-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148a-1 in the first region 10. According to some embodiments, FIG. 2K-5(c-2) shows a porous layer 170c-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148c-2 in the first region 10.

[0068] FIG. 2K-6 illustrates an enlarged cross-sectional schematic view of region R 2K-4 shown in FIG. 2K-4 , according to various embodiments. More specifically, FIG. 2K-6(a-1) illustrates a porous layer 170a-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148a-1 in the second region 20 , according to some embodiments. FIG. 2K-6(a-2) illustrates a porous layer 170a-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148a-2 in the second region 20 , according to some embodiments. FIG. 2K-6(b-1) illustrates a porous layer 170b-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148b-1 in the second region 20 , according to some embodiments. FIG. 2K-6(b-2) illustrates a porous layer 170b-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148b-2 in the second region 20 , according to some embodiments. According to some embodiments, FIG. 2K-6(c-1) shows a porous layer 170c-1 formed on the concave inner sidewalls of the sacrificial inner spacer 148c-1 in the second region 20. According to some embodiments, FIG. 2K-6(c-2) shows a porous layer 170c-2 formed on the substantially vertical inner sidewalls of the sacrificial inner spacer 148c-2 in the second region 20.

[0069] According to some embodiments, as shown in Figures 2L-1, 2L-2, 2L-3, and 2L-4, after forming the porous layer 170, an etching process is performed from the gate trench 166 to remove the sacrificial inner spacers 148 and the bottom sacrificial layer 149. More specifically, according to some embodiments, during the etching process, the etchant penetrates the pores in the porous layer 170 and reaches the sacrificial inner spacers 148 and the bottom sacrificial layer 149. Then, according to some embodiments, the sacrificial inner spacers 148 and the bottom sacrificial layer 149 are etched and removed by the etchant, thereby forming air gaps 172-1 and 172-2 and bottom air gaps 174-1 and 174-2 in the first region 10 and the second region 20, respectively.

[0070] In some embodiments, the etching process is a dry etching process. In some embodiments, the etchant used in the etching process includes fluorine radicals, hydrogen radicals, or the like. As described above, the source / drain structure 150-1 includes a first source / drain layer 151. The first source / drain layer 151 may be made of SiB. The first source / drain layer 151 may serve as a protective layer for the source / drain structure 150-1, preventing damage to the second source / drain layer 152 (which may be made of SiGeB) during the etching process.

[0071] In some embodiments, air gaps 172-1 and 172-2 are formed by removing sacrificial inner spacers 148, and bottom air gaps 174-1 and 174-2 are formed by removing bottom sacrificial layer 149. Thus, according to some embodiments, air gap 172-1 is laterally (i.e., in the X-direction) sandwiched between the porous layer 170 and the first source / drain layer 151 in the first region 10, while air gap 172-2 is laterally (i.e., in the X-direction) sandwiched between the porous layer 170 and the first source / drain layer 154 in the second region 20. Furthermore, according to some embodiments, bottom air gaps 174-1 and 174-2 are vertically (i.e., in the Z-direction) sandwiched between the pedestal fin structure 104B and the source / drain structures 150-1 and 150-2. Furthermore, according to some embodiments, bottom air gaps 174-1 and 174-2 are laterally (i.e., in the X-direction) sandwiched between the two porous layers 170.

[0072] FIG. 2L-5 illustrates an enlarged cross-sectional view of region R 2L-3 shown in FIG. 2L-3 , according to various embodiments. More specifically, FIG. 2L-5(a-1) illustrates air gap 172-1a1 exposing porous layer 170a-1 and having a shape substantially similar to sacrificial internal spacer 148a-1 in first region 10, according to some embodiments. FIG. 2L-5(a-2) illustrates air gap 172-1a2 exposing porous layer 170a-2 and having a shape substantially similar to sacrificial internal spacer 148a-2 in first region 10, according to some embodiments. FIG. 2L-5(b-1) illustrates air gap 172-1b1 exposing porous layer 170b-1 and having a shape substantially similar to sacrificial internal spacer 148b-1 in first region 10, according to some embodiments. According to some embodiments, FIG. 2L-5(b-2) shows that the air gap 172-1b2 exposes the porous layer 170b-2 and has a shape substantially similar to the sacrificial inner spacer 148b-2 in the first region 10. According to some embodiments, FIG. 2L-5(c-1) shows that the air gap 172-1c1 exposes the porous layer 170c-1 and has a shape substantially similar to the sacrificial inner spacer 148c-1 in the first region 10. According to some embodiments, FIG. 2L-5(c-2) shows that the air gap 172-1c2 exposes the porous layer 170c-2 and has a shape substantially similar to the sacrificial inner spacer 148c-2 in the first region 10.

[0073] FIG2L-6 illustrates an enlarged cross-sectional view of region R 2L-4 shown in FIG2L-4 , according to various embodiments. More specifically, FIG2L-6(a-1) illustrates air gap 172-2a1 exposing porous layer 170a-1 and having a shape substantially similar to sacrificial internal spacer 148a-1 in second region 20, according to some embodiments. FIG2L-6(a-2) illustrates air gap 172-2a2 exposing porous layer 170a-2 and having a shape substantially similar to sacrificial internal spacer 148a-2 in second region 20, according to some embodiments. FIG2L-6(b-1) illustrates air gap 172-2b1 exposing porous layer 170b-1 and having a shape substantially similar to sacrificial internal spacer 148b-1 in second region 20, according to some embodiments. According to some embodiments, FIG. 2L-6(b-2) shows that the air gap 172-2b2 exposes the porous layer 170b-2 and has a shape substantially similar to the sacrificial inner spacer 148b-2 in the second region 20. According to some embodiments, FIG. 2L-6(c-1) shows that the air gap 172-2c1 exposes the porous layer 170c-1 and has a shape substantially similar to the sacrificial inner spacer 148c-1 in the second region 20. According to some embodiments, FIG. 2L-6(c-2) shows that the air gap 172-2c2 exposes the porous layer 170c-2 and has a shape substantially similar to the sacrificial inner spacer 148c-2 in the second region 20.

[0074] According to some embodiments, as shown in Figures 2M-1, 2M-2, 2M-3, and 2M-4, after forming the air gaps 172-1 and 172-2 and the bottom air gaps 174-1 and 174-2, a gate structure 180 is formed in the gate trench 166. In some embodiments, the gate structure 180 surrounds the channel structures 108'-1 and 108'2 in the first region 10 and the second region 20 and extends longitudinally in the Y direction. In some embodiments, the gate structure 180 includes an interface layer 182, a gate dielectric layer 184, and a gate stack layer 186.

[0075] Interfacial layer 182 can be used to improve the interface between channel structures 108'-1 and 108'2 and subsequently formed dielectric layers. Furthermore, interfacial layer 182 can help suppress mobility degradation of charge carriers in channel structures 108'-1 and 108'2, which serve as the channel region of the transistor. In some embodiments, interfacial layer 182 is an oxide layer formed by a thermal process. In some embodiments, interfacial layer 182 has a thickness in a range from approximately 0.5 nm to approximately 1.5 nm.

[0076] According to some embodiments, after forming the interfacial layer 182, a gate dielectric layer 184 is conformally formed to cover the interfacial layer 182 and the bottom surface and sidewalls of the gate trench 166. In some embodiments, the gate dielectric layer 184 is made of a dielectric material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, La2O3-Al2O3 or LaO, other applicable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 184 is formed using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof. In some embodiments, the gate dielectric layer 184 has a thickness in a range from approximately 1 nm to approximately 2 nm.

[0077] According to some embodiments, after forming the gate dielectric layer 184, a gate stack layer 186 is formed over the gate dielectric layer 184. In some embodiments, the gate stack layer 186 includes multiple layers. In some embodiments, the gate stack layer 186 includes a work function metal layer. In some embodiments, the work function metal layers in the first region 10 and the second region 20 are made of different materials. In some embodiments, the work function metal layer is made of titanium nitride, tantalum nitride, tungsten nitride, tantalum, or the like.

[0078] In some embodiments, the gate stack layer 186 includes a gate-fill layer formed above the work function layer. In some embodiments, the gate-fill layer is made of a conductive material, such as tungsten, titanium, tantalum, cobalt, copper, or the like. In some embodiments, the gate-fill layer is formed using chemical vapor deposition, atomic layer deposition, electroplating, other applicable methods, or a combination thereof. In some embodiments, after depositing the gate dielectric layer 184 and the gate stack layer 186, a polishing process, such as a chemical mechanical polishing process, is performed.

[0079] FIG2M-5 illustrates an enlarged cross-sectional view of region R2M-3 shown in FIG2M-3 according to various embodiments. More specifically, according to some embodiments, FIG2M-5(a-1) illustrates air gap 172-1a1 and gate structure 180 located on both sides of porous layer 170a-1 in first region 10. According to some embodiments, FIG2M-5(a-2) illustrates air gap 172-1a2 and gate structure 180 located on both sides of porous layer 170a-2 in first region 10. According to some embodiments, FIG2M-5(b-1) illustrates air gap 172-1b1 and gate structure 180 located on both sides of porous layer 170b-1 in first region 10. According to some embodiments, FIG2M-5(b-2) illustrates air gap 172-1b2 and gate structure 180 located on both sides of porous layer 170b-2 in first region 10. According to some embodiments, FIG. 2M-5(c-1) shows that the air gap 172-1c1 and the gate structure 180 are located on both sides of the porous layer 170c-1 in the first region 10. According to some embodiments, FIG. 2M-5(c-2) shows that the air gap 172-1c2 and the gate structure 180 are located on both sides of the porous layer 170c-2 in the first region 10.

[0080] FIG. 2M-6 illustrates an enlarged cross-sectional view of region R 2M-4 shown in FIG. 2M-4 , according to various embodiments. More specifically, FIG. 2M-6(a-1) illustrates air gap 172-2a1 and gate structure 180 located on both sides of porous layer 170a-1 in second region 20, according to some embodiments. FIG. 2M-6(a-2) illustrates air gap 172-2a2 and gate structure 180 located on both sides of porous layer 170a-2 in second region 20, according to some embodiments. FIG. 2M-6(b-1) illustrates air gap 172-2b1 and gate structure 180 located on both sides of porous layer 170b-1 in second region 20, according to some embodiments. FIG. 2M-6(b-2) illustrates air gap 172-2b2 and gate structure 180 located on both sides of porous layer 170b-2 in second region 20, according to some embodiments. According to some embodiments, FIG. 2M-6(c-1) shows that the air gap 172-2c1 and the gate structure 180 are located on both sides of the porous layer 170c-1 in the second region 20. According to some embodiments, FIG. 2M-6(c-2) shows that the air gap 172-2c2 and the gate structure 180 are located on both sides of the porous layer 170c-2 in the second region 20.

[0081] According to some embodiments, as shown in Figures 2M-1, 2M-3, and 2M-4, after forming the gate structure 180, a silicide layer 190 and source / drain contacts 192 are formed over the source / drain structures 150-1 and 150-2. More specifically, contact trenches may be formed through the contact etch stop layer 160 and the interlayer dielectric layer 162 to expose the source / drain structures 150-1 and 150-2. Subsequently, according to some embodiments, a silicide layer 190 is formed over the exposed portions of the source / drain structures 150-1 and 150-2, and source / drain contacts 192 are formed in the contact trenches over the silicide layer 190.

[0082] The silicide layer 190 may be formed by forming a metal layer over the top surfaces of the source / drain structures 150-1 and 150-2 and annealing the metal layer so that the metal layer reacts with the source / drain structures 150-1 and 150-2. After forming the silicide layer 190, the unreacted metal layer may be removed.

[0083] In some embodiments, the source / drain contacts 192 are made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or combinations thereof.

[0084] The source / drain contacts 192 may further include a liner and / or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The liner may be formed using plasma-assisted chemical vapor deposition (PECVD), although other applicable processes (such as physical vapor deposition or thermal processes) may also be used as alternatives. A barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, or the like may also be used.

[0085] FIG. 2M-7 illustrates an enlarged cross-sectional view of region R 2M-3W shown in FIG. 2M-3 according to various embodiments. More specifically, FIG. 2M-7(a) illustrates a source / drain structure 150-1a in the first region 10 having four air gaps 172-1a partially exposing its sidewalls and a bottom air gap 174-1 exposing its bottom, according to some embodiments. FIG. 2M-7(b) illustrates a source / drain structure 150-1b in the first region 10 having four air gaps 172-1b partially exposing its sidewalls and a bottom air gap 174-1 exposing its bottom, according to some embodiments. FIG. 2M-7(c) illustrates a source / drain structure 150-1c in the first region 10 having four air gaps 172-1c partially exposing its sidewalls and a bottom air gap 174-1 exposing its bottom, according to some embodiments.

[0086] FIG2M-8 illustrates an enlarged cross-sectional view of region R 2M-4W shown in FIG2M-4 according to various embodiments. More specifically, FIG2M-8(a) illustrates a source / drain structure 150-2a in the second region 20 having four air gaps 172-2a partially exposing its sidewalls and a bottom air gap 174-2 exposing its bottom, according to some embodiments. FIG2M-8(b) illustrates a source / drain structure 150-2b in the second region 20 having four air gaps 172-2b partially exposing its sidewalls and a bottom air gap 174-2 exposing its bottom, according to some embodiments. FIG2M-8(c) illustrates a source / drain structure 150-2c in the second region 20 having four air gaps 172-2c partially exposing its sidewalls and a bottom air gap 174-2 exposing its bottom, according to some embodiments.

[0087] In some embodiments, the width of the air gaps 172-1 and 172-2 is in a range of approximately 3 nm to approximately 8 nm. The air gaps 172-1 and 172-2 should be wide enough to separate the gate structure 180 and the source / drain structures 150-1 and 150-2. On the other hand, the air gaps 172-1 and 172-2 should not be too wide, as this may reduce the space available for forming the gate structure 180. In some embodiments, the width of the air gaps 172-1 and 172-2 in the X direction is smaller than the width of the gate spacer 140.

[0088] In some embodiments, the width of the portion of the first source / drain layer 151 laterally sandwiched between the air gap 172-1 and the second source / drain layer 152 ranges from approximately 2 nm to approximately 3 nm. As described above, the first source / drain layer 151 is formed to prevent damage to the source / drain structure 150-1 during the etching process used to remove the sacrificial inner spacers 148 and the bottom sacrificial layer 149. Therefore, the portion of the first source / drain layer 151 between the air gap 172-1 and the second source / drain layer 152 should not be too thin, as this may increase the risk of source / drain damage. In some embodiments, the first source / drain layer 151 has a wavy profile that contacts the second source / drain layer 152.

[0089] In some embodiments, the width of the portion of the first source / drain layer 154 laterally sandwiched between the air gap 172-2 and the second source / drain layer 155 is in a range of about 3 nm to about 4 nm. In some embodiments, the first source / drain layer 154 has a wavy profile that contacts the second source / drain layer 155. In some embodiments, the width of the portion of the first source / drain layer 154 laterally sandwiched between the air gap 172-2 and the second source / drain layer 155 is greater than the width of the portion of the first source / drain layer 151 laterally sandwiched between the air gap 172-1 and the second source / drain layer 152.

[0090] In some embodiments, bottom air gap 174-1 has a height H1 (in the Z direction) below the middle portion (in the X direction) of source / drain structure 150-1, and bottom air gap 174-2 has a height H2 (in the Z direction) below the middle portion (in the X direction) of source / drain structure 150-2. Height H1 can be defined as the distance between the lowest point of source / drain structure 150-1 and the lowest point of bottom air gap 174-1, as measured in the Z direction. Height H2 can be defined as the distance between the lowest point of source / drain structure 150-2 and the lowest point of bottom air gap 174-2, as measured in the Z direction. In some embodiments, height H1 is substantially equal to height H2.

[0091] Because the bottoms of the source / drain structures 150-1 and 150-2 are lower than the topmost surfaces of the bottom air gaps 174-1 and 174-2, necking regions exist. These regions have the narrowest distance between the source / drain structures 150-1 / 150-2 and the pedestal fin structure 104B within the bottom air gaps 174-1 and 174-2. In some embodiments, the dimension DN of the necking regions within the bottom air gaps 174-1 and 174-2 is greater than approximately 2 nm. The necking regions should be large enough to completely remove the bottom sacrificial layer 149 during the etching process shown in Figures 2L-1 through 2L-4.

[0092] According to some embodiments, as shown in Figures 2M-1 through 2M-8, the semiconductor structure 100 includes vertically spaced channel structures 108'-1 / 108'2, with the gate structure 100 surrounding the channel structures. Furthermore, according to some embodiments, a porous layer 170 is formed on the sidewalls of the gate structure 100 below the channel structures 108'-1 / 108'2. Furthermore, source / drain structures 150-1 and 150-2 are attached to the channel structures 108'-1 / 108'2 and laterally separated from the porous layer by an air gap 172. In some embodiments, the porous layer 170 and the gate structure 180 have a curved interface. In some embodiments, the bottommost porous layer 170 contacts the bottommost channel structure 108'-1 / 108'2 and the top surface of the pedestal fin structure 104B.

[0093] In some embodiments, bottom air gap 174-1 / 174-2 exposes the bottom surface of source / drain structure 150-1 / 150-2 and the bottom surface of the bottommost channel structure 108'-1 / 108'2. In some embodiments, bottom air gap 174 is wider than air gap 172. In some embodiments, bottom air gap 174-1 / 174-2 overlaps the gate stack in the Z direction. In some embodiments, bottom air gap 174-1 / 174-2 is larger than the source / drain structure 150-1 / 150-2 in the X direction.

[0094] In some embodiments, the source / drain structure 150-1 has a laterally extending portion that contacts the channel structure 108'-1, and the air gap 172 exposes the bottom surface of the extended portion of the source / drain structure 150-1. In some embodiments, the source / drain structure 150-1 has a first portion that contacts the sidewall surface of the bottommost channel structure 108'-1 and a second portion above the first portion, and the first portion is wider than the second portion in the X direction. In some embodiments, the gate spacer 140 is formed above the topmost channel structure 108'-1, and the extended portion of the source / drain structure 150-1 contacts the bottom surface of the gate spacer.

[0095] Figures 3A, 3B, 3C, and 3D illustrate schematic cross-sectional views of a semiconductor structure 100' according to some embodiments. According to some embodiments, the semiconductor structure 100' may be similar to the aforementioned semiconductor structure 100, except that the second semiconductor material layer 108 in the first region 10 is not recessed prior to forming the source / drain structure 150-1. The processes and materials used to form the semiconductor structure 100' may be similar to or identical to those used to form the aforementioned semiconductor structure 100 and are therefore not described in detail herein.

[0096] More specifically, according to some embodiments, the processes shown in Figures 2A-1 to 2F-1, 2A-2 to 2F-2, 2A-3 to 2F-3, and 2A-4 to 2F-4 are performed to form sacrificial inner spacers 148 and a bottom sacrificial layer 149. Subsequently, the processes shown in Figures 2H-1 to 2M-1, 2H-2 to 2M-2, 2H-3 to 2M-3, and 2H-4 to 2M-4 are performed to form the semiconductor structure 100', as shown in Figures 3A, 3B, 3C, and 3D. According to some embodiments, since the recess process shown in Figures 2G-1 to 2G-4 is not performed, the sidewalls of the channel structures 108'-1 and 108'2 are substantially aligned with the sidewalls of the gate spacers 140.

[0097] In some embodiments, a source / drain structure 150'-1 is formed in the semiconductor structure 100'. Furthermore, the source / drain structure 150'-1 includes a first source / drain layer 151', a second source / drain layer 152, and a third source / drain layer 153. The first source / drain layer 151' is similar to the first source / drain layer 151, except that the first source / drain layer 151' does not extend below the gate spacer 140.

[0098] FIG3E illustrates an enlarged cross-sectional view of region R3C shown in FIG3C according to various embodiments. More specifically, according to some embodiments, FIG3E(a) illustrates that the source / drain structure 150'-1a in the first region 10 has four air gaps 172-1a that partially expose the sidewalls of the first source / drain layer 151', and a bottom air gap 174-1 that exposes the bottom of the first source / drain layer 151'. According to some embodiments, FIG3E(b) illustrates that the source / drain structure 150'-1b in the first region 10 has four air gaps 172-1b that partially expose the sidewalls of the first source / drain layer 151', and a bottom air gap 174-1 that exposes the bottom of the first source / drain layer 151'. According to some embodiments, FIG. 3E(c) shows that the source / drain structure 150-1c in the first region 10 has four air gaps 172-1c partially exposing the sidewalls of the first source / drain layer 151' and a bottom air gap 174-1 exposing the bottom of the first source / drain layer 151'.

[0099] Generally, an internal spacer is formed to separate the gate structure from the source / drain structure and provide low electrical capacitance. According to an embodiment of the present invention, an air gap 172 and a bottom air gap 174 having a low dielectric constant are formed as the internal spacer. The formation of air gap 172 and bottom air gap 174 can help improve the capacitance of the final device and prevent leakage from the bottom of the device.

[0100] Furthermore, according to some embodiments, before forming the air gap 172 and the bottom air gap 174, the sacrificial inner spacer 148 and the bottom sacrificial layer 149 are formed, and the source / drain structures 150-1 and 150-2 are formed between the sacrificial inner spacer 148 and the bottom sacrificial layer 149 and above the sacrificial inner spacer 148 and the bottom sacrificial layer 149. Because the sacrificial inner spacer 148 and the bottom sacrificial layer 149 are formed of a semiconductor material (e.g., silicon germanium), the source / drain structures 150-1 and 150-2 formed thereon can have smoother profiles.

[0101] It should be understood that the elements shown in semiconductor structures 100 and 100' may be combined and / or interchanged. Furthermore, it should be noted that identical elements in Figures 1A through 3E are labeled with identical reference symbols and may comprise identical or similar materials and be formed using identical or similar processes. Therefore, for the sake of brevity, these redundant details have been omitted. Furthermore, Figures 1A through 3E describe a method. It should be understood that the structure disclosed in Figures 1A through 3E is not limited to this method and may exist independently of this method. Similarly, the method illustrated in Figures 1A through 3E is not limited to the disclosed structure and may exist independently of the structure. Furthermore, according to some embodiments, the aforementioned channel structure (e.g., nanostructure) may comprise a nanowire, nanosheet, or other applicable nanostructure.

[0102] Furthermore, although the disclosed methods are illustrated and described above as a series of actions or events, it should be understood that in some other embodiments, the order of these actions or events illustrated may be changed. For example, some actions may occur in a different order and / or concurrently with other actions or events than those illustrated and / or described above. Furthermore, not all illustrated actions are required to implement one or more aspects or embodiments described above. Furthermore, one or more of the aforementioned actions may be performed as one or more separate actions and / or stages.

[0103] Furthermore, the terms "approximately," "substantially," "roughly," and "about" as used above take into account small variations and may vary in different technologies and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or circumstance, these terms may refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in a very close manner.

[0104] Embodiments for forming a semiconductor structure may include forming a gate dielectric layer in a first region and a second region, and modifying the gate dielectric layer with a first metal element in the first region but not in the second region. A capping layer may then be formed over the modified gate dielectric layer to densify the gate dielectric layer, thereby improving its quality. A work function metal layer may then be formed in the first region and the second region. Doping the gate dielectric layer in the first region with the first metal element can alter the threshold voltages of the first and second transistors.

[0105] A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes channel structures vertically spaced apart from each other; and a gate structure surrounding the channel structures. The semiconductor structure further includes a first porous layer formed on a first sidewall of the gate structure below the channel structure; and a source / drain structure attached to the channel structure. Furthermore, the source / drain structure is laterally spaced apart from the first porous layer by a first air gap.

[0106] In some other embodiments, the first air gap exposes the bottom surface of the source / drain structure.

[0107] In some other embodiments, the semiconductor structure further includes a second porous layer covering the second sidewall of the gate structure and contacting the bottom surface of the topmost one of the channel structures, wherein the source / drain structure is laterally separated from the second porous layer by a second air gap.

[0108] In some other embodiments, the first air gap is wider than the second air gap.

[0109] In some other embodiments, the source / drain structure has a lateral extension portion contacting the channel structure, and the first air gap exposes a bottom surface of the lateral extension portion of the source / drain structure.

[0110] In some other embodiments, the first porous layer comprises SiO 2 .

[0111] In some other embodiments, the first porous layer has a curved profile in the cross-sectional schematic view.

[0112] A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a pedestal fin structure protruding from a substrate; a channel structure formed above the pedestal fin structure. The semiconductor structure further includes a source / drain structure attached to the channel structure in a first direction; and a gate structure surrounding the channel structure and longitudinally oriented in a second direction different from the first direction. The semiconductor structure further includes a porous layer covering the sidewalls of the gate structure. Furthermore, a bottommost portion of the porous layer connects to a bottommost portion of the channel structure and a top surface of the pedestal fin structure. The source / drain structure is separated from the porous layer in the first direction by an air gap. Furthermore, a bottom air gap exposes the bottom surface of the source / drain structure and the bottom surface of the bottommost portion of the channel structure.

[0113] In some other embodiments, the semiconductor structure further includes a gate spacer formed above a topmost one of the channel structures, wherein an extension portion of the source / drain structure contacts a bottom surface of the gate spacer.

[0114] In some other embodiments, the bottom air gap overlaps the gate spacer in a third direction different from the first direction and the second direction.

[0115] In some other embodiments, in the first direction, the size of the bottom air gap is larger than the size of the source / drain structure.

[0116] In some other embodiments, the source / drain structure has a first portion contacting a sidewall surface of a bottommost one of the channel structures and a second portion above the first portion, and in the first direction, the first portion is wider than the second portion.

[0117] A semiconductor structure and a method for forming the same are provided. The method includes alternately stacking a first semiconductor material layer and a second semiconductor material layer in a first direction to form a semiconductor stack above a substrate; patterning the semiconductor stack to form a fin structure oriented longitudinally along a second direction perpendicular to the first direction. The method further includes forming a source / drain trench in the fin structure; and recessing the first semiconductor material layer to form a notch. The method further includes forming a sacrificial inner spacer in the notch and forming a sacrificial bottom layer in the bottom region of the source / drain trench. A source / drain structure is formed above the sacrificial bottom layer. The method further includes removing the first semiconductor material layer to form a gate trench; and forming a porous layer on the sidewalls of the sacrificial inner spacer and the sidewalls of the sacrificial bottom layer. The method further includes removing the sacrificial inner spacer and the sacrificial bottom layer; and forming a gate structure in the gate trench.

[0118] In some other embodiments, the method further includes applying an etchant from the gate trench to remove the sacrificial inner spacer and the sacrificial bottom layer through the porous layer.

[0119] In some other embodiments, the method further includes recessing the second semiconductor material layer after forming the sacrificial inner spacer in the notch.

[0120] In some other embodiments, the source / drain structure partially covers the sacrificial inner spacer in the first direction.

[0121] In some other embodiments, the bottom air gap is formed by removing a sacrificial bottom layer, and the bottom air gap exposes the bottom surface of the source / drain structure.

[0122] In some other embodiments, the air gap is formed by removing a sacrificial internal spacer, and the source / drain structure is separated from the porous layer by the air gap.

[0123] In some other embodiments, the porous layer and the gate structure have a curved interface.

[0124] The foregoing description summarizes the features of many embodiments, enabling those skilled in the art to better understand the various aspects of the present invention. Those skilled in the art should understand and readily design or modify other processes and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, and modifications may be made to the present invention without departing from the spirit and scope of the present invention.

[0125] 10: District 1 20: Second District 100,100':Semiconductor structure 102: Base 104-1, 104-2: Fin structure 104B: Base fin structure 106: first semiconductor material layer 108: second semiconductor material layer 108'-1, 108'-2: Channel structure 108T: Thinning part 110:Mask structure 116: Isolation Structure 130: dummy gate structure 132: dummy gate dielectric layer 134: dummy gate electrode layer 135: Oxide layer 136: Nitride layer 137: Hard Mask Layer 138: Spacer layer 140: Gate spacer 142: Fin spacer 144: Source / Drain Notch 146: Gap 148,148a,148b,148c,148a-1,148a-2,148b-1,148b-2,148c-1,148c-2: Sacrificial internal spacer 149,149a,149b,149c: Bottom sacrificial layer 150-1, 150-2, 150-1a, 150-1b, 150-1c, 150-2a, 150-2b, 150-2c, 150'-1, 150'-1a, 150'-1b, 150'-1c: Source / Drain Structure 151, 154, 151': first source / drain layer 152, 155: second source / drain layer 153: third source / drain layer 160: contact etch stop layer 162: interlayer dielectric layer 166: Gate trench 170,170a-1,170a-2,170b-1,170b-2,170c-1,170c-2: porous layer 172-1,172-2,172-1a,172-1b,172-1c,172-2a,172-2b,172-2c,172-1a1,172-1a2,172-1b1,172-1b2,172-1c1,172-1c2,172-2a1,172-2a2,172-2b1,172-2b2,172-2c1,172-2c2: Air gap 174-1, 174-2: Bottom air gap 180: Gate structure 182: Interface layer 184: Gate dielectric layer 186: Gate stack layer 190: Silicide layer 192: Source / drain contact D1,D2: distance DN: size R 2F,R 2F_B,R 2G-3,R 2H-3,R 2H-4,R 2J-3,R 2J-4,R 2K-3,R 2K-4,R 2L-3,R 2L-4,R 2M-3,R 2M-3W,R 2M-4,R 2M-4W,R 3C: Area S 1: Surface S 2: Side wall ST: Step shape W 148, W 150-1N, W 150-1W, W 150-2N, W 150-2W: Width H1,H2:Height H 149: Height difference

Claims

1. A semiconductor structure comprising: a plurality of channel structures perpendicularly spaced from each other; a gate structure surrounding the plurality of channel structures; a first porous layer formed on a first sidewall of the gate structure below the plurality of channel structures; and a source / drain structure attached to the plurality of channel structures, wherein the source / drain structure is laterally spaced from the first porous layer through a first air gap, wherein the first air gap exposes the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the plurality of channel structures.

2. The semiconductor structure of claim 1 further includes: a second porous layer covering a second sidewall of the gate structure and contacting the bottom surface of the topmost one of the plurality of channel structures, wherein the source / drain structure is laterally separated from the second porous layer through a second air gap.

3. The semiconductor structure of claim 2, wherein the first air gap is wider than the second air gap.

4. The semiconductor structure of claim 1, wherein the source / drain structure has a lateral extension that contacts the plurality of channel structures, and the first air gap exposes the bottom surface of the lateral extension of the source / drain structure.

5. The semiconductor structure of claim 1, wherein the first porous layer has a curved profile in a cross-sectional schematic diagram.

6. A semiconductor structure comprising: a base fin structure protruding from a substrate; a plurality of channel structures formed above the base fin structure; a source / drain structure attached to the plurality of channel structures in a first direction; and a gate structure surrounding the plurality of channel structures and longitudinally oriented in a second direction different from the first direction, wherein a bottom air gap exposes the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the plurality of channel structures.

7. The semiconductor structure of claim 6 further includes: a plurality of porous layers covering the sidewalls of the gate structure, wherein the bottommost of the plurality of porous layers is connected to the bottommost of the plurality of channel structures and the top surface of the base fin structure, and the source / drain structure is separated from the plurality of porous layers in the first direction by a plurality of air gaps.

8. The semiconductor structure of claim 6 or 7, wherein the source / drain structure has a first portion of a sidewall surface that contacts the bottommost one of the plurality of channel structures and a second portion above the first portion, and the first portion is wider than the second portion in the first direction.

9. A method of manufacturing a semiconductor structure, comprising: alternately stacking a plurality of first semiconductor material layers and a plurality of second semiconductor material layers in a first direction to form a semiconductor stack over a substrate; patterning the semiconductor stack to form a fin structure longitudinally oriented in a second direction perpendicular to the first direction; forming a source / drain trench in the fin structure; recessing the plurality of first semiconductor material layers to form a notch; forming a sacrificial internal spacer wall in the notch and a sacrificial bottom layer in a bottom region of the source / drain trench; forming a source / drain structure over the sacrificial bottom layer; removing the plurality of first semiconductor material layers to form a gate trench; forming a porous layer on the sidewalls of the sacrificial internal spacer wall and the sidewalls of the sacrificial bottom layer; removing the sacrificial internal spacer wall and the sacrificial bottom layer to form a bottom air gap exposing the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the plurality of second semiconductor material layers; and forming a gate structure in the gate trench.

10. The method of manufacturing a semiconductor structure as claimed in claim 9 further includes: applying an etchant from the gate trench to remove the sacrificial internal spacer wall and the sacrificial bottom layer through the porous layer.

11. The method of manufacturing a semiconductor structure as claimed in claim 9 or 10 further includes: after forming the sacrificial internal spacer wall in the notch, recessing the plurality of second semiconductor material layers.

12. A method of manufacturing a semiconductor structure as claimed in claim 11, wherein the source / drain structure partially covers the sacrificial internal spacer wall in the first direction.

13. A method of manufacturing a semiconductor structure as claimed in claim 9 or 10, wherein an air gap is formed by removing the sacrificial internal spacer wall, and the source / drain structure is separated from the porous layer by the air gap.

Images