Flash memory and manufacturing method thereof

Abstract

A flash memory and a method for manufacturing the same are provided. The method includes: forming pad oxides in an array region and a peripheral region on a substrate; and performing a batch control process for etching the pad oxides in the array region. The batch control process for etching the pad oxides in the array region includes: measuring the thickness of the pad oxides in the array region; and etching the pad oxides in the array region until the thickness reaches a desired value. The method further includes: forming a tunneling oxide layer on the substrate, wherein the tunneling oxide layer includes the pad oxides, and the edge thickness of the tunneling oxide layer is greater than the central thickness.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing flash memory with batch control to adjust thickness and the resulting flash memory. [Previous Technology]

[0002] In traditional flash memory manufacturing processes, self-aligned technology is used to fill floating gate material between isolation structures to form floating gates. As flash memory manufacturing processes become increasingly miniaturized, the aspect ratio of the floating gates becomes larger. During the fabrication of floating gates, when the top profile or spacing of the isolation structures loaded onto the wafer does not match the originally set floating gate process conditions, pitting of the floating gates can easily occur, leading to decreased yield and reliability degradation. To improve this problem, conventional flash memory manufacturing processes need to detect the top spacing of the isolation structures loaded onto the wafer and adjust the floating gate process conditions based on the detection results (e.g., changing the deposition and etching amounts of the floating gate material), and then fabricate the floating gates in batches under different floating gate process conditions. This results in a decrease in flash memory production efficiency, thus failing to meet mass production standards. [Summary of the Invention]

[0003] This invention provides a method for manufacturing flash memory that can improve the phenomenon of floating gate depression without adjusting the floating gate process conditions according to different top contours or spacing of the isolation structure, thereby improving yield and reliability.

[0004] This invention provides a method for manufacturing flash memory. The method includes: forming pad oxides in an array region and a peripheral region on a substrate; and performing a batch control process for etching the pad oxides in the array region. The batch control process for etching the pad oxides in the array region includes: measuring the thickness of the pad oxides in the array region; and etching the pad oxides in the array region until the thickness reaches a desired value. The method further includes: forming a tunneling oxide layer on the substrate, wherein the tunneling oxide layer includes pad oxides, and the edge thickness of the tunneling oxide layer is greater than the central thickness.

[0005] This embodiment of the invention provides a flash memory, comprising a substrate, a plurality of isolation structures disposed in the substrate, a tunneling oxide layer disposed on the substrate, a floating gate disposed on the tunneling oxide layer, a dielectric substrate disposed along the sidewalls and top surface of the floating gate, and a control gate disposed on the dielectric substrate. The edge thickness of the tunneling oxide layer is greater than the central thickness. The tunneling oxide layer includes a pad oxide, the thickness of which is controlled by an array region pad oxide etching batch control process.

[0006] According to embodiments of the present invention, the shape of the subsequently formed floating gate and the thickness and contour of the tunneling oxide layer can be precisely controlled to improve productivity and reliability.

Implementation Method

[0008] The following provides different embodiments for implementing the flash memory disclosed herein; however, these are merely examples and not intended to limit the scope of the disclosure. For example, if the description mentions that a first component is formed on a second component, unless specifically defined, it may include embodiments where the first and second components are in direct contact, or embodiments where they are not in direct contact. For clarity, the embodiments provided in this disclosure may use the same or similar element symbols to identify the same or similar elements in different examples, but this is not intended to limit the relationship between different embodiments. Additional steps may be included before, during, and after the manufacturing method mentioned in this disclosure, and some steps may be replaced or deleted in other embodiments.

[0009] The embodiments of the present invention use multiple batch control to precisely control the shape of the subsequently formed floating gate and the thickness and contour of the tunneling oxide layer, thereby improving the yield and reliability of flash memory.

[0010] Figures 1A and 1B are flowcharts illustrating a method for manufacturing flash memory according to some embodiments of the present invention. Figures 2-14 are cross-sectional schematic diagrams illustrating flash memory at different stages of the manufacturing method according to some embodiments of the present invention. Figure 15 is a cross-sectional schematic diagram illustrating flash memory according to some embodiments of the present invention. In some embodiments, the flash memory may be NOR flash memory.

[0011] As shown in Figure 2, a pad oxide P and a mask layer 300 are formed on a substrate 100 having an array region A1 and a peripheral region A2. An isolation structure 200 is also formed in the substrate 100. The peripheral region A2 surrounds, for example, the outer side of the array region A1. In some embodiments, the thickness of the pad oxide P1 formed in the array region A1 is greater than the thickness of the pad oxide P2 formed in the peripheral region A2. In one embodiment, the peripheral region A2 may include a flat area for thickness measurement by optical instruments. It should be noted that the array region A1 and the peripheral region A2 shown in the figures are only examples of portions of each region, not the area where they are connected.

[0012] In some embodiments, the substrate 100 may comprise silicon, gallium arsenide, gallium nitride, germanium silicon, silicon on insulator (SOI), other suitable semiconductor materials, or combinations thereof. In some embodiments, other structures may also be formed in the substrate 100, such as doped regions (not shown). In this embodiment of the invention, the substrate 100 is a silicon substrate.

[0013] In some embodiments, a mask layer 300 may be formed on the pad oxide P by a deposition process. In some embodiments, the mask layer 300 may comprise a nitride, oxynitride, carbide, or other suitable dielectric material. The isolation structure 200 may be selected from a similar but different material from the mask layer 300 to facilitate subsequent selective removal of the mask layer 300. For example, the isolation structure 200 may be silicon oxide, and the mask layer 300 may be silicon nitride. Any known process may be used to form the isolation structure 200. The material of the pad oxide P may be an oxide, such as silicon oxide. In this embodiment, since the material of the pad oxide P is the same as the material of the isolation structure 200, the boundary between the two is not drawn. In other embodiments, the material of the pad oxide P may also be different from the material of the isolation structure 200.

[0014] Next, referring to Figures 1A and 3, these isolation structures 200 can be selectively etched back (step S1) to remove impurities (e.g., oxides) remaining on the mask layer 300, thereby improving the efficiency of subsequent etch-back of the mask layer 300. In some embodiments, step S1 may include wet etching and vapor phase etching processes.

[0015] Next, referring to Figures 1A and 4, the etched-back mask layer 300 is etched back such that the top surface of the etched-back mask layer 300 is lower than the top surface of the isolation structure 200, thereby forming an opening O between adjacent isolation structures 200 (step S2). In some embodiments, the etched-back mask layer 300 may include a wet etching process, for example, using an acidic solution.

[0016] Next, referring to Figures 1A, 4, and 5, the isolation structure etch batch control process R1 is performed on the isolation structure 200 in the array region A1. In this embodiment, the isolation structure etch batch control process R1 includes steps S3 and S4. In step S3, the opening size TCD between adjacent isolation structures 200 is measured for each wafer, that is, the spacing size between the top surfaces of adjacent isolation structures 200 is measured. Furthermore, it is determined whether the measured opening size TCD reaches the expected value.

[0017] When it is determined that the measured aperture size TCD does not reach the expected value, step S4 is executed. In step S4, the etching time for the isolation structure 200 of each wafer is determined based on the measured aperture size TCD, and the isolation structure 200 is etched according to the determined etching time, as shown in Figure 5. In this embodiment, the narrower the measured aperture size TCD, the longer the determined etching time, to ensure that different wafers have a consistent aperture size TCD. A database can be pre-established based on the relationship between etching amount and etching time to determine the etching time for different aperture sizes TCD. In some embodiments, the isolation structure 200 can be etched by a wet etching process.

[0018] In this embodiment, the isolation structure 200 is etched using an isotropic wet etching process, so the upper part of the isolation structure 200 can have an arc-shaped bevel. In addition, by improving the etching selectivity of the isolation structure 200, the impact on the mask layer 300 in the isolation structure etching batch control process R1 can be reduced.

[0019] After step S4 is completed, return to step S3 to measure the opening size TCD between adjacent isolation structures 200 on each wafer again, and determine whether the measured opening size TCD meets the expected value. By using the isolation structure etching batch control process R1 proposed in this embodiment, different wafers can be made to have a consistent opening size TCD, making it easier to match the subsequent process of filling the floating gate, thereby avoiding the phenomenon of floating gate depression, and thus improving yield and reliability.

[0020] Continuing to refer to Figure 1A and Figure 6, when it is determined that the measured opening size TCD has reached the expected value, the mask layer 300 is removed by etching process to expose the pad oxide P (step S5).

[0021] Next, referring to Figures 1A and 6-7, the peripheral region pad oxide etching batch control process R2 is performed on the flash memory. In this embodiment, the peripheral region pad oxide etching batch control process R2 includes steps S6 and S7. In step S6, the thickness T2 of the pad oxide P2 in the peripheral region A2 is measured, and it is confirmed whether the thickness T2 meets the expected value. In some embodiments, the thickness T2 is measured using an optical film thickness gauge.

[0022] If the thickness T2 does not reach the expected value, in step S7, the pad oxide P is etched (trimmed) according to the thickness T2, as shown in Figure 7. That is, the thinner the measured thickness T2, the shorter the etching time; the thicker the thickness T2, the longer the etching time, to ensure that the flash memory of different wafers has a consistent thickness T2. A database can be established in advance based on the relationship between etching amount and etching time to determine the etching time for different thicknesses T2. In this embodiment, in step S7, the pad oxides P1 and P2 are etched. After step S7 is completed, return to step S6 to measure the thickness T2 of the pad oxide P2 in the peripheral area A2 of each wafer again and confirm whether the thickness T2 reaches the expected value.

[0023] It should be noted that if the pad oxide P is damaged before the tunneling oxide layer is formed, it may affect the quality of the subsequently formed tunneling oxide layer, thereby reducing the yield. In particular, for the thinner peripheral region A2, if the corner of the pad oxide P2 is damaged, it may cause the corner of the subsequent tunneling oxide layer to be recessed, thereby reducing the yield. Therefore, in this embodiment, the thickness of the pad oxide P2 is precisely controlled by the peripheral region pad oxide etching batch control process R2, so that the thickness T2 is approximately consistent, avoiding damage to the pad oxide P before the tunneling oxide layer is formed, thereby improving the quality of the tunneling oxide layer (e.g., thickness uniformity) and thus improving the yield.

[0024] In some embodiments, the opening size TCD between the isolation structures 200 can be further widened by the peripheral region pad oxide etching batch control process R2, thereby avoiding the subsequent formation of floating gates and improving yield and reliability.

[0025] Continuing with reference to Figures 1A and 8, when it is determined that the thickness T2 has reached the desired value, step S9 is performed to form a photoresist 400 that shields the surrounding area A2 and exposes the array area A1. In some embodiments, the elements in the array area A1 may be subjected to ion implantation processes, thermal processes, etc., according to actual needs, but the present invention is not limited thereto.

[0026] Next, referring to Figures 1B and 8-9, the array region pad oxide etching batch control process R3 is performed on the array region A1 of the flash memory. In this embodiment, the array region pad oxide etching batch control process R3 includes steps S10 and S11. In step S10, the thickness T1 of the pad oxide P1 of the array region A1 is measured, and it is confirmed whether the thickness T1 reaches the expected value.

[0027] If the thickness T1 does not reach the expected value, in step S11, the pad oxide P1 is etched (trimmed) according to the thickness T1, as shown in Figure 9. That is, the thinner the measured thickness T1, the shorter the etching time; the thicker the thickness T1, the longer the etching time, to ensure that the flash memory of different wafers has a consistent thickness T1. A database can be pre-established based on the relationship between etching amount and etching time to determine the etching time for different thicknesses T1. After step S11 is completed, return to step S10 to measure the thickness T1 of the pad oxide P1 of the array region A1 again for each wafer and confirm whether the thickness T1 reaches the expected value. In some embodiments, through the array region pad oxide etching batch control process R3, the corners of the top surface of the pad oxide P1 can be rounded (that is, the bottom surface of the opening O has rounded corners), and the opening size TCD between the isolation structures 200 can be further widened.

[0028] It should be noted that uneven thickness of the pad oxide P1 may affect the quality of the subsequently formed tunneling oxide layer, thereby affecting the breakdown voltage of the flash memory. Therefore, by using the array region pad oxide etching batch control process R3 proposed in this embodiment, the thickness T1 of the pad oxide P1 of different wafers can be precisely controlled step by step, thereby improving the uniformity of the thickness of the pad oxide P1. In this way, the quality of the tunneling oxide layer (e.g., thickness uniformity) can be improved, thereby keeping the breakdown voltage of the flash memory within a suitable range. In addition, by using the array region pad oxide etching batch control process R3 proposed in this embodiment, the bottom surface of the opening O can have rounded corners and the opening size TCD is further widened, thereby avoiding the subsequent formation of a recessed floating gate, thereby improving yield and reliability.

[0029] Continuing with Figures 1B and 10, when it is determined that the thickness T1 has reached the desired value, step S13 is performed to remove the photoresist 400. The removal method may include known methods such as photoresist ashing and cleaning, which will not be described in detail here. In some embodiments, thermal oxidation processes, thermal drive-in processes, etc., may be performed as needed, but the present invention is not limited thereto.

[0030] Next, referring to Figures 1B and 10-11, the flash memory is subjected to a pad oxide etching batch control process R4. In this embodiment, the pad oxide etching batch control process R4 includes steps S14 and S15. In step S14, the thickness T1 of the pad oxide P1 in the array region A1 is measured, and it is confirmed whether the thickness T1 has reached the expected value.

[0031] If the thickness T1 does not reach the expected value, in step S15, the pad oxide P is etched (trimmed) according to the thickness T1, as shown in Figure 11. That is, the thinner the measured thickness T1, the shorter the etching time; the thicker the measured thickness T1, the longer the etching time, to ensure that the flash memory of different wafers has a consistent thickness T1. A database can be established in advance based on the relationship between etching amount and etching time to determine the etching time for different thicknesses T1. In this embodiment, in step S15, the pad oxides P1 and P2 are etched. After step S15 is completed, the process returns to step S14 to measure the thickness T1 of the pad oxide P1 of the array region A1 of each wafer again and confirm whether the thickness T1 reaches the expected value. By using the pad oxide etching batch control process R4, the quality of the tunneling oxide layer (e.g., thickness uniformity) can be improved, thereby controlling the collapse voltage of the flash memory within a suitable range.

[0032] It should be noted that since the thickness of the pad oxide P1 obtained by the array region pad oxide etching batch control process R3 may still have slight differences, the pad oxide etching batch control process R4 is used to make the thickness T1 more accurately reach the desired value. In some embodiments, the concentration of the etching solution used in step S15 is lower than the concentration of the etching solution used in step S11.

[0033] Continuing with Figures 1B and 12, when it is determined that the thickness T1 has reached the desired value, step S17 is performed to pre-clean the flash memory to completely remove the pad oxide P2 in the peripheral region A2. When completely removing the pad oxide P2 in the peripheral region A2, due to the influence of the aforementioned oxidation process, a small amount of pad oxide P1 may still remain in the array region A1, and the thickness of the pad oxide P1 at the edge is greater than the thickness at the center.

[0034] Continuing with reference to Figures 1B and 13, step S18 is performed to form the tunneling oxide layer Tox. In one embodiment, an oxide layer may be formed on the pad oxide P to form the tunneling oxide layer Tox including the pad oxide P. In this embodiment, the thickness of the tunneling oxide layer Tox is greater at both sides than at the center.

[0035] In some embodiments, the tunneling oxide layer Tox may comprise a material similar to or the same as the pad oxide P, which will not be described further here. In embodiments of the present invention, since the tunneling oxide layer Tox and the pad oxide P are made of the same material, such as silicon oxide, there is no clear boundary in the drawings. In some embodiments, the tunneling oxide layer Tox may be formed by an oxidation process or deposition process similar to that described above, which will not be described further here.

[0036] Continuing with reference to Figures 1B and 14, step S19 is performed to form a floating gate 600 on the tunneling oxide layer Tox. In this embodiment, the bottom surface of the opening O formed according to the array region pad oxide etching batch control process R3 has rounded corners, and the floating gate 600 filled in the opening O also has rounded corners at the corners of the bottom surface. In the array region A1 and the peripheral region A2, the floating gate 600 may have a generally flat top surface. In some embodiments, the material of the floating gate 600 may comprise doped polysilicon (e.g., p-type doped polysilicon or n-type doped polysilicon).

[0037] The following will only describe the structure of array region A1 in detail.

[0038] Referring to Figures 1B and 15, steps S20 and S21 are performed to form a dielectric substrate 700 on the floating gate 600 and a control gate 800 on the dielectric substrate 700. In some embodiments, the isolation structure 200 is first etched back to make the floating gate 600 protrude from the top surface of the isolation structure 200, thereby increasing the subsequent gate coupling ratio. Then, the dielectric substrate 700 is formed on the top surface of the isolation structure 200 and the sidewalls and top surface of the floating gate 600. The dielectric substrate 700 may be an interpoly dielectric and sequentially includes oxide 710, nitride 720 and oxide 730. In some embodiments, the control gate 800 may contain a material similar to that of the floating gate 600, which will not be described in detail here. It should be noted that after the control gate 800 is formed, other conventional processes may be performed as needed to complete the flash memory 1. Other well-known manufacturing processes will not be elaborated upon here.

[0039] In summary, the embodiments of the present invention reduce the phenomenon of floating gate depression by making the outline of the flash memory match the set floating gate process conditions. Furthermore, the embodiments of the present invention, through the isolation structure etching batch control process, eliminate the need to adjust the floating gate process conditions based on detection results (e.g., changing the deposition and etching amounts of the floating gate material), and then fabricate floating gates in batches under different floating gate process conditions, thereby improving productivity. Moreover, the embodiments of the present invention, through the peripheral area pad oxide etching batch control process, the array area pad oxide etching batch control process, or the pad oxide etching batch control process, ensure that the pad oxide has a uniform thickness, thereby improving yield and reliability. Furthermore, through the isolation structure etching batch control process and / or the peripheral area pad oxide etching batch control process, the distance between the top surfaces of the isolation structures in the array area can be adjusted to control the floating gates to have substantially the same shape (i.e., different loaded wafers have substantially the same spacing size), thereby improving yield and reliability.

[0040] This invention is applicable to the fabrication of miniaturized flash memory to increase the total number of dies on a wafer. Therefore, this invention can reduce the production cost and energy consumption of manufacturing a single IC, as well as the energy consumption of subsequent packaging, thereby reducing carbon emissions during flash memory manufacturing. Furthermore, since the reliability and yield of the flash memory of this invention are improved, this invention provides a green semiconductor technology.

[0041] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0007] Figures 1A and 1B are flowcharts illustrating a method for manufacturing flash memory according to some embodiments of the present invention. Figures 2-14 are cross-sectional schematic diagrams illustrating flash memory at different stages of the manufacturing method according to some embodiments of the present invention. Figure 15 is a cross-sectional schematic diagram illustrating flash memory according to some embodiments of the present invention.

Claims

1. A method for manufacturing flash memory, comprising: A pad oxide is formed in an array region and a peripheral region on a substrate; Multiple isolation structures are formed in the substrate; A batch control process for etching pad oxide in an array region includes: measuring the thickness of the pad oxide in the array region; The process involves etching the pad oxide in the array region until the thickness reaches a desired value; and forming a tunneling oxide layer on the substrate, wherein the tunneling oxide layer includes the pad oxide layer and the edge thickness of the tunneling oxide layer is greater than the central thickness, wherein the tunneling oxide layer is located between the isolation structures.

2. The method for manufacturing flash memory as described in claim 1 further includes, before performing the batch control process for etching the array region pad oxide, the following: A cover layer is formed on the pad oxide; the isolation structures are etched back; The masking layer is etched back so that the top surface of the etched masking layer is lower than the top surface of each isolation structure, thereby forming an opening between adjacent isolation structures, wherein the thickness of the pad oxide formed in the array region is greater than the thickness of the pad oxide formed in the peripheral region.

3. The method for manufacturing flash memory as described in claim 2 further includes an isolation structure etching batch control process, and the isolation structure etching batch control process includes: Measure the opening size of the opening; And etch the isolation structures in the array region until the opening size reaches a desired value.

4. The method for manufacturing flash memory as described in claim 2 further includes: Remove the covering layer; And to carry out a batch control process for etching a peripheral area pad oxide, including: measuring a thickness of the pad oxide in the peripheral area; And etch the pad oxide until the thickness reaches a desired value.

5. The method for manufacturing flash memory as described in claim 3 further includes: After the batch control process for etching the isolation structure is completed, the mask layer is removed; And after removing the cover layer, a batch control process for etching a peripheral area pad oxide is performed, including: measuring a thickness of the pad oxide in the peripheral area; And etch the pad oxide until the thickness reaches a desired value.

6. The method for manufacturing flash memory as described in claim 1 further includes: Before performing the batch control process of etching the pad oxide in the array region, a photoresist is formed on the pad oxide in the peripheral region. And after the batch control process of etching the pad oxide in the array region, the photoresist is removed.

7. The method for manufacturing flash memory as claimed in claim 6, further comprising, after removing the photoresist, a pad oxide etching batch control process, wherein the pad oxide etching batch control process includes: Measure the thickness of the pad oxide in the array region; And etch the pad oxide until the thickness reaches a desired value.

8. The method for manufacturing flash memory as claimed in claim 6, further comprising, after performing the pad oxide etching batch control process: A pre-cleaning process is performed to completely remove the pad oxide in the peripheral area and partially remove the pad oxide in the array area.

9. The method for manufacturing flash memory as claimed in claim 8, further comprising, after performing the pad oxide etching batch control process: A floating gate is formed on the tunneling oxide layer; a dielectric liner is formed on the floating gate; And form a control gate on the dielectric substrate.

10. The method for manufacturing flash memory as described in claim 5 further includes: Before performing the batch control process for etching the pad oxide in the array region, a photoresist is formed on the pad oxide in the peripheral region; after performing the batch control process for etching the pad oxide in the array region, the photoresist is removed. The process further includes a pad oxide etching batch control process after removing the photoresist, and the pad oxide etching batch control process includes: measuring the thickness of the pad oxide in the array region. And etch the pad oxide until the thickness reaches a desired value.

11. The method for manufacturing flash memory as claimed in claim 7, wherein the concentration of the etchant used in the pad oxide etching batch control process is lower than the concentration of the etchant used in the pad oxide in the array region in the array region pad oxide etching batch control process.

12. A flash memory, comprising: One substrate; Multiple isolation structures are disposed in the substrate; A tunneling oxide layer is disposed on the substrate, wherein the edge thickness of the tunneling oxide layer is greater than the central thickness, wherein the tunneling oxide layer includes a pad oxide, the thickness of which is controlled by an array region pad oxide etching batch control process, wherein the tunneling oxide layer is located between the isolation structures; a floating gate is disposed on the tunneling oxide layer; a dielectric substrate is disposed along the sidewall and top surface of the floating gate; and a control gate is disposed on the dielectric substrate.

13. The flash memory of request 12, wherein the floating gate has a rounded corner at the corner of the bottom surface.

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