Method of creating ion energy distribution functions (IEDF)

Abstract

This invention relates to a system and method for generating ion energy distribution functions of arbitrary shapes using shaped pulse bias voltages. In one embodiment, a method includes the steps of: applying a positive jump voltage to electrodes in a processing chamber to neutralize the wafer surface, applying a negative jump voltage to electrodes to set a wafer voltage, and modulating the amplitude of the wafer voltage to generate a predetermined number of pulses to determine the ion energy distribution function. In another embodiment, a method includes the steps of: applying a positive jump voltage to electrodes in a processing chamber to neutralize the wafer surface, applying a negative jump voltage to electrodes to set a wafer voltage, and applying a ramp voltage to electrodes that overcompensates the ion current on the wafer or undercompensates the ion current on the wafer.

Description

Method for generating an ion energy distribution function Embodiments of the present disclosure are generally related to systems and methods for processing substrates, and more particularly, to systems and methods for plasma processing of substrates. A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that provides an RF voltage to a "power electrode", and a metal bottom plate (more commonly referred to as a "cathode") embedded in an "electrostatic chuck" (ESC). FIG. 1(a) shows a line graph of a typical RF voltage supplied to the power electrode in a typical processing chamber. The power electrode is capacitively coupled to the plasma of the processing system through a ceramic layer that is part of the ESC assembly. The non-linear, diode-like characteristics of the plasma sheath cause rectification of the applied RF field, such that a direct current (DC) voltage drop or "self-bias" appears between the cathode and the plasma. This voltage drop determines the average energy of the plasma ions accelerated towards the cathode, and thus determines the etching anisotropy. More specifically, ion directionality, feature distribution, and selectivity to masks and termination layers are controlled by the ion energy distribution function (IEDF). In a plasma with an RF bias, the IEDF typically has two peaks at low and high energies, and there are some ion populations in between. The presence of the ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the cathode and the plasma oscillates at the bias frequency. When an RF bias generator with a lower frequency (such as 2 MHz) is used to obtain a higher self-bias voltage, the energy difference between the two peaks may be significant, and since the ions are at the low energy peak, the etching is more isotropic, which may cause feature wall bowing. Compared with high-energy ions, low-energy ions are less efficient at reaching the corners at the bottom of the feature (e.g., due to charging effects), but result in less sputtering of the mask material. This is important in high aspect ratio etching applications, such as hard mask openings. As feature sizes continue to decrease and aspect ratios increase, while the requirements for feature distribution control become more stringent, a well-controlled IEDF on the substrate surface is more needed during processing. A unimodal IEDF can be used to construct any IEDF, including a bimodal IEDF with independently controlled peak height and energy, which is very beneficial for high-precision plasma processing. Generating a unimodal IEDF requires the substrate surface to have an almost constant voltage relative to the plasma, i.e., the sheath voltage that determines the ion energy. Assuming a plasma potential with a time constant that is typically close to zero or the ground potential in the processing plasma, this requires the substrate to maintain an almost constant voltage relative to the ground (i.e., the substrate voltage). This cannot be simply achieved by applying a DC voltage to the power electrode because the ion current constantly charges the substrate surface. As a result, all the applied DC voltage will drop across the substrate and the ceramic part of the ESC (i.e., the chuck capacitance), rather than across the plasma sheath (i.e., the sheath capacitance). To overcome this problem, a special shaped pulse biasing scheme has been developed, which separates the applied voltage between the chuck and the sheath capacitance (we ignore the voltage drop on the substrate because its capacitance is usually much larger than the sheath capacitance). This scheme compensates for the ion current, allowing the sheath voltage and the substrate voltage to remain constant for up to 90% of each bias voltage cycle. More precisely, this biasing scheme allows a specific substrate voltage waveform to be maintained, which can be described as a periodic series of short positive pulses on top of a negative dc-offset (Figure 1(b)). During each pulse, the substrate potential reaches the plasma potential and the sheath briefly collapses, but for about 90% of each cycle, the sheath voltage remains constant and equal to the negative voltage jump at the end of each pulse, thus determining the average ion energy. Figure 1(a) shows a line graph of the special shaped pulse biasing voltage waveform developed to generate this specific substrate voltage waveform, and the special shaped pulse biasing voltage waveform can thus maintain the sheath voltage almost constant. As shown in Figure 2, the shaped pulse biasing waveform includes: (1) a positive jump to remove the extra charge accumulated on the chuck capacitance during the compensation phase; (2) a negative jump (V OUT ), used to set the value of the sheath voltage (V SH ), i.e., V OUTSeparate between the capacitively coupled chuck and the sheath capacitor, and thus determine (but typically greater than) the negative-going transition of the substrate voltage waveform; and (3) a negative voltage ramp to compensate for the ion current and maintain a constant sheath voltage during this long "ion current compensation phase". We emphasize that there can be other shaped pulse bias waveforms that also allow maintaining the specific substrate voltage waveform shown in FIG. 1(b) (characterized by an almost constant sheath voltage), and thus are capable of generating a single energy IEDF. For example, if the electrostatic chuck capacitance is much larger than the sheath capacitance, the negative voltage ramp phase described in (3) above can be replaced by a constant voltage phase. The partial systems and methods described below can also be implemented with these other shaped pulse bias waveforms, and we will specifically note this where applicable. Although a unimodal IEDF is widely considered to be a highly desirable IEDF shape for improving selectivity and profile, in some etching applications, an IEDF with a different shape is required, such as a broader-shaped IEDF. This specification provides systems and methods for using shaped pulse bias to generate an ion energy distribution function of any shape. In some embodiments, a method includes the steps of: applying a shaped pulse bias to an electrode of a processing chamber and modulating the amplitude of a negative voltage transition (V OUT ), and thus modulating the sheath voltage (V SH ), such that the relative number of pulses at a particular amplitude determines the relative ion ratio of ions with an ion energy corresponding to the particular amplitude. We emphasize that this scheme can be implemented with any shaped pulse bias waveform (not necessarily the one shown in FIG. 1(a)) that allows maintaining the specific substrate voltage waveform shown in FIG. 1(b) (characterized by an almost constant sheath voltage), and thus is capable of generating a single energy IEDF. In some other embodiments, a method includes the steps of: applying a shaped pulse bias with the voltage waveform shown in FIG. 1(a), and generating a voltage ramp during the ion compensation phase that has a more negative slope (more negative slope) than the negative slope (dV / dt) required to maintain a constant substrate voltage, i.e., overcompensating for the ion current. In some other embodiments, a method includes the steps of: applying a shaped pulse bias with the voltage waveform shown in FIG. 1(a), and generating a voltage ramp during the ion compensation phase that has a less negative slope (less negative slope) than the negative slope (dV / dt) required to maintain a constant substrate voltage, i.e., undercompensating for the ion current. Other and further embodiments of this disclosure are described below. This specification provides systems and methods for using a shaped pulse bias to generate an ion energy distribution function of any shape. The systems and methods of the present invention advantageously generate an ion energy distribution function (IEDF) of any shape by modulating the amplitude of the shaped pulse bias waveform. Embodiments of the method of the present invention can advantageously provide shaping of the voltage waveform to provide any IEDF shape, such as an IEDF with a broader profile. In the description of this specification, the terms wafer and substrate may be used interchangeably. FIG. 2 illustrates a high-level schematic diagram of a substrate processing system 200 in which embodiments according to the principles herein can be applied. The substrate processing system 200 of FIG. 2 exemplarily includes a substrate support assembly 205 and a bias supply 230. In the embodiment of FIG. 2, the substrate support assembly 205 includes a substrate support pedestal 210, a power electrode 213, and a ceramic layer 214 separating the power electrode 213 from the surface 207 of the substrate support assembly 205. In various embodiments, the system 200 of FIG. 2 can include components of a plasma processing chamber, such as SYM3 ® 、DPS ® 、ENABLER ® 、ADVANTEDGE TM and AVATAR TM or other processing chambers. In some embodiments, the bias supply 230 includes a memory for storing a control program and a processor for executing the control program to control, according to embodiments of the principles described herein, the voltage to be provided by the bias supply 230 to the power electrode 213 and at least modulate the amplitude of the wafer voltage to generate a predetermined number of pulses, and / or, or even more, apply a negative voltage step to the electrode to set the wafer voltage of the wafer, or apply a ramp voltage to the electrode that overcompensates or undercompensates the ion current on the wafer. In an alternative embodiment, the substrate processing system 200 of FIG. 2 can include an optional controller 220 that includes a memory for storing a control program and a processor for executing the control program to communicate with the bias supply 230, for at least controlling the voltage to be provided by the bias supply 230 to the power electrode 213 according to embodiments of the principles of the present invention described herein, and at least modulating the amplitude of the wafer voltage to generate a predetermined number of pulses, and / or, or even more, applying a negative voltage step to the electrode to set the wafer voltage of the wafer or applying a ramp voltage to the electrode that overcompensates or undercompensates the ion current on the wafer. In operation, the substrate to be processed is positioned on the surface of the substrate support pedestal 210. In the system 200 of FIG. 2, a voltage (shaped pulse bias) from the bias supply 230 is applied to the power electrode 213. The non-linear, diode-like characteristics of the plasma sheath cause the applied RF field to rectify, such that a direct current (DC) voltage drop or "self-bias" appears between the cathode and the plasma. This voltage drop determines the average energy of the plasma ions accelerated towards the cathode. The ion directionality and characteristics are controlled by the ion energy distribution function (IEDF). According to an embodiment of the principles described herein, the bias supply 230 can supply a specially shaped pulse bias to the power electrode 213. This bias scheme allows for maintaining a specific substrate voltage waveform, which can be described as a periodic series of short positive pulses on top of a negative dc-offset (FIG. 1(b)). During each pulse, the substrate potential reaches the plasma potential and the sheath collapses briefly, but for about 90% of each period, the sheath voltage remains constant and equal to the negative voltage jump at the end of each pulse, thus determining the average ion energy. Referring again to FIG. 1(a), the amplitude of the shaped pulse bias signal and the wafer voltage are represented by V out . The inventors have determined that in at least some embodiments according to the present principles, the shape of the IEDF can be controlled by modulating the amplitude and frequency of the shaped pulse bias signal. The method includes the steps of applying a shaped pulse bias to an electrode of a processing chamber and modulating the amplitude of the negative voltage jump (V OUT ) and thus the sheath voltage (V SH ) in a predetermined manner such that the relative number of pulses at a particular amplitude determines the relative ion ratio of ions with an energy corresponding to the particular amplitude. The number of pulses for each amplitude must be sufficient to cause a transition from one sheath voltage to the next, during which the corresponding ESC charge is established. Then, during the processing step, a burst of pulse trains (trains of pulses) having a given amplitude (FIG. 3) is repeated again and again. The active pulse trains (on-phases) can be interleaved with silence periods (off-phases). The duration of each on-phase relative to the total duration of the pulse train (combining on and off phases) is determined by the duty cycle, and the total duration (period) of the pulse train is equal to the reciprocal of the pulse train frequency. Alternatively, each pulse train can consist of a series of pulses having a given (and the same) amplitude, and then a series of pulse trains having different amplitudes are used to define the IEDF. The relative number of pulse trains having a given amplitude determines the relative proportion of ions at a specific energy, and the negative jump amplitude of the pulses in these pulse trains (V OUT )(ii) determines the ion energy. Subsequently, a predetermined pulse train is repeatedly applied during the duration of the fabrication method step. For example, to generate a bimodal IEDF that contains 25% ions in the low energy peak and 75% ions in the high energy peak, the pulse train needs to consist of a 3-pulse train with a negative jump amplitude corresponding to the high ion energy and a 1-pulse train with an amplitude corresponding to the low ion energy. Such a pulse train can be referred to as "HHHL". Conversely, to generate an IEDF with 3 energy peaks of the same height (high (H), medium (M), and low (L)), a pulse train of 3 pulse trains with different amplitudes corresponding to the H, M, and L ion energies is required, and can be referred to as "HML". A pulse train consisting of a single pulse train (with on and off phases) with a predetermined negative jump amplitude generates a unimodal IEDF. We emphasize that this scheme can use any shaped pulse bias waveform (not necessarily the one shown in Fig. 1(a)) that allows maintaining the specific substrate voltage waveform shown in Fig. 1(b) (characterized by an almost constant sheath voltage), and can thus generate a single energy IEDF. For example, Fig. 3 shows a line graph of the voltage pulses to be provided by a power supply to a processing chamber electrode to set the substrate voltage value according to an embodiment of the present principle. In the embodiment of Fig. 3, the full jump of the wafer voltage determines the ion energy, and the number of pulses corresponding to the voltage jump (such as the total duration) determines the relative ion ratio at this energy (i.e., IEDF). Fig. 4 shows a graphical representation of the IEDF obtained for the selected voltage pulses of Fig. 3 according to an embodiment of the present principle. As shown in Fig. 4, the multiple voltage pulses of Fig. 3 result in a wider IEDF, which can be advantageous in applications such as hard mask opening high aspect ratio etching that require a wider ion energy distribution. According to the present principle, the control of the amplitude and frequency of the voltage pulses provided by the power supply to the processing chamber electrode can provide good control and a well-defined IEDF shape required for specific etching processes and applications. In another embodiment in accordance with the present principles, a method includes the steps of applying a shaping pulse bias with the voltage waveform shown in FIG. 1(a), and generating a voltage ramp during an ion compensation phase having a more negative slope (dV / dt) than that required to maintain a constant substrate voltage, i.e., overcompensating for the ion current. This contributes to the substrate voltage waveform shown in FIG. 6, where the amplitude of the substrate voltage (as well as the sheath voltage and the instantaneous ion energy) increases during the ion current compensation phase. This results in the ion energy spread and non-monochromatic IEDF shown in FIG. 7, where the IEDF width is controlled by the negative slope of the applied shaped pulse bias waveform. For example, in accordance with an embodiment of the present principles, FIG. 5 depicts a plot modifying the specific shaping pulse of FIG. 1(a) to overcompensate for the ion current transitioning to charge the wafer. As shown in FIG. 5, the voltage ramp intended to compensate for the ion current charging the wafer in FIG. 1(a) is modified in the specific shaping pulse of FIG. 5 in accordance with the present principles to overcompensate for the ion current charging the wafer. As shown in FIG. 5, the positive jump intended to neutralize the wafer surface in FIG. 1 no longer neutralizes the wafer surface in the specific shaping pulse of FIG. 5 in accordance with the present principles. FIG. 6 depicts a plot of the induced voltage pulse on the wafer resulting from the specific shaping pulse bias of FIG. 5. As shown in FIG. 6, the voltage jump determines the ion energy, and the energy width is determined by the minimum and maximum wafer voltage jumps during the cycle. FIG. 7 depicts a graphical representation of the resulting IEDF for the voltage pulse of FIG. 6 in accordance with an embodiment of the present principles. As shown in FIG. 7, the IEDF resulting from the application of the specifically overcompensating shaping pulse of FIG. 5 includes a broader bimodal distribution, where V min and V max determine the IEDF width, but do not necessarily coincide with the energy peaks. The overcompensation in accordance with the present principles enables a higher control precision than can be achieved by mixing 2 RF frequencies, such as 2 and 13.56 MHz. In another embodiment according to the present principle, a method includes the steps of applying a shaping pulse bias with the voltage waveform shown in FIG. 1(a), and generating a voltage ramp during the ion compensation phase having a less negative slope (dV / dt) than that required to maintain a constant substrate voltage, i.e., insufficient compensation for the ion current. This results in the substrate voltage waveform shown in FIG. 6, where the amplitude of the substrate voltage (as well as the sheath voltage and the instantaneous ion energy) decreases during the ion current compensation phase. This produces the ion energy spread and non-monochromatic IEDF shown in FIG. 7, where the IEDF width is controlled by the negative slope of the applied shaped pulse bias waveform. For example, referring back to FIG. 5, according to an embodiment of the present principle, FIG. 5 depicts a plot modifying the specific shaping pulse of FIG. 1 to overcompensate for the ion current transition charging the wafer. As shown in FIG. 5, the voltage ramp intended to compensate for the ion current charging the wafer in FIG. 1 is modified in the specific shaping pulse of FIG. 5 according to the present principle to undercompensate for the ion current charging the wafer. As shown in FIG. 5, the positive jump intended to neutralize the wafer surface in FIG. 1 no longer neutralizes the wafer surface in the specific shaping pulse of FIG. 5 according to the present principle. Referring back to FIG. 7, a graphical representation of the IEDF resulting from undercompensation according to an embodiment of the present principle is shown. As shown in FIG. 7, the IEDF produced by the application of the specific shaping pulse of FIG. 5 with undercompensation includes a wider single-peak distribution. FIG. 8 depicts a flowchart of a method for generating an ion energy distribution function of any shape according to an embodiment of the present principle. Method 800 may begin at 802, during which a positive jump voltage is applied to the electrodes of the processing chamber to neutralize the wafer surface. Method 800 may then proceed to 804. At 804, a negative jump voltage is applied to the electrodes to set the wafer voltage. Method 800 may then proceed to 806. At 806, the amplitude of the wafer voltage is modulated to generate a predetermined number of pulses to determine the ion energy distribution function. Method 800 may then exit. FIG. 9 depicts a flowchart of a method for generating an ion energy distribution function of any shape according to another embodiment of the present principle. Method 900 may begin at 902, during which a positive jump voltage is applied to the electrodes of the processing chamber to neutralize the wafer surface. Method 900 may then proceed to 904. At 904, a negative jump voltage is applied to the electrodes to set the wafer voltage. Method 900 may then proceed to 906. At 906, a ramp voltage that overcompensates for the ion current on the wafer is applied to the electrodes. Method 900 may then exit. FIG. 10 illustrates a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to another embodiment of the present principle. Method 1000 may start at 1002, during which a positive jump voltage is applied to the electrodes of the processing chamber to neutralize the wafer surface. Method 1000 may then proceed to 1004. At 1004, a negative jump voltage is applied to the electrodes to set the wafer voltage. Method 1000 may then proceed to 1006. At 1006, a ramp voltage that undercompensates for the ion current on the wafer is applied to the electrodes. Method 1000 may then exit. Although the foregoing has been directed to embodiments of the present disclosure, other and further embodiments of the present disclosure disclosed herein may be devised without departing from the basic scope of the invention. 200: Processing system 205: Substrate support system 207: Surface 210: Substrate support pedestal 213: Power electrode 214: Ceramic 220: Controller 230: Bias supply 800: Method 802: Step 804: Step 806: Step 900: Method 902: Step 904: Step 906: Step 1000: Method 1002: Step 1004: Step 1006: Step Embodiments of the present disclosure have been briefly outlined above and will be discussed in more detail below. The embodiments of the present disclosure may be understood by reference to the embodiments illustrated in the accompanying drawings. However, the accompanying drawings only illustrate typical embodiments of the present disclosure, and since the present disclosure may permit other equivalent embodiments, the accompanying drawings are not considered to limit the scope of the present disclosure. FIG. 1(a) illustrates a line graph of a specially shaped pulse developed to maintain a constant sheath voltage. FIG. 1(b) illustrates a line graph of a specific substrate voltage waveform generated by the bias scheme of FIG. 1(a), which allows the sheath voltage and the substrate voltage to remain constant for up to 90% of each bias voltage cycle. FIG. 1(c) illustrates a line graph of a single-peak IEDF obtained from the bias scheme of FIG. 1(a). FIG. 2 illustrates a substrate processing system in which embodiments of the present principle may be applied. FIG. 3 illustrates a line graph of a voltage pulse for setting the value of the substrate voltage according to an embodiment of the present principle. FIG. 4 illustrates a graphical representation of an IEDF obtained from the selected voltage pulse of FIG. 3 according to an embodiment of the present principle. FIG. 5 illustrates a line graph of modifying the specially shaped pulse of FIG. 1 to overcompensate and undercompensate for the ion current according to an embodiment of the present principle. FIG. 6 illustrates a graph of the induced voltage pulse on the wafer biased by the specific shaped pulse of FIG. 5. Figure 7 shows a graphical representation of the obtained IEDF for the voltage pulse of FIG. 6 according to an embodiment of the present principle. Figure 8 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to an embodiment of the present principle. Figure 9 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to another embodiment of the present principle. Figure 10 shows a flowchart of a method for generating an ion energy distribution function of an arbitrary shape according to another embodiment of the present principle. For ease of understanding, wherever possible, the same numerical reference numerals are used to represent the same elements in the drawings. For clarity, the drawings are not drawn to scale and may be simplified. The elements and features in one embodiment may be advantageously used in other embodiments without further elaboration. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None

Claims

1. A method for processing a wafer, comprising the steps of: applying a negative switching voltage to an electrode of a processing chamber to set a wafer voltage for a wafer; modulating an amplitude of the wafer voltage to generate a plurality of groups of a plurality of pulse trains having different amplitudes, wherein each group of the plurality of pulse trains consists of a plurality of pulse trains having the same amplitude; repeating the step of modulating the amplitude of the wafer voltage to repeat the plurality of groups of the plurality of pulse trains to generate an ion energy distribution function having more than one energy peak; wherein based on a number of pulses of different amplitudes generated during a corresponding modulation of the wafer voltage, a relative number of a plurality of pulses of a particular amplitude in each pulse train determines a relative ion ratio corresponding to an ion energy of the particular amplitude; and wherein the relative number of pulse trains having a given amplitude in the series determines a relative proportion of ions at a particular energy.

2. The method as described in claim 1, comprising the steps of: applying a positive switching voltage to the electrode of the processing chamber to neutralize a surface of the wafer.

3. The method as described in claim 2, wherein the positive switching voltage is applied to the electrode of the processing chamber before the negative switching voltage is applied.

4. The method as described in claim 1, wherein the desired ion energy distribution function is generated to induce a specific bias voltage waveform on the wafer.

5. The method as described in claim 1, comprising the steps of: modulating the wafer voltage at different points in time to generate the ion energy distribution function having more than one energy peak.

6. The method as described in claim 5, wherein the ion ratio of one of the energy peaks is determined by the number of pulses generated during a corresponding modulation period of the wafer voltage at the different points in time.

7. The method as claimed in claim 1 further comprises the steps of: applying a positive jump voltage to the electrode of the processing chamber to neutralize a surface of a wafer; and applying a ramp voltage to the electrode to compensate for the ion current overcurrent on the wafer.

8. The method of claim 7, wherein the step of applying a ramp voltage to the electrode to compensate for the overcompensation of the ion current on the wafer comprises the following steps: applying a ramp voltage to the electrode, the ramp voltage comprising a slope having a more negative slope than the slope required to maintain a constant voltage on the wafer.

9. The method as described in claim 8, wherein a minimum voltage and a maximum voltage of a current induced on the wafer determine a width of a resulting ion energy distribution function.

10. The method of claim 1, comprising the step of applying a ramp voltage to the electrode to compensate for insufficient ion current on the wafer, further comprising the step of applying a ramp voltage to the electrode, the ramp voltage comprising a slope having a less negative slope than that required to maintain a constant voltage on the wafer.

11. The method as described in claim 10, wherein a minimum voltage and a maximum voltage of a current induced on the wafer determine a width of a resulting ion energy distribution function.

12. The method as described in claim 7 further comprises the following steps: adjusting a slope of the ramp voltage to generate a desired ion energy distribution function to induce a specific bias voltage waveform on the wafer.

13. The method as described in claim 1, further comprising: a period during which no voltage pulse is supplied to the electrode between the plurality of groups of pulses.

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