Manufacturing method of electronic device

Abstract

This disclosure provides a method for manufacturing an electronic device, comprising: providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements, wherein the packaging process includes disposing a plurality of filler material layers on the sidewalls of each of the plurality of semiconductor elements; providing a substrate, the substrate including a plurality of working regions, each of the plurality of working regions including at least one first groove; and disposing the plurality of packaged semiconductor elements in the at least one first groove of the plurality of working regions by fluid transfer.

Description

Method for manufacturing electronic device The present disclosure relates to a method for manufacturing an electronic device, and more particularly to a method for manufacturing an electronic device including a fluid transfer process. Electronic components can be transferred to a target substrate through mass transfer technology. However, in existing mass transfer technology, the use of stamp transfer to transfer electronic components may result in insufficient randomness in the distribution of electronic components on the target substrate, resulting in regional differences in the performance of the electronic components on the target substrate, that is, uneven performance overall, which in turn leads to decreased product performance. On the other hand, the stamp transfer method may also fail to completely transfer electronic components, thereby increasing production costs. Therefore, how to improve the performance of electronic devices formed through mass transfer technology or reduce the production cost of electronic devices formed through mass transfer technology is one of the important issues in this field. In some embodiments, the present disclosure provides a method for manufacturing an electronic device, comprising providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements; providing a substrate comprising a plurality of working areas, each of the plurality of working areas respectively comprising at least one first groove; and disposing the plurality of packaged semiconductor elements in at least one first groove of the plurality of working areas in a fluid transfer manner, wherein the packaging process comprises disposing a plurality of filling material layers respectively on the side walls of each of the plurality of semiconductor elements. In some embodiments, the present disclosure provides a method for manufacturing an electronic device, comprising providing a plurality of semiconductor elements; performing a packaging process on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements; providing a first substrate, the first substrate including a plurality of grooves; disposing the plurality of packaged semiconductor elements in the plurality of grooves of the first substrate in a fluid transfer manner; providing a second substrate, the second substrate including a plurality of working areas; and transferring at least a portion of the plurality of packaged semiconductor elements from at least a portion of the plurality of grooves of the first substrate to the plurality of working areas, wherein the packaging process includes disposing a plurality of filling material layers respectively on the side walls of each of the plurality of semiconductor elements. The present disclosure will be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, many of the drawings in this disclosure depict only a portion of the device, and certain components in the drawings are not drawn to scale. Furthermore, the number and size of components in the drawings are for illustration only and are not intended to limit the scope of this disclosure. Throughout this disclosure and the accompanying claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and patent claims, words such as “including” and “comprising” are open-ended words and should be interpreted as meaning “including but not limited to…”. It should be understood that when an element or film layer is referred to as being "disposed on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or film layer, or there can be an intervening element or film layer between the two (indirect case). Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there can be no intervening element or film layer between the two. When an element or film layer is referred to as being "electrically connected" to another element or film layer, it can be interpreted as a direct electrical connection or an indirect electrical connection. The electrical connection or coupling described in this disclosure can refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable component, or a combination of the above components between the endpoints of the components on the two circuits, but is not limited to these. While the terms "first," "second," "third," etc. may be used to describe various components, these terms are not intended to limit the components to these terms. These terms are used solely to distinguish a single component from other components within the specification. The claims may not use the same terms, but may be replaced with "first," "second," "third," etc., in the order in which the components are declared in the claims. Thus, in the following description, the first component may be the second component within the claims. In the present disclosure, the thickness, length and width may be measured using an optical microscope, and the thickness or width may be measured using a cross-sectional image from an electron microscope, but the present invention is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. The terms "approximately", "equal", "equal" or "same", "substantially" or "approximately" are generally interpreted as being within a range of plus or minus 20% of the given value, or within a range of plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1% or plus or minus 0.5% of the given value. In addition, the phrases “a given range is from a first value to a second value” and “a given range falls within the range from a first value to a second value” mean that the given range includes the first value, the second value and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure. It should be noted that the following embodiments may be implemented by replacing, reorganizing, or mixing the technical features of several different embodiments without departing from the spirit of the present disclosure to implement other embodiments. The electronic devices mentioned in the present disclosure may include display devices, sensing devices, backlight devices, antenna devices, splicing devices or other suitable electronic devices, but are not limited thereto. The electronic devices disclosed in the present disclosure may include any suitable device applied to the above devices. The electronic device may be a bendable, flexible or stretchable electronic device. The display device may be applied to, for example, a notebook computer, a public display, a spliced ​​display, a car display, a touch display, a television, a monitor, a smartphone, a tablet computer, a light source module, a lighting device or an electronic device applied to the above products, but is not limited thereto. The sensing device may include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors or a combination of the above types of sensors. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, such as a liquid crystal antenna device, but is not limited thereto. The splicing device may, for example, include a display splicing device or an antenna splicing device, but is not limited thereto. The appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may include an electronic unit, wherein the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may, for example, include an organic light emitting diode (OLED) or an inorganic light emitting diode, and the inorganic light emitting diode may, for example, include a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED, but is not limited thereto. It should be noted that the electronic device disclosed herein may be various combinations of the above devices, but is not limited thereto. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including a car windshield), or a splicing device. Please refer to Figures 14 to 16. Figure 14 is a flow chart of a method for manufacturing an electronic unit of an electronic device according to an embodiment of the present disclosure. Figure 15 is a process chart of the electronic unit of an electronic device according to an embodiment of the present disclosure. Figure 16 is a cross-sectional schematic diagram of the electronic unit of an electronic device according to an embodiment of the present disclosure. According to the present disclosure, an electronic unit (e.g., the electronic unit EU shown in Figures 6 and 13) of an electronic device (e.g., the electronic device ED shown in Figures 6 and 13) includes a packaged semiconductor component PU. The packaged semiconductor component PU includes a semiconductor element SU. The semiconductor element SU may refer to any suitable element including a semiconductor layer or formed through a semiconductor process. The semiconductor element SU may include any suitable element depending on the type or purpose of the electronic device. For example, in one embodiment, the electronic device may include a display device, and the semiconductor element SU may include a light-emitting unit, wherein the light-emitting unit includes, for example, but is not limited to, a light-emitting diode. In some embodiments, the electronic device may include a sensing device, and the semiconductor element SU may include any suitable sensing unit, such as, but is not limited to, a photodiode. The following describes the method for manufacturing an electronic device using the example of a semiconductor element SU including a light-emitting diode. Specifically, the packaged semiconductor component PU can be formed by performing a packaging process on the semiconductor component SU. After the packaged semiconductor component PU is formed, the packaged semiconductor component PU can be transferred to a target substrate (e.g., the substrate SB shown in FIG. 6 or the third substrate SB3 shown in FIG. 13 ) through a fluid transfer process to form an electronic device. In other words, a packaging process can be first performed on the semiconductor component to form a packaged semiconductor component PU, and then the packaged semiconductor component PU can be transferred to the target substrate through a fluid transfer process to form an electronic device. According to this embodiment, the manufacturing method M300 of the packaged semiconductor component PU may include the following steps: S300: providing a plurality of semiconductor components; S302: Disposing a plurality of filling material layers on the sidewalls of each semiconductor element; S304: Disposing a first electrode on the first surface of each semiconductor element; S306: forming a conductive layer on the sidewalls of each filling material layer; S308: Disposing a second electrode on the second surface of each semiconductor element. The following will describe in detail the steps of the manufacturing method M300 for packaging the semiconductor device PU. The manufacturing method M300 for packaging semiconductor components PU includes first performing step S300 to provide a plurality of semiconductor components SU. Specifically, as shown in process (I) of Figure 15, a substrate GB and a plurality of semiconductor components SU disposed on the substrate GB can be provided. The substrate GB may include a growth substrate, but is not limited thereto. For example, the semiconductor components SU can be formed on the substrate GB through an epitaxial process. In some embodiments, the substrate GB can be used to support the semiconductor components SU or provide support for the semiconductor components SU. Then, the plurality of semiconductor components SU can be transferred from the substrate GB to the carrier CR. In this embodiment, the plurality of semiconductor components SU can be transferred from the substrate GB to the carrier CR by an imprint transfer method, but is not limited thereto. For example, the semiconductor components SU can be picked up at a specific interval on the substrate GB and transferred to the carrier CR so that the specific interval exists between two adjacent semiconductor components SU on the carrier CR, thereby facilitating the subsequent packaging process of the semiconductor components SU. In some embodiments, the semiconductor components SU can be transferred from the substrate GB to the carrier CR by a laser transfer method. The carrier CR may include a base BS and a material layer ML disposed on the base BS, and the semiconductor element SU may be attached to the base BS via the material layer ML. The base BS may include a rigid substrate or a flexible substrate. Rigid substrates include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof, while flexible substrates include, for example, but are not limited to, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof. The material layer ML may include any suitable material that has temporary adhesion to the semiconductor element SU, thereby temporarily securing the semiconductor element SU to the base BS. In this embodiment, the semiconductor element SU may include, but is not limited to, a light-emitting diode, such as an inorganic light-emitting diode. For example, the semiconductor element SU may include a first semiconductor layer S1, a second semiconductor layer S2, and a light-emitting layer LEL disposed between the first semiconductor layer S1 and the second semiconductor layer S2. Specifically, the semiconductor device SU may include a structure formed by sequentially stacking a second semiconductor layer S2, a light-emitting layer LEL, and a first semiconductor layer S1 along a normal direction (i.e., direction Z) to the carrier CR, wherein the second semiconductor layer S2 may contact the material layer ML, but the present invention is not limited thereto. In some embodiments, the semiconductor device SU may include a structure formed by sequentially stacking a first semiconductor layer S1, a light-emitting layer LEL, and a second semiconductor layer S2 along a normal direction to the carrier CR, wherein the first semiconductor layer S1 may contact the material layer ML. The semiconductor device SU may also include other suitable film layers, such as an ohmic contact layer, but is not limited to the aforementioned film layers.The semiconductor element SU includes a first surface SR1 and a second surface SR2 opposite to the first surface SR1. The first surface SR1 may refer to a surface of the semiconductor element SU away from the carrier CR, while the second surface SR2 may refer to a surface of the semiconductor element SU adjacent to the carrier CR, or a surface of the semiconductor element SU contacting the material layer ML. In this embodiment, the first surface SR1 may be the surface of the first semiconductor layer S1, and the second surface SR2 may be the surface of the second semiconductor layer S2. It should be noted that although process (I) in Figure 15 only shows a structure in which a single semiconductor element SU is transferred to the carrier CR, the carrier CR may include multiple semiconductor elements SU transferred from the substrate GB. After transferring the plurality of semiconductor components SU to the carrier CR, step S302 may be performed to deposit a plurality of filler material layers FM on the sidewalls SW of each semiconductor component SU. Specifically, as shown in process (II) of FIG. 15 , the semiconductor component SU may include sidewalls SW connected between the first surface SR1 and the second surface SR2, and the filler material layers FM may be disposed on the carrier CR and surround the sidewalls SW of the semiconductor component SU. In other words, as shown in process (II) of FIG. 15 , when viewing the semiconductor component SU from above, the filler material layers FM may surround the semiconductor component SU. The filler material layers FM may cover the sidewalls of the semiconductor component SU, but not the first surface SR1 and the second surface SR2 of the semiconductor component SU. Specifically, the filler material layer FM may include a third surface SR3 and a fourth surface SR4 opposite to the third surface SR3. The third surface SR3 is adjacent to the first surface SR1 of the semiconductor device SU, while the fourth surface SR4 is adjacent to the second surface SR2 of the semiconductor device SU. In a direction normal to the carrier CR, the third surface SR3 may be substantially aligned with the first surface SR1, and the fourth surface SR4 may be substantially aligned with the second surface SR2, but the present invention is not limited thereto. The filler material layer FM may include any suitable material with high light transmittance, such as acrylic, siloxane, silica, other suitable materials, or combinations thereof. In this embodiment, the filler material layer FM may have a visible light transmittance greater than 90%. According to this embodiment, as shown in process (II) of Figure 15, when observing the filling material layer FM from above, the outer edge of the third surface SR3 and the outer edge of the fourth surface SR4 of the filling material layer FM may be circular or approximately circular (for example, elliptical, but not limited to this). In this way, the packaged semiconductor component PU may have a circular outline in the top view direction of the electronic device ED. Specifically, the third surface SR3 (or the fourth surface SR4) has an annular shape, wherein the outer edge of the annular shape is circular or approximately circular, and the shape of the inner edge of the annular shape is the same as the shape of the semiconductor component SU. When observing the semiconductor component SU from above, the shape of the semiconductor component SU may include a rectangle, a circle, a polygon, an irregular shape or other suitable shapes. For example, in this embodiment, when observing the semiconductor component SU from above, the shape of the semiconductor component SU may be a rectangle, but is not limited to this. The filling material layer FM also includes a sidewall SW1 connected between the third surface SR3 and the fourth surface SR4. In some embodiments, the dimensions (e.g., area) of the third surface SR3 and the dimensions of the fourth surface SR4 may differ. For example, the third surface SR3 may be smaller than the fourth surface SR4, and the sidewall SW1 may not be perpendicular to the third and fourth surfaces SR3 and SR4, as shown in process (II) of Figure 15 . In some embodiments, the dimensions of the third surface SR3 and the fourth surface SR4 may be substantially the same, and the sidewall SW1 may be perpendicular to the third and fourth surfaces SR3 and SR4. Depending on the shape of the filler material layer FM, a semiconductor element SU and the filler material layer FM surrounding the semiconductor element SU may form a disk structure (or cylindrical structure). The manufacturing method M300 of the packaged semiconductor component PU of this embodiment also includes step S304, setting a first electrode E1 on the first surface SR1 of each semiconductor component SU. Specifically, after the semiconductor component SU is transferred to the carrier CR, the first electrode E1 can be set on the first surface SR1 of the semiconductor component SU away from the carrier CR. The first electrode E1 contacts the first surface SR1, that is, contacts the first semiconductor layer S1. The first electrode E1 may include any suitable conductive material, such as a metal material or a transparent conductive material. It should be noted that in some embodiments, after the semiconductor component SU is transferred to the carrier CR, the first electrode E1 may be set first, and then the filling material layer FM may be set. In other embodiments, after the semiconductor component SU is transferred to the carrier CR, the filling material layer FM may be set first, and then the first electrode E1 may be set. The manufacturing method M300 of the packaged semiconductor component PU of this embodiment further includes step S306, forming a conductive layer CD on the side wall SW1 of each filling material layer FM. In detail, as shown in process (II) of Figure 15, after the filling material layer FM is provided, the conductive layer CD can be formed along the side wall SW1 of the filling material layer FM. The conductive layer CD can be provided around the side wall SW1 of the filling material layer FM, thereby covering the side wall SW1 of the filling material layer FM. In this embodiment, as shown in process (II) of Figure 15, the conductive layer CD can further extend on the third surface SR3 of the filling material layer FM, but does not contact the first electrode E1 and the first semiconductor layer S1. In this case, when observing the conductive layer CD from above, the portion of the conductive layer CD located on the third surface SR3 can have an annular structure, wherein the annular structure can expose the first electrode E1 and the first semiconductor layer S1. In some embodiments, the conductive layer CD may not extend over or contact the third surface SR3 of the filler material layer FM. For example, the end of the conductive layer CD adjacent to the third surface SR3 may be substantially aligned with the third surface SR3. Furthermore, while process (II) in FIG. 15 illustrates a structure in which the conductive layer CD further extends over the carrier CR (or the material layer ML), this embodiment is not limited thereto. In some embodiments, the conductive layer CD may not extend over the carrier CR. According to the present disclosure, the conductive layer CD may include a highly reflective material, or the conductive layer CD may at least partially include a highly reflective material. For example, in some embodiments, the material of the conductive layer CD may be a highly reflective conductive material, such as silver (Ag) or aluminum (Al), but is not limited thereto. In some embodiments, the conductive layer CD may include a composite structure, wherein the composite structure includes a conductive material layer and a reflective material layer, and the reflective material layer is located between the conductive material layer and the side wall SW1 of the filling material layer FM. The conductive material layer may include a metal material with high conductivity, such as gold (Au) or copper (Cu), but is not limited thereto. The reflective material layer may include any suitable element or film layer with high reflectivity, such as a distributed bragg reflector (DBR), but is not limited thereto. By making the conductive layer CD highly reflective, the light extraction effect of the packaged semiconductor element PU can be improved. It should be noted that in the manufacturing method M300 , the step of forming the conductive layer CD (step S306 ) and the step of disposing the first electrode E1 (step S304 ) may be performed in any order or simultaneously, and the present embodiment is not limited thereto. The manufacturing method M300 of the packaged semiconductor component PU of this embodiment also includes step S308, which is to set the second electrode E2 on the second surface SR2 of each semiconductor component SU. In detail, after forming the structure shown in process (II) of Figure 15, the structure can be transferred from the carrier CR to the carrier CR'. The carrier CR' may include a base BS' and a material layer ML'. The features of the base BS' and the material layer ML' can refer to the description of the base BS and the material layer ML above, but are not limited thereto. Specifically, as shown in process (III) of Figure 15, after transferring the structure shown in process (II) of Figure 15 to the carrier CR', the structure can be set on the carrier CR' with the first electrode E1 (or the first surface SR1 of the semiconductor component SU) facing downward. In this case, the second surface SR2 of the semiconductor component SU can face upward, or can be away from the carrier CR'. The material layer ML' can contact the first electrode E1 and / or the conductive layer CD, but is not limited thereto. Then, the second electrode E2 can be set on the second surface SR2. Specifically, the second electrode E2 can be disposed on the second surface SR2 of the semiconductor element SU, the fourth surface SR4 of the filler material layer FM, and the conductive layer CD, contacting the second semiconductor layer S2 and the conductive layer CD. In this case, the second electrode E2 is electrically connected to the second semiconductor layer S2 and the conductive layer CD, respectively, or in other words, the second electrode E2 is electrically connected between the second semiconductor layer S2 and the conductive layer CD. For example, in this embodiment, the second electrode E2 can be disposed entirely over the semiconductor element SU, the filler material layer FM, and the conductive layer CD, but this is not a limitation. In this case, the outer edge of the second electrode E2 can be, for example, circular or nearly circular in the direction normal to the carrier CR', depending on the shape of the filler material layer FM. With this structural design, the second semiconductor layer S2 can be electrically connected to the conductive layer CD via the second electrode E2. In other words, the portion of the conductive layer CD extending above the third surface SR3 can serve as a bonding element for the second semiconductor layer S2 and be located on the same side as the bonding element of the first semiconductor layer S1 (i.e., the first electrode E1). This facilitates bonding of the packaged semiconductor element PU to the target substrate when it is subsequently transferred to the target substrate. The second electrode E2 may comprise any suitable transparent conductive material, such as, but not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium oxide (IGO). In some embodiments, the second electrode E2 may comprise a thin metal or a metal mesh. For example, the second electrode E2 may be formed by forming a very thin metal layer (e.g., a magnesium layer or a silver layer), or by forming a metal mesh layer having light-transmitting openings through screen printing or other patterning processes. After providing the second electrode E2, the manufacturing method M300 of the packaged semiconductor unit PU of this embodiment may further include providing an auxiliary element AE. The auxiliary element AE may be provided on the second electrode E2, or on a side of the second electrode E2 opposite from the semiconductor unit SU, such that the second electrode E2 is located between the auxiliary element AE and the second semiconductor layer S2. After providing the auxiliary element AE, the packaged semiconductor unit PU can be formed. It should be noted that FIG15 merely illustrates the manufacturing process of a single packaged semiconductor unit PU. Other semiconductor units SU transferred to the carrier CR may be packaged in the same manner to form a packaged semiconductor unit PU. Furthermore, the manufacturing method of the packaged semiconductor unit PU of this embodiment is not limited to the aforementioned steps and may include other suitable steps depending on the structural design of the packaged semiconductor unit PU. As shown in FIG16 , the packaged semiconductor component PU of this embodiment may include a semiconductor component SU, a filler material layer FM disposed around the sidewalls SW of the semiconductor component SU, a first electrode E1 and a second electrode E2 disposed on the first and second surfaces SR1 and SR2 of the semiconductor component SU, respectively, and a conductive layer CD disposed around the sidewalls SW1 of the filler material layer FM. The second electrode E2 contacts the conductive layer CD, thereby electrically connecting the second semiconductor layer S2 to the conductive layer CD. In addition to being disposed around the sidewalls SW1, the conductive layer CD may also extend onto the third surface SR3 of the filler material layer FM. In this case, the packaged semiconductor component PU may have a vertical embedded flip chip structure. Specifically, the semiconductor element SU in the packaged semiconductor element PU may include a vertical type light emitting diode element and be embedded in the filling material layer FM. When the packaged semiconductor element PU is subsequently transferred to a target substrate to form an electronic device, the first semiconductor layer S1 and the second semiconductor layer S2 of the semiconductor element SU can be electrically connected to the bonding pad on the target substrate (for example, the bonding pad BP4 shown in Figure 5 or the bonding pad BP6 shown in Figure 12) through the first electrode E1 and a portion of the conductive layer CD located on the same side of the semiconductor element SU as the first electrode E1 (that is, the portion of the conductive layer CD extending on the third surface SR3), that is, the packaged semiconductor element PU can be bonded to the target substrate in a flip-chip manner. In a cross-sectional view of the packaged semiconductor component PU (as shown in FIG16 ), the packaged semiconductor component PU has a first side F1 and a second side F2 opposite to the first side F1, wherein the first side F1 is defined as the side where the first electrode E1 of the packaged semiconductor component PU is located, and the second side F2 is defined as the side where the second electrode E2 of the packaged semiconductor component PU is located. According to this embodiment, the first side F1 of the packaged semiconductor component PU may have a width W1, wherein the width W1 may range from 10 micrometers (μm) to 50 μm (i.e., 10 μm ≤ W1 ≤ 50 μm), but is not limited thereto. The width W1 may be defined as the maximum distance between the two ends of the first side F1 of the packaged semiconductor component PU in the cross-sectional view of the packaged semiconductor component PU. For example, in this embodiment, the width W1 may be the maximum distance between the two ends of the conductive layer CD located on the first side F1. In some embodiments, the width W1 may range from 15 μm to 45 μm (i.e., 15 μm ≤ W1 ≤ 45 μm). In some embodiments, the width W1 may range from 20 μm to 40 μm (ie, 20 μm ≤ W1 ≤ 40 μm). According to this embodiment, in a cross-sectional view of the packaged semiconductor component PU (as shown in FIG16 ), the packaged semiconductor component PU may have a thickness TH1. The thickness TH1 may be defined as the maximum thickness of the packaged semiconductor component PU in its normal direction. For example, the thickness TH1 may be defined as the maximum distance between the surface of the second electrode E2 opposite to the semiconductor component SU and the surface of the first electrode E1 opposite to the semiconductor component SU (or the conductive layer CD) in the normal direction of the packaged semiconductor component PU. According to this embodiment, the thickness TH1 may range from 10 μm to 50 μm (i.e., 10 μm ≤ TH1 ≤ 50 μm), but is not limited thereto. In some embodiments, the thickness TH1 may range from 15 μm to 45 μm (i.e., 15 μm ≤ TH1 ≤ 45 μm). In some embodiments, the thickness TH1 may range from 20 μm to 40 μm (i.e., 20 μm ≤ TH1 ≤ 40 μm). According to this embodiment, a portion of the conductive layer CD extending on the third surface SR3 and another portion of the conductive layer CD extending on the sidewall SW1 may define an angle θ1. Angle θ1 can also be considered the angle between the third surface SR3 and the sidewall SW1. In other words, the value of angle θ1 can be determined by the shape design of the filler material layer FM. According to this embodiment, angle θ1 can range from 90 degrees to 135 degrees (i.e., 90° ≤ θ1 ≤ 135°), but is not limited thereto. When angle θ1 is 90 degrees, the portion of the conductive layer CD extending on the third surface SR3 is perpendicular to the other portion of the conductive layer CD extending on the sidewall SW1, or in other words, the third surface SR3 is perpendicular to the sidewall SW1. In some embodiments, angle θ1 can range from 95 degrees to 130 degrees (i.e., 95° ≤ θ1 ≤ 130°). In some embodiments, angle θ1 can range from 100 degrees to 125 degrees (i.e., 100° ≤ θ1 ≤ 125°). By making the value of the angle θ1 fall within the above range, the light extraction effect of the packaged semiconductor element PU can be improved. Please refer to Figure 17, which is a schematic cross-sectional view of an electronic unit of an electronic device according to another embodiment of the present disclosure. One of the main differences between the packaged semiconductor component PU of this embodiment and the packaged semiconductor component PU shown in Figure 16 lies in the location of the conductive layer CD. Specifically, as shown in Figure 17, the conductive layer CD of the packaged semiconductor component PU of this embodiment may not be disposed on the third surface SR3 of the filling material layer FM, or may not extend on the third surface SR3. Specifically, the conductive layer CD may extend on the sidewall SW1 of the filling material layer FM and be substantially aligned with the third surface SR3. In this case, the packaged semiconductor component PU may have a vertical embedded chip structure. Specifically, the semiconductor component SU may include a vertical light-emitting diode component embedded in the filling material layer FM. In addition, in this embodiment, the first electrode E1 of the packaged semiconductor component PU may also extend on the third surface SR3 of the filling material layer FM. That is, the first electrode E1 may simultaneously contact the first surface SR1 of the semiconductor component SU (or the first semiconductor layer S1) and the third surface SR3 of the filling material layer FM. It should be noted that although the conductive layer CD contacts the second electrode E2 in FIG17 , this embodiment is not limited thereto. In some embodiments, the conductive layer CD may not contact the second electrode E2, and the second electrode E2 may be electrically connected to a bonding pad on the target substrate via other traces (not shown). According to the present disclosure, after the packaged semiconductor element PU is formed by the above-mentioned manufacturing method M300, the packaged semiconductor element PU can be transferred to the target substrate through a fluid transfer process to form an electronic device. In other words, the semiconductor element SU can be subjected to a packaging process before the fluid transfer process is performed on the semiconductor element SU. Since the semiconductor element SU in the present disclosure may include a vertical light-emitting diode element, the arrangement compactness of the semiconductor element SU on the substrate (such as a wafer) can be increased, thereby improving the substrate utilization rate. In addition, by performing a packaging process on the semiconductor element SU before the fluid transfer process of the semiconductor element SU to form the packaged semiconductor element PU, the bonding element of the first semiconductor layer S1 (i.e., the first electrode E1) and the bonding element of the second semiconductor layer S2 (i.e., the portion of the conductive layer CD extending on the third surface SR3) in the semiconductor element SU can be located on the same side of the packaged semiconductor element PU, thereby facilitating the bonding of the packaged semiconductor element PU to the target substrate to form an electronic device. The steps of the fluid transfer process of the packaged semiconductor element PU will be described in detail below. It should be noted that the electronic unit EU mentioned below (including electronic unit EUA, electronic unit EUB, electronic unit EUC, first electronic unit EU1, and second electronic unit EU2) may refer to any one of the packaged semiconductor components PU in the above embodiments, and the structure of the electronic unit EU shown in the figure below is only exemplary. For its structural details, please refer to Figures 16 and 17 and the relevant content above. Please refer to Figures 1 to 6. Figure 1 is a schematic flow chart of a method for manufacturing an electronic device according to a first embodiment of the present disclosure, while Figures 2 to 6 are schematic diagrams of a method for manufacturing an electronic device according to this embodiment. Specifically, Figures 2 to 6 illustrate a transfer process for packaging a semiconductor element PU. According to this embodiment, a method M100 for manufacturing an electronic device ED (shown in Figure 6) may include the following steps: S102: Providing a substrate, the substrate comprising a plurality of working areas, and each working area comprising at least one first groove and at least one second groove; S104: disposing a plurality of first electronic units in at least one first groove of a plurality of working areas by fluid transfer; S106: Identifying a defective working area from a plurality of working areas; and S108: Disposing at least one repair electronic unit in at least one of the at least one second grooves in the defective working area by laser transfer. The following will describe in detail the steps of the manufacturing method M100 for the electronic device ED. Please refer to Figures 2 and 3. Figure 2 is a schematic diagram of the fluid transfer process of the first embodiment of the present disclosure, and Figure 3 is a schematic top view of the substrate and electronic unit of the first embodiment of the present disclosure. In this embodiment, the manufacturing method M100 of the electronic device ED includes first performing step S102 to provide a substrate SB. The substrate SB may include a plurality of working areas WR, and each working area WR may include at least one first recess R1 and at least one second recess R2. As shown in Figures 2 and 3, the substrate SB may include a base BS and a circuit layer CL disposed on the base BS. The base BS may include a rigid substrate or a flexible substrate. Rigid substrates include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof, while flexible substrates include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof, but are not limited thereto. The circuit layer CL may include, but is not limited to, various wires, circuits, and electronic units (such as active and / or passive components) applicable to the electronic device ED. For example, the circuit layer CL may include a driver unit, where the driver unit can be electrically connected to subsequently provided electronic units to drive the electronic units, but is not limited to this. The circuit layer CL may include, but is not limited to, a thin film transistor (TFT), i.e., a thin film transistor (TFT), which may include, but is not limited to, components and / or film layers such as a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor layer may include silicon or a metal oxide, such as a low-temperature polysilicon (LTPS) semiconductor or an amorphous silicon (a-Si) semiconductor, or a metal oxide semiconductor, such as, but not limited to, an indium gallium zinc oxide (IGZO) semiconductor. It should be noted that the circuit layer CL may include any suitable components depending on the application or type of the electronic device ED, and is not limited to the aforementioned components. In this embodiment, the substrate SB may be a complementary metal oxide semiconductor (CMOS) substrate or a thin film transistor substrate, but is not limited thereto. In the present embodiment, the working area WR on the substrate SB can be arranged in a matrix, but the present disclosure is not limited to this. The working area WR may include at least one first groove R1 and at least one second groove R2. For example, as shown in Figure 3, each working area WR may include three first grooves R1 and three second grooves R2, wherein the first grooves R1 may be arranged side by side along a direction (for example, direction X), and the second grooves R2 may also be arranged side by side along the direction, and one second groove R2 may be adjacent to one first groove R1, for example, one second groove R2 corresponds to one first groove R1, but is not limited to this. It should be noted that in other embodiments, the number and arrangement of the first grooves R1 and the second grooves R2 in the working area WR can be adjusted according to the design of the electronic device ED and are not limited to that shown in Figure 3. Specifically, the substrate SB may further include a retaining wall structure BK, which is arranged on the circuit layer CL. The retaining wall structure BK may be arranged on the side of the circuit layer CL opposite to the base BS. The retaining wall structure BK may define the first groove R1 and the second groove R2. Specifically, the retaining wall structure BK may include a plurality of openings, which may form a first recess R1 and a second recess R2. That is, the first recess R1 and the second recess R2 may be surrounded by the retaining wall structure BK. The retaining wall structure BK may be made of any suitable insulating material. According to this embodiment, in subsequent manufacturing processes, the electronic unit is disposed in the working region WR of the substrate SB, for example, in the first recess R1 of the working region WR. After providing the substrate SB, step S104 may be performed to arrange a plurality of first electronic units EU1 in at least one first recess R1 of a plurality of working areas WR by fluid transfer. Specifically, a carrier (not shown) may be provided first, wherein a plurality of first electronic units EU1 may be arranged on the carrier. The carrier here may include a wafer or any other suitable substrate that can carry the first electronic units EU1. Then, the first electronic units EU1 located on the carrier may be transferred to the substrate SB through a fluid transfer process, and the first electronic units EU1 may be arranged in the first recess R1 of the working area WR. In detail, as shown in the upper half of FIG2 , the first electronic units EU1 may be transferred from the carrier to the substrate SB through the fluid FL and enter the first recess R1, wherein the first electronic units EU1 may be electrically connected to the circuit layer CL. Specifically, the circuit layer CL may include a plurality of bonding pads BP1 exposed by the first recess R1. When the first electronic unit EU1 enters the first recess R1, the bonding pad BP2 of the first electronic unit EU1 may contact the bonding pad BP1 of the circuit layer CL, thereby electrically connecting the first electronic unit EU1 to the circuit layer CL. In this embodiment, the bonding pads BP1 and BP2 may be bonded to each other through any suitable process, such as eutectic bonding, conductive film bonding, metal bonding, conductive paste bonding, or other suitable processes. In this way, the operation of the first electronic unit EU1 can be controlled through the circuit layer CL. It should be noted that the positions of the bonding pads shown in Figure 2 and the following figures are merely exemplary. The positions of the bonding pads (or bonding elements) of the electronic unit EU (i.e., the packaged semiconductor device PU) can be referred to the structures shown in Figures 16 and 17 and the relevant content above. The positions of the bonding pads of the circuit layer CL may correspond to the positions of the bonding pads of the electronic unit EU. The first electronic unit EU1 may include an auxiliary element AE, which may be a columnar structure disposed on the side of the first electronic unit EU1 opposite the bonding pad BP2, but is not limited thereto. During the transfer process of the first electronic unit EU1, the auxiliary element AE can help orient the bonding pad BP2 of the first electronic unit EU1 downward, or toward the substrate SB, thereby bringing the bonding pad BP2 into contact with the bonding pad BP1. After the transfer process of the first electronic unit EU1 is completed, as shown in the lower half of Figure 2 and Figure 3, the first electronic unit EU1 is disposed in the first recess R1 and electrically connected to the circuit layer CL, while the second recess R2 may be vacant, or not contain the first electronic unit EU1. The auxiliary element AE can then be removed. In this embodiment, the first electronic unit EU1 can be disposed in the first recess R1 but not in the second recess R2 through a fluid transfer process. Specifically, the first and second recesses R1 and R2 can be designed with different shapes or sizes, while the shape or size of the first electronic unit EU1 matches that of the first recess R1. In some embodiments, although not shown, the second recess R2 and the first recess R1 can have the same shape, while the size of the first recess R1 can be larger than that of the second recess R2. The "sizes of the first and second recesses R1 and R2" herein can refer to, but are not limited to, the areas of the first and second recesses R1 and R2 when viewed from above the substrate SB (e.g., parallel to the direction Z) or the volumes of the first and second recesses R1 and R2. The definition of "size" below can be referred to above and will not be repeated here. Furthermore, the size of the first electronic unit EU1 can be smaller than or equal to the size of the first recess R1 but larger than the size of the second recess R2. Therefore, the first electronic unit EU1 can be disposed outside the second recess R2. In some embodiments, although not shown, the first recess R1 and the second recess R2 may have different shapes. The shape of the first electronic unit EU1 may match the shape of the first recess R1 but not the shape of the second recess R2, thereby allowing the first electronic unit EU1 to be disposed within the first recess R1 but not within the second recess R2. For example, when viewed from above the substrate SB, the first recess R1 and the first electronic unit EU1 may have circular contours, while the second recess R2 may have a rectangular contour, but this is not limiting. It should be noted that the shape or size of the first electronic unit EU1 may be determined by the shape or size of the filler material layer FM that encapsulates the semiconductor device PU. In some embodiments, the electronic device ED may include a sensing device. In this case, the first electronic unit EU1 (or the semiconductor element SU) may include any suitable sensing unit, such as, but not limited to, a photodiode. In some embodiments, the electronic device ED may include a display device. In this case, the first electronic unit EU1 (or the semiconductor element SU) may be a light-emitting unit, such as, but not limited to, a light-emitting diode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a quantum dot diode (QLED), an inorganic light-emitting diode (LED), any other suitable light-emitting element, or a combination thereof. The inorganic light-emitting diode may, for example, include, but not limited to, a sub-millimeter light-emitting diode (mini LED) or a micro light-emitting diode (micro LED). In some embodiments, the chip size of the light-emitting diode is approximately 300 microns (μm) to 10 millimeters (mm), the chip size of the sub-millimeter light-emitting diode (mini LED) is approximately 100 microns to 300 microns, and the chip size of the micro light-emitting diode (micro LED) is approximately 1 micron to 100 microns, but is not limited thereto. In some embodiments, the electronic device ED may include a self-luminous display device. In this case, the electronic device ED may include a display medium layer, wherein the display medium layer may include a light-emitting diode, but is not limited thereto. In some embodiments, the electronic device ED may include a non-self-luminous display device. In this case, the electronic device ED may include a display medium layer, wherein the display medium layer may include liquid crystal, but is not limited thereto. The following will take the electronic device ED as an example of a display device to illustrate some examples of the transfer process of the first electronic unit EU1 of this embodiment. In some embodiments, the first electronic unit EU1 may include a light-emitting unit that emits light of the same color or wavelength, such as, but not limited to, a blue light-emitting unit. In this case, the first electronic units EU1 can be transferred to the substrate SB through a fluid transfer process and disposed in the first recess R1 to form the structure shown in FIG3 . Subsequently, a light conversion layer can be disposed on the substrate SB to convert the color or wavelength of the light emitted by the first electronic unit EU1. For example, the first electronic unit EU1 can be an optical unit that emits blue light, and the light conversion layer can be used to convert a portion of the light emitted by the first electronic unit EU1 into green or red light, but the present invention is not limited to this. The light conversion layer can be disposed corresponding to the first electronic unit EU1, or in other words, can be disposed corresponding to the first recess R1 and / or the second recess R2. In some embodiments, after the light conversion layer is provided, each working region WR may include three first recesses R1. One of the three first recesses R1 corresponds to the light conversion layer that converts light to a red wavelength, another corresponds to the light conversion layer that converts light to a green wavelength, and yet another may not correspond to the light conversion layer. This allows the first electronic units EU1 in the three first recesses R1 to emit red, green, and blue light, respectively, and to mix them to produce white light. In this case, one working region WR can be considered a pixel, and the three first recesses R1 in the working region WR can each be considered a sub-pixel, but the present disclosure is not limited thereto. It should be noted that the above-mentioned configuration and type of light conversion layer are merely exemplary and are not intended to limit the present disclosure. In some embodiments, the first electronic unit EU1 may include light-emitting units that emit light of different colors or wavelengths. For example, the first electronic unit EU1 may include a blue light-emitting unit, a green light-emitting unit, and a red light-emitting unit, wherein the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit can be collectively considered as a pixel, but is not limited to this. In some embodiments, each working area WR may include three first recesses R1, each of which may be provided with a blue light-emitting unit, a green light-emitting unit, and a red light-emitting unit. In this case, the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit can be transferred to the first recesses R1 of the substrate SB through three fluid transfer processes. In some embodiments, the three first recesses R1 in each working area WR may have a first size, a second size, and a third size, respectively, wherein the first size may be larger than the second size, and the second size may be larger than the third size. During the transfer process of the first electronic unit EU1, the largest light-emitting unit among the blue, green, and red light-emitting units can be transferred first, wherein the size of this light-emitting unit can be less than or equal to the first size and greater than the second and third sizes, such that this light-emitting unit can enter the first recess R1 having the first size but cannot enter the first recess R1 having the second and third sizes. Next, the second largest light-emitting unit among the blue, green, and red light-emitting units can be transferred first, wherein the size of this light-emitting unit can be less than or equal to the second size and greater than the third size, such that this light-emitting unit can enter the first recess R1 having the second size but cannot enter the first recess R1 having the third size. Thereafter, the smallest light-emitting unit among the blue, green, and red light-emitting units can be transferred, wherein the size of this light-emitting unit can be less than or equal to the third size, such that this light-emitting unit can enter the first recess R1 having the third size. Through the above design, the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit can be set in the first groove R1 through several fluid transfer processes, and the three first grooves R1 in each working area WR can be respectively provided with a blue light-emitting unit, a green light-emitting unit, and a red light-emitting unit. It should be noted that the design of the first groove R1 is not limited to the above. In some embodiments, the three first grooves R1 in each working area WR can have different shapes, and the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit can respectively have shapes that match one, another, and another of the three first grooves R1, so that light-emitting units of different colors can be set in the first grooves R1 corresponding to their shapes. It should be noted that the above-mentioned fluid transfer process of the first electronic unit EU1 can be applied to any suitable embodiment in which the first electronic unit EU1 includes different types of electronic components. It should be noted that, depending on the design or usage of the electronic device ED, the working region WR may include any number of first grooves R1 and second grooves R2 , and the first grooves R1 and second grooves R2 may be arranged in any suitable manner. After the first electronic unit EU1 is transferred to the first groove R1 through the fluid transfer process, step S106 can be performed to identify the defective working area from a plurality of working areas. Specifically, a detection step can be performed on the first electronic unit EU1 in the first groove R1, and the defective first electronic unit or the first groove R1 without the first electronic unit EU1 can be found. When the first groove R1 in a working area WR has a defective first electronic unit or does not have the first electronic unit EU1, the working area WR can be defined as a defective working area. In other words, at least one of the first grooves R1 in the defective working area does not have any first electronic unit or has a defective first electronic unit. The detection step of the first electronic unit EU1 can be performed in any suitable manner, such as optical inspection by photoluminescence or electroluminescence, but is not limited thereto. Figure 6 is a schematic top view of the substrate and the electronic unit after the repair process of the first embodiment of the present disclosure. For example, as shown in FIG6 , after the first electronic unit EU1 is inspected, four defective first electronic units DEU1 are detected, and the working region WR where these four defective first electronic units DEU1 are located is identified and defined as a defective working region DWR. Although not shown in FIG6 , in some embodiments, when at least one of the first recesses R1 in a working region WR is vacant, the working region WR is also considered a defective working region DWR. After identifying the defective working region DWR, step S108 may be performed to place at least one repair electronic unit (REU) in at least one of the at least one second recesses in the defective working region using a laser transfer process. Specifically, as shown in FIG6 , after identifying the defective working region DWR, the repair electronic unit (REU) may be transferred into at least one second recess (R2) of the defective working region (DWR) using a laser transfer process. In this embodiment, the second recess (R2) in each working region WR may be located adjacent to a first recess (R1), but this is not limited to the embodiment. In this case, when placing the repair electronic unit (REU), the repair electronic unit (REU) may be located in the second recess (R2) adjacent to the first recess (R1) where the defective first electronic unit (DEU1) is located, but this is not limited to the embodiment. For example, as shown in FIG6 , in a defective working region DWR, if the defective first electronic unit (DEU1) is located in the middle first recess (R1), the repair electronic unit (REU) may be located in the middle second recess (R2) of the defective working region (DWR). In some embodiments, the repair electronic unit (REU) may be located in the second recess (R2) adjacent to the first recess (R1) where no first electronic unit (EU1) is located. In some embodiments, when a defective working area DWR includes a plurality of first grooves R1 in which defective first electronic units DEU1 are disposed, repair electronic units REU may be respectively disposed in second grooves R2 adjacent to the first grooves R1. It should be noted that the above description of the location of the repair electronic unit REU is merely exemplary and the present disclosure is not limited thereto. Optionally, when the defective first electronic unit DEU1 is disposed in the first groove R1, the electrical connection path between the defective first electronic unit DEU1 and the drive unit may be cut off before or after step S108. The method for cutting off the electrical connection path may include laser cutting or other suitable methods, and the present disclosure is not limited thereto. In some embodiments, the repair electronic unit REU may include a packaged semiconductor element PU, that is, the semiconductor element SU may be packaged first and then the repair process may be performed. In some embodiments, the repair electronic unit REU may include a semiconductor element SU, that is, the semiconductor element SU may not need to be packaged before the repair process. Several variations of the present embodiment of transferring and repairing the electronic unit by laser transfer will be described in detail below. Please refer to Figure 4, which is a schematic diagram of the arrangement of a repair electronic unit according to the first embodiment of the present disclosure. In some embodiments, the aforementioned step of laser-transferring the repair electronic unit REU into at least one second recess R2 of the defective operating region may first include providing a first carrier CR1, wherein the first carrier CR1 may include a plurality of second electronic units EU2. Specifically, the first carrier CR1 may include a base BS1 and a first material layer ML1 disposed on the base BS1, wherein the second electronic units EU2 may be attached to the base BS1 through the first material layer ML1. In this embodiment, the second electronic units EU2 may be disposed on the first carrier CR1 with their bonding pads BP3 facing the first material layer ML1. The material of the base BS1 may refer to, but is not limited to, the material of the base BS described above. The first material layer ML1 may include any suitable material that reacts with laser light, such as, but is not limited to, an organic material that reacts with laser light. The aforementioned “the first material layer ML1 can react with the laser light” may include the first material layer ML1 being vaporized, peeled off from the substrate BS1 , disappearing, or generating gas after being irradiated by the laser light, but is not limited thereto. Next, at least one of the plurality of second electronic units EU2 can be irradiated with a laser LB to transfer the second electronic unit EU2 from the first carrier CR1 to a second carrier CR2. The second carrier CR2 may include a base BS2 and a second material layer ML2 disposed on the base BS2. The material of the base BS2 may refer to the material of the base BS described above, but is not limited thereto. The second material layer ML2 may include any suitable material that has temporary adhesion to the second electronic unit EU2. For example, the second material layer ML2 may include silicone, acrylic, resin, photo resin, or other suitable materials. Specifically, the first carrier CR1 may be positioned on the second carrier CR2, wherein the first material layer ML1 of the first carrier CR1 and the second material layer ML2 of the second carrier CR2 may face each other. Next, a portion of the second electronic unit EU2 can be irradiated with laser LB. The portion of the first material layer ML1 corresponding to this portion of the second electronic unit EU2 can react with the laser LB, causing it to disappear, vaporize, or generate gas. This allows the portion of the second electronic unit EU2 to detach from the first carrier CR1 and fall onto the second carrier CR2. This allows the second electronic unit EU2 to be attached to the substrate BS2 through the second material layer ML2, or in other words, transferred to the second carrier CR2. In this case, the bonding pad BP3 of the second electronic unit EU2 can face upward, or be positioned away from the second material layer ML2. In this embodiment, when transferring the second electronic unit EU2 from the first carrier CR1 to the second carrier CR2, a distance T1 can be maintained between the substrate BS1 of the first carrier CR1 and the substrate BS2 of the second carrier CR2. According to this embodiment, the distance T1 can range from 1 micrometer (μm) to 200 micrometers, but is not limited thereto. Maintaining the distance T1 within this range reduces the likelihood of damage to the second electronic unit EU2 during the manufacturing process. After transferring a portion of the second electronic unit EU2 to the second carrier CR2, the portion of the second electronic unit EU2 can be transferred from the second carrier CR2 to at least one second recess R2 in the defective working region DWR of the substrate SB. Specifically, the second carrier CR2 can be positioned on the substrate SB, with the second electronic unit EU2 on the second carrier CR2 corresponding to the second recess R2 where the repair electronic unit REU is intended to be located. The second carrier CR2 can be positioned with the second material layer ML2 facing the substrate SB, such that the bonding pad BP3 of the second electronic unit EU2 faces the second recess R2. The second carrier CR2 can then be moved toward the substrate SB, thereby bringing the bonding pad BP3 of the second electronic unit EU2 into contact with the bonding pad BP4 of the circuit layer CL of the substrate SB, thereby electrically connecting the second electronic unit EU2 to the circuit layer CL. The bonding pad BP4 in the circuit layer CL can be positioned corresponding to the second recess R2 and exposed by the second recess R2. In this embodiment, bonding pads BP3 and BP4 can be bonded together using any suitable process, such as eutectic bonding, conductive film bonding, metal-metal bonding, conductive paste bonding, or other suitable processes. After bonding pads BP3 and BP4 are bonded, the second carrier CR2 can be removed, and the second electronic unit EU2 transferred to the second recess R2 can serve as the repair electronic unit REU. This completes the process of transferring the repair electronic unit REU. In this embodiment, when transferring the second electronic unit EU2 from the first carrier CR1 to the second carrier CR2, the irradiation position of the laser LB on the first carrier CR1, or in other words, the second electronic unit EU2 irradiated by the laser LB, can be determined based on the location of the first recess R1 where the defective first electronic unit DEU1 is located or the location of the first recess R1 where the first electronic unit EU1 is not located. Specifically, the locations of the first recess R1 where the defective first electronic unit DEU1 is located or is vacant in the defective working area DWR can be first determined, and the locations of the second recess R2 where the repair electronic unit REU is expected to be located can be determined accordingly. Subsequently, the portions of the second electronic unit EU2 irradiated by the laser LB can be determined based on the locations of these second recesses R2. Through this design, the second electronic unit EU2 located on the second carrier CR2 can be aligned with the locations of the second recess R2 where the repair electronic unit REU is expected to be located, thereby completing the transfer process of the repair electronic unit REU in one go. Please refer to Figure 5, which is a schematic diagram of a modified embodiment of the first embodiment of the present disclosure for setting a repair electronic unit. In some embodiments, the step of setting the repair electronic unit REU in at least one second recess R2 of the defective working area by laser transfer may first include providing a carrier CR3, wherein the carrier CR3 may include a plurality of second electronic units EU2. The carrier CR3 may include a base BS3 and a third material layer ML3 disposed on the base BS3, wherein the second electronic unit EU2 may be attached to the base BS3 through the third material layer ML3. In this embodiment, the second electronic unit EU2 may be set on the carrier CR3 in such a manner that its bonding pad BP3 is away from the third material layer ML3. The material of the base BS3 may refer to the material of the above-mentioned base BS, but is not limited thereto. The third material layer ML3 may include any suitable material that can react with laser light. The material of the third material layer ML3 may, for example, refer to the material of the above-mentioned first material layer ML1, but is not limited thereto. Next, a portion of the second electronic unit EU2 can be irradiated with a laser LB, causing the portion of the second electronic unit EU2 to be transferred from the carrier CR3 to at least one of the second recesses R2 of the defective working region DWR of the substrate SB. Specifically, the carrier CR3 can be positioned on the substrate SB, with the third material layer ML3 of the carrier CR3 facing the substrate SB, such that the bonding pad BP3 of the second electronic unit EU2 faces the second recess R2. Next, a portion of the second electronic unit EU2 corresponding to the second recess R2 where the repair electronic unit REU is intended to be located can be irradiated with a laser LB. The portion of the third material layer ML3 of the second electronic unit EU2 corresponding to the portion of the second electronic unit EU2 can react with the laser LB to disappear, vaporize, or generate gas, allowing the portion of the second electronic unit EU2 to detach from the carrier CR3 and fall into the second recess R2 where the repair electronic unit REU is intended to be located. The bonding pad BP3 of the second electronic unit EU2 can then contact the bonding pad BP4, thereby electrically connecting the second electronic unit EU2 to the circuit layer CL. In this embodiment, the bonding pad BP3 and the bonding pad BP4 can be bonded to each other through any suitable process, such as eutectic bonding, conductive film bonding, metal bonding, conductive paste bonding, or other suitable processes. The second electronic unit EU2 transferred to the second groove R2 can serve as the repair electronic unit REU. In this way, the process of transferring the repair electronic unit REU can be completed. According to this embodiment, the position of the second groove R2 where the repair electronic unit REU is expected to be set can be confirmed first, and then the part of the second electronic unit EU2 irradiated by the laser LB or the irradiation position of the laser LB on the carrier CR3 can be determined based on the position of these second grooves R2. According to this embodiment, the method for manufacturing an electronic device ED may first include transferring a first electronic unit onto a substrate SB through a fluid transfer process. This can improve the randomness of the distribution of the first electronic units or reduce the waste of the first electronic units. For example, in some embodiments, when the electronic device ED includes a display device, using a fluid transfer process to transfer the first electronic unit EU1 can reduce the uneven brightness distribution of the electronic device ED. In addition, using a fluid transfer process can increase the proportion of transferred first electronic units EU1, thereby reducing production costs. In addition, after transferring the first electronic unit EU1, the method for manufacturing the electronic device ED of this embodiment may further include transferring a repair electronic unit through a laser transfer process. Through the above process, the yield of the electronic device ED can be improved. After performing the above steps, the electronic device ED can be formed. In other words, the electronic device ED of this embodiment can be formed by sequentially performing the manufacturing method M300 and the manufacturing method M100. It should be noted that the components and / or film layers included in the electronic device ED are not limited to those described above, and other suitable components and / or film layers may be included depending on the type of electronic device ED. Furthermore, other steps may be inserted between any steps in the manufacturing method M100 of this embodiment as needed. Furthermore, any steps in the manufacturing method M100 may be reordered or deleted as needed. A method for manufacturing an electronic device according to another embodiment of the present disclosure will be described in detail below. Please refer to Figures 7 and 9 to 13. Figure 7 is a schematic flow chart of a method for manufacturing an electronic device according to a second embodiment of the present disclosure, while Figures 9 to 13 are schematic diagrams of the method for manufacturing an electronic device according to this embodiment. Specifically, Figures 9 to 13 illustrate a transfer process for encapsulating a semiconductor element PU. According to this embodiment, the method M200 for manufacturing an electronic device ED may include the following steps: S202: providing a first substrate, wherein the first substrate includes a plurality of electronic units; S204: Providing a second substrate, wherein the second substrate comprises a plurality of grooves, and a first distance exists between the plurality of grooves; S206: transferring the plurality of electronic units from the first substrate to the plurality of grooves of the second substrate by fluid transfer; S208: Providing a third substrate, wherein the third substrate includes a plurality of working areas, and a second distance exists between the plurality of working areas; and S210: Transferring at least a portion of the plurality of electronic units from at least a portion of the plurality of grooves of the second substrate to a plurality of working areas. The following will describe in detail the steps of the manufacturing method M200 of the electronic device ED. Please refer to Figure 9, which is a schematic diagram of the fluid transfer process of the second embodiment of the present disclosure. In this embodiment, the manufacturing method M200 of the electronic device ED may first include step S202, providing a first substrate SB1, wherein the first substrate SB1 includes a plurality of electronic units EU. The first substrate SB1 may include any suitable substrate that can carry the electronic units EU, and the electronic units EU may be arranged on the first substrate SB1. The electronic units EU may be formed on the first substrate SB1, but are not limited to this. The first substrate SB1 may have any suitable shape. In this embodiment, the first substrate SB1 may be circular, but is not limited to this. For example, the first substrate SB1 of this embodiment may include a wafer, but is not limited to this. In some embodiments, the first substrate SB1 may be, for example, the carrier CR' shown in Figure 15, on which a plurality of electronic units EU (i.e., packaged semiconductor elements PU) are arranged. Next, step S204 may be performed to provide a second substrate SB2, wherein the second substrate SB2 includes a plurality of grooves RS. The structural features of the second substrate SB2 may refer to the above-mentioned substrate SB, but are not limited thereto. For example, the second substrate SB2 may include a base BS' and a retaining wall structure BK1 disposed on the base BS', wherein the base BS' may include a base and a circuit layer. In some embodiments, the base BS' may include a base but not a circuit layer. The retaining wall structure BK1 may define the groove RS, that is, the groove RS may be surrounded by the retaining wall structure BK1. The second substrate SB2 may have any suitable shape. In this embodiment, the second substrate SB2 may be rectangular, but is not limited thereto. It should be noted that the above-mentioned step S202 and step S204 can be performed in any order or simultaneously. Next, step S206 can be performed to transfer the plurality of electronic units EU from the first substrate SB1 to the plurality of recesses RS of the second substrate SB2 using a fluid transfer method. Specifically, the electronic units EU on the first substrate SB1 can be transferred to the second substrate SB2 using the fluid FL, wherein the electronic units EU can enter the plurality of recesses RS of the second substrate SB2, thereby allowing the electronic units EU to be disposed in the recesses RS. In this embodiment, the electronic units EU can fill the recesses RS of the second substrate SB2, but the present invention is not limited thereto. In this embodiment, the electronic units EU can be transferred from a substrate having one shape to a substrate having another shape, for example, from a circular substrate (first substrate SB1) to a rectangular substrate (second substrate SB2), but the present invention is not limited thereto. The electronic units EU can include auxiliary elements AE, wherein the auxiliary elements AE can assist in making the bonding pads BP5 of the electronic units EU face downward, or toward the second substrate SB2, during the transfer process of the electronic units EU. After the transfer process of the electronic units EU is completed, the auxiliary elements AE can be removed, as shown in FIG. 9 . Please refer to Figure 8, which shows a schematic diagram of transferring electronic units from a first substrate using an imprint transfer method. Specifically, if the imprint transfer method is used to transfer electronic units EU from the first substrate SB1, due to the shape limitations of the imprint tool, a portion of the electronic units EU on the first substrate SB1 may not be transferred using the imprint transfer method, resulting in some electronic units EU being wasted, thereby increasing production costs. For example, Figure 8 shows a scenario in which the imprint transfer method is used to transfer electronic units EU, where the imprint tool picks up electronic units EU within a region ST at a time, completing the transfer process of the electronic units EU through multiple pick-ups. After the imprint tool picks up the electronic units EU, they are transferred to the first recess R1 of the substrate SB. Details of this process are described above and will not be repeated here. However, in this scenario, a portion of the electronic units EU on the first substrate SB1 cannot be picked up by the imprint tool. For example, the electronic units EU in region A1 in Figure 8 cannot be transferred using the imprint transfer process. As a result, the electronic units EU in region A1 may be wasted, increasing the production cost of the electronic device ED. Furthermore, in some embodiments, the electronic units EU disposed on different regions of the first substrate SB1 may be of the same type, but may have different specific characteristics. These differences in characteristics may, for example, be caused by, but are not limited to, the manufacturing process of the electronic units EU. Specifically, the electronic units EU may include electronic units EUA, electronic units EUB, and electronic units EUC, disposed in different regions of the first substrate SB1. The electronic units EUA, electronic units EUB, and electronic units EUC may be of the same type, but may have different specific characteristics. For example, in some embodiments, the electronic units EU may include light-emitting units, and the electronic units EUA, electronic units EUB, and electronic units EUC may be light-emitting units of the same color, but the wavelengths of light emitted by the electronic units EUA, electronic units EUB, and electronic units EUC may differ. In this case, using an imprint transfer method to transfer the electronic units EU may result in insufficient randomness in the distribution of the electronic units EUA, electronic units EUB, and electronic units EUC with different specific characteristics, thereby affecting the performance of the electronic device ED. For example, as shown in FIG8 , after the electronic units EU are transferred to the substrate SB using an imprint transfer method, the electronic units EUA, EUB, and EUC are not randomly arranged on the substrate SB. In this case, when the electronic device ED includes a display device, the electronic device ED may experience uneven brightness distribution, thereby affecting the display effect of the electronic device ED. Referring back to Figure 9 , according to this embodiment, since the electronic units EU on the first substrate SB1 can be transferred to the second substrate SB2 through a fluid transfer process, the electronic units EU can be moved into the recess RS substantially through the fluid FL. This reduces the waste of electronic units EU. In other words, in this embodiment, electronic units EU on substrates of any shape can be transferred to another substrate, while also reducing the waste of electronic units EU. Furthermore, after the electronic units EU are transferred into the recess RS through the fluid FL, the electronic units EU (e.g., the aforementioned electronic units EUA, EUB, and EUC) on different areas of the first substrate SB1 can be randomly arranged on the second substrate SB2, or in other words, randomly positioned within the recess RS. Consequently, when the electronic units EU are subsequently transferred to the third substrate SB3, the electronic units EUA, EUB, and EUC can be randomly distributed across the third substrate SB3 (as shown in Figure 13 ), thereby reducing the impact of the differences in the characteristics of the electronic units EUA, EUB, and EUC on the performance of the electronic device ED. For example, when the electronic device ED includes a display device, the above design can improve the brightness uniformity of the electronic device ED. Please refer to Figure 18, which is a schematic diagram of a fluid transfer process of a variant embodiment of the second embodiment of the present disclosure. In this variant embodiment, the shape of the retaining wall structure BK1 can be determined according to the shape of the electronic unit EU. Specifically, as described above, the electronic unit EU may include a packaged semiconductor element PU, wherein the third surface SR3 of the filling material layer FM (not shown) of the packaged semiconductor element PU and the side wall SW1 may have an angle θ1. In this case, the retaining wall structure BK1 may have a surface SR5 away from the second substrate SB2 and a side wall SW2, and in the cross-sectional view of the retaining wall structure BK1, the surface SR5 of the retaining wall structure BK1 and the side wall SW2 may have an angle θ2, wherein the angle θ2 may be substantially the same as the angle θ1, but is not limited thereto. The range of the angle θ2 may refer to the range of the above-mentioned angle θ1. The shape design of the retaining wall structure BK1 can reduce the possibility of the electronic unit EU flipping during the transfer process, thereby improving the process yield. After the electronic unit EU is moved into the groove RS of the second substrate SB2, step S208 can be performed to provide a third substrate SB3, wherein the third substrate SB3 includes a plurality of working areas WR. The structural features of the third substrate SB3 can refer to the structural description of the substrate SB described above. For example, as shown in Figures 10 to 12, the third substrate SB3 may include a base BS4, a circuit layer CL1 disposed on the base BS4, and a retaining wall structure BK2 disposed on the circuit layer CL1, wherein the retaining wall structure BK2 may define at least one first groove R1 and at least one second groove R2 (as shown in Figure 13). The structural features of the base BS4, the circuit layer CL1, and the retaining wall structure BK2 can refer to the aforementioned base BS, circuit layer CL, and retaining wall structure BK, respectively. As shown in Figure 13, the third substrate SB3 may include a plurality of working areas WR, wherein the working areas WR may be arranged in a matrix, but is not limited thereto. Each working area WR of the third substrate SB3 may include at least one first groove R1 and at least one second groove R2, but is not limited thereto. Next, step S210 may be performed to transfer a portion of the plurality of electronic units EU from a portion of the plurality of recesses RS of the second substrate SB2 to the plurality of working areas WR. Specifically, a portion of the electronic units EU in the recesses RS of the second substrate SB2 may be transferred to the first recesses R1 in the working area WR of the third substrate SB3, such that the electronic units EU are disposed in the first recesses R1. Several variations of the method for transferring the electronic units EU from the second substrate SB2 to the third substrate SB3 according to this embodiment will be described in detail below. Please refer to Figure 10, which is a schematic diagram of transferring an electronic unit from a second substrate to a third substrate according to a second embodiment of the present disclosure. In some embodiments, the method of transferring the electronic unit EU from the second substrate SB2 to the third substrate SB3 may first include providing a carrier CR, wherein the carrier CR may include a base BS5 and a fourth material layer ML4 disposed on the base BS5. The material of the base BS5 can refer to, but is not limited to, the material of the base BS described above. The fourth material layer ML4 may include any suitable material that reacts with laser light. The material of the fourth material layer ML4 can refer to, but is not limited to, the material of the first material layer ML1 described above. Next, the plurality of electronic units EU can be transferred from the recess RS to the carrier CR. Specifically, the carrier CR can be moved toward the second substrate SB2, and the fourth material layer ML4 of the carrier CR can be brought into contact with the electronic units EU disposed in the recess RS (e.g., contacting the surface SR of the electronic units EU opposite the bonding pads BP5). In this manner, the electronic units EU can be attached to the substrate BS5 through the fourth material layer ML4, thereby transferring the electronic units EU in the recess RS to the carrier CR. In this case, the bonding pads BP5 of the electronic units EU can be on the side of the electronic units EU opposite the fourth material layer ML4. Next, a laser LB can be used to irradiate a portion of the plurality of electronic units EU, causing the portion of the electronic units EU to be transferred from the carrier CR to the third substrate SB3, or in other words, to the working region WR of the third substrate SB3. Specifically, the laser LB can be used to irradiate a portion of the electronic units EU, where a portion of the fourth material layer ML4 corresponding to the portion of the electronic units EU can react with the laser LB and disappear, vaporize, or generate gas, allowing the portion of the electronic units EU to detach from the carrier CR. In this embodiment, the portion of the electronic units EU irradiated by the laser LB can correspond to a recess (i.e., the first recess R1) in the third substrate SB3, allowing the portion of the electronic units EU to enter the first recess R1 of the third substrate SB3 after detaching from the carrier CR, thereby being disposed in the first recess R1 in the working region WR of the third substrate SB3. In this case, the bonding pad BP5 of the electronic unit EU facing the third substrate SB3 can contact the bonding pad BP6 of the circuit layer CL1 of the third substrate SB3, which is exposed by the first recess R1, thereby electrically connecting the electronic units EU to the circuit layer CL1. After the electronic units EU are transferred to the third substrate SB3 , an electronic device ED can be formed. It should be noted that the electronic device ED may also include other suitable components and / or film layers and is not limited to that shown in FIG. 10 . Please refer to Figure 11, which is a schematic diagram of transferring an electronic unit from a second substrate to a third substrate according to a variation of the second embodiment of the present disclosure. In some embodiments, the method of transferring an electronic unit EU from the second substrate SB2 to the third substrate SB3 may first include picking up a portion of the electronic unit EU from a portion of the recess RS. For example, a transfer head TH may be used to pick up a portion of the electronic unit EU from a portion of the recess RS of the second substrate SB2. Specifically, the transfer head TH may include a plurality of protrusion structures PP, wherein the protrusion structures PP may correspond to the electronic unit EU to be picked up. Then, the transfer head TH may be moved toward the second substrate SB2, and each protrusion structure PP may contact the surface SR of the electronic unit EU to which it corresponds, thereby picking up the corresponding electronic unit EU. The spacing of the protrusion structures PP may be determined according to the spacing of the first recess R1 of the third substrate SB3, but is not limited thereto. In addition, the structural design of the transfer head TH and the method of picking up the electronic unit EU shown in Figure 11 are merely exemplary, and the present disclosure is not limited thereto. Next, a portion of the electronic unit EU picked up by the transfer head TH can be transferred to the third substrate SB3, or in other words, transferred to the working area WR of the third substrate SB3. Specifically, the protruding structure PP of the transfer head TH can first be made to correspond to the first groove R1 of the third substrate SB3, and then the transfer head TH can be moved toward the third substrate SB3, so that the electronic unit EU enters the first groove R1, and then the electronic unit EU is set in the first groove R1 in the working area WR of the third substrate SB3. In this case, the bonding pad BP5 of the electronic unit EU facing the third substrate SB3 can contact the bonding pad BP6 of the circuit layer CL1 of the third substrate SB3, thereby electrically connecting the electronic unit EU to the circuit layer CL1. After the electronic unit EL is transferred to the third substrate SB3, an electronic device ED can be formed. It should be noted that the electronic device ED may also include other suitable components and / or film layers, and is not limited to that shown in Figure 11. It should be noted that after the electronic unit EU is transferred to the working area WR of the third substrate SB3, the electronic unit EU can be selectively inspected and / or repaired. For details, please refer to the first embodiment above and will not be described in detail. Please refer to Figures 10 to 12. Figure 12 is a schematic cross-sectional view of an electronic device according to a second embodiment of the present disclosure. Specifically, the electronic device ED shown in Figures 10 and 11 may be a schematic cross-sectional view of the electronic device ED shown in Figure 13 taken along line A-A', while the electronic device ED shown in Figure 12 may be a schematic cross-sectional view of the electronic device ED shown in Figure 13 taken along line BB'. According to this embodiment, as described above, when transferring the electronic units EU from the second substrate SB2 to the third substrate SB3 to form the electronic device ED, only a portion of the electronic units EU on the second substrate SB2 may be transferred, but this is not a limitation. In other words, the electronic units EU in the electronic device ED may be a portion of the electronic units EU on the second substrate SB2. In this case, the electronic units EU on the second substrate SB2 can be used in multiple transfer processes, or a single second substrate SB2 can be used to form multiple electronic devices ED. Specifically, the electronic units EU on the first substrate SB1 can be transferred to the second substrate SB2 via a fluid transfer process and then arranged on the second substrate SB2. Next, a portion of the electronic units EU on the second substrate SB2 can be transferred (for example, through a laser transfer process or an imprint transfer process, but not limited thereto) to the working area WR of the third substrate SB3. In some embodiments, the transferred portions of the electronic units EU in the second substrate SB2 may be spaced apart, where this spacing may be determined by, but not limited to, the spacing of the first recesses R1 of the third substrate SB3. In this case, the spacing between the recesses RS of the second substrate SB2 may be smaller than the spacing between the working areas WR of the third substrate SB3. For example, as shown in Figures 10 and 12, the recesses RS of the second substrate SB2 may be spaced apart by a first spacing P1, while the working areas WR of the third substrate SB3 may be spaced apart by a second spacing P2, where the second spacing P2 is greater than the first spacing P1. In a cross-sectional view of the second substrate SB2, the first spacing P1 can be defined as the distance between the edges of two adjacent recesses RS on the same side. For example, the first spacing P1 can be the distance between the left edges of two adjacent recesses RS, but not limited thereto. In a cross-sectional view of the third substrate SB3, the second spacing P2 can be defined as the distance between the edges of two adjacent working areas WR on the same side. For example, the second pitch P2 may be the distance between the left edges of two adjacent working areas WR, but is not limited thereto. In this embodiment, the first pitch P1 may be the distance between two adjacent grooves RS in the direction in which the grooves RS are arranged, while the second pitch P2 may be the distance between two adjacent working areas WR in the same direction. For example, the first pitch P1 may be the distance between two adjacent grooves RS in the direction X, while the second pitch P2 may be the distance between two adjacent working areas WR in the direction X, but is not limited thereto.In some embodiments, the first pitch P1 may be the distance between two adjacent grooves RS in direction Y, and the second pitch P2 may be the distance between two adjacent working areas WR in direction Y. In some embodiments, the second pitch P2 may be an integer multiple of the first pitch P1 (i.e., P2 = n*P1, where n is a positive integer). In some embodiments, as shown in FIG12 , each working area WR may include a plurality of sub-working areas SWR, wherein one sub-working area SWR may, for example, include a first groove R1 and / or a second groove R2 adjacent to the first groove R1. When the electronic device ED includes a display device, one sub-working area SWR may be considered a sub-pixel, but is not limited thereto. In this case, a third spacing P3 may exist between the sub-working areas SWR in one working area WR. In a cross-sectional view of the third substrate SB3, the third spacing P3 may be defined as the distance between the same side edges of two adjacent sub-working areas SWR. For example, the third spacing P3 may be the distance between the left edges of two adjacent sub-working areas SWR, but is not limited thereto. The third spacing P3 may be defined in the same direction as the first spacing P1 and the second spacing P2. For example, the first spacing P1 may be the spacing between two adjacent grooves RS in the direction X, and the third spacing P3 may be the spacing between two adjacent sub-working areas SWR in the direction X. According to this embodiment, the third spacing P3 is greater than the first spacing P1. Furthermore, in some embodiments, the third pitch P3 may be an integer multiple of the first pitch P1 (ie, P3=n*P1, where n is a positive integer). It should be noted that the electronic unit EU of the electronic device ED of this embodiment can be transferred to the third substrate SB3 through one or more transfer processes, and the present disclosure is not limited to this. In some embodiments, the electronic unit EU can be transferred to the third substrate SB3 through a single transfer process. In some embodiments, the electronic unit EU may include different types of electronic components (for example, the light-emitting units of different colors mentioned above, but not limited to this), and the electronic unit EU can be transferred to the third substrate SB3 through multiple transfer processes, so that different types of electronic components can be transferred to their corresponding first grooves R1 respectively. The design of the above-mentioned first spacing P1, second spacing P2 and third spacing P3 can help to use a single second substrate SB2 to perform multiple transfer processes under the transfer process of various electronic units EU to form a plurality of electronic devices ED, thereby simplifying the process of the electronic device ED or reducing the production cost of the electronic device ED. Please refer to Figure 19, which is a schematic diagram of applying the electronic device disclosed herein to a vehicle display. In detail, as shown in Figure 19, the electronic device ED can be used in a vehicle VH as a vehicle display. Specifically, the light emitted by the electronic device ED can be reflected by the windshield WH and enter the eyes of the user UR, and then be observed by the user. The electronic device ED shown in Figure 19 can be the electronic device ED shown in Figure 6 or the electronic device ED shown in Figure 13. According to this embodiment, since the electronic unit EU (not shown) in the electronic device ED includes a vertically embedded flip-chip structure or a vertically embedded chip structure light-emitting diode element, which has the advantages of high brightness, low power consumption, high contrast, and wide viewing angle, when the electronic device ED is used as a vehicle display, the driver can understand the information displayed by the electronic device ED through the windshield WH more quickly, thereby reducing the possibility of driving risks caused by the driver's line of sight being diverted. In summary, the present disclosure provides a method for manufacturing an electronic device, which includes using a fluid transfer method to transfer an electronic unit and using a laser transfer method to perform a repair process for the electronic unit. Therefore, the waste of electronic units can be reduced, or the yield of the electronic device can be improved. In addition, the present disclosure also provides a method for manufacturing an electronic device, which includes using a fluid transfer method to transfer the electronic unit to a substrate, and then transferring a portion of the electronic unit on the substrate to another substrate. Therefore, the waste of electronic units can be reduced, or the process of manufacturing the electronic device can be simplified or the production cost of the electronic device can be reduced. Furthermore, the method for manufacturing an electronic device of the present disclosure also includes performing a packaging process on the semiconductor element before the fluid transfer process to form a packaged semiconductor element, thereby facilitating the bonding of the packaged semiconductor element to the target substrate during the fluid transfer process when the semiconductor element includes a vertical embedded flip-chip structure or a vertical embedded chip structure. The above description is only an embodiment of the present disclosure, and all equivalent changes and modifications made according to the scope of the patent application of the present disclosure should fall within the scope of the present disclosure. AE: auxiliary element BK, BK1, BK2: barrier structure BP2, BP1, BP3, BP4, BP5, BP6: bonding pad BS, BS1, BS2, BS3, BS4, BS5, BS': substrate CD: conductive layer CL, CL1: circuit layer CR1: first carrier CR2: second carrier CR3, CR, CR': carrier DEU1: defective first electronic unit DWR: defective working area E1: first electrode E2: second electrode ED: electronic device EU, EUA, EUB, EUC: electronic unit EU1: first electronic unit EU2: second electronic unit F1: first side F2: second side FL: fluid FM: filling material layer LB: laser LEL: light-emitting layer M100, M200, M300: manufacturing method ML, ML': material layer ML1: first material layer ML2: second material layer ML3: third material layer ML4: fourth material layer P1: first pitch P2: second pitch P3: Third pitch PP: protruding structure PU: packaged semiconductor element R1: first groove R2: second groove REU: repair electronic unit RS: groove S1: first semiconductor layer S2: second semiconductor layer S102, S104, S106, S108, S202, S204, S206, S208, S210, S300, S302, S304, S306, S308: steps SB, GB: substrate SB1: first substrate SB2: second substrate Board SB3: Third substrate SR, SR5: Surface SR1: First surface SR2: Second surface SR3: Third surface SR4: Fourth surface ST, A1: Area SU: Semiconductor element SW, SW1, SW2: Sidewall SWR: Sub-working area T1: Distance TH: Transfer head TH1: Thickness UR: User VH: Vehicle W1: Width WH: Windshield WR: Working area X, Y, Z: Directions A-A', BB': Tangent θ1, θ2: Angle Figure 1 is a schematic flow chart of a method for manufacturing an electronic device according to a first embodiment of the present disclosure. Figure 2 is a schematic flow chart of a fluid transfer process according to the first embodiment of the present disclosure. Figure 3 is a schematic top view of a substrate and an electronic unit according to the first embodiment of the present disclosure. Figure 4 is a schematic flow chart of the arrangement and repair of an electronic unit according to the first embodiment of the present disclosure. Figure 5 is a schematic flow chart of an arrangement and repair of an electronic unit according to a variation of the first embodiment of the present disclosure. Figure 6 is a schematic top view of a substrate and an electronic unit after the repair process according to the first embodiment of the present disclosure. Figure 7 is a schematic flow chart of a method for manufacturing an electronic device according to a second embodiment of the present disclosure. Figure 8 is a schematic flow chart of transferring an electronic unit from a first substrate using an imprint transfer method. Figure 9 is a schematic flow chart of a fluid transfer process according to the second embodiment of the present disclosure. Figure 10 is a schematic flow chart of transferring an electronic unit from a second substrate to a third substrate according to the second embodiment of the present disclosure. Figure 11 is a schematic flow chart of transferring an electronic unit from a second substrate to a third substrate according to a variation of the second embodiment of the present disclosure. Figure 12 is a schematic cross-sectional view of an electronic device according to the second embodiment of the present disclosure. Figure 13 is a schematic top view of a substrate and an electronic unit according to the second embodiment of the present disclosure. Figure 14 is a schematic flow chart of a method for manufacturing an electronic unit according to an embodiment of the present disclosure. Figure 15 is a schematic diagram of the manufacturing process of an electronic unit of an electronic device according to one embodiment of the present disclosure. Figure 16 is a schematic cross-sectional view of an electronic unit of an electronic device according to one embodiment of the present disclosure. Figure 17 is a schematic cross-sectional view of an electronic unit of an electronic device according to another embodiment of the present disclosure. Figure 18 is a schematic diagram of the fluid transfer process according to a variation of the second embodiment of the present disclosure. Figure 19 is a schematic diagram of the application of the electronic device according to the present disclosure to an automotive display. M100: Manufacturing Method S102, S104, S106, S108: Steps

Claims

1. A method for manufacturing an electronic device, comprising: Provide a plurality of semiconductor elements; A packaging process is performed on the plurality of semiconductor elements to form a plurality of packaged semiconductor elements, the packaging process comprising: disposing a plurality of filler material layers on the sidewall of each of the plurality of semiconductor elements; A substrate is provided, the substrate including a plurality of working regions, each of the plurality of working regions including at least one first groove and at least one second groove; a plurality of packaged semiconductor elements are disposed in the at least one first groove of the plurality of working regions by fluid transfer; a defective working region is identified from the plurality of working regions, wherein at least one of the at least one first groove in the defective working region is not provided with any packaged semiconductor element or is provided with a defective packaged semiconductor element; and at least one repair packaged semiconductor element is disposed in at least one of the at least one second groove of the defective working region.

2. The manufacturing method according to claim 1, wherein, The packaging process further includes: disposing a first electrode on a first surface of each of the plurality of semiconductor elements; disposing a conductive layer on a sidewall of each of the plurality of filling material layers; and disposing a second electrode on a second surface of each of the plurality of semiconductor elements, wherein the second surface is opposite to the first surface.

3. The manufacturing method according to claim 2, wherein, In each of the plurality of packaged semiconductor elements, the conductive layer contacts the second electrode.

4. The manufacturing method according to claim 2, wherein, Each of the plurality of filler material layers includes a third surface and a fourth surface opposite to the third surface, the third surface being adjacent to the first surface, the fourth surface being adjacent to the second surface, and the second electrode extending on the fourth surface.

5. The manufacturing method according to claim 4, wherein, The conductive layer extends on the third surface.

6. The manufacturing method according to claim 1, wherein, In a top view of the electronic device, the plurality of packaged semiconductor elements have a circular outline.

7. A method for manufacturing an electronic device, comprising the following steps: Provide a plurality of semiconductor elements; A packaging process is performed on a plurality of semiconductor elements to form a plurality of packaged semiconductor elements, the packaging process comprising: disposing a plurality of filler material layers on the sidewalls of each of the plurality of semiconductor elements; providing a first substrate, the first substrate including a plurality of recesses; disposing the plurality of packaged semiconductor elements in the plurality of recesses of the first substrate by fluid transfer; providing a second substrate, the second substrate including a plurality of working regions, each of the plurality of working regions including at least one first recess and at least one second recess; transferring at least a portion of the plurality of packaged semiconductor elements from at least a portion of the plurality of recesses of the first substrate to at least one first recess of the plurality of working regions; identifying a defective working region from the plurality of working regions, wherein at least one of the at least one first recess in the defective working region is either without any packaged semiconductor element or has a defective packaged semiconductor element; and disposing at least one repair packaged semiconductor element in at least one of the at least one second recess of the defective working region.

8. The manufacturing method according to claim 7, wherein, The plurality of grooves are spaced apart by a first distance, and the plurality of working areas are spaced apart by a second distance, wherein the second distance is greater than the first distance.

9. The manufacturing method according to claim 7, wherein, The packaging process further includes: disposing a first electrode on a first surface of each of the plurality of semiconductor elements; disposing a conductive layer on a sidewall of each of the plurality of filling material layers; and disposing a second electrode on a second surface of each of the plurality of semiconductor elements, wherein the second surface is opposite to the first surface.

10. The manufacturing method according to claim 9, wherein, In each of the plurality of packaged semiconductor elements, the conductive layer contacts the second electrode.

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