Semiconductor devices

Abstract

This invention provides a semiconductor device with high reliability. The semiconductor device of this invention includes: an oxide semiconductor layer comprising an impurity region containing impurity elements and having a polycrystalline structure; a gate electrode located on the oxide semiconductor layer; an insulating layer located between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole at least penetrating the insulating layer and having a depth greater than the depth of the first contact hole; and a connecting wire electrically connecting the impurity region to the layer exposed through the second contact hole via the first contact hole and the second contact hole; the connecting wire includes a first conductive layer and a second conductive layer above the first conductive layer, wherein the portion of the first conductive layer exposed from the second conductive layer contains impurity elements.

Description

Semiconductor device One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. In recent years, a semiconductor device including an oxide semiconductor film has been developed in place of a silicon semiconductor film using amorphous silicon, low-temperature polycrystalline silicon, single-crystalline silicon, etc. (for example, refer to Patent Documents 1 to 6). The semiconductor device including the oxide semiconductor film has a simple structure like the semiconductor device including the amorphous silicon film and can be formed by a low-temperature process. Further, it is known that the semiconductor device including the oxide semiconductor film has a higher field-effect mobility than the semiconductor device including the amorphous silicon film. [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Application Laid-Open No. 2021-153196 [Patent Document 4] Japanese Patent Application Laid-Open No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Japanese Patent Application Laid-Open No. 2021-108405 [Problems to be Solved by the Invention] A semiconductor device not only needs to have a relatively high field-effect mobility but also needs to have high reliability. One object of one embodiment of the present invention is to provide a semiconductor device having high reliability. [Technical Means for Solving the Problems] A semiconductor device according to one embodiment of the present invention includes: an oxide semiconductor layer including an impurity region containing an impurity element and having a polycrystalline structure; a gate electrode located above the oxide semiconductor layer; an insulating layer located between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole penetrating at least the insulating layer and having a depth greater than that of the first contact hole; and a connection wiring electrically connecting the impurity region to a layer exposed through the second contact hole via the first contact hole and the second contact hole; the connection wiring includes a first conductive layer and a second conductive layer above the first conductive layer, and a portion of the first conductive layer exposed from the second conductive layer contains an impurity element. Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. While ensuring the gist of the invention, configurations that can be easily conceived by those skilled in the art by appropriately changing the configurations of the embodiments are of course included in the scope of the present invention. To make the description clearer, in the drawings, the widths, film thicknesses, shapes, etc. of the constituent elements may sometimes be schematically shown compared to the actual aspect. However, the shapes shown are merely examples and do not limit the interpretation of the present invention. In this specification and the drawings, the same reference numerals are given to the constituent elements that are the same as those described above with respect to the already shown drawings, and the detailed description may sometimes be appropriately omitted. In this specification and the like, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for convenience of explanation, the terms "above" or "below" are used for description, but the vertical relationship between the substrate and the oxide semiconductor layer may also be arranged in the opposite orientation to that shown in the drawings. Also, the expression "oxide semiconductor layer on the substrate" only explains the vertical relationship between the substrate and the oxide semiconductor layer, and other members may also be arranged between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure having a plurality of stacked layers. In the case of expressing "a pixel electrode above the semiconductor device", it may also be a positional relationship where the semiconductor device and the pixel electrode do not overlap in a plan view. On the other hand, in the case of expressing "a pixel electrode directly above the semiconductor device", it means a positional relationship where the semiconductor device and the pixel electrode overlap in a plan view. Furthermore, a plan view means observing from a direction perpendicular to the surface of the substrate. In this specification and the like, with respect to the expressions "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C", if not particularly specified, the case where α includes a plurality of combinations of A to C is not excluded. Furthermore, these expressions do not exclude the case where α includes other constituent elements. In this specification and the like, a "semiconductor device" refers to all devices that can exhibit functions by utilizing semiconductor characteristics. Transistors and semiconductor circuits are included in one form of semiconductor devices. The semiconductor devices in the embodiments shown below may, for example, also be transistors used in display devices, integrated circuits (ICs) such as microprocessors (MPUs), or memory circuits. In the present specification and the like, the "display device" refers to a structure that displays an image using a photoelectric layer. For example, the term "display device" sometimes refers to a display panel including a photoelectric layer, or sometimes also refers to a structure formed by mounting other optical members (such as a polarizing member, a backlight, a touch panel, etc.) on a display unit. As long as there is no technical contradiction, the "photoelectric layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. In the present specification and the like, the terms "film" and "layer" may be interchangeable depending on the situation. Furthermore, as long as there is no technical contradiction, the following embodiments can be combined with each other. <First Embodiment> Referring to FIGS. 1 to 7, a semiconductor device 1 according to an embodiment of the present invention will be described. [1. Configuration of Semiconductor Device 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device 1 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 1 includes a first transistor TR1 and a second transistor TR2 on a substrate 10. Further, the semiconductor device 1 includes insulating layers 11 to 14 that are commonly provided for the first transistor TR1 and the second transistor TR2. The first transistor TR1 includes an insulating layer 11, an insulating layer 12, a light-shielding layer LS, an insulating layer 13, an oxide semiconductor layer OS, an insulating layer 14, and a gate electrode GE1. The insulating layer 11 is provided on the substrate 10. The insulating layer 12 is provided on the insulating layer 11. The light-shielding layer LS is provided on the insulating layer 12. The insulating layer 13 covers the upper surface and end surfaces of the light-shielding layer LS and is provided on the insulating layer 12. The oxide semiconductor layer OS is provided on the insulating layer 13. The insulating layer 14 covers the upper surface and end surfaces of the oxide semiconductor layer OS and is provided on the insulating layer 13. The gate electrode GE1 overlaps with the oxide semiconductor layer OS and is provided on the insulating layer 14. In the first transistor TR1, the insulating layer 11 and the insulating layer 12 function as a base insulating layer, the insulating layer 13 functions as an interlayer insulating layer, and the insulating layer 14 functions as a gate insulating layer. The gate electrode GE1 is an electrode electrically connected to a gate line. Furthermore, the detailed configuration of the oxide semiconductor layer OS will be described below. The second transistor TR2 includes an insulating layer 11, a silicon semiconductor layer SS, an insulating layer 12, a gate electrode GE2, an insulating layer 13, and an insulating layer 14. The insulating layer 11 is disposed on the substrate 10. The silicon semiconductor layer SS is disposed on the insulating layer 11. The insulating layer 12 covers the upper surface and the end surface of the silicon semiconductor layer SS and is disposed on the insulating layer 11. The gate electrode GE2 overlaps with the silicon semiconductor layer SS and is disposed on the insulating layer 12. The insulating layer 13 covers the upper surface and the end surface of the gate electrode GE2 and is disposed on the insulating layer 12. The insulating layer 14 is disposed on the insulating layer 13. In the second transistor TR2, the insulating layer 11 functions as a base insulating layer, the insulating layer 12 functions as a gate insulating layer, and the insulating layer 13 and the insulating layer 14 function as interlayer insulating layers. The gate electrode GE2 is an electrode electrically connected to the gate line. As the silicon semiconductor layer SS, for example, polysilicon semiconductor can be used, but the material of the silicon semiconductor layer SS is not limited thereto. As the silicon semiconductor layer SS, other silicon-based semiconductors can also be used. The first transistor TR1 and the second transistor TR2 are electrically connected via a connection wiring CN. Specifically, the connection wiring CN directly electrically connects the oxide semiconductor layer OS of the first transistor TR1 and the second transistor TR2. The connection wiring CN functions as one of the source electrode and the drain electrode of the first transistor TR1. Also, the connection wiring CN also functions as one of the source electrode and the drain electrode of the second transistor TR2. Furthermore, in FIG. 1, the illustration of the other of the source electrode and the drain electrode of the second transistor TR2 is omitted. The substrate 10 can support the respective layers constituting the semiconductor device 1. For example, as the substrate 10, a rigid substrate having light transmissivity such as a glass substrate, a quartz substrate, or a sapphire substrate can be used. Also, as the substrate 10, a rigid substrate having no light transmissivity such as a silicon substrate can be used. Also, as the substrate 10, a flexible substrate having light transmissivity such as a polyimide resin substrate, an acrylic resin substrate, a silicone resin substrate, or a fluororesin substrate can be used. In order to improve the heat resistance of the substrate 10, impurities can also be introduced into the flexible substrate. The light-shielding layer LS can reflect or absorb the light incident from the substrate 10 side. In other words, the light-shielding layer LS can shield the light incident on the oxide semiconductor layer OS. The light-shielding layer LS is formed of the same layer as the gate electrode GE2. That is, the light-shielding layer LS is formed of the same material as the gate electrode GE2. For example, as the light-shielding layer LS and the gate electrode GE2, metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof can be used. The light-shielding layer LS can have a single-layer structure or a laminated structure. As each of the insulating layers 11 to 14, for example, silicon oxide (SiO x) Silicon oxynitride (SiO x N y ) Aluminum oxide (AlO x ) or aluminum oxynitride (AlO x N y ) and other oxides such as silicon nitride (SiN x ) Silicon oxynitride (SiN x O y ) Aluminum nitride (AlN x ) or aluminum oxynitride (AlN x O y ) and other nitrides. Each of the insulating layers 11 to 14 may have a single-layer structure or a laminated structure. Here, silicon oxynitride (SiO x N y ) and aluminum oxynitride (AlO x N y ) are oxides containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). Also, silicon oxynitride (SiN x O y ) and aluminum oxynitride (AlN x O y ) are nitrides containing oxygen in a ratio less than that of nitrogen (x > y). Furthermore, for the sake of convenience in explanation, sometimes silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) are simply referred to as "silicon oxide", and silicon nitride (SiN x ) and silicon oxynitride (SiN x O y) Abbreviated as "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxynitride (AlO x N y ) are sometimes abbreviated as "aluminum oxide", and aluminum nitride (AlN x ) and aluminum oxynitride (AlN x O y ) are abbreviated as "aluminum nitride". The insulating layers 13 and 14 in contact with the oxide semiconductor layer OS preferably contain oxides. If the oxide semiconductor layer OS is in contact with an oxide, oxygen can be supplied to the oxide semiconductor layer OS from the oxide by heat treatment. For example, the insulating layer 13 may also have a laminated structure including silicon nitride and silicon oxide on the silicon nitride. Also, the insulating layer 14 may have a single-layer structure of silicon oxide. The gate electrode GE1 is formed of the same layer as the connection wiring CN. That is, the gate electrode GE1 is formed of the same material as the connection wiring CN. Each of the gate electrode GE1 and the connection wiring CN has a laminated structure. Specifically, the gate electrode GE1 has a laminated structure including a first conductive layer L1 and a second conductive layer L2 on the first conductive layer L1. Also, the connection wiring CN has a laminated structure including a third conductive layer L3 and a fourth conductive layer LS4 on the third conductive layer L3. The first conductive layer L1 is formed of the same layer as the third conductive layer L3, and the second conductive layer L2 is formed of the same layer as the fourth conductive layer L4. In the channel length direction of the first transistor TR1 (the direction from the source electrode to the drain electrode or from the drain electrode to the source electrode of the first transistor TR1), the width of the first conductive layer L1 is greater than the width of the second conductive layer L2. Therefore, in a plan view, the first conductive layer L1 includes a portion exposed from the second conductive layer L2. Also, the film thickness t1 of the first conductive layer L1 is less than the film thickness t2 of the second conductive layer L2 (t1 < t2). The film thickness t2 of the second conductive layer L2 is 3 times or more the film thickness t1 of the first conductive layer L1. For example, the film thickness t1 is about 30 nm, and the film thickness t2 is about 100 nm. The first conductive layer L1 is formed of a material different from that of the second conductive layer L2. When selecting the materials for the first conductive layer L1 and the second conductive layer L2, it is preferable that the density of the material forming the first conductive layer L1 is less than the density of the material forming the second conductive layer L2. As the first conductive layer L1 and the second conductive layer L2, the same material as that of the gate electrode GE2 can be used. For example, the first conductive layer L1 contains at least one of titanium (Ti) and aluminum (Al), and the second conductive layer L2 contains at least one of molybdenum (Mo) and tungsten (W). However, since the first conductive layer L1 is in contact with the oxide semiconductor layer OS, the first conductive layer L1 preferably contains a material that is not easily oxidized. For example, the first conductive layer L1 preferably has a single-layer structure of titanium, or a laminated structure containing titanium and aluminum on titanium. A first contact hole CH1 is provided in the first transistor TR1, and the first contact hole CH1 penetrates the insulating layer 14 to expose a part of the oxide semiconductor layer OS. Further, a second contact hole CH2 is provided in the second transistor TR2, and the second contact hole CH2 penetrates the insulating layers 12 to 14 to expose a part of the silicon semiconductor layer SS. The depth of the second contact hole CH2 is greater than the depth of the first contact hole CH1. The connection wiring CN electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS via the first contact hole CH1 and the second contact hole CH2. As described above, the connection wiring CN includes a third conductive layer L3 formed of the same layer as the first conductive layer L1 and a fourth conductive layer LS4 formed of the same layer as the second conductive layer L2. Therefore, the film thickness t3 of the third conductive layer L3 is less than the film thickness t4 of the fourth conductive layer L4 (t3 < t4). The film thickness t4 of the fourth conductive layer L4 is 3 times or more the film thickness t3 of the third conductive layer L3. For example, the film thickness t3 is about 30 nm, and the film thickness t4 is about 100 nm. The third conductive layer L3 extends from the first contact hole CH1 to the second contact hole CH2 so as to cover the first contact hole CH1 and the second contact hole CH2. The third conductive layer L3 is in contact with the oxide semiconductor layer OS via the first contact hole CH1 and is in contact with the silicon semiconductor layer SS via the second contact hole CH2. The fourth conductive layer L4 overlaps with the second contact hole CH2 but does not overlap with the first contact hole CH1. That is, in the connection wiring CN, a part of the third conductive layer L3 is exposed from the fourth conductive layer L4. The part of the third conductive layer exposed from the fourth conductive layer L4 is in contact with the oxide semiconductor layer OS via the first contact hole CH1. Here, with reference to FIG. 2, the electrical connection between the connection wiring CN and the oxide semiconductor layer will be described. FIG. 2 is a schematic enlarged cross-sectional view showing the configuration of the semiconductor device 1 according to an embodiment of the present invention. Specifically, FIG. 2 is a cross-sectional view obtained by enlarging the region A in FIG. 1. The oxide semiconductor layer OS includes a channel region OS_1 and an impurity region OS_2 adjacent to the channel region. The channel region OS_1 has the properties of a semiconductor. Therefore, when a voltage is applied to the gate electrode GE1, a channel serving as a current path is formed in the channel region OS_1. The impurity region OS_2 contains impurity elements and has the properties of a conductor. Therefore, the carrier concentration in the impurity region OS_2 is greater than that in the channel region OS_1. In other words, the channel region OS_1 has a resistivity higher than that of the impurity region OS_2 (or a conductivity lower than that of the impurity region OS_2). For example, the sheet resistance of the impurity region OS_2 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. Furthermore, the impurity region OS_2 is sometimes referred to as a source region or a drain region. The impurity elements contained in the impurity region OS_2 are, for example, boron (B) or phosphorus (P), but are not limited thereto. By implanting impurity elements into the oxide semiconductor layer OS, an impurity region OS_2 containing impurity elements can be formed, and the details will be described below. The impurity region OS_2 in the oxide semiconductor layer OS may contain more impurity elements. This means that more oxygen vacancies are generated in the impurity region OS_2, and the impurity region OS_2 has a sufficiently large carrier concentration. Therefore, the resistance of the impurity region OS_2 is sufficiently low. The boundary between the channel region OS_1 and the impurity region OS_2 substantially coincides with the end of the second conductive layer L2. That is, the end of the impurity region OS_2 overlaps with the portion exposed from the second conductive layer L2 in the first conductive layer L1. The third conductive layer L3 is connected to the impurity region OS_2 via the first contact hole CH1. Since the resistance of the impurity region OS_2 is sufficiently low, the electrical connection between the third conductive layer L3 and the impurity region OS_2 becomes an ohmic contact. [2. Structure of Oxide Semiconductor Layer OS] [2-1. Composition of Oxide Semiconductor Layer OS] As the oxide semiconductor layer OS, an oxide semiconductor containing two or more metal elements including indium (In) can be used. As the metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanide elements can be used. The oxide semiconductor layer OS has light transmittance and has a polycrystalline structure including a plurality of crystal grains. In order to make the oxide semiconductor layer OS have a polycrystalline structure, it is preferable to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio. If the ratio of indium increases, the oxide semiconductor layer OS is likely to crystallize. Also, as the metal element other than indium, gallium is preferably included. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer OS is hardly hindered by gallium. The oxide semiconductor layer OS includes a channel region OS_1 and an impurity region OS_2. Sometimes, not only the channel region OS_1 has a polycrystalline structure, but the impurity region OS_2 also has a polycrystalline structure. In this case, the crystal structure of the channel region OS_1 is the same as that of the impurity region OS_2. The oxide semiconductor layer OS has properties different from those of the previous oxide semiconductors having a polycrystalline structure, and the details will be described below. Therefore, in order to distinguish the oxide semiconductor contained in the oxide semiconductor layer OS from the previous oxide semiconductors having a polycrystalline structure, the oxide semiconductor contained in the oxide semiconductor layer OS is hereinafter referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for explanation. The Poly-OS contained in the oxide semiconductor layer OS can be formed by a sputtering method and heat treatment. Here, the method for forming the oxide semiconductor layer OS will be described. First, an oxide semiconductor film is formed by a sputtering method. The formed oxide semiconductor film has an amorphous structure. Here, the amorphous structure means a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an oxide semiconductor film having an amorphous structure is observed by an X-ray Diffraction (XRD) method, no specific peak based on the crystal structure can be obtained in the diffraction pattern. Furthermore, an oxide semiconductor film having an amorphous structure sometimes has a short-range ordered structure in a minute region. However, such an oxide semiconductor film does not exhibit the characteristics of Poly-OS, and thus can be classified as an oxide semiconductor film having an amorphous structure. The oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate for forming the oxide semiconductor film is 150°C or lower, preferably 100°C or lower, and more preferably 50°C or lower. If the temperature of the substrate is high, microcrystals are likely to be generated in the formed oxide semiconductor. Also, the oxygen partial pressure in the chamber during film formation is 1% or more and 10% or less, preferably 1% or more and 5% or less, and more preferably 2% or more and 4% or less. If the oxygen partial pressure is high, microcrystals will be generated in the oxide semiconductor film due to the excessive oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes non-uniform, and an oxide semiconductor film containing a large amount of microcrystals or an oxide semiconductor film that will not crystallize even after heat treatment is formed. Next, a heat treatment is performed on the oxide semiconductor film formed by the sputtering method. The heat treatment is carried out in the atmosphere, but the atmosphere of the heat treatment is not limited thereto. The temperature of the heat treatment is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. Also, the time of the heat treatment is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized to form an oxide semiconductor layer OS containing Poly-OS. The composition of the oxide semiconductor layer OS is substantially the same as the composition of the sputtering target. Therefore, the composition of the metal elements in the oxide semiconductor layer OS can be specified based on the composition of the metal elements in the sputtering target. Also, the composition of the oxide semiconductor layer OS can be specified using the XRD method. Specifically, the composition of the metal elements in the oxide semiconductor layer OS can be specified based on the crystal structure and lattice constant of the oxide semiconductor layer OS obtained from the XRD method. Furthermore, the composition of the metal elements in the oxide semiconductor layer OS can also be specified using fluorescence X-ray analysis or electron probe micro analyzer (EPMA) analysis, etc. Moreover, the oxygen contained in the oxide semiconductor layer OS varies depending on the process conditions of the sputtering method, etc., and thus is not limited thereto. [2-2. Characteristics of the oxide semiconductor layer OS] Next, the characteristics of the oxide semiconductor layer OS containing Poly-OS will be described. The oxide semiconductor layer OS has excellent etching resistance. Specifically, the etching rate when etching the oxide semiconductor layer OS using an etching solution for wet etching is extremely small. This means that the oxide semiconductor layer OS is hardly etched by the etching solution. When etching the oxide semiconductor layer OS at 40 °C using an etching solution containing phosphoric acid as the main component (hereinafter referred to as "mixed acid etching solution"), the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the mixed acid etching solution is 50% or more, 60% or more, or 70% or more. In addition to phosphoric acid, the mixed acid etching solution may also contain acetic acid and nitric acid. Furthermore, regarding an oxide semiconductor film that does not include Poly-OS, for example, an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate when etching the oxide semiconductor film at 40 °C using the mixed acid etching solution is 100 nm / min or more. Also, when etching the oxide semiconductor layer OS at room temperature using a 0.5% hydrofluoric acid solution, the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Regarding an oxide semiconductor film that does not include Poly-OS, the etching rate when etching the oxide semiconductor film at room temperature using a 0.5% hydrofluoric acid solution is 15 nm / min or more. Here, "40 °C" means 40 ± 5 °C, which can be the temperature of the etching solution or the set temperature of the etching solution. Also, "room temperature" means 25 ± 5 °C. Examples of the oxide semiconductor layer OS are shown in Table 1. Table 1 shows the etching rates of each sample produced with respect to the mixed acid etching solution ("Mixed Acid AT-2F" manufactured by RASA Industries Co., Ltd. in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and the 0.5% hydrofluoric acid solution. Also, when etching each sample, the temperature of the mixed acid etching solution is 40 °C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature (22 °C). In Table 1, Sample 1 is an oxide semiconductor layer OS including Poly-OS, Sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor film of indium gallium zinc oxide (IGZO) in which the ratio of indium is less than 50%. [Table 1] As shown in Table 1, regarding Sample 1 (including the oxide semiconductor layer OS of Poly-OS), it was hardly etched at all when using a mixed acid etching solution. Even when using a 0.5% hydrofluoric acid solution, the etching rate was at most 2 nm / min. In the etching using the mixed acid etching solution, the etching rate of Sample 1 was 1 / 100 or less of the etching rate of Sample 2 (the oxide semiconductor film with an amorphous structure before heat treatment). In the etching using the 0.5% hydrofluoric acid solution, the etching rate of Sample 1 was about 1 / 10 of the etching rate of Sample 2. Also, in the etching using the mixed acid etching solution, the etching rate of Sample 1 was 1 / 100 or less of the etching rate of Sample 3 (the oxide semiconductor film of IGZO with an indium ratio of less than 50%). That is, the etching resistance of Sample 1 was significantly superior to that of Sample 2 and Sample 3. This excellent etching resistance of the oxide semiconductor layer OS including Poly-OS is a characteristic that cannot be obtained in a previous oxide semiconductor with a polycrystalline structure fabricated by a process at 500°C or lower. Regarding the excellent etching resistance of the oxide semiconductor layer OS including Poly-OS, the detailed mechanism is unknown, but it is considered that Poly-OS has a polycrystalline structure different from the previous one. As described above, the etching rate of the oxide semiconductor layer OS including Poly-OS with respect to the etching solution is very small. Therefore, patterning of the oxide semiconductor layer OS is very difficult. Therefore, when forming an island-shaped oxide semiconductor layer OS, the oxide semiconductor film with an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize it. Thereby, an island-shaped oxide semiconductor layer OS including Poly-OS can be formed. [3. Manufacturing Method of Semiconductor Device 1] Referring to FIGS. 3 to 6, the manufacturing method of semiconductor device 1 will be described. FIGS. 3 to 6 are respectively schematic cross-sectional views showing the manufacturing method of semiconductor device 1 according to an embodiment of the present invention. First, as shown in FIG. 3, an insulating layer 11, a silicon semiconductor layer SS, an insulating layer 12, a gate electrode GE2, a light-shielding layer LS, an insulating layer 13, an oxide semiconductor layer OS, and an insulating layer 14 are sequentially formed on a substrate 10. In the formation of the silicon semiconductor layer SS, impurity elements are implanted into the silicon semiconductor layer SS using the gate electrode GE1 as a mask. At this time, the implanted impurity element is phosphorus (P) in the case of an n-channel type and boron (B) in the case of a p-channel type. In the formation of the oxide semiconductor layer OS, after patterning the oxide semiconductor film formed by a sputtering method, heat treatment (hereinafter referred to as "OS annealing") is performed. By performing OS annealing, an oxide semiconductor layer OS including Poly-OS is formed. Further, after forming the insulating layer 14, a first contact hole CH1 penetrating the insulating layer 14 and a second contact hole CH2 penetrating the insulating layers 12 to 14 are formed. The first contact hole CH1 exposes a part of the oxide semiconductor layer OS, and the second contact hole CH2 exposes a part of the silicon semiconductor layer SS. Next, as shown in FIG. 4, a metal film is formed over the insulating layer 14, and then the metal film is patterned, whereby a first conductive layer L1 of the gate electrode GE2 and a third conductive layer L3 of the connection wiring CN are formed. The third conductive layer L3 is connected to the oxide semiconductor layer OS via the first contact hole CH1 and to the silicon semiconductor layer SS via the second contact hole CH2. The first conductive layer L1 overlaps with the oxide semiconductor layer OS and is separated from the third conductive layer L3. Next, as shown in FIG. 5, a metal film is formed over the first conductive layer L1 and the third conductive layer, and then the metal film is patterned, whereby a second conductive layer L2 of the gate electrode GE1 and a fourth conductive layer L4 of the connection wiring CN are formed. The fourth conductive layer L4 overlaps with the second contact hole CH2 but does not overlap with the first contact hole CH1. The second conductive layer L2 overlaps with the oxide semiconductor layer OS and is separated from the fourth conductive layer L4. Next, as shown in FIG. 6, an impurity element is implanted into the oxide semiconductor layer OS using the gate electrode GE1 as a mask. For example, boron (B) as an impurity element is implanted into the oxide semiconductor layer OS by ion implantation. Furthermore, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer OS instead of boron. When ion implantation is performed, the second conductive layer L2 and the fourth conductive layer L4 having a relatively high density and a relatively large film thickness have a relatively high ability to block the implantation of impurity elements. Therefore, almost no impurity elements are implanted into the regions overlapping with the second conductive layer L2 and the fourth conductive layer L4. On the other hand, the first conductive layer L1 and the third conductive layer L3 have a relatively low density and a relatively small film thickness. Therefore, impurity elements easily pass through the portions of the first conductive layer L1 that do not overlap with the second conductive layer L2 and the portions of the third conductive layer that do not overlap with the fourth conductive layer L4. Therefore, impurity elements are implanted into the regions that do not overlap with the second conductive layer L2 and the fourth conductive layer L4. Thereby, impurity elements are implanted into the regions of the oxide semiconductor layer OS that do not overlap with the second conductive layer L2, forming an impurity region OS_2 with reduced resistance. Also, no impurity elements are implanted into the regions of the oxide semiconductor layer OS that overlap with the second conductive layer L2, forming a channel region OS_1. As described above, although impurity elements pass through the portions of the first conductive layer L1 that are exposed from the second conductive layer L2, these portions may contain impurity elements. Similarly, although impurity elements also pass through the portions of the third conductive layer L3 that are exposed from the fourth conductive layer L4, these portions may contain impurity elements. As described above, in the case where the second transistor TR2 is an n-channel transistor, the impurity element implanted into the silicon semiconductor layer SS is phosphorus. That is, the impurity element (phosphorus) contained in the silicon semiconductor layer SS is different from the impurity element (boron) implanted into the oxide semiconductor layer OS. In this case, it is necessary to protect the silicon semiconductor layer SS so that the impurity element (boron) implanted into the oxide semiconductor layer OS is not implanted into the silicon semiconductor layer SS. Therefore, a fourth conductive layer L4 is formed on the third conductive layer L3 in the second contact hole CH2 to prevent the impurity element (boron) implanted into the oxide semiconductor layer OS from being implanted into the silicon semiconductor layer SS. Further, in the case where the second transistor TR2 is a p-channel transistor, the impurity element implanted into the silicon semiconductor layer SS is boron. In the case where the impurity element implanted into the oxide semiconductor layer OS is phosphorus, the impurity element (boron) contained in the silicon semiconductor layer SS is different from the impurity element (phosphorus) implanted into the oxide semiconductor layer OS. In this case as well, a fourth conductive layer L4 is formed on the third conductive layer L3 in the second contact hole CH2 to prevent the impurity element (phosphorus) implanted into the oxide semiconductor layer OS from being implanted into the silicon semiconductor layer SS. FIG. 7 shows the simulation result of the concentration distribution of boron implanted into the oxide semiconductor layer OS. The horizontal axis and the vertical axis of the graph in FIG. 7 respectively represent the distance from the surface and the concentration of boron. Further, in FIG. 7, not only the concentration distribution of Poly-OS contained in the oxide semiconductor layer OS (the solid line in FIG. 7) is shown, but also the concentration distribution of indium gallium zinc oxide (IGZO) as a prior example (the dashed line in FIG. 7) is shown. The simulation was performed using "VICTORY PROCESS" manufactured by SILVACO at an acceleration voltage of 30 keV and a dose of 1×10 13 cm -2 under the conditions. As described above, Poly-OS contains a large amount of indium and has a high density. Therefore, in the simulation, the densities of Poly-OS and IGZO were set to 7.179 g / cm 3 and 6.1 g / cm 3 respectively for calculation. As shown in FIG. 7, the distance of boron implantation in Poly-OS is smaller than that in IGZO. That is, in Poly-OS as compared with IGZO, boron is not implanted to a position far from the surface. This means that the implanted boron tends to stay in Poly-OS. In other words, Poly-OS has a higher blocking ability for implanted impurity elements. Therefore, impurity elements do not pass through the oxide semiconductor layer OS including Poly-OS, and the oxide semiconductor layer OS can contain more impurity elements. As a result, more oxygen vacancies are generated in the impurity region OS_2, and the impurity region OS_2 can be sufficiently low in resistance. In the semiconductor device 1, since impurity elements are implanted into the oxide semiconductor layer OS via the first conductive layer L1 and the third conductive layer L3, there is a case where the acceleration voltage in ion implantation increases. In this case, the blocking ability for impurity elements is significantly exhibited. Specifically, even under the condition that impurity elements pass through the previous oxide semiconductor layer including IGZO, the impurity elements can stay in the oxide semiconductor layer OS including Poly-OS. Therefore, in the semiconductor device 1, the impurity region OS_2 overlapping with the first conductive layer L1 and the third conductive layer L3 is sufficiently low in resistance. As described above, in the semiconductor device 1, the connection wiring CN that directly electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS has a stacked structure including a third conductive layer L3 having a relatively thin film thickness and a fourth conductive layer L4 having a relatively thick film thickness. However, the fourth conductive layer L4 is not formed to overlap the first contact hole CH1 that makes the third conductive layer L3 contact the oxide semiconductor layer OS. Different from this embodiment, when impurity elements are implanted by ion implantation in the case where a connection wiring having a relatively thick film thickness is formed to overlap the first contact hole CH1, the impurity elements are implanted only from the gap between the gate electrode and the connection wiring. In this case, the impurity region including the impurity elements does not overlap the first contact hole CH1. Therefore, the electrical connection between the connection wiring and the oxide semiconductor layer does not become an ohmic contact, and the second transistor TR2 does not have the desired performance. Also, since the electrical connection between the connection wiring and the oxide semiconductor layer is unstable, the reliability of the second transistor TR2 is reduced. On the other hand, according to this embodiment, by implanting impurity elements into the oxide semiconductor layer OS via the third conductive layer L3, an impurity region OS_2 can be formed to overlap the first contact hole CH1. Therefore, the electrical connection between the connection wiring CN and the oxide semiconductor layer becomes an ohmic contact, and the second transistor TR2 has the desired performance. Also, since the electrical connection between the connection wiring CN and the oxide semiconductor layer OS is stable, the second transistor TR2 has high reliability. Further, according to the present embodiment, a fourth conductive layer L4 is formed in a first contact hole CH1 where the third conductive layer L3 is in contact with the silicon semiconductor layer SS. Therefore, even if the impurities contained in the silicon semiconductor layer SS are different from the impurities implanted into the oxide semiconductor layer OS, it is possible to prevent the impurity elements implanted into the oxide semiconductor layer OS from being implanted into the silicon semiconductor layer SS. Thereby, an increase in the contact resistance between the silicon semiconductor layer SS and the connection wiring CN can be suppressed. Therefore, a decrease in the driving ability of the second transistor TR2 can also be suppressed. Furthermore, there is no need for an additional step to suppress the implantation of unwanted impurity elements into the silicon semiconductor layer SS, and an increase in the manufacturing cost can be suppressed. Furthermore, in the present embodiment, the configuration in which the impurity region OS_2 of the oxide semiconductor layer OS is electrically connected to the silicon semiconductor layer SS has been described, but it may also be configured such that the impurity region OS_2 of the oxide semiconductor layer OS is electrically connected to a metal layer such as a wiring. <Variation Example 1> Referring to FIG. 8, a variation example of the present embodiment will be described. Furthermore, the description of the configuration identical to the above configuration may be omitted hereinafter. FIG. 8 is a schematic cross-sectional view showing the configuration of a semiconductor device 1A according to a variation example of an embodiment of the present invention. Compared with the semiconductor device 1, the configuration of the fourth conductive layer L4 is different in the semiconductor device 1A shown in FIG. 8. The third conductive layer L3 in contact with the fourth conductive layer L4 has the same configuration as the above configuration. That is, the third conductive layer L3 is in contact with the silicon semiconductor layer SS via the second contact hole CH2 and is in contact with the oxide semiconductor layer OS via the first contact hole CH1. Further, the third conductive layer L3 includes an extension portion EX that extends from the position in contact with the oxide semiconductor layer OS in the first contact hole CH1 toward the gate electrode GE1. The fourth conductive layer L4 is formed between the first contact hole CH1 and the second contact hole CH2. The fourth conductive layer L4 is in contact with the third conductive layer L3 not only in the second contact hole CH2 but also in the first contact hole CH1. However, the fourth conductive layer L4 is not formed in the extension portion EX. That is, the end face of the fourth conductive layer L4 on the side of the first transistor TR1 overlaps with the first contact hole CH1. In the semiconductor device 1A, the implantation of impurity elements into the region overlapping with the first contact hole CH1 in the oxide semiconductor layer OS is suppressed. However, when the third conductive layer L3 is a material that easily absorbs oxygen, since the third conductive layer L3 is in contact with this region, oxygen in this region is absorbed, and oxygen vacancies are generated. Thereby, a source region or a drain region having a sufficiently low resistance is formed adjacent to the channel region OS_1. In the semiconductor device 1A, the fourth conductive layer L4 is not formed in the extension portion EX either, so the same effect as that of the semiconductor device 1 can be obtained. <Variation Example 2> Referring to FIG. 9, another variation example of the present embodiment will be described. Furthermore, the description of the same components as those described above may sometimes be omitted below. FIG. 9 is a schematic cross-sectional view showing the configuration of a semiconductor device 1B, which is another variation example of an embodiment of the present invention. The semiconductor device 1B shown in FIG. 9 has a different gate electrode GE1 configuration compared to the semiconductor device 1. In the gate electrode GE1 of the semiconductor device 1B, a second conductive layer L2 is formed so as to cover the upper surface and end surfaces of the first conductive layer L1. In the channel direction, the width of the second conductive layer L2 is greater than the width of the first conductive layer L1. Also, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap the first contact hole CH1. In the semiconductor device 1B, impurity elements may also be implanted into the oxide semiconductor layer OS in a state where the connection wiring CN is connected to the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed adjacent to the channel region OS_1 and overlapping the first contact hole CH1. Therefore, in the semiconductor device 1B, the same effect as that of the semiconductor device 1 can also be obtained. <Variation Example 3> Referring to FIG. 10, another variation example of the present embodiment will be described. Furthermore, the description of the same components as those described above may sometimes be omitted below. FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor device 1C, which is a variation example of an embodiment of the present invention. The semiconductor device 1C shown in FIG. 10 has a different gate electrode GE1 configuration compared to the semiconductor device 1. In the gate electrode GE1 of the semiconductor device 1C, a second conductive layer L2 is formed, but the first conductive layer L1 is not formed. That is, the second conductive layer L2 is in contact with the insulating layer 14. Also, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap the first contact hole CH1. In the semiconductor device 1C, impurity elements may also be implanted into the oxide semiconductor layer OS in a state where the connection wiring CN is connected to the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed adjacent to the channel region OS_1 and overlapping the first contact hole CH1. Therefore, in the semiconductor device 1C, the same effect as that of the semiconductor device 1 can also be obtained. <Variation Example 4> Referring to FIG. 11, another variation example of the present embodiment will be described. Furthermore, the description of the same components as those described above may sometimes be omitted below. FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device 1D, which is a variation example of an embodiment of the present invention. Compared with the semiconductor device 1, the semiconductor device 1D shown in FIG. 11 includes a metal oxide layer MO. That is, in the semiconductor device 1D, a metal oxide layer MO in contact with the oxide semiconductor layer OS is provided under the oxide semiconductor layer OS. The end face of the metal oxide layer MO is substantially aligned with the end face of the oxide semiconductor layer OS. The insulating layer 14 covers the end face of the metal oxide layer MO and the upper surface and end face of the oxide semiconductor layer OS, and is provided on the insulating layer 13. The metal oxide layer MO can function as a buffer layer for improving the crystallinity of the oxide semiconductor layer OS. In the first transistor TR1 including the oxide semiconductor layer OS with improved crystallinity, the field-effect mobility is further improved. As the metal oxide layer MO, a metal oxide mainly composed of aluminum can be used. The ratio of aluminum contained in the metal oxide layer MO can be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer MO. The above ratio can be a mass ratio or a weight ratio. The film thickness of the metal oxide layer MO is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. As the metal oxide layer MO, aluminum oxide is preferably used. Aluminum oxide has a high barrier property against gases such as oxygen or hydrogen. Here, the barrier property refers to the function of suppressing the permeation of gases such as oxygen or hydrogen. Furthermore, as the metal oxide layer MO, a metal oxide mainly composed of a metal other than aluminum can also be used. For example, as the metal oxide layer MO, indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) can be used. The metal oxide layer MO can be formed by a sputtering method or an atomic layer deposition method (ALD method). Also, the metal oxide layer MO can be patterned using the oxide semiconductor layer OS as a mask. As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, in the patterning of the metal oxide layer MO, even when the metal oxide layer MO is etched, the oxide semiconductor layer 140 used as a mask is not etched. In the semiconductor device 1D, in the formation of the metal oxide layer MO, since the oxide semiconductor layer OS can be used as a mask, the photolithography step can be omitted. In the semiconductor device 1D, impurity elements can also be implanted into the oxide semiconductor layer OS in a state where the connection wiring CN is connected to the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed adjacent to the channel region OS_1 and overlapping with the first contact hole CH1. Therefore, in the semiconductor device 1D, the same effect as that of the semiconductor device 1 can also be obtained. Further, in the semiconductor device 1D, since the metal oxide layer MO is used as a buffer layer to form Poly-OS, the crystallinity of the oxide semiconductor layer OS including Poly-OS is improved. As a result, the first transistor TR1 has a higher field-effect mobility. <Second Embodiment> Referring to FIG. 12, a semiconductor device 2 according to an embodiment of the present invention will be described. Further, the description of the configuration that is the same as that of the first embodiment may be omitted hereinafter. FIG. 12 is a schematic cross-sectional view showing the configuration of a semiconductor device 2 according to an embodiment of the present invention. Compared with the semiconductor device 1, the configuration of the connection wiring CN in the semiconductor device 2 shown in FIG. 12 is different. In the connection wiring CN of the semiconductor device 2, the fourth conductive layer L4 is formed on the third conductive layer L3 between the first contact hole CH1 and the second contact hole CH2, and is not formed in the first contact hole CH1 and the second contact hole CH2. That is, the end face of the fourth conductive layer L4 does not overlap with the first contact hole CH1 and the second contact hole CH2. In this case, when ion implantation is performed, impurity elements are implanted not only into the oxide semiconductor layer OS but also into the silicon semiconductor layer SS. However, in the semiconductor device 2, the impurity elements contained in the silicon semiconductor layer SS are the same as the impurity elements implanted into the oxide semiconductor layer OS. Specifically, the impurity elements contained in the silicon semiconductor layer SS and the impurity elements implanted into the oxide semiconductor layer OS are both phosphorus, or the impurity elements contained in the silicon semiconductor layer SS and the impurity elements implanted into the oxide semiconductor layer OS are both boron. Therefore, even if the impurity is implanted into the silicon semiconductor layer SS and then the impurity elements are implanted into the oxide semiconductor layer OS, the performance of the first transistor TR1 will not deteriorate. Further, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap with the first contact hole CH1. In the semiconductor device 2, impurity elements can also be implanted into the oxide semiconductor layer OS in a state where the connection wiring CN is connected to the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed adjacent to the channel region OS_1 and overlapping with the first contact hole CH1. Therefore, in the semiconductor device 2, the same effect as that of the semiconductor device 1 can also be obtained. As long as the above-described embodiments and variations of the embodiments of the present invention do not conflict with each other, they can be appropriately combined and implemented. In addition, those obtained by appropriately adding, deleting, or changing the design of the constituent elements based on each embodiment and variation, or those obtained by adding, omitting, or changing the conditions of the steps, as long as they possess the gist of the present invention, are also included in the scope of the present invention. Even if they are other effects different from the effects brought about by the aspects of the above-described embodiments, those that are clear from the description of this specification or can be easily predicted by those skilled in the art can of course also be understood as the effects brought about by the present invention. 1, 1A, 1B, 1C, 1D, 2: Semiconductor device 10: Substrate 11, 12, 13, 14: Insulating layer A: Region CH1: First contact hole CH2: Second contact hole CN: Connection wiring EX: Extension GE1, GE2: Gate electrode L1: First conductive layer L2: Second conductive layer L3: Third conductive layer L4: Fourth conductive layer LS: Light-shielding layer MO: Metal oxide layer OS: Oxide semiconductor layer OS_1: Channel region OS_2: Impurity region SS: Silicon semiconductor layer TR1: First transistor TR2: Second transistor FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic enlarged cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a simulation result showing the concentration distribution of boron implanted into the oxide semiconductor layer. FIG. 8 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a variation of an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a variation of an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a variation of an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a variation of an embodiment of the present invention. FIG. 12 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. 1: Semiconductor device 10: Substrate 11, 12, 13, 14: Insulating layer A: Region CH1: First contact hole CH2: Second contact hole CN: Connection wiring GE1, GE2: Gate electrode L1: First conductive layer L2: Second conductive layer L3: Third conductive layer L4: Fourth conductive layer LS: Light-shielding layer OS: Oxide semiconductor layer SS: Silicon semiconductor layer TR1: First transistor TR2: Second transistor

Claims

1. A semiconductor device comprising: an oxide semiconductor layer including an impurity region containing an impurity element and having a polycrystalline structure; a gate electrode located on the oxide semiconductor layer; an insulating layer located between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole at least penetrating the insulating layer and having a depth greater than the depth of the first contact hole; and a connecting wire electrically connecting the impurity region to the layer exposed through the second contact hole via the first contact hole and the second contact hole; the connecting wire comprising a first conductive layer and a second conductive layer above the first conductive layer, wherein the portion of the first conductive layer exposed from the second conductive layer contains the impurity element, and the etching rate of the oxide semiconductor layer when etched at 40°C using an etchant containing phosphoric acid as the main component does not reach 3 nm / min.

2. The semiconductor device of claim 1, wherein the oxide semiconductor layer further includes a channel region adjacent to the impurity region and having a resistivity higher than that of the impurity region, the gate electrode includes a third conductive layer formed of the same layer as the second conductive layer, and the boundary between the channel region and the impurity region is substantially consistent with the end of the third conductive layer.

3. The semiconductor device of claim 2, wherein the gate electrode further includes a fourth conductive layer formed of the same layer as the first conductive layer.

4. The semiconductor device of claim 3, wherein the fourth conductive layer includes a portion exposed from the third conductive layer.

5. The semiconductor device of claim 3, wherein the end face of the fourth conductive layer is covered by the third conductive layer.

6. The semiconductor device of claim 1, wherein the second conductive layer overlaps with the first contact hole.

7. The semiconductor device of claim 1, wherein the second conductive layer overlaps with the second contact hole.

8. The semiconductor device of claim 1, wherein the layer exposed through the second contact hole is a silicon semiconductor layer.

9. The semiconductor device of claim 1, wherein the layer exposed through the second contact hole is a metal layer.

10. The semiconductor device of claim 1, wherein the etching solution comprises nitric acid and acetic acid.

11. The semiconductor device of claim 1, wherein the oxide semiconductor layer is formed by heat treatment of an oxide semiconductor film having an amorphous structure, and the etching rate of the oxide semiconductor film when etched with the etching solution at the aforementioned 40°C is 100 nm / min or more.

12. The semiconductor device of claim 1, wherein the etching rate of the oxide semiconductor layer when etched at room temperature using a 0.5% hydrofluoric acid solution does not reach 5 nm / min.

13. The semiconductor device of claim 1, wherein the sheet resistance of the aforementioned impurity region is 1000 Ω / sq. or less.

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