Semiconductor package and manufacturing method of semiconductor package

Abstract

The semiconductor package includes a photonic chip with an optical coupler, an electronic chip bonded to the photonic chip, and an optical support bonded to the electronic chip, the optical support including multiple lens structures, wherein light from an external optical signal source is sequentially coupled to the optical coupler through the multiple lens structures.

Description

[Previous Technology]

[0001] As data networks scale to meet ever-increasing bandwidth demands, the drawbacks of copper data channels become apparent. Signal attenuation and crosstalk caused by radiated electromagnetic energy are major obstacles faced by designers of such systems. These problems can be mitigated to some extent through equalization, coding, and shielding, but these techniques require considerable power, complexity, and cable bulk penalties, while offering only limited improvements in transmission distance and very limited scalability. Optical communication, not being limited by such channels, is considered the successor to copper links. However, modern optical communication systems are expensive and complex to manufacture.

Implementation Method

[0007] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may further include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, the disclosure may repeat schematic designations and / or letters in various instances. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "above," and "upper part" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0009] Figures 1 to 8 show cross-sectional views of intermediate stages in the manufacture of semiconductor packages according to some embodiments of the present disclosure. Referring to Figure 1, a substrate 101 is provided according to some embodiments. In some embodiments, the substrate 101 may be a dielectric substrate, for example, formed of silicon oxide. In this embodiment, the substrate 101 may be a silicon-on-insulator (SOI) substrate. For example, the substrate 101 may include an oxide layer 102b formed on a carrier substrate 111' and a silicon layer 102a formed on the oxide layer 102b. The carrier substrate 111' may be a material such as glass, ceramic, dielectric material, semiconductor, similar material, or a combination thereof. In some embodiments, the carrier substrate 111' may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., doped with p-type or n-type dopant) or undoped. Integrated circuit devices may be formed on and / or therein on the carrier substrate 111'. According to some embodiments of this disclosure, the integrated circuit device may include active devices such as transistors and / or diodes (which may include optical diodes). The integrated circuit device may also include passive devices such as capacitors, resistors, or the like. According to alternative embodiments of this disclosure, no active devices are formed, but passive devices may be formed on / in the carrier substrate 111'. The carrier substrate 111' may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 102C may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. In some embodiments, the carrier substrate 111' may have a thickness ranging from about 300 μm to about 2000 μm. The oxide layer 102b may be, for example, silicon oxide or the like. In some embodiments, the oxide layer 102b may have a thickness ranging from about 0.5 μm to about 4 μm. In some embodiments, the silicon layer 102a may have a thickness ranging from about 0.1 μm to about 1.5 μm. Other thicknesses are also possible. The substrate 101 may be referred to as having a front side or front surface (e.g., the side facing upwards in FIG. 1) and a back side or back surface (e.g., the side facing downwards in FIG. 1). The term "about" can be used to include any numerical value that may vary without altering the basic function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of the two endpoints, e.g., "about 2 to about 4" also discloses a range "from 2 to 4". The term "about" may refer to plus or minus 10% of the number shown.

[0010] Referring to FIG2, according to some embodiments, silicon layer 102a is patterned to form silicon regions for waveguide 104, photonic element 106, and optical coupler 112. Thus, silicon layer 102a may be considered as an "optical layer" in some cases. Silicon layer 102a may be patterned using suitable lithography and etching techniques. For example, in some embodiments, a hardmask layer (e.g., a nitride layer or other dielectric material, not shown in FIG2) may be formed and patterned on silicon layer 102a. The pattern of the hardmask layer may then be transferred to silicon layer 102a using an etching process. The etching process may include, for example, dry etching and / or wet etching processes. The etching process may be anisotropic. For example, silicon layer 102a may be etched to form a recess defining waveguide 104 (also referred to as silicon waveguide 104), with the sidewalls of the remaining unrecessed portion defining the sidewalls of waveguide 104. In some embodiments, more than one lithography and etching sequence may be used to pattern the silicon layer 102a.

[0011] One or more waveguides 104 can be patterned from the silicon layer 102a. If multiple waveguides 104 are formed, they can be individual, separate waveguides 104 or connected to form a single continuous structure. In some embodiments, one or more waveguides 104 form a continuous loop. Other configurations or arrangements of the waveguides 104, photonic elements 106, or optical couplers 112 are possible, and other types of photonic elements 106 or photonic structures can be formed. In some cases, the waveguides 104, photonic elements 106, and grating couplers 112 can be collectively referred to as a "photonic layer" or a "photonic integrated circuit (PIC)".

[0012] The photonic element 106 may be integrated with the waveguide 104 and may be formed together with the silicon waveguide 104. The photonic element 106 may be optically coupled to the waveguide 104 and may interact with optical signals within the waveguide 104. The photonic element 106 may include, for example, photonic devices such as photodetectors, modulators, other photonic devices, or the like. For example, a photodetector may be optically coupled to the waveguide 104 to detect optical signals within the waveguide 104 and generate an electrical signal corresponding to the optical signal. As another example, a modulator may be optically coupled to the waveguide 104 to receive electrical signals and generate a corresponding optical signal within the waveguide 104 by modulating the optical power within the waveguide 104. Thus, the photonic element 106 may facilitate the input / output (I / O) of optical signals entering and exiting the waveguide 104. In other embodiments, the photonic element may include other active or passive elements, such as laser diodes, optical signal splitters, phase shifters, interferometers, oscillators, or other types of photonic structures or devices.

[0013] In some embodiments, a photodetector can be formed by partially etching multiple regions of waveguide 104 and growing epitaxial material on the remaining silicon of the etched regions. Acceptable lithography and etching techniques can be used to etch waveguide 104. The epitaxial material may include, for example, a semiconductor material such as germanium, which may be doped or undoped. In some embodiments, an implantation process can be performed to introduce a dopant into the silicon of the etched regions as part of forming the photodetector. The silicon of the etched regions may be doped with P-type dopant, N-type dopant, or a combination thereof. In some embodiments, a modulator can be formed, for example, by partially etching regions of waveguide 104 and then implanting an appropriate dopant within the remaining silicon of the etched regions. Acceptable lithography and etching techniques can be used to etch waveguide 104. In some embodiments, the etched regions for the photodetector and the etched regions for the modulator can be formed using one or more of the same lithography or etching steps. The silicon of the etched regions may be doped with P-type dopant, N-type dopant, or a combination thereof. In some embodiments, the etched areas for the photodetector and the etched areas for the modulator can be implanted using one or more of the same implantation steps.

[0014] In some embodiments, one or more optical couplers 112 may be formed together with waveguide 104. In one embodiment, the optical coupler 112 is, for example, but not limited to, a grating coupler or the like. In this embodiment, the top of the optical coupler 112 may have a grating, enabling the optical coupler 112 to receive or transmit light. The optical coupler 112 for receiving light receives light from an upper light source or optical signal source (such as an optical fiber) and transmits the light to waveguide 104. The optical coupler 112 for transmitting light receives light from waveguide 104 and transmits the light to an optical fiber or the waveguide of another photonic system.

[0015] In some embodiments, the optical coupler 112 may be formed using acceptable lithography and etching techniques. In one embodiment, the optical coupler 112 is formed after the waveguide 104 is defined. For example, a photoresist may be formed and patterned on the waveguide 104, the pattern of which corresponds to the optical coupler 112. The patterned photoresist may then be used as an etching mask to perform one or more etching processes on the waveguide 104 to form the optical coupler 112. The etching processes may include one or more dry etching processes and / or wet etching processes, which may include anisotropic processes. In some embodiments, other types of couplers (not separately labeled in the figures) may be formed, such as structures that couple optical signals between the waveguide 104 and other waveguides in the semiconductor package (such as nitride waveguides). Edge couplers (not shown in the figures) may also be formed, which allow the transmission of optical signals and / or optical power between the waveguide 104 and photonic elements horizontally mounted near the sidewalls of the semiconductor package. These and other photonic structures are considered to be within the scope of this disclosure.

[0016] Referring to FIG3, a dielectric layer 103 is formed on the optical layer to form a photonic routing structure. That is, the dielectric layer 103 is formed on the waveguide 104, the photonic element 106, the optical coupler 112, and the oxide layer 102b. The dielectric layer 103 may be formed from one or more silicon oxide layers, silicon nitride layers, combinations thereof, or the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), spin coating dielectric processes, similar processes, or combinations thereof. In some embodiments, the dielectric layer 108 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by curing to transform it into another material, such as an oxide), similar processes, or combinations thereof. Any other dielectric material formed by an acceptable process may be used. In some embodiments, the dielectric layer 103 is then planarized using a planarization process, such as a chemical mechanical polishing (CMP) process, a grinding process, or a similar process. In some cases, a thinner dielectric layer 103 may allow for more efficient optical coupling between the grating coupler 112 and a vertically mounted photonic element, or more efficient optical coupling between the waveguide 104 and an upper waveguide (such as a nitride waveguide). In other embodiments, the planarization process may expose the surfaces of the waveguide 104, the photonic element 106, and / or the grating coupler 112.

[0017] Due to the difference in refractive indices between the waveguide 104 and the dielectric layer 103, the waveguide 104 exhibits high internal reflection, effectively confining light within the waveguide 104, depending on the wavelength of the light and the refractive index of the respective materials. In one embodiment, the refractive index of the waveguide 104 material is higher than that of the dielectric layer 103 material. For example, the waveguide 104 may comprise silicon, and the dielectric layer 103 may comprise silicon oxide and / or silicon nitride. Therefore, the waveguide 104 may be referred to herein as a "silicon waveguide".

[0018] Then, according to some embodiments, an interconnect structure 114 is formed on the dielectric layer 103 and the optical layer including the optocoupler 112. The interconnect structure 114 includes a plurality of dielectric layers, metal lines, and vias. The dielectric layers may be formed of a light-transmitting material (such as silicon oxide). The dielectric layers may also be formed of silicon oxynitride, silicon nitride, or the like, or of a low-k dielectric material with a k value less than about 3.0. Low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ), or the like. The metal lines and vias 116 may be formed using an damascene process and may include, for example, copper on a diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0019] In some embodiments, one or more nitride waveguides (not shown) may be formed within the interconnect structure 114. In some embodiments, the nitride waveguide (also referred to as a "silicon nitride waveguide") may be optically coupled to an upper or lower nitride waveguide. In some embodiments, one or more bottom-level nitride waveguides may be coupled to one or more lower silicon waveguides 104. In this way, the nitride waveguides can be used to transmit optical signals and / or optical power to or from other nitride waveguides and / or silicon waveguides 104.

[0020] In some cases, waveguides formed from silicon nitride (e.g., nitride waveguides) may have advantages over waveguides formed from silicon (e.g., waveguide 104). For example, silicon nitride has a higher dielectric constant than silicon, so nitride waveguides may have greater internal optical confinement than silicon waveguides. This may also make the performance or leakage of nitride waveguides less sensitive to process variations, dimensional uniformity, and surface roughness (e.g., edge roughness or linewidth roughness). In some cases, reduced process sensitivity may make nitride waveguides easier or less costly to process than silicon waveguides. These characteristics may result in lower propagation losses for nitride waveguides than for silicon waveguides. In some cases, the propagation loss (dB / cm) of nitride waveguides may be between about 0.1% and about 50% of that of silicon waveguides. In some cases, nitride waveguides may also be less sensitive to ambient temperature than silicon waveguides. For example, nitride waveguides may be as sensitive to temperature as about 1% of silicon waveguides.

[0021] In some embodiments, a plurality of bonding pads 117 are formed above and connected to the metal wire / via 116. At this time, the photonic chip 110', including the optocoupler 112, is substantially formed. The bonding pads 117 may be formed of aluminum or copper, but are not limited thereto. The bonding pads 117 are electrically connected to an integrated circuit device and / or a buried via 115' via an interconnect structure 114, which may be a photoelectric conversion device and / or an electro-optical conversion device. The photoelectric conversion device and / or the electro-optical conversion device may be built into the photonic chip 110' or externally attached to the photonic chip 110'. The photoelectric conversion device may include a photodiode. The electro-optical conversion device may include a light-emitting diode, a lamp, or the like.

[0022] According to some disclosed embodiments, the photonic chip 110' shown in FIG3 may be part of a wafer comprising a plurality of (identical) photonic chips 110' arranged in an array, although only one photonic chip 110' is described herein. In some embodiments, the photonic chip 110' includes an optical coupler 112 configured to optically couple with an optical signal source such as an optical fiber or the like (e.g., optical signal source 180 shown in FIG7). That is, the photonic chip 110' has the functions of receiving optical signals, transmitting optical signals within the photonic chip 110', transmitting optical signals out of the photonic chip 110', and electronically communicating with an electronic chip (e.g., electronic chip 120 shown in FIG5). Therefore, the photonic chip 110' is also responsible for the input / output (I / O) of optical signals in a photonic package (also called an optical engine), which may be part of a semiconductor package or other structure.

[0023] According to some embodiments of this disclosure, the photonic die 110' can be used as an interposer and includes through-holes (also referred to as through-substrate vias or through-silicon vias) penetrating the substrate. These vias (e.g., vias 115 shown in FIG. 8) are formed of a conductive material, which may also be a metallic material such as tungsten, copper, titanium, or the like. The process of forming the vias may begin as shown in FIG. 3 from a plurality of blind vias 115', ultimately exposing the metal to be substantially coplanar with the back surface of the substrate as shown in FIG. 8.

[0024] Referring now to Figures 4 and 5, an electronic die 122 is provided and bonded above a photonic die 110'. The electronic die 122 may be, for example, a semiconductor device, die, or wafer that communicates with the photonic element 106 using electrical signals. In some embodiments, the electronic die 122 may process electrical signals received from the photonic element 106 or may generate electrical signals that the photonic element 106 converts into optical signals. Figure 5 shows one electronic die 122, but in other embodiments, the semiconductor package may include two or more electronic dies 122 to reduce processing costs or increase functionality. The electronic die 122 includes connectors (e.g., bonding pads 1223), which may be, for example, conductive pads, conductive posts, or the like. In some embodiments, the electronic die 122 may have a thickness ranging from about 10 μm to about 35 μm. Other thicknesses are also possible.

[0025] Electronic die 122 may include integrated circuitry for interfacing with photonic element 106, such as circuitry for controlling the operation of photonic element 106. For example, electronic die 122 may include a controller, driver, transimpedance amplifier, the like, or a combination thereof. In some embodiments, electronic die 122 may include CPU or memory functionality. In some embodiments, electronic die 122 includes circuitry for processing electrical signals received from photonic element 106, such as processing electrical signals received from photonic element 106 including a photodetector. In some embodiments, electronic die 122 may control high-frequency signals of photonic element 106 based on electrical signals (digital or analog) received from another device or die. In some embodiments, electronic die 122 may be an electronic integrated circuit (EIC) or the like that providing serializer / deserializer (SerDes) functionality. Thus, the electronic die 122 can serve as part of the input / output (I / O) interface between optical and electrical signals within the photonic package 100. In some cases, the photonic package 100 described herein can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device.

[0026] In some embodiments, the electronic die 122 is bonded to the interconnect structure 114 of the photonic die 110' using dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, or the like). In these embodiments, dielectric-to-dielectric bonding may occur between the topmost dielectric layer of the photonic die 110' and the bonding layer (not shown separately) of the electronic die 122. During the bonding process, metal-to-metal bonding may also occur between the bonding pad 1223 of the electronic die 122 and the topmost bonding pad 117 of the photonic die 110'.

[0027] According to some embodiments of this disclosure, from a top view, the electronic chip 122 does not overlap with the optical coupler 112, so the optical coupler 112 can be optically coupled to the optical signal source 180 (FIG. 7) without being interfered with by the electronic chip 122.

[0028] In some embodiments, the electronic die 122 may initially be part of a wafer comprising a plurality of electronic dies 122 arranged in an array, and then diced into a plurality of (separate) electronic dies 122. The electronic die 122 may include a substrate 1221, and the interconnect structure 1222 includes a plurality of dielectric layers, metal lines, and vias. The dielectric layers may also be formed of silicon oxide, silicon oxynitride, silicon nitride, or the like, or of a low-k dielectric material having a k value below about 3.0. Low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, silsesquioxane hydrogenation (HSQ), methylsilsesquioxane (MSQ), or the like. The metal lines and vias may be formed using a damascene process and may include, for example, copper on a diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. A bonding pad 1223 is formed above and connected to the metal wire / via. The bonding pad 1223 may be formed of aluminum or copper, but this disclosure is not limited thereto.

[0029] In this embodiment, the photonic die 110' is in wafer form, and the diced electronic die 122 can be selected and placed on the photonic die 110'. In other words, in this embodiment, the bonding process shown in FIG. 5 is a die-to-wafer process. It is worth noting that more or fewer dies can be provided on the photonic die 110'. In this embodiment, the electronic die 122 is bonded to the photonic die 110' through a die-to-wafer bonding process. For example, direct metal-to-metal thermocompression bonding or any type of hybrid bonding technology can be applied. After the bonding process, the bonding pads 1223 of the electronic die 122 are bonded to the bonding pads 117 of the photonic die 110', respectively.

[0030] Referring to FIG6, an encapsulation material 124 is provided on the photonic die 110'. The encapsulation material 124 encapsulates the electronic die 122 at least laterally. In some embodiments, the encapsulation material 124 may be formed of a light-transmitting material, such as silicon oxide or any other suitable oxide material. In some embodiments, the upper surface of the encapsulation material 124 may initially be higher than the upper surface of the electronic die 122. In other words, the encapsulation material 124 may initially cover the upper surface of the electronic die 122.

[0031] Then, a thinning process can be performed on the encapsulation material 124 to expose the upper surface of the electronic die 122 for further processing. The thinning process can be, for example, mechanical polishing or CMP, in which chemical etchants and abrasives are used to react and polish away the encapsulation material 124 until the electronic die 122 is exposed. The resulting structure is shown in FIG. 4. After the thinning process, the upper surface of the electronic die 122 is substantially flush with the upper surface of the encapsulation material 124. However, although the above CMP process is presented as an illustrative embodiment, it is not intended to limit the embodiment. Alternatively, any other suitable removal process can be used to thin the encapsulation material 124 and the electronic die 122. For example, a series of chemical etchings or any other suitable processes can be used, all of which are fully intended to be included within the scope of the embodiment. In another embodiment, the thinning process can be omitted, and the encapsulation material 124 can cover or expose the upper surface of the electronic die 122. Throughout the description, the resulting structure, including the electronic die 122 and the encapsulation material 124, is referred to as the encapsulated electronic device 120, which may be in wafer form during the manufacturing process.

[0032] Then, referring to FIG7, according to some embodiments, an optical support 130 (also referred to as a support substrate) is bonded to the encapsulated electronic die 120 via a bonding layer 140. The optical support 130 is a rigid structure attached to the encapsulated electronic die 120 to provide structural or mechanical stability. Using the optical support 130 can reduce warpage or bending, thereby improving the performance of optical structures such as waveguide 104 or photonic element 106. According to some embodiments, the optical support 130 can be attached to the encapsulated electronic die 120 (e.g., attached to the encapsulation material 124 and / or the electronic die 122) using a bonding layer 140 formed on the encapsulation material 124 and the electronic die 122. The bonding layer 140 can be, for example, an adhesive layer or dielectric layer for dielectric-to-dielectric bonding of the optical support 130. The dielectric bonding layer 140 can be a dielectric material suitable for bonding. In some embodiments, a planarization process is performed on the bonding layer 140. In other embodiments, no bonding layer 140 is formed. In other embodiments, the bonding layer 140 may be an oxide material that is the same as or similar to the encapsulation material 124, so that the optical support 130 is bonded to the encapsulated electronic die 120 by oxide bonding. In some embodiments, the bonding layer 140 may be a high thermal conductivity hybrid bonding layer, which may include a diamond-like carbon (DLC) coating, a silicon carbide coating, a copper-silicon oxide (Cu-SiO₂) coating, a silicon oxynitride (SiON) coating, or the like.

[0033] The optical support 130 may include one or more materials, such as silicon (e.g., silicon wafers, bulk silicon, or the like), silicon oxide, metals, organic core materials, the like, or other types of materials. In some embodiments, the optical support 130 may include semiconductor elements, such as germanium (Ge), or compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the optical support 130 may have a thickness ranging from about 500 μm to about 700 μm. The optical support 130 may also have a lateral dimension (e.g., length, width, and / or area) greater than, about equal to, or smaller than that of the structure. In some embodiments, the optical support 130 includes a bonding layer (not shown separately), which may be an adhesive layer or a layer adapted to bond with the bonding layer 140.

[0034] In some embodiments, the optical support 130 is formed of a material transparent to light of the relevant wavelength, allowing optical signals to be transmitted through the optical support 130. In the example of FIG. 7, multiple lens structures (e.g., first lens structure 152 and second lens structure 154) are formed on the optical support 130. Lens structures 152, 154 can facilitate improved optical coupling between the optical coupler 112 and an external optical signal source (e.g., optical fiber 180 in FIG. 8). Referring to FIG. 7 and FIG. 8, light from the external optical signal source is coupled sequentially to the optical coupler 112 of the photonic chip 110' via the first lens structure 152 and the second lens structure 154. That is, the light from the optical signal source first passes through the first lens structure 152 and then through the second lens structure 154 to further focus (e.g., modify / reduce) the beam size projected onto the optical coupler 112. In these embodiments, the size of the first lens structure 152 (e.g., diameter D1) is substantially larger than the size of the second lens structure 154 (e.g., diameter D2) to further focus the light coupled to the optical coupler 112. In some embodiments, the lens structures 152, 154 are pre-formed on the optical support 130, which is then bonded to the encapsulated electronic die 120.

[0035] The configuration of the optical support 130 provides mechanical strength to the semiconductor package, increasing the distance between the optical signal source 180 and the optical coupler 112, which may cause attenuation and / or divergence of the light beam from the optical signal source. Therefore, multiple lens structures 152, 154 are configured to focus the light beam from the optical signal source, allowing the optical coupler 112 to be optically coupled to the optical signal source through the lens structures 152, 154. Furthermore, one lens structure (e.g., the first lens structure 152) can be used to collimate the light from / to the optical signal source 180, and another lens structure (e.g., the second lens structure 154) is used to modify (e.g., reduce) the size of the light beam projected onto the optical coupler 112. Therefore, the size of the light beam projected onto the optical coupler 112, such as that of a grating coupler (GC) and / or an edge coupler (EC), is adjustable and can be tailored to match different optical coupler (e.g., grating coupler and / or edge coupler) designs to optimize coupling efficiency.

[0036] Referring to Figures 7 and 8, in this embodiment, the first lens structure 152 and the second lens structure 154 are respectively disposed on two opposing surfaces of the optical support 130. For example, the second lens structure 154 is disposed on the lower surface S2 of the optical support 130, which is bonded to the encapsulated electronic chip 120, while the first lens structure 152 is disposed on the upper surface S1 of the optical support 130, which is opposite to the lower surface S2. In this embodiment, the second lens structure 154 formed on the lower surface S2 to be bonded to the encapsulated electronic chip 120 is filled with a filler material 1541, such that the top surface of the filler material 1541 is substantially coplanar with the surface S2 of the optical support 130. The filler material 1541 may include inorganic materials, such as, but not limited to, alumina (Al₂O₃), silicon dioxide (SiO₂), silicon nitride (SiNₓ), or the like. In some embodiments, the material of the filler 1541 may be the same as or similar to the encapsulating material 124, i.e., a light-transparent oxide material.

[0037] The optical signal source 180 is disposed on the substrate and optically coupled to the first lens structure 152 on the upper surface S1. In some embodiments, viewed from a top view, the second lens structure 154 overlaps with the optical coupler 112, and the first lens structure 152 overlaps with the second lens structure 154. Therefore, light from the optical signal source 180 first passes through the first lens structure 152, and then sequentially passes through the second lens structure 154 for further focusing and coupling to the optical coupler 112. By adjusting the size and position of the first lens structure 152 and the second lens structure 154, the beam size projected onto the optical coupler 112 can be precisely adjusted to match different optical coupler designs. It is worth noting that two lens structures are illustrated in the embodiment; however, this disclosure is not limited thereto. More lens structures can be formed on the optical support 130 to meet different optical requirements of semiconductor packaging.

[0038] Referring now to Figures 7 and 8, after the optical support 130 is bonded to the encapsulated electronic die 120, according to some embodiments, the resulting structure shown in Figure 7 is then flipped and attached to a carrier (not shown). The carrier may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, or the like. The structure may be attached to the carrier using, for example, an adhesive or a release layer (not shown). The back side of the carrier substrate 111' is then thinned until the end of the blind via 115' is exposed to form a through (substrate) via 115 as shown in Figure 8. The carrier substrate 111 may be thinned by a chemical mechanical polishing process, mechanical polishing, etching process, similar processes, or a combination thereof.

[0039] Then, according to some embodiments, a plurality of conductive pads 172 are formed on the through-hole 115 and the carrier substrate 111. The conductive pads 172 may be conductive pads or conductive pillars electrically connected to the interconnect structure 114. The conductive pads 172 may be formed of conductive materials such as copper, other metals or metal alloys, the like, or combinations thereof. The material of the conductive pads 172 may be formed by a suitable process, such as electroplating. For example, in some embodiments, the conductive pads 172 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar processes. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive pads 172. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process. In some embodiments, a bottom metal layer (UBM, not shown) may be formed on the conductive pads 172. In some embodiments, a passivation layer 173, such as silicon oxide or silicon nitride, may be formed on the carrier substrate 111 to surround or partially cover the conductive pad 172.

[0040] Then, according to some embodiments, a plurality of conductive connectors 170 may be formed on conductive pads 172 to form a semiconductor package 100. The conductive connectors 170 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using an electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. The conductive connectors 170 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connectors 170 are formed by initially forming a solder layer using common methods such as vapor deposition, electroplating, printing, solder transfer, balling, or similar methods. Once the solder layer is structurally formed, reflow soldering may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 170 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar processes. The metal pillar may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive connector 170. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process. In some embodiments, the conductive connector 170 is electrically connected to the through-hole 115 and may serve as an electrical terminal of the semiconductor package 100.

[0041] Then, after the above process is completed, the resulting structure is in the form of a wafer and is prepared to be divided into individual semiconductor packages 100 by cutting multiple dicing (scribing) lines, so as to provide the individual semiconductor packages 100 shown in FIG8.

[0042] Through this process and configuration, the electronic die 120 is directly bonded to the photonic die 110, for example, through hybrid bonding technology, to improve the electrical performance of the semiconductor package 100. The optical support 130 provides mechanical strength, and the lens structures 172 and 174 collimate and further focus the light beam from the optical signal source. Therefore, the optical coupler 112 can be optically coupled to the optical signal source via the lens structures 172 and 174 to avoid or at least reduce the attenuation and / or divergence of the light beam from the optical signal source due to the increased distance between the optical signal source 180 and the optical coupler 112.

[0043] FIG9 shows a cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure. It should be noted that the semiconductor package 100a shown in FIG9 contains many features that are the same as or similar to those of the semiconductor packages disclosed in the previous embodiments. For clarity and brevity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals denote the same or similar parts.

[0044] Referring to FIG9, in this embodiment, the first lens structure 152 and the second lens structure 154 are disposed on the upper surface S1 of the optical support 130, away from the encapsulated electronic die 120. In this embodiment, the semiconductor package 100a may further include a reflector 156 disposed on the lower surface S2 of the optical support 130 bonded to the encapsulated electronic die 120. Furthermore, one of the first lens structure 152 and the second lens structure 154 is coated with a reflective layer 1542. In this embodiment, the reflective layer 1542 is coated on the outer surface of the second lens structure 154. Therefore, light from an external optical signal source (e.g., the optical fiber 180 shown in FIG8) passes through the first lens structure 152 and is sequentially reflected by the reflective layer 1542 on the reflector 156 and the second lens structure 154 to couple to the optical coupler 112. In these embodiments, the size (e.g., diameter) of the first lens structure 152 through which light first passes is substantially larger than the size (e.g., diameter) of the second lens structure 154 through which light subsequently strikes, such that the second lens structure 154, having a smaller size, can further focus the light coupled to the optical coupler 112.

[0045] In this embodiment, the reflector 156 may be formed below the first lens structure 152 to reflect light passing through the first lens structure 152 toward the second lens structure 154. Thus, the first lens structure 152 and the second lens structure 154 may be disposed on the same surface (e.g., the upper surface S1) and may be formed simultaneously before or after the optical support 130 is bonded to the encapsulated electronic die 120. According to some embodiments, the reflector 156 and the reflective layer 1542 may be formed by depositing a reflective material. The reflective material may comprise a metallic or dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may comprise metals such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal may be deposited using suitable processes such as sputtering, electroplating, chemical vapor deposition, or similar processes. In some embodiments, a seed layer may be deposited first, and then the metal may be deposited on the seed layer. In other embodiments, the reflective material may comprise a dielectric material such as silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the thickness of the reflective material is in the range of about 10 nanometers to about 1000 nanometers, but other thicknesses are also possible. In some embodiments, the reflective material has a reflectivity greater than about 90% for light of a suitable wavelength, but other values ​​are also possible.

[0046] FIG10 illustrates a cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure. It is worth noting that the semiconductor package 100b shown in FIG10 includes many features that are the same as or similar to those of the semiconductor packages disclosed in the previous embodiments. For clarity and brevity, detailed descriptions of the same or similar features may be omitted, and the same or similar elements are indicated by the same or similar reference numerals.

[0047] Referring to FIG10, in this embodiment, the optical coupler 112b is an edge coupler (EC), which allows optical signals and / or optical power to be transmitted to / from the waveguide 104, which is horizontally mounted to the vicinity of the sidewall of the photonic package 100. Therefore, a first lens structure 152 and a second lens structure 154 are disposed on the upper surface S1 of the optical support 130, away from the encapsulated electronic die 120, while a reflector 156 is disposed on the lower surface S2 of the optical support 130, and the second lens structure 154 is coated with a reflective layer 1542. Furthermore, the semiconductor package 100b further includes another reflector 118 disposed in the photonic die 110. In some embodiments, the reflector 118 may be formed in the dielectric layer 103 covering the waveguide 104 and the edge coupler 112. The reflector 118 is configured such that light reflected by the reflective layer 1542 on the second lens structure 154 strikes the reflector 118 and is reflected as a horizontal beam toward the edge coupler 112b. Therefore, light from an external optical signal source (e.g., fiber optic 180 shown in FIG8) first passes through the first lens structure 152, and is then sequentially reflected by mirror 156, the reflective layer 1542 on the second lens structure 154, and mirror 118 to be horizontally coupled to the edge coupler 112b. In such embodiments, the size (e.g., diameter) of the first lens structure 152 through which the light first passes is substantially larger than the size (e.g., diameter) of the second lens structure 154 to which the light subsequently hits, such that the smaller second lens structure 154 can further focus the light coupled to the edge coupler 112b.

[0048] Figures 11 to 16 illustrate partial cross-sectional views of an intermediate manufacturing stage of forming a lens structure on a semiconductor package, according to some exemplary embodiments of the present disclosure. Various methods are suitable for forming the optical support 130 shown in Figure 8, which has a first lens structure 152 and a second lens structure 154 on two opposing surfaces of the optical support 130. Figures 11 to 16 are merely illustrative of one possible method, and the present disclosure is not limited thereto.

[0049] Referring to Figures 8 and 11, in this embodiment, a lens structure (i.e., a second lens structure 154) is first formed on the surface of the optical support 130 (the lower surface S2 to be bonded to the encapsulated electronic die 120). The method of forming the lens structure 154 includes the following steps. First, a patterned polymer layer 160 is formed on the surface S2 of the optical support 130. A polymer layer may be deposited on the optical support 130 first, and then patterned using a typical lithography process to form the patterned polymer layer 160. The patterned polymer layer 160 is a cylindrical pattern of polymer material covering the area where the lens structure 154 will be formed. The patterned polymer layer 160 can be used as an etch protection layer in a later etching step of the optical support 130. In this sense, at least the surface portion of the optical support 130 may be formed of a material with etch selectivity to the patterned polymer layer 160. For example, the patterned polymer layer 160 may be made of polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl alcohol (PVA), polytetrafluoroethylene (PTFE), polymethyl methacrylate (PMMA), polyvinyl chloride (PVC), poly(ethylene terephthalate) (PET), polyester, phenolic resin, urea resin, or urethane resin. The patterned polymer layer 160 is made of resin, polyurethane, etc. The patterned polymer layer 160 can be formed to an appropriate thickness, for example, 1 μm or less considering the patterning burden. The patterned polymer layer 160 can be formed using suitable coating or printing methods, such as spin coating, blade coating, electrostatic spraying, etc. Then, a reflow process is performed on the patterned polymer layer 160 to form a polymer lens structure 160, as shown in Figure 11, which has a curved surface formed by the surface tension of the polymer.

[0050] Then, referring to FIG12, an etching process is performed on the surface S2 of the optical support 130 on which the polymer lens structure 160 is provided to transfer the curved profile of the polymer lens structure 160 onto the surface S2 of the optical support 130 and form a lens structure 154'. The lens structure 154' protruding from the surface S2 of the optical support 130 can also be used as a lens for collimating and / or focusing a beam. However, in this embodiment, the top surface of the lens structure 154 shown in FIG8 is substantially equal to or lower than the surface S2 of the optical support 130. Therefore, another etching process is used.

[0051] Referring to FIG13, a patterned mask layer 162 is provided on surface S2 of optical support 130, and the patterned mask layer 162 includes an opening OP1 exposing the lens structure 154' shown in FIG12. Then, another etching process is performed to form the lens structure 154 shown in FIG13. The etching process may include one or more dry etching processes and / or wet etching processes. In this embodiment, the etching process includes a dry etching process, which involves selective material removal by ion-assisted processes such as ion beam etching (IBE), reactive ion etching (RIE), and inductively coupled plasma (ICP) etching or similar processes, but this disclosure is not limited thereto. Therefore, the resulting lens structure 154 includes a notch recessed from the outer surface (e.g., surface S2) of optical support 130, and the notch includes a non-vertical sidewall 1543 and a convex bottom surface 1544 having a circular or spherical shape. Then, remove the patterned mask layer 162.

[0052] Referring to FIG14, the resulting structure shown in FIG13 is then flipped over, and a first lens structure 152 is formed on the upper surface S1 of the optical support 130 through a process similar to that shown in FIG11 to FIG13.

[0053] Then, referring to Figures 15 and 16, a filler material 1541 is provided to fill the notch of the second lens structure 154. The filler material 1541 can be dispensed onto the surface S2 of the optical support 130 to form a filler material layer 1541'. The filler material layer 1541' can be dispensed in a liquid form and has high viscosity. After dispensing, the filler material layer 1541' can be solidified into a solid form. Then, referring to Figure 16, a planarization process can be performed on the filler material layer 1541' to remove excess filler material until the surface S2 of the optical support 130 is exposed. The planarization process may include a CMP process, an etching process, or a similar process. Thus, the filler material 1541 fills the notch of the second lens structure 154, and the top surface of the filler material 1541 is substantially coplanar with the surface S2 of the optical support 130. The filler material 1541 may include inorganic materials, such as, but not limited to, alumina (Al₂O₃), silicon dioxide (SiO₂), silicon nitride (SiNₓ), or the like. In some embodiments, the filler material 1541 may be the same as or similar to the encapsulating material 124, and is a light-transparent oxide material.

[0054] After the filler material 1541 is filled into the recess of the second lens structure 154, the lower surface S2 of the optical support 130 having the second lens structure 174 filled with the filler material 1541 is then bonded to the encapsulated electronic die 120 as shown in FIG8. It is worth noting that in other embodiments, the filler material 1541 may be provided immediately after the second lens structure 174 is formed, and then the optical support 130 may be flipped to form the first lens structure 172 on the upper surface S1. This disclosure does not limit the process sequence disclosed herein.

[0055] Figures 17 to 21 illustrate partial cross-sectional views of an intermediate stage in the fabrication of a lens structure on a semiconductor package according to other exemplary embodiments of the present disclosure. Various methods are suitable for forming the optical support 130a shown in Figure 9, wherein the first lens structure 152 and the second lens structure 154 are located on the same surface of the optical support 130a. Figures 17 to 21 show only one possible method for illustrative purposes, and the present disclosure is not limited thereto.

[0056] Referring to FIG17, in this embodiment, a reflector 156 is formed on surface S2 of optical support 130a, which will be bonded to encapsulated electronic die 120 as shown in FIG9. According to some embodiments, an opening OP2 is formed on surface S2 of optical support 130a. The opening OP2 can be formed using acceptable lithography and etching techniques, such as by forming and patterning photoresist, and then using the patterned photoresist as an etching mask to perform an etching process. The etching process may include, for example, dry etching and / or wet etching processes, which may be anisotropic etching. Then, according to some embodiments, a reflective material is deposited in the opening OP2 to form the reflector 156. The reflective material may include a metallic or dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may include copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal may be deposited using suitable processes such as sputtering, electroplating, CVD, or similar processes. In some embodiments, a seed layer may be deposited first, and then the metal may be deposited on the seed layer. In other embodiments, the reflective material may include a dielectric material of silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as PVD, CVD, ALD, or similar processes. In some embodiments, the thickness of the reflective material is between about 10 nm and about 1000 nm, but other thicknesses are also possible. In some embodiments, the reflective material may fill the opening OP2. A planarization process (e.g., CMP or polishing) may be performed to remove excess reflective material. After the planarization process, the top surface of the mirror 156 and the surface S2 of the optical support 130a may be substantially flush or coplanar. In some embodiments, the reflectivity of the reflective material to light of an appropriate wavelength is greater than about 90%, but other values ​​are also possible.

[0057] In other embodiments, the reflector 156 can be directly deposited or sputtered onto the surface S2 of the optical support 130a without forming an opening OP2. Then, a filler material can be applied to cover the surface S2 of the reflector 156 and the optical support 130a. Next, a planarization process (e.g., CMP process or polishing process) can be performed on the filler material to make the surface flat for subsequent bonding processes.

[0058] Referring to FIG18, the optical support 130a is then flipped to form a first lens structure and a second lens structure on the upper surface S1 of the optical support 130a. The process for forming the first lens structure and the second lens structure may be similar to the process shown in FIGS. 11 to 13. For example, a patterned polymer layer is formed on the upper surface S1 of the optical support 130a to cover the areas where the first lens structure 152 and the second lens structure 154 will be formed. Then, a reflow process is performed on the patterned polymer layer to form a plurality of polymer lens structures 160', corresponding to the areas where the first lens structure 152 and the second lens structure 154 will be formed, respectively. As shown in FIG18, each polymer lens structure 160' has a curved surface formed by the surface tension of the polymer. For example, the polymer lens structure 160' can be made of polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl alcohol (PVA), polytetrafluoroethylene (PTFE), polymethyl methacrylate (PMMA), polyvinyl chloride (PVC), polyethylene terephthalate (PET), polyester, phenolic resin, urea resin, amino resin, polyurethane, etc.

[0059] Then, referring to FIG19, an etching process is performed on the upper surface S1 of the optical support 130a having polymer lens structures 160' to transfer the curved profile of each polymer lens structure 160 onto the upper surface S1 of the optical support 130a. Thus, a first lens structure 152' and a second lens structure 154' as shown in FIG19 are formed. The first lens structure 152' and the second lens structure 154' protruding from the upper surface S1 of the optical support 130a can also be used as lenses for collimating and / or focusing beams. However, in this embodiment, the top surfaces of the first lens structure 152 and the second lens structure 154 shown in FIG9 are substantially equal to or lower than the upper surface S1 of the optical support 130a. Therefore, another etching process is employed.

[0060] Referring to FIG20, a patterned mask layer 162 is provided on the upper surface S1 of the optical support 130a. The patterned mask layer 162 includes a plurality of openings OP1, which expose the first lens structure 152 and the second lens structure 154, respectively. Then, another etching process is performed to form the first lens structure 152 and the second lens structure 154 shown in FIG20. In some embodiments, from a top view, a reflector 156 is located between the first lens structure 172 and the second lens structure 174. The etching process may include one or more dry etching processes and / or wet etching processes. In this embodiment, the etching process includes a dry etching process, which involves selective material removal by ion-assisted processes (such as ion beam etching (IBE), reactive ion etching (RIE), and inductively coupled plasma (ICP) etching) or similar processes, but is not limited thereto. Therefore, the first lens structure 152 and the second lens structure 154 each include a recess from the upper surface S1 of the optical support 130a, the recess including a non-vertical sidewall and a convex bottom surface (having an arc or spherical shape). Then, the patterned mask layer 162 is removed.

[0061] Next, a reflective layer 1542 is formed on the surface of the second lens structure 174. Therefore, a reflector 156 is formed below the first lens structure 152 to reflect light passing through the first lens structure 152 toward the second lens structure 154. The light is reflected by the reflective layer 1542 on the second lens structure 154 to couple to the optical coupler 112, as shown in FIG9. In this way, the first lens structure 152 and the second lens structure 154 are located on the same surface (e.g., the upper surface S1) and can be formed simultaneously, thereby simplifying the manufacturing process. According to some embodiments, the reflector 156 and the reflective layer 1542 can be formed by depositing a reflective material. The reflective material may include a metallic material or a dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may include metals such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal can be deposited using suitable processes such as sputtering, electroplating, chemical vapor deposition, or similar processes. In some embodiments, a seed layer may be deposited first, and then the metal may be deposited on the seed layer. In other embodiments, the reflective material may include dielectric materials such as silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the thickness of the reflective material ranges from about 10 nm to about 1000 nm, but other thicknesses are also possible. In some embodiments, the reflective material has a reflectivity greater than about 90% for light of a suitable wavelength, but other values ​​are also possible.

[0062] Based on the above discussion, it can be seen that this disclosure provides various advantages. However, it should be understood that not all advantages need to be discussed herein, and other embodiments may provide different advantages, and no particular advantage is required in any embodiment.

[0063] Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and similar operations. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0064] According to some embodiments of this disclosure, a semiconductor package includes a photonic die comprising an optical coupler, an electronic die bonded to the photonic die, and an optical support member bonded to the electronic die and including a plurality of lens structures. Light from an external optical signal source is sequentially coupled to the optical coupler through the plurality of lens structures. In one embodiment, the semiconductor package further includes an encapsulation material that at least laterally encapsulates the electronic die. In one embodiment, the photonic die includes a carrier substrate, a photonic layer including the optical coupler, and an interconnect structure disposed on the photonic layer. In one embodiment, the electronic die is bonded to and electrically connected to the interconnect structure. In one embodiment, the plurality of lens structures includes a first lens structure and a second lens structure respectively disposed on two opposing surfaces of the optical support member. In one embodiment, the second lens structure is disposed on the lower surface of the optical support member bonded to the electronic die, and, from a top view, the second lens structure overlaps with the optical coupler. In one embodiment, the plurality of lens structures, including the first lens structure and the second lens structure, are disposed on the upper surface of the optical support member away from the electronic die. In one embodiment, one of the first lens structure and the second lens structure is coated with a reflective layer. In one embodiment, the semiconductor package further includes a reflector disposed on a lower surface of the optical support opposite to the upper surface, wherein light from the external optical signal source passes through the first lens structure and is sequentially reflected by the reflector and the second lens structure to couple to the optical coupler. In one embodiment, the semiconductor package further includes a first reflector disposed on the lower surface of the optical support opposite to the upper surface and a second reflector disposed in the photonic die. In one embodiment, light from the external optical signal source passes through the first lens structure and is sequentially reflected by the first reflector, the second lens structure, and the second reflector to couple to the optical coupler.

[0065] According to some embodiments of this disclosure, a semiconductor package includes a photonic die containing an optical coupler, an electronic die bonded to the photonic die, and an optical support bonded to the electronic die. The optical support includes a first lens structure and a second lens structure configured to sequentially couple light to the optical coupler via the first lens structure and the second lens structure, wherein the size of the first lens structure is substantially larger than the size of the second lens structure. In one embodiment, each of the first lens structure and the second lens structure includes a notch recessed from an outer surface of the optical support. In one embodiment, the notch includes a non-vertical sidewall and a convex bottom surface. In one embodiment, the first lens structure and the second lens structure are respectively disposed on two opposing surfaces of the optical support, and the size of the first lens structure is substantially larger than the size of the second lens structure. In one embodiment, both the first lens structure and the second lens structure are disposed on the upper surface of the optical support away from the encapsulated electronic die.

[0066] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package includes: providing a photonic die, wherein the photonic die includes an optical coupler; bonding an electronic die to the photonic die; providing an encapsulating material on the photonic die to form an encapsulated electronic die, wherein the encapsulating material at least laterally encapsulates the electronic die; forming a first lens structure and a second lens structure on an optical support; and bonding the optical support to the encapsulated electronic die, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the first lens structure and the second lens structure. In one embodiment, forming the first lens structure and the second lens structure on the optical support further includes: forming the second lens structure on a lower surface of the optical support to be bonded to the encapsulated electronic die, wherein the second lens structure includes a notch; forming the first lens structure on an upper surface of the optical support opposite to the lower surface; and providing a filler material to fill the notch, wherein the lower surface of the optical support having the second lens structure filled with the filler material is bonded to the encapsulated electronic die. In one embodiment, the method further includes: forming a reflector on the lower surface of the optical support to be bonded to the encapsulated electronic die, wherein forming the first lens structure and the second lens structure on the optical support further includes: forming the first lens structure and the second lens structure on an upper surface of the optical support opposite to the lower surface; and forming a reflective layer on the surface of the second lens structure, wherein, from a top view, the reflector is located between the first lens structure and the second lens structure. In one embodiment, forming the first lens structure and the second lens structure on the optical support further includes: forming a patterned polymer layer on the optical support; performing a reflow process on the patterned polymer layer to form a polymer lens structure; and performing an etching process on the surface of the optical support having the polymer lens structure to transfer the outline of the polymer lens structure onto the optical support.

[0067] The foregoing has summarized features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various modifications, substitutions, and alterations can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0002] When reading in conjunction with the diagrams, the various aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0003] Figures 1 to 8 show cross-sectional views of some embodiments of the present disclosure during intermediate stages of the manufacture of semiconductor packages.

[0004] Figures 9 and 10 show cross-sectional views of semiconductor packages according to different embodiments of the present disclosure.

[0005] Figures 11 to 16 show partial cross-sectional views of intermediate stages in the fabrication of a lens structure on a semiconductor package according to some embodiments of the present disclosure.

[0006] Figures 17 to 21 show partial cross-sectional views of an intermediate stage in the fabrication of a lens structure on a semiconductor package according to other embodiments of the present disclosure.

Claims

1. A semiconductor package, comprising: Photonic chip, including an optical coupler; electronic chip, bonded to the photonic chip; And an optical support, coupled to the electronic chip and including a first lens structure and a second lens structure disposed on the upper surface of the optical support away from the electronic chip, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the first lens structure and the second lens structure.

2. The semiconductor package as claimed in claim 1, wherein one of the first lens structure and the second lens structure is coated with a reflective layer.

3. The semiconductor package as claimed in claim 1, wherein the photonic die comprises a carrier substrate, a photonic layer including the optical coupler, and an interconnect structure disposed on the photonic layer.

4. The semiconductor package as claimed in claim 1 further includes a reflector disposed on a lower surface of the optical support opposite the upper surface, wherein the light from the external optical signal source passes through the first lens structure and is sequentially reflected by the reflector and the second lens structure to couple to the optical coupler.

5. The semiconductor package as claimed in claim 1, further comprising a first reflector disposed on a lower surface of the optical support opposite to the upper surface and a second reflector disposed in the photonic die.

6. A semiconductor package, comprising: A photonic chip, including an optical coupler; an encapsulated electronic chip, bonded to the photonic chip; And an optical support, coupled to the encapsulated electronic chip and including a first lens structure and a second lens structure for sequentially coupling light to the optical coupler, wherein the first lens structure and the second lens structure are disposed on the upper surface of the optical support away from the electronic chip.

7. The semiconductor package of claim 6, wherein each of the first lens structure and the second lens structure includes a notch recessed from the outer surface of the optical support, and the notch includes a non-vertical sidewall and a convex bottom surface.

8. A method for manufacturing a semiconductor package, comprising: Provide a photonic die, wherein the photonic die includes an optical coupler; attach an electronic die to the photonic die; An encapsulating material is provided on the photonic die to form an encapsulated electronic die, wherein the encapsulating material at least laterally encapsulates the electronic die; A first lens structure and a second lens structure are formed on an optical support, wherein the first lens structure and the second lens structure are disposed on the upper surface of the optical support away from the electronic chip; and the optical support is bonded to the encapsulated electronic chip, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the first lens structure and the second lens structure.

9. The method of manufacturing a semiconductor package as claimed in claim 8, wherein forming the first lens structure and the second lens structure on the optical support further comprises: A patterned polymer layer is formed on the optical support; A reflow process is performed on the patterned polymer layer to form a polymer lens structure; an etching process is performed on the surface of the optical support having the polymer lens structure to transfer the outline of the polymer lens structure onto the optical support.

10. The method of manufacturing a semiconductor package as claimed in claim 8, further comprising forming a reflector on a lower surface of the optical support to be bonded to the encapsulated electronic die, wherein forming the first lens structure and the second lens structure on the optical support further comprises: The first lens structure and the second lens structure are formed on the upper surface of the optical support member opposite to the lower surface; And a reflective layer is formed on the surface of the second lens structure, wherein, from a top view, the reflector is located between the first lens structure and the second lens structure.

Images