Memory device and method for programming memory cells

Abstract

This invention provides a method for programmable memory cells, comprising reading the memory cells to determine individual read currents of the memory cells. Each individual memory cell is assigned to one of a plurality of groups of memory cells, wherein each individual in the plurality of groups of memory cells is associated with a different read current range, such that the determined read current of one individual memory cell is within the read current range of the group of memory cells to which the memory cell is assigned. The memory cells are programmable using programmable currents, which vary according to the group of memory cells to which the memory cell is assigned.

Description

Technical Field

[0001] [Related Applications] This application claims the benefit of U.S. Provisional Application No. 63 / 606,008, filed on December 4, 2023, and U.S. Patent Application No. 18 / 586,350, filed on February 23, 2024.

[0002] The present invention relates to non-volatile memory cells and, more particularly, to techniques for programming memory cells. Prior Art

[0003] Split-gate non-volatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a quad-gate memory cell configuration and is incorporated herein by reference for all purposes. Specifically, FIG. 1 of the present disclosure illustrates a pair of split-gate memory cells 10, each having a spaced-apart source region 14 and a drain region 16 formed in a silicon semiconductor substrate 12. Source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and drain region 16 is typically connected to a bit line. A channel region 18 of substrate 12 extends between source region 14 and drain region 16. A floating gate 20 is disposed over (i.e., vertically above and laterally overlapping) and insulated from (and directly controls) a first portion of channel region 18 (and partially overlies and insulated from) source region 14). A control gate 22 is disposed above and insulated from the floating gate 20. A select gate 24 (also known as a word line gate) is disposed above and insulated from the second portion of the channel region 18 (and directly controls its conduction). An erase gate 26 is disposed above and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 may include a notch facing the edge of the floating gate 20.

[0004] A plurality of such memory cells 10 can be arranged in rows and columns to form a memory cell array, as illustrated in FIG2 . While FIG1 shows only a pair of memory cells (sharing a common source region 14 and erase gate 26), the memory cell pairs can be placed end-to-end to form memory cell rows (where the memory cell pairs can share a common drain region). While FIG2 shows only two such rows, many such rows may exist. Each row can include a bit line 16a electrically connecting all drain regions 16 in that row. Each column of memory cells can include a control gate line 22a electrically connecting all control gates 22 in the column. For example, all control gates 22 in each column of memory cells can be formed as a continuous line of conductive material, with a portion of the continuous line passing through any given memory cell serving as its control gate 22. Each column of memory cells can also include a select gate line 24a electrically connecting all select gates 24 in the column of memory cells. For example, all select gates 24 in each column of memory cells can be formed as a continuous line of conductive material, with the portion of the continuous line passing through any given memory cell serving as its select gate 24. Each column of memory cell pairs can include an erase gate line 26a that electrically connects all erase gates 26 in that column of memory cell pairs. For example, all erase gates 26 in each column of memory cell pairs can be formed as a continuous line of conductive material, with the portion of the continuous line passing through any given memory cell pair serving as its erase gate 26. Finally, each column of memory cell pairs can include a source line 14a that electrically connects all source regions 14 in that column of memory cell pairs. For example, all source regions 14 in each column of memory cell pairs can be formed as a continuous line of conductive diffusion in the substrate 12, with the portion of the continuous line passing through any given memory cell pair serving as its source region 14.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and the source and drain regions 14, 16 to program the split-gate memory cell 10 (i.e., inject electrons onto the floating gate 20), erase the split-gate memory cell 10 (i.e., remove electrons from the floating gate 20), and read the split-gate memory cell 10 (i.e., measure or detect the conductivity of the channel region 18, such as by measuring or detecting a read current flowing through the channel region 18 to determine the programmed state of the floating gate 20).

[0006] The split-gate memory cell 10 can be digitally operated, wherein the split-gate memory cell 10 is set to one of only two possible states: a programmed state and an erased state. The split-gate memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and, optionally, a negative voltage to the control gate 22, thereby inducing electron tunneling from the floating gate 20 to the erase gate 26 (placing the floating gate 20 in a more positively charged state—the erased state). The split-gate memory cell 10 can be programmed by applying a positive voltage to the control gate 22, the erase gate 26, the select gate 24, and the source region 14, and applying a current to the drain region 16. The electrons will then flow along the channel region 18 from the drain region 16 toward the source region 14, becoming accelerated and heated, whereby some of the electrons are injected into the floating gate 20 by hot electron injection (causing the floating gate 20 to be in a more negatively charged state - the programmed state).

[0007] One technique for programming memory cells is sequential programming, which involves applying a programming voltage as a series of pulses, where each pulse of the programming voltage injects more electrons onto the floating gate, thereby increasing the programmed state of the memory cell with each pulse until the desired programmed state is reached. With sequential programming, there may be intervening read operations between programming pulses to determine whether the desired programmed state has been reached by the last applied programming pulse (in which case programming stops) or has not yet been reached (in which case programming continues with one or more programming pulses). For example, each desired programmed state can be associated with a target read current, Irtarget (i.e., the desired current flowing through the channel region 18 during the read operation associated with the desired programmed state, and therefore the target current). The higher the programmed state (i.e., the more electrons on the floating gate), the lower the read current, Ir. Consequently, the read current, Ir, will decrease after each programming pulse. Once the target read current Irtarget is reached (reflecting the desired programming state), programming of the memory cell stops.

[0008] If the same set of programming voltages is applied during each pulse in sequential programming, the amount of programming decreases from pulse to pulse because, as the floating gate becomes more negatively charged with each pulse, fewer electrons are injected into the floating gate if the parameters of the programming pulse (applied voltage, supplied current, duration) remain constant. Therefore, whenever it is determined after any given pulse that the memory cell has not yet reached its desired programmed state, one or more of the programming parameters can be stepped to higher values in the next pulse to compensate for the decreasing amount of programming that would otherwise occur from pulse to pulse. For example, for the memory cell of FIG1 , the programming parameters that can be stepped from one programming pulse to the next can include increases in one or more of the following: the voltage applied to the control gate, the voltage applied to the erase gate, the voltage applied to the source region, the current supplied to the drain region, and the duration of the programming pulse.

[0009] The split-gate memory cell 10 can be read by placing a positive voltage on the select gate 24 (turning on the portion of the channel region 18 below the select gate by making the select gate 24 conductive) and on the drain region 16 (and optionally, on the erase gate 26 and the control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (i.e., the split-gate memory cell 10 is erased), the split-gate memory cell 10 will turn on because both portions of the channel region 18 are conductive due to the lack of electrons on the floating gate 20, and current will flow from the drain region 16 to the source region 14 (i.e., based on the sensed current, the split-gate memory cell 10 is sensed to be in its erased "1" state). If the floating gate 20 is negatively charged (i.e., the split-gate memory cell 10 is programmed), the portion of the channel region 18 below the floating gate is disconnected (less conductive), thereby preventing significant current flow (i.e., the split-gate memory cell 10 is sensed as being in its programmed "0" state due to no or minimal current flow). The memory cell 10 is considered non-volatile because it maintains its programmed state even when power is not applied to the semiconductor device. The memory cell 10 can be referred to as a split-gate memory cell because two different gates (the floating gate 20 and the select gate 24) directly control the conduction of two different portions of the channel region 18.

[0010] The split-gate memory cell 10 can alternatively operate in an analog manner, where the memory state of the split-gate memory cell 10 (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can be gradually changed from a fully erased state (minimum number of electrons on the floating gate 20) to a fully programmed state (maximum number of electrons on the floating gate 20), or only a portion of this range. This means that the split-gate memory cell 10 storage is analog, which allows for very precise and individual tuning of each split-gate memory cell 10 in an array of split-gate memory cells 10. Alternatively, the split-gate memory cell 10 can operate as an MLC (multi-level cell), in which it is configured to be programmed to one of many discrete values (such as 16 or 64 different values).

[0011] Split-gate memory cells with fewer gates are also known. For example, FIG3 illustrates a conventional split-gate memory cell 10, which is identical to the split-gate memory cell of FIG1 , except that the control gate 22 is omitted. See, for example, U.S. Patent 7,315,056. The voltage coupling to the floating gate 20 provided by the control gate 22 of the split-gate memory cell of FIG1 is instead provided by the erase gate 26 and source region 14 of the split-gate memory cell of FIG3 . FIG4 illustrates an example layout of an array of the split-gate memory cells 10 of FIG3 .

[0012] As another example, FIG5 illustrates a conventional split-gate memory cell 10, which is similar to the split-gate memory cell of FIG1 , except that the control gate 22 and erase gate 26 are omitted. See, for example, U.S. Patent 5,029,130. In the split-gate memory cell of FIG5 , the erase voltage is applied to the select gate 24, which has a first portion laterally adjacent to the floating gate 20 and a second portion extending above the floating gate 20. FIG6 illustrates an example layout of an array of the split-gate memory cells 10 of FIG5 .

[0013] As another example, FIG7 illustrates a conventional split-gate memory cell 10, which is similar to the split-gate memory cell of FIG5, except that a block of conductive material 28 is formed to contact the source region 14 to serve as an extended source line. See, for example, U.S. Patent 6,855,980. An example layout for an array of split-gate memory cells 10 of FIG7 can be the same as the layout of FIG6.

[0014] Although any of the split-gate memory cells 10 of Figures 1, 3, 5, and 7 can be operated digitally, analogically, or as an MLC, the accuracy of memory cell programming for analog and MLC operation can be particularly important. Summary of the Invention

[0015] The aforementioned problems and needs are addressed by a method for programming memory cells, the method comprising: reading the memory cells to determine respective read currents of the memory cells; assigning respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different read current range such that the determined read current of a respective one of the memory cells is within the read current range of the group of the memory cells to which the memory cell is assigned; and programming the memory cells using programming currents, which, for respective ones of the memory cells, vary according to the group of the memory cells to which the memory cell is assigned.

[0016] A method for programming memory cells comprises: reading the memory cells to determine respective first read currents of the memory cells; pre-programming the memory cells after the reading of the memory cells; reading the memory cells after the pre-programming of the memory cells to determine respective second read currents of the memory cells; assigning respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein the plurality of groups of the memory cells Each of the memory cells is associated with a different read current difference range, so that a read current difference between the first read current and the second read current of each of the memory cells is within the read current difference range of the group of memory cells to which the memory cell is assigned; and the memory cells are programmed using programming currents, which vary for each of the memory cells according to the group of memory cells to which the memory cell is assigned.

[0017] A method for programming memory cells includes: programming the memory cells; reading the memory cells to determine respective read currents of the memory cells relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current; programming the memory cells having a read current greater than the reference read current using a first programming current; programming the memory cells having a read current less than the reference read current and greater than the target read current using a second programming current less than the first programming current; and stopping programming the memory cells having a read current less than the target read current.

[0018] A memory device includes memory cells and a control circuit system. The control circuit system reads the memory cells to determine respective read currents of the memory cells; assigns respective ones of the memory cells to one of a plurality of groups of memory cells, wherein respective ones of the plurality of groups of memory cells are associated with different read current ranges such that the determined read current of a respective one of the memory cells is within the read current range of the group of memory cells to which the memory cell is assigned; and programs the memory cells using programming currents that vary for respective ones of the memory cells according to the group of memory cells to which the memory cell is assigned.

[0019] A memory device includes memory cells and a control circuit system. The control circuit system: reads the memory cells to determine respective first read currents of the memory cells; pre-programs the memory cells after the reading of the memory cells; reads the memory cells after the pre-programming of the memory cells to determine respective second read currents of the memory cells; assigns respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein the respective ones of the plurality of groups of the memory cells are The memory cells are associated with a different read current difference range so that a read current difference between the first read current and the second read current for each of the memory cells is within the read current difference range of the group of memory cells to which the memory cell is assigned; and the memory cells are programmed using programming currents that vary for each of the memory cells according to the group of memory cells to which the memory cell is assigned.

[0020] A memory device includes memory cells and a control circuit system. The control circuit system programs the memory cells; reads the memory cells to determine respective read currents of the memory cells relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current; programs the memory cells having a read current greater than the reference read current using a first programming current; programs the memory cells having a read current less than the reference read current and greater than the target read current using a second programming current less than the first programming current; and stops programming the memory cells having a read current less than the target read current.

[0021] Other objects and features of the present disclosure will become apparent by reviewing the specification, claims and drawings. Simple diagram description

[0022] FIG. 1 is a cross-sectional view of a pair of conventional memory cells.

[0023] FIG. 2 is a schematic layout diagram of a conventional memory cell array of the memory cell of FIG. 1 .

[0024] FIG. 3 is a side cross-sectional view of a pair of conventional memory cells.

[0025] FIG. 4 is a schematic layout diagram of a conventional memory cell array of the memory cell of FIG. 3 .

[0026] FIG. 5 is a side cross-sectional view of a pair of conventional memory cells.

[0027] FIG. 6 is a schematic layout diagram of a conventional memory cell array of the memory cell of FIG. 5 .

[0028] FIG. 7 is a side cross-sectional view of a pair of conventional memory cells.

[0029] FIG8 is a diagram illustrating components of a memory device.

[0030] FIG. 9 is a graph showing the read current Ir of various memory cells versus programming.

[0031] FIG. 10 is a flow chart illustrating a programming method according to a first embodiment.

[0032] FIG. 11 is a graph showing a read current Ir versus programming according to a first example.

[0033] FIG. 12 is a flow chart illustrating a programming method according to a second example.

[0034] FIG. 13 is a graph showing a read current Ir with respect to programming according to a second example.

[0035] FIG. 14 is a flow chart illustrating a programming technique according to a third example.

[0036] FIG. 15 is a graph showing a read current Ir versus programming according to a third example.

[0037] FIG. 16 is a graph of read current Ir versus programming according to a combination of the first example and the third example.

[0038] FIG. 17 is a graph showing a read current Ir with respect to programming according to a combination of the second example and the third example. Implementation Method

[0039] The present invention illustrates a memory cell programming method that includes memory cell programming speed compensation to improve programming efficiency without unduly reducing programming accuracy. The programming method can be implemented as part of a control circuitry 46 that controls various device elements of a memory array, as best understood from the architecture of an example memory device, as shown in FIG8 . The memory device includes an array 30 of split-gate memory cells 10, which can be separated into two separate planes (Plane A 32 a and Plane B 32 b). Split-gate memory cells 10 can be of the type shown in FIG1 , FIG3 , FIG5 , or FIG7 , arranged in a plurality of rows and columns in a semiconductor substrate 12 as depicted in FIG2 , FIG4 , or FIG6 , and thus formed on a single chip. Adjacent to the array 30 of split-gate memory cells 10 are an address decoder 34 (e.g., XDEC), a source line driver 36 (e.g., SLDRV), a row decoder 38 (e.g., YMUX), a high-voltage column decoder 40 (e.g., HVDEC), and a bit line controller 42 (e.g., BLINHCTL) for decoding addresses and supplying various voltages to the various gates and regions of the split-gate memory cells 10 during read, program, and erase operations of selected split-gate memory cells 10 of the array 30. The row decoder 38 includes sense amplifiers containing circuitry for measuring current on the bit lines during read operations. Control circuitry 46 controls the various device elements to perform the various operations (program, erase, read) on the selected split-gate memory cells 10 of the array 30 as described herein. A charge pump 44 (e.g., CHRGPMP) provides various voltages used to read, program, and erase selected split-gate memory cells 10 of the array 30 under the control of the control circuitry 46. The control circuitry 46 operates the memory device to program, erase, and read selected split-gate memory cells 10 of the array 30. As part of these operations, the control circuitry 46 is enabled to access incoming data (which is data to be programmed into the selected split-gate memory cells 10 of the array 30) along with program, erase, and read commands provided on the same or different lines. Data read from the array 30 (i.e., from the selected split-gate memory cells 10 of the array 30) is provided as outgoing data.

[0040] The programming method involves control circuitry 46 performing memory cell programming. Thus, control circuitry 46 may be loaded with software (i.e., non-transitory electronically readable instructions) or firmware, or may be comprised of separate circuits, or any combination thereof, to perform the techniques described herein. Control circuitry 46 may be implemented by a microcontroller, dedicated circuitry, a processor, a general-purpose processor executing firmware or software, or any combination thereof.

[0041] In analog memory cell operation, programming can be performed by applying a programming voltage in discrete pulses, with intervening read operations verifying the programmed state between the programming pulses (i.e., sequential programming). Specifically, after each programming pulse, a program-verify read operation is performed to determine whether the selected cell has reached its corresponding target programmed state (i.e., reached its target read current Irtarget associated with the target programmed state). If the determination is yes for any given memory cell, a program-inhibit voltage can be applied to that given memory cell so that subsequent programming pulses for other cells do not further program that given memory cell. For example, once a memory cell is determined to have reached its desired programmed state, a program-inhibit voltage can be applied to the corresponding bit line to prevent further programming of that memory cell. Memory cells that are determined not to have reached their desired programmed state are programmed using additional programming pulses (also referred to as a program retry pulse train) that typically have a stepped increase in programming voltage (e.g., for the memory cell of FIG. 1 , the programming voltages placed on control gate 22, select gate 24, erase gate 26, source region 14, or a combination thereof, may be stepped higher with each successive program pulse). The program retry pulse train continues until all memory cells to be programmed have reached their target programmed state.

[0042] It has been determined that manufacturing process variations can lead to cell-to-cell variations in programming efficiency, meaning that some memory cells program faster (i.e., to a higher programmed state) than others given the same programming voltage pulse. This cell-to-cell variation can manifest as an offset (Type 1), where the starting programming state is different, or a different slope (Type 2), where the programming state increases by different amounts in response to the same incremental increase in programming voltage, or both, as illustrated in the graph of read current Ir versus programming in Figure 9. To ensure that all memory cells reach their respective target programming states with high accuracy, the program retry pulse train can be quite long, balancing several factors. For example, the amplitude of the first programming pulse voltage should be low enough so that the fastest memory cell does not overshoot its desired programming state after the first programming pulse. The voltage of the last programming pulse should be high enough so that the slowest memory cell does not overshoot its desired programming state after the last pulse and does not take too long to program. The step size of the voltage increase between pulses in the programming pulse train should be small enough so that all memory cells do not overshoot their desired programmed state by a significant amount when they reach their target programmed state. There is a trade-off between programming accuracy and throughput because larger programming voltage step sizes require fewer programming pulses but reduce programming accuracy. Conversely, smaller programming voltage step sizes require more programming pulses but provide greater accuracy.

[0043] The programming method according to the first example identifies fast and slow programmable memory cells, ideally resolving inter-cell variations manifested as the offset (Type 1) discussed above. A higher-bit threaded programming current is applied to slower memory cells during programming, while a lower-bit threaded programming current is applied to faster memory cells. This allows for a more uniform programming speed across all memory cells, thereby tightening the programming cell current distribution. In this way, the total number of programming pulses can be reduced to save power and programming time without sacrificing programming accuracy and precision.

[0044] As shown in FIG10 , in block 1, selected memory cells (i.e., those memory cells selected to be programmed to a target programmed state providing a target read current Irtarget during a read operation, which may be a subset of the memory cells in the memory cell array) may optionally undergo an erase operation. In block 2, the selected memory cells may optionally undergo pre-programming using one or more programming pulses. As non-limiting examples, pre-programming may include a single pre-programming pulse, or may include two pre-programming pulses, with the second pre-programming pulse having at least one higher programming voltage relative to the first pre-programming pulse.

[0045] In block 3, the selected memory cells are then read, where their respective read currents Ir are determined. In block 4, each memory cell is assigned to one of a plurality of groups of memory cells based on the respective determined read currents Ir, where each group is associated with a different read current range. As a non-limiting example, three groups may be used, with a first group associated with read currents less than a first reference read current Iref1, a second group associated with read currents greater than or equal to the first reference read current Iref1 but less than a second reference read current Iref2, and a third group associated with read currents greater than or equal to the second reference read current Iref2. In this example, memory cells with read currents Ir less than the first reference read current Iref1 are assigned to the first group. Memory cells with read currents Ir greater than or equal to the first reference read current Iref1 but less than the second reference read current Iref2 are assigned to the second group. Those memory cells having a read current Ir greater than or equal to the second reference read current Iref2 are assigned to the third group.

[0046] In block 5, after assigning the selected memory cells to the appropriate groups, sequential programming to target programmed states of the selected memory cells is performed (e.g., during normal operation programming, where the memory cells are programmed to the target programmed states to represent data), wherein during programming, a programming current (e.g., a bit line current) is selected for each memory cell based on the group to which the memory cell is assigned. For example, during programming to the target programmed states, a nominal programming current (e.g., 1 uA) may be provided to the memory cells assigned to the second group (e.g., via their bit lines) along with nominal programming voltages for the erase gate (e.g., 4.5 V), control gate (e.g., 6 to 11 V), select gate (e.g., 1 V), and source line (e.g., 4.5 V) during programming of the memory cells. During programming of memory cells assigned to the third group, a programming current higher than the nominal programming current (e.g., 3 μA) may be provided to those memory cells along with the above-described example programming voltages for the other gate and source lines. During programming of memory cells assigned to the first group, a programming current lower than the nominal programming current (e.g., 0.3 μA) may be provided to those memory cells along with the above-described example programming voltages for the other gate and source lines. Once a target programmed state is achieved for any given memory cell (i.e., a target read current is achieved), programming is stopped by either terminating programming pulses to that memory cell or applying a program inhibit voltage to that memory cell to prevent further programming from subsequent programming pulses used to continue programming other memory cells.

[0047] FIG11 illustrates the effect of providing different programming currents to different groups of memory cells after a pre-programming pulse, where the programming curves for the slow and fast groups (indicated by the solid lines) without programming speed compensation are shifted toward the average cell (indicated by the dashed line) by implementing programming speed compensation as described in FIG10 . This causes fast memory cells to reach their target programming state more slowly (for higher programming accuracy) and slow memory cells to reach their target programming state more quickly (for higher programming efficiency). This technique can reduce the number of programming pulses without sacrificing accuracy. FIG11 further illustrates the grouping of memory cells based on the cell read current Ir after optional pre-programming, showing slow cells assigned to the third group having a current greater than or equal to Iref2 after optional pre-programming, average memory cells assigned to the second group having a read current Ir greater than or equal to the first reference read current Iref1 but less than the second reference read current Iref2, and fast cells assigned to the first group having a current less than Iref1 after optional pre-programming.

[0048] The above examples have been described in which the "equal to" condition is resolved toward slower cells, but this is not intended to be limiting in any way. In other examples, the "equal to" condition may be resolved toward faster cells (e.g., memory cells having a read current less than or equal to a first reference read current may be assigned to a first group, memory cells having a read current greater than the first reference read current but less than or equal to a second reference read current may be assigned to a second group, and memory cells having a read current greater than the second reference read current may be assigned to a third group), or may be resolved toward average cells (e.g., memory cells having a read current less than the first reference read current may be assigned to a first group, memory cells having a read current greater than or equal to the first reference read current but less than or equal to the second reference read current may be assigned to a second group, and memory cells having a read current greater than the second reference read current may be assigned to a third group), or any possible combination, without limitation.

[0049] Although the above example utilizes two reference read currents to place the selected cell into one of three groups (where different programming currents are used to program the memory cells in the three groups), a single reference read current can be used to place the selected cell into one of two groups, or more than two reference currents can be used to place the selected cell into one of four or more groups, where different programming currents are used to program the memory cells in each group (i.e., the higher the read current for a group, the higher the programming current used in block 5 to program the memory cells in that group).

[0050] A programming method according to a second example, illustrated in Figures 12 and 13, is ideal for addressing cell-to-cell variations (manifested as the different slopes (Type 2) discussed above), where the amount by which the programming state varies from cell to cell in response to incremental increases in the same programming voltage. In Block 1, selected memory cells (i.e., those memory cells selected to be programmed to a target programming state that provides a target read current Irtarget during a read operation, which may be a subset of the memory cells in the memory cell array) may undergo an erase operation, which is optional. In Block 2, the selected memory cells may undergo a first pre-programming operation using one or more programming pulses, which is also optional. As non-limiting examples, pre-programming may include a single programming pulse, or may include two programming pulses, with the second programming pulse having at least one higher programming voltage relative to the first programming pulse. In Block 3, the selected memory cells are read to determine their respective first read currents Ir1. In block 4, the selected memory cell undergoes a second pre-programming operation, which may include one or more programming pulses. In block 5, the selected memory cell is read to determine a respective second read current Ir2. If block 2 is not performed, block 4 would be the first pre-programming operation, which may include one or more programming pulses.

[0051] In block 6, each memory cell is assigned to one of a plurality of groups of memory cells based on the respective read current differences between the first read current Ir1 and the second read current Ir2, where each group is associated with a different read current difference range. As a non-limiting example, three groups may be used, with a first group (fast) associated with read current differences greater than a first reference difference Idiff1 (i.e., the difference between Ir1 and Ir2), a second group associated with read current differences less than or equal to the first reference difference Idiff1 but greater than the second reference difference Idiff2, and a third group (slow) associated with read current differences less than or equal to the second reference difference Idiff2. In this example, memory cells having respective read current differences greater than the first reference difference Idiff1 (i.e., the difference between Ir1 and Ir2) are assigned to the first group. Memory cells having read current differences less than or equal to the first reference difference Idiff1 but greater than the second reference difference Idiff2 are assigned to the second group. Memory cells with a read current difference less than or equal to the second reference difference Idiff2 are assigned to the third group. The above example describes the "equal to" condition as being resolved towards the second and third groups, respectively. However, this is not intended to be limiting in any way. In other examples, the "equal to" condition may be resolved towards slower cells, faster cells, average cells, or any combination thereof, without limitation.

[0052] In block 7, after assigning the selected memory cells to the appropriate groups, sequential programming to the target programmed states of the selected memory cells is performed (e.g., during normal operation programming, wherein the memory cells are programmed to the target programmed states to represent data), wherein during programming, a programming current (e.g., a bit line current) is adjusted for each memory cell according to the group to which the memory cell is assigned. For example, during normal operation programming, a nominal programming current (e.g., 1 uA) may be provided to the memory cells assigned to the second group (e.g., via their bit lines) along with nominal programming voltages for the erase gate (e.g., 4.5 V), control gate (e.g., 6 to 11 V), select gate (e.g., 1 V), and source line (e.g., 4.5 V) during programming of the memory cells. During programming of memory cells assigned to the third group, a programming current (e.g., 3 uA) higher than the nominal programming current may be provided to those memory cells along with the above examples of programming voltages for other gate and source lines. During programming of memory cells assigned to the first group, a programming current (e.g., 0.3 uA) lower than the nominal programming current may be provided to those memory cells along with the above examples of programming voltages for other gate and source lines. FIG13 further illustrates the grouping of memory cells based on cell read current Ir after optional first and second pre-programming. The grouping shows slow cells assigned to a third group, having a slope greater than Idiff1 between the first and second pre-programming times, average memory cells assigned to a second group, having a slope less than or equal to a first reference difference Idiff1 but greater than a second reference difference Idiff2 between the first and second pre-programming times, and fast cells assigned to a first group, having a slope less than or equal to a second reference difference Idiff2 between the first and second pre-programming times. Once a target programmed state is achieved for any given memory cell (i.e., a target read current is achieved), programming is stopped by either terminating programming pulses to that memory cell or applying a program inhibit voltage to that memory cell to prevent further programming from subsequent programming pulses used to continue programming other memory cells.

[0053] FIG13 illustrates the effect of providing different programming currents to different groups of memory cells after pre-programming. The programming curves for the slow and fast groups (indicated by the solid lines) without programming speed compensation are shifted toward the average cell (indicated by the dashed line) by implementing programming speed compensation, causing fast memory cells to reach their target programming state more slowly (for higher programming accuracy) and slow memory cells to reach their target programming state more quickly (for higher programming efficiency). This technique can reduce the number of programming pulses without sacrificing accuracy.

[0054] Although the above example utilizes two reference change values to place the selected cell into one of three groups (where different programming currents are used to program the memory cells in the three groups), a single reference change value may be used to place the selected cell into one of two groups, or more than two reference change values may be used to place the selected cell into one of four or more groups, where different programming currents are used to program the memory cells in each group (i.e., the higher the difference in read currents between groups, the lower the programming current used in block 7 to program the memory cells in that group).

[0055] The programming method according to the third example is illustrated in FIGS. 14 to 15 and is used to program selected memory cells to a programmed state corresponding to a target read current Irtarget. In block 1, the selected memory cells are programmed by applying a programming voltage pulse and a first programming current, which can be regarded as a nominal programming current. In block 2, a read operation is performed, in which the selected memory cells are read to determine their respective read currents Ir relative to the target read current Irtarget and a reference read current Iref greater than the target read current Irtarget (e.g., Iref = Irtarget + ∆I). In block 3, for those selected memory cells having a read current Ir greater than the reference read current Iref (i.e., Ir > Iref), the programming continues by returning to block 1. In block 4, for those selected memory cells having a read current Ir greater than Irtarget and less than or equal to the reference read current Iref (i.e., Irtarget < Ir ≤ Iref), the programming continues by returning to block 1, but the selected memory cells are programmed by applying a programming voltage pulse and a second programming current, which is less than the first programming current. In block 5, for those selected memory cells having a read current Ir less than or equal to Irtarget (i.e., Ir ≤ Irtarget), the programming is stopped (i.e., by stopping any further programming pulses applied to the selected memory cells or using a programming inhibit voltage on the selected memory cells to prevent further programming from subsequent programming pulses used to continue programming other memory cells). This programming method reduces the programming speed (i.e., reduces the decrease in the read current Ir caused by each subsequent programming pulse, because the selected memory cells are close to their respective target read currents Irtarget, i.e., within the read current range between Iref and Irtarget), and thereby improves the accuracy of the final programmed level. This technique improves the accuracy of programming without sacrificing programming throughput.

[0056] The above examples have been described as "equal to" conditions resolving towards lower read currents. However, this is not intended to be restrictive in any way. In other examples, the "equal to" condition can resolve towards higher read currents, towards the range of Irtarget - Iref, or any possible combination, without limitation.

[0057] FIG15 illustrates the effect of providing different programming currents to different memory cells, where the slope of the tail end of the programming curve (indicated by the solid line) without programming speed compensation is reduced by implementing programming speed compensation (indicated by the dashed line) as described with respect to FIG14 , so that the programming speed is slowed down (for better accuracy) for those memory cells within ∆I of the target read current Irtarget, while the programming speed is not slowed down (for better speed) for those memory cells not within ∆I of the target read current Irtarget. This technique can reduce the number of programming pulses without unduly sacrificing accuracy.

[0058] Although the above example uses a single reference read current to slow the programming rate of memory cells within ∆I of the target read current Irtarget, more than one reference current can be used to gradually step down the programming rate as the memory cell approaches Irtarget (i.e., the closer the read current is to Irtarget, the lower the programming current used for programming).

[0059] In yet another example, the third example of Figures 14-15 can be combined with the first example of Figures 10-11. Specifically, blocks 1-5 of Figure 10 can be executed, but in block 5 of Figure 10, as the programming state of the memory cell approaches but has not yet reached the target programming state, blocks 1-5 of Figure 14 are then executed to complete programming. Figure 16 illustrates the effect of this example.

[0060] In yet another example, the third example of Figures 14-15 can be combined with the second example of Figures 12-13. Specifically, blocks 1-7 of Figure 12 can be executed, but in block 7 of Figure 12, as the programming state of the memory cell approaches but has not yet reached the target programming state, blocks 1-5 of Figure 14 are then executed to complete programming. Figure 17 illustrates the effect of this example.

[0061] It should be understood that the present disclosure is not limited to the examples described above and illustrated herein, but encompasses any and all variations within the scope of any technical solution. For example, references herein to the present disclosure, invention, or examples are not intended to limit the scope of any technical solution or claim, but rather to reference one or more features that may be encompassed by one or more technical solutions. Although the examples are described with respect to the quad-gate memory cell of FIG1 , the above-described techniques can equally be applied using any of the memory cell configurations of FIG1 , FIG3 , FIG5 , and FIG7 . The materials, procedures, and numerical examples described above are merely illustrative and should not be construed as limiting any technical solution.

[0062] 10: Split gate memory cell / memory cell 12: (Silicon) semiconductor substrate / substrate 14: Source region 14a: Source line 16: Drain area 16a: Bit line 18: Channel Area 20: Floating Gate 22: Control gate 22a: Control gate line 24: Select gate 24a: Select gate line 26: Erase Gate 26a: Erase gate line 28: Conductive material block 30: Array 32a: Plane A 32b: Plane B 34: Address decoder 36: Source line driver 38: Row Decoder 40: High voltage column decoder 42: Bit line controller 44: Charge Pump 46: Control circuit system

Claims

1. A method for programming memory cells, comprising: reading the memory cells to determine an individual read current of the memory cells; assigning each of the memory cells to one of a plurality of groups of memory cells, wherein each of the plurality of groups of memory cells is associated with a different read current range such that the determined read current of one of the memory cells is within the read current range of the group of memory cells to which the memory cell is assigned; and programming the memory cells using a programmed current, wherein for each of the memory cells, the programmed current varies according to the group of memory cells to which the memory cell is assigned; wherein: The plurality of groups of memory cells includes at least a first group, a second group, and a third group; the first group is associated with a read current range less than a first reference read current; the second group is associated with a read current range greater than the first reference read current and less than a second reference read current; the third group is associated with a read current range greater than the second reference read current; the programming of the memory cells assigned to the first group includes the use of a first programming current; the programming of the memory cells assigned to the second group includes the use of a second programming current; the programming of the memory cells assigned to the third group includes the use of a third programming current; the first programming current is less than the second programming current; and the second programming current is less than the third programming current.

2. A method for programmable memory cells, comprising: reading the memory cells to determine an individual read current of the memory cells; assigning each individual memory cell to one of a plurality of groups of memory cells, wherein each individual of the plurality of groups of memory cells is associated with a different read current range, such that the determined read current of one individual memory cell is within the read current range of the group of memory cells to which the memory cell is assigned; and programmable memory cells using programmable currents, wherein for each individual memory cell, the programmable currents vary according to the group of memory cells to which the memory cell is assigned; wherein... After this programming: read the memory cells to determine the respective second read current of the memory cells; program the memory cells having a second read current greater than a reference read current using a first programming current; and program the memory cells having a second read current less than the reference read current using a second programming current less than the first programming current.

3. A method for programming memory cells, comprising: reading the memory cells to determine a first read current of each of the memory cells; preprogramming the memory cells after the reading; and reading the memory cells after the preprogramming to determine a second read current of each of the memory cells. Assigning individual memory cells to one of a plurality of groups of memory cells, wherein each of the plurality of groups of memory cells is associated with a different range of read current differences, such that the difference in read current between a first read current and a second read current and between the individual memory cells is within the range of the read current differences of the group of memory cells to which the memory cell is assigned; and programming the memory cells using programmed currents, wherein for each individual memory cell, the programmed currents vary according to the group of memory cells to which the memory cell is assigned.

4. The method of claim 3, comprising: erasing the memory cells before the read of the memory cells.

5. The method of request 3, comprising: preprogramming the memory cells prior to the read of the memory cells.

6. As in request item 3, where: The plurality of groups of memory cells includes at least a first group, a second group, and a third group; the first group is associated with a read current difference range greater than a first reference difference; the second group is associated with a read current difference range greater than the first reference difference and less than a second reference difference; the third group is associated with a read current difference range greater than the second reference difference; the programming of the memory cells assigned to the first group includes the use of a first programming current; the programming of the memory cells assigned to the second group includes the use of a second programming current; the programming of the memory cells assigned to the third group includes the use of a third programming current; the first programming current is less than the second programming current; and the second programming current is less than the third programming current.

7. As in request item 3, wherein, After this programming, the method includes: reading the memory cells to determine a second read current for each of the memory cells; programming the memory cells having a second read current greater than a reference read current using a first programming current; and programming the memory cells having a second read current less than the reference read current using a second programming current less than the first programming current.

8. A method for programming memory cells, comprising: programming memory cells; reading the memory cells to determine a read current of each of the memory cells relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current; programming memory cells having a read current greater than the reference read current using a first programming current; programming memory cells having a read current less than the reference read current and greater than the target read current using a second programming current less than the first programming current; and stopping programming memory cells having a read current less than the target read current.

9. A memory device comprising: memory cells; and a control circuit system for: reading the memory cells to determine an individual read current of the memory cells; assigning each of the memory cells to one of a plurality of groups of memory cells, wherein each of the plurality of groups of memory cells is associated with a different read current range such that the determined read current of one of the memory cells is within the read current range of the group of memory cells to which the memory cell is assigned; and programming the memory cells using programmed currents, wherein for each of the memory cells, the programmed currents vary according to the group of memory cells to which the memory cell is assigned; wherein: The plurality of groups of memory cells includes at least a first group, a second group, and a third group; the first group is associated with a read current range less than a first reference read current; the second group is associated with a read current range greater than the first reference read current and less than a second reference read current; the third group is associated with a read current range greater than the second reference read current; the programming of the memory cells assigned to the first group includes the use of a first programming current; the programming of the memory cells assigned to the second group includes the use of a second programming current; the programming of the memory cells assigned to the third group includes the use of a third programming current; the first programming current is less than the second programming current; and the second programming current is less than the third programming current.

10. A memory device comprising: memory cells; and a control circuit system for: reading the memory cells to determine an individual read current of the memory cells; assigning each of the memory cells to one of a plurality of groups of memory cells, wherein each of the plurality of groups of memory cells is associated with a different read current range such that the determined read current of one of the memory cells is within the read current range of the group of memory cells to which the memory cell is assigned; and programming the memory cells using programmed currents, wherein for each of the memory cells, the programmed currents vary according to the group of memory cells to which the memory cell is assigned; wherein, After the programming of these memory cells, the control circuit system is used to: read the memory cells to determine the respective second read current of the memory cells; program the memory cells having a second read current greater than a reference read current using a first programming current; and program the memory cells having a second read current less than the reference read current using a second programming current less than the first programming current.

11. A memory device comprising: memory cells; and a control circuit system for: reading the memory cells to determine a first read current of each of the memory cells; preprogramming the memory cells after the reading; and reading the memory cells after the preprogramming to determine a second read current of each of the memory cells. The memory cells are assigned individually to one of a plurality of groups of memory cells, wherein each of the plurality of groups of memory cells is associated with a different range of read current differences, such that a read current difference between a first read current and a second read current for one of the memory cells is within the range of the read current difference of the group of memory cells to which the memory cell is assigned; and the memory cells are programmed using programmed currents, which vary for each of the memory cells according to the group of memory cells to which the memory cell is assigned.

12. The memory device as claimed in claim 11, wherein, The control circuit system is used to erase the memory cells before they are read.

13. The memory device as claimed in claim 11, wherein, The control circuit system is used to: preprogram the memory cells before the read.

14. The memory device as claimed in claim 11, wherein: The plurality of groups of memory cells includes at least a first group, a second group, and a third group; the first group is associated with a read current difference range greater than a first reference difference; the second group is associated with a read current difference range greater than the first reference difference and less than a second reference difference; the third group is associated with a read current difference range greater than the second reference difference; the programming of the memory cells assigned to the first group includes the use of a first programming current; the programming of the memory cells assigned to the second group includes the use of a second programming current; the programming of the memory cells assigned to the third group includes the use of a third programming current; the first programming current is less than the second programming current; and the second programming current is less than the third programming current.

15. The memory device as claimed in claim 11, wherein, After the programming of these memory cells, the control circuit system is used to: read the memory cells to determine the respective second read current of the memory cells; program the memory cells having a second read current greater than a reference read current using a first programming current; and program the memory cells having a second read current less than the reference read current using a second programming current less than the first programming current.

16. A memory device comprising: memory cells; and a control circuit system for: programming the memory cells; reading the memory cells to determine a read current of each memory cell relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current; programming the memory cells having a read current greater than the reference read current using a first programming current; programming the memory cells having a read current less than the reference read current and greater than the target read current using a second programming current less than the first programming current; and stopping programming the memory cells having a read current less than the target read current.

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