Iii-nitride transistor with high n doping in access region

Abstract

A novel transistor structure for use in group III nitride semiconductor structures is disclosed. The transistor includes heavily doped n++ layers located in the source and drain regions. The source and drain electrodes are disposed on their respective heavily doped n++ layers. Furthermore, in some embodiments, a portion of the gate electrode may be disposed on one or both of the heavily doped n++ regions. These regions improve the on-resistance of the transistor, particularly for low-voltage applications.

Description

Group III nitride transistors with high N-doped access regions This application claims priority to U.S. Provisional Patent Application No. 63 / 548,315, filed November 13, 2023, and U.S. Patent Application No. 18 / 937,593, filed November 5, 2024, the disclosures of which are incorporated herein by reference. The embodiments disclosed herein relate to a transistor and a method of manufacturing a transistor having low on-resistance in low-voltage applications. Figure 1 shows a typical conventional group III nitride semiconductor transistor, comprising a substrate 1, a buffer layer 2 on top of the substrate, a gallium nitride (GaN) channel layer 3 on top of the buffer layer, and an aluminum gallium nitride (AlGaN) barrier layer 4 on top of the channel layer. The substrate 1 is silicon carbide (SiC), sapphire, silicon, or a free-standing gallium nitride semiconductor. A nucleation layer exists between the buffer layer 2 and the substrate 1. The AlGaN barrier layer 4 has a wider band gap than the GaN channel 3. The source electrode 7 and drain electrode 8 are located on opposite sides of the gate electrode 6. Due to the resistance of the access region and the contact resistance, this structure has the disadvantage of relatively high on-resistance for low-voltage applications. Therefore, if a new transistor structure exists that overcomes the shortcomings of traditional device structures, it may be beneficial. A novel transistor structure for use with group III nitride semiconductor structures is disclosed. This transistor includes heavily doped n++ layers located in the source and drain regions. The source and drain electrodes are disposed on their respective heavily doped n++ layers. Furthermore, in some embodiments, a portion of the gate may be disposed on one or both of the heavily doped n++ regions. These regions increase the on-resistance of the transistor, particularly for low-voltage applications. According to one embodiment, a semiconductor structure for use in a group III nitride (III-N) semiconductor device is disclosed. The structure includes a channel layer; a barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; a source electrode disposed in a source region; and a drain electrode disposed in a drain region; a gate electrode disposed between the source electrode and the drain electrode in a gate region; a capping layer disposed between at least a portion of the gate electrode and the barrier layer; and a heavily doped n++ layer disposed on both sides of the capping layer; wherein the source electrode and the drain electrode respectively contact at least a portion of the corresponding heavily doped n++ layer. In some embodiments, the heavily doped n++ layer has a higher n-type doping density than the capping layer. In some embodiments, the heavily doped n++ layer has a density of at least 1e18 cm⁻¹. -3 One of the n-type doping densities. In some embodiments, the heavily doped n++ layer and the capping layer have different n-type doping distributions in a vertical direction. In some embodiments, a top surface of the heavily doped n++ layer is flush with a top surface of the capping layer. In some embodiments, a top surface of the heavily doped n++ layer is not flat, and a portion of the top surface adjacent to the capping layer is flush with a top surface of the capping layer. In a particular embodiment, this portion has a length between 0 nm and 2000 nm. In some embodiments, a portion of the gate electrode is disposed above the heavily doped n++ layer in the source region. In some embodiments, a portion of the gate electrode is disposed above the heavily doped n++ layer in the drain region. In some embodiments, the heavily doped n++ layer is disposed on top of the barrier layer. In some embodiments, the heavily doped n++ layer is at least partially disposed in the barrier layer. In some embodiments, the heavily doped n++ layer is disposed on top of the channel layer. In some embodiments, the heavily doped n++ layer is at least partially disposed in the channel layer. According to another embodiment, a semiconductor structure for a group III nitride (III-N) semiconductor device is disclosed. The structure includes a channel layer; a barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; a source electrode disposed in a source region; and a drain electrode disposed in a drain region; a capping layer disposed on top of the barrier layer in a gate region; a gate trench disposed between the source electrode and the drain electrode in the gate region and extending through the capping layer; a gate electrode disposed in the gate trench; and heavily doped n++ layers disposed on both sides of the capping layer; wherein the source electrode and the drain electrode respectively contact at least a portion of the opposing heavily doped n++ layers. In some embodiments, the gate trench extends to a top surface of the barrier layer. In some embodiments, the gate trench extends through at least a portion of the barrier layer. In some embodiments, a gate dielectric layer is disposed along the bottom and sidewalls of the gate trench, and the gate electrode is disposed on the gate dielectric layer. In some embodiments, the gate recess extends through a portion of one or more of the heavily doped n++ layers. In some embodiments, the heavily doped n++ layers have a higher n-type doping density than the capping layer. In some embodiments, the heavily doped n++ layers and the capping layer have different n-type doping distributions in a vertical direction. This disclosure describes a group III nitride transistor device with low on-resistance. Referring to Figure 2, the transistor structure includes a substrate 10, a buffer layer 11, a channel layer 12, a barrier layer 13, and a capping layer 14. A nucleation layer may be disposed between the buffer layer 11 and the substrate 10. The substrate 10 can be silicon carbide, sapphire, silicon, free-standing GaN, or any other substrate including a multilayer of polycrystalline aluminum nitride (AlN). A nucleation layer can be disposed between the buffer layer 11 and the surface of the substrate 10. The nucleation layer can contain AlN. A buffer layer 11 is formed above the nucleation layer. The buffer layer 11 may have a thickness between 0.5 nanometers and a few micrometers, but other thicknesses are also within the scope of this disclosure. The buffer layer 11 may include a group III nitride semiconductor comprising GaN, AlGaN, InGaN, InAlN, InAlGaN, and AlN. Channel layer 12 is formed over buffer layer 11. Channel layer 12 comprises a semiconductor material selected from AlGaN, InGaN, GaN, or any other suitable semiconductor material or combination of materials. Carriers (which can be free electrons) exist in channel layer 12 to conduct current between drain contacts and source contacts. Channel layer 12 may comprise a single layer, such as a GaN layer, or multiple layers. In one example, channel layer 12 includes a back-barrier structure, such as a GaN layer above an AlGaN layer (GaN / AlGaN) or a GaN layer above an InGaN layer and another GaN layer (GaN / InGaN / GaN). In another example, channel layer 12 has a superlattice structure formed by repeating AlGaN / GaN or AlN / GaN bilayer structures. The thickness of channel layer 12 may be greater than 5 nm, for example, between 50 nm and 400 nm, but other thicknesses may be used. A barrier layer 13 is formed above the channel layer 12. The barrier layer 13 may be made of a group III nitride semiconductor selected from AlGaN, InAlN, AlN, AlScN, or InAlGaN having a non-zero aluminum content. The barrier layer 13 may be undoped or doped with silicon or other impurities. The barrier layer 13 has a wider band gap than the channel layer 12. The barrier layer 13 can be between 0.2 nm and 30 nm in thickness. Thin barrier layers, such as those less than 10 nm, can be used. The barrier layer 13 may contain a sublayer. For example, an AlN sublayer may be adjacent to the channel layer 12, and an AlGaN or InAlN sublayer may be disposed on top of the AlN sublayer. The capping layer 14 comprises a group III nitride semiconductor, such as GaN, AlN, AlGaN, or a combination thereof. The capping layer 14 may be n-type doped or undoped. In some embodiments, the capping layer 14 may have a thin delta-doped layer. The capping layer 14 may also have different doping levels in the vertical direction. The capping layer 14 may also include sublayers. For example, the bottom of the capping layer 14 may have a sublayer made of AlN or AlGaN as an etch stop layer, and the top of the capping layer 14 may have a sublayer made of GaN disposed on top of the bottom. The thickness of the capping layer 14 may be less than 200 nm, for example, between 0.5 and 50 nm. The top of the device structure includes a gate electrode 15, a source electrode 16, and a drain electrode 17. On the opposite side of the gate, a heavily n-type doped (n++) layer 18 is formed on top of the barrier layer 13. One of these heavily doped n++ layers is called the source region, and the other is called the drain region. The composition of this heavily doped n++ layer 18 can be different from or the same as the capping layer 14. Furthermore, the doping distribution of the heavily doped n++ layer differs from that of the capping layer 14. The heavily doped n++ layer 18 has a doping density higher than 1e18 cm⁻¹. -3 The n-type doping density. In some embodiments, the heavily doped n++ layer 18 can have 1e20 cm⁻¹. -3 Or a higher n-type doping density. The capping layer 14 can have a lower doping density or a different doping distribution in the vertical (or height) direction. The n-type dopant can be silicon. The heavily doped n++ layer 18 is made of a group III nitride semiconductor, such as GaN, InGaN, or AlGaN. The heavily doped n++ layer 18 may not have the same sublayers as in the capping layer 14. For example, the etch stop sublayer of the capping layer 14 may not be present in the heavily doped n++ layer 18. The heavily doped n++ layer 18 can be formed by epitaxial growth such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). The heavily doped n++ layer 18 can also be formed by ion distribution. Source electrode 16 and drain electrode 17 are deposited on heavily doped n++ layers 18 in the source and drain regions, respectively. Source electrode 16 and drain electrode 17 are in contact with at least a portion of the heavily doped n++ layers 18 in the source and drain regions, respectively. Source electrode 16 and drain electrode 17 may be made of Ti, TiN, Al, W, Au, or other suitable materials and / or combinations of materials forming ohmic contacts with the heavily doped n++ layers 18. Gate electrode 15 is deposited on capping layer 14. Gate electrode 15 may be made of materials such as Ni, Ti, TiN, W, WN, Pt, Al, Au, polycrystalline silicon, and any other suitable conductive materials and combinations thereof. A passivation dielectric material 19 may be deposited on top of the exposed portions of the capping layer 14 and the heavily doped n++ layer 18. The passivation dielectric material 19 may be made of materials such as SiO2. 2. Si x N y SiO x N y Al 2O 3. HfO 2. Made of dielectric materials and any other suitable dielectric materials. Figure 2 shows that the tops of the heavily doped n++ layer 18 and the top of the capping layer 14 are aligned at the same height at their junction boundary, such that the top surface of the heavily doped n++ layer 18 is flush with the top surface of the capping layer 14. Figure 2 also shows that the top surface of the heavily doped n++ layer 18 is flat. However, other embodiments are also possible. Figure 3 shows an example of a heavily doped n++ layer 18 with non-flat surfaces in the source and drain regions. The height difference of the heavily doped n++ layer 18 can be hundreds of nanometers. At the boundary between the heavily doped n++ layer 18 and the capping layer 14, a portion of the heavily doped n++ layer 18 of length L has the same height and is flush with the top surface of the capping layer 14. The length L can range from 0 nm to greater than 2000 nm. Other components in Figure 3 are as described with respect to Figure 2. Please note that in Figures 2 and 3, the gate electrode 15 does not overlap with the heavily doped n++ layer 18. However, other embodiments are also possible. In another embodiment, as shown in FIG4, the gate electrode 15 is formed on a portion of the top surface of the capping layer 14 and overlaps with the heavily doped n++ layer 18 in the source region. In another embodiment (not shown), the gate electrode 15 may overlap with the heavily doped n++ layer 18 in both the source and drain regions. The gate electrode 15 may form a Schottky contact with the capping layer 14, or a gate dielectric material may be disposed between the gate electrode 15 and the capping layer 14 and the underlying heavily doped n++ layer 18. Other components in FIG4 are as described with respect to FIG2. In the foregoing embodiment, the heavily doped n++ layer 18 is deposited on top of the barrier layer 13. However, other embodiments are also possible. As shown in Figure 5, the heavily doped n++ layer 18 can extend through the barrier layer 13 and into the channel layer 12. In another embodiment (not shown), the heavily doped n++ region can extend into the barrier layer 13 but not into the channel layer 12. In another embodiment (not shown), the heavily doped n++ region can extend through the barrier layer 13 and be disposed on top of the channel layer 12. Other components in Figure 5 are as described with respect to Figure 2. Figure 6 shows another embodiment in which a gate recess is formed in the gate region through a portion of the heavily doped n++ layer 18 in the capping layer 14 and the source region. The gate recess may also be etched through a portion of the heavily doped n++ layer 18 in the source and drain regions. The bottom of the gate recess may be located at the top surface of the barrier layer 13, as shown in Figure 6, or inside the barrier layer 13 or in the channel layer 12. A gate dielectric layer 20 is formed in the gate recess, and a gate electrode 15 is formed above the gate dielectric layer 20. The gate dielectric layer 20 may be along the bottom and sides of the gate recess. The gate dielectric layer 20 may be made of a dielectric material, such as Si. x N y SiO 2. Si x O y N z Al 2O 3. AlN, AlO x N y Or any other suitable dielectric material or combination thereof. Other components in Figure 6 are as described with respect to Figure 2. It should be noted that these are not the only embodiments. For example, the flat, heavily doped n++ layer 18 shown in FIG2 can be used with any of the embodiments in FIG4 to FIG6. The deeper, heavily doped n++ layer 18 shown in FIG5 can also be used with the offset gate electrode 15 shown in FIG4, or with the gate dielectric layer 20 shown in FIG6. The gate groove and gate dielectric layer 20 shown in FIG6 can be used with any of the embodiments in FIG2 to FIG5. Each transistor shown in Figures 2 to 6 can be a normally-on transistor, which has electrons in the channel layer 12 located below the gate electrode 15 when the gate electrode 15 connecting the source and drain is not biased; or it can be a normally-off transistor, in which electrons are not present in the channel layer 12 below the gate when the gate electrode 15 is not biased. Figure 7 illustrates the fabrication sequence that can be used to create the device structure of Figure 2. First, as shown in box 700, a buffer layer 11, a channel layer 12, a barrier layer 13, and a capping layer 14 are deposited on substrate 10. Then, as shown in box 710, a sacrificial dielectric layer is deposited on top of the capping layer 14. The region where the heavily doped n++ layer 18 will form is then etched. This etching extends at least through the sacrificial layer and the capping layer 14. In some embodiments, the etching extends to the barrier layer 13 and optionally to the channel layer 12. Next, as shown in box 720, the heavily doped n++ layer 18 is grown in the etched region. This can be accomplished using MBE or MOCVD. Next, as shown in box 730, the sacrificial dielectric layer and any n++ layers grown on it are removed. As shown in box 740, the protective dielectric material 19 can then be deposited on the top surface of the structure. As shown in box 750, the protective dielectric material 19 is then etched to form an opening for the gate electrode 15. The gate electrode 15 is then formed in this opening. Finally, as shown in box 760, the protective dielectric material is etched to form openings for the source electrode 16 and the drain electrode 17. These electrodes are then formed in these openings. This manufacturing sequence can be varied. For example, the formation order of the gate electrode 15, as well as the source and drain electrodes, can be changed. Additionally, extra process steps, not shown here, include depositing additional dielectric layers, forming field plates, and interconnects. In addition, additional protective dielectric and field plate structures can be applied to the transistors shown in Figures 2 to 6. Furthermore, the gate electrode 15, source electrode 16, and drain electrode 17 may have overhang or sloped sidewalls in addition to the rectangular shapes shown in Figures 2 to 6. The system described in this paper has many advantages. Even in low-voltage applications, the use of the heavily doped n++ layer 18 reduces the on-resistance. Furthermore, the shape of the heavily doped n++ region reduces the transistor source resistance and parasitic capacitance. The scope of this disclosure is not limited to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure, besides those described herein, will be apparent to those skilled in the art from the foregoing description and drawings. Therefore, such other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, although this disclosure has been described herein in the context of a specific implementation in a specific environment for a particular purpose, those skilled in the art will recognize that its usefulness is not limited thereto and that this disclosure can be beneficial. Multiple purposes are implemented in any number of environments. Therefore, the claims set forth below should be interpreted in accordance with the full breadth and spirit of this disclosure as described herein. 1: Substrate 2: Buffer Layer 3: Gallium Nitride Channel Layer 4: Gallium Al Nitride Barrier Layer 6: Gate Electrode 7: Source Electrode 8: Drain Electrode 10: Substrate 11: Buffer Layer 12: Channel Layer 13: Barrier Layer 14: Capping Layer 15: Gate Electrode 16: Source Electrode 17: Drain Electrode 18: Heavily N-type Doped (n++) Layer 19: Protective Dielectric Material 20: Gate Dielectric Layer L: Length 700: Box 710: Box 720: Box 730: Box 740: Box 750: Box 760: Box For a better understanding of this disclosure, reference may be made to the accompanying drawings incorporated herein by reference, wherein: Figure 1 shows a design of a conventional group III nitride transistor according to the prior art; Figure 2 shows an improved group III nitride transistor including a heavily doped n++ region; Figure 3 shows a variation of the group III nitride transistor of Figure 2; Figure 4 shows a variation of the group III nitride transistor of Figure 3; Figure 5 shows a variation of the group III nitride transistor of Figure 3; Figure 6 shows a variation of the group III nitride transistor of Figure 4; and Figure 7 is a flowchart showing the sequence for manufacturing any of the group III nitride transistors shown in the figures. 10: Base 11: Buffer layer 12: Channel Layer 13: Barrier Layer 14: Covering layer 15: Gate electrode 16: Source electrode 17: Drain electrode 18: Heavily doped n++ layers 19: Protective dielectric layer

Claims

1. A semiconductor structure for a group III nitride (III-N) semiconductor device, comprising: One channel layer; A barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; a source electrode disposed in a source region and a drain electrode disposed in a drain region; a gate electrode disposed between the source electrode and the drain electrode in a gate region; a capping layer disposed between at least a portion of the gate electrode and the barrier layer; and a heavily doped n++ layer disposed on both sides of the capping layer, wherein a top surface of the heavily doped n++ layer is not flat, and a portion of the top surface adjacent to the capping layer is flush with a top surface of the capping layer; wherein the source electrode and the drain electrode respectively contact at least a portion of the corresponding heavily doped n++ layer.

2. The semiconductor structure of claim 1, wherein the heavily doped n++ layer has a higher n-type doping density than the capping layer.

3. The semiconductor structure of claim 1, wherein the heavily doped n++ layer has an n-type doping density of at least 1e18 cm-3.

4. The semiconductor structure of claim 1, wherein the heavily doped n++ layer and the capping layer have different n-type doping distributions in a vertical direction.

5. The semiconductor structure of claim 1, wherein the portion has a length between 0 nm and 2000 nm.

6. The semiconductor structure of claim 1, wherein a portion of the gate electrode is disposed on the heavily doped n++ layer in the source region.

7. The semiconductor structure of claim 6, wherein a portion of the gate electrode is disposed on the heavily doped n++ layer in the drain region.

8. The semiconductor structure of claim 1, wherein the heavily doped n++ layer is disposed on top of the barrier layer.

9. The semiconductor structure of claim 1, wherein the heavily doped n++ layer is at least partially disposed in the barrier layer.

10. The semiconductor structure of claim 1, wherein the heavily doped n++ layer is disposed on top of the channel layer.

11. The semiconductor structure of claim 1, wherein the heavily doped n++ layer is at least partially disposed in the channel layer.

12. A semiconductor structure for a group III nitride (III-N) semiconductor device, comprising: One channel layer; A barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; A source electrode is disposed in a source region, and a drain electrode is disposed in a drain region; a capping layer is disposed on top of the barrier layer in a first portion of a gate region, wherein the gate region is disposed between at least a portion of the gate electrode and the barrier layer; a gate groove is disposed in a second portion of the gate region and passes through the capping layer; a gate electrode is disposed in the gate groove; and a heavily doped n++ layer is disposed on both sides of the capping layer, wherein a top surface of the heavily doped n++ layer is not flat, and a portion of the top surface adjacent to the capping layer is flush with a top surface of the capping layer; wherein the source electrode and the drain electrode respectively contact at least a portion of the opposing heavily doped n++ layer.

13. The semiconductor structure of claim 12, wherein the gate recess extends to a top surface of the barrier layer.

14. The semiconductor structure of claim 12, wherein the gate recess extends through at least a portion of the barrier layer.

15. The semiconductor structure of claim 12, wherein a gate dielectric layer is disposed along the bottom and sidewalls of the gate recess, and the gate electrode is disposed on the gate dielectric layer.

16. The semiconductor structure of claim 12, wherein the gate recess extends through a portion of one or more of the heavily doped n++ layers.

17. The semiconductor structure of claim 12, wherein the heavily doped n++ layer has a higher n-type doping density than the capping layer.

18. The semiconductor structure of claim 12, wherein the heavily doped n++ layer and the capping layer have different n-type doping distributions in a vertical direction.

19. The semiconductor structure of claim 1, wherein the capping layer is located beneath the entire gate electrode.

20. The semiconductor structure of claim 1, wherein the heavily doped n++ layer is disposed below a portion of the gate electrode, and wherein the entire heavily doped n++ layer disposed below the gate electrode is flush with the capping layer.

21. The semiconductor structure of claim 12, wherein the capping layer is disposed only on one side of the gate recess, and a top surface of the heavily doped n++ layer located on the other side of the gate recess is flush with a top surface of the capping layer.

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