Package structure and method for fabricating the same

Abstract

A method for manufacturing a package structure includes placing an integrated voltage regulator in a first package element, placing a resistor-capacitor element in a second package element, electrically connecting the resistor-capacitor element to the integrated voltage regulator, and electrically connecting a device die to the resistor-capacitor element. The resistor-capacitor element is located in the conductive path connecting the integrated voltage regulator to the device die.

Description

[Technical Field]

[0001] This disclosure relates to a packaging structure and a method of manufacturing the same, and more particularly to a packaging structure and a method of manufacturing the same having a resistor-capacitor element electrically connected to an integrated voltage regulator. [Previous Technology]

[0002] Voltage regulators are used in integrated circuits to provide power. A voltage regulator has the ability to regulate the supply voltage. Within a package, a voltage regulator can be formed as a discrete die bonded to a printed circuit board. The voltage generated by the voltage regulator is supplied to integrated circuit elements also bonded to the printed circuit board. [Summary of the Invention]

[0003] This disclosure provides a method for manufacturing a package structure, including placing an integrated voltage regulator in a first package element; placing a resistor-capacitor element in a second package element; electrically connecting the resistor-capacitor element to the integrated voltage regulator; and electrically connecting a first device die to the resistor-capacitor element, wherein the resistor-capacitor element is located in the conductive path connecting the integrated voltage regulator to the first device die.

[0004] This disclosure provides a package structure including an integrated voltage regulator, a resistor-capacitor element located above and electrically coupled to the integrated voltage regulator, a first element die located above the integrated voltage regulator and the resistor-capacitor element, a first electrical connection path connecting the integrated voltage regulator to the input terminal of the resistor-capacitor element, and a second electrical connection path connecting the output terminal of the resistor-capacitor element to the first element die.

[0005] This disclosure provides a packaging structure including a packaging substrate, which includes a first redistribution structure; a dielectric core located above the first redistribution structure; a second redistribution structure located above the dielectric core; a plurality of vias located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator located in the dielectric core; a resistive-capacitive element located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a packaging element located above the packaging substrate and bonded to the packaging substrate, wherein the packaging element includes a device die electrically connected to the resistive-capacitive element.

Implementation Method

[0007] The following disclosure provides many different embodiments or examples to implement different features of the embodiments disclosed herein. Reference numerals and / or letters may be repeated in the various examples described in this disclosure. These repetitions are for the purpose of brevity and clarity and do not in themselves imply any relationship between the various embodiments and / or configurations disclosed. In addition, specific examples of components and configurations are described below to simplify the description of the embodiments disclosed herein. Of course, these specific examples are merely illustrative and are not intended to limit the embodiments disclosed herein. For example, in the following description, it is mentioned that a first feature is formed on or above a second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, or it may include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetitions are for the purpose of brevity and clarity and do not in themselves limit the relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatial terms may be used herein. For example, terms such as "below," "under," "lower," "above," "higher," and similar terms are used to describe the relationship between one element or feature depicted in the diagram and another element(s). In addition to the orientation shown in the diagram, these spatial terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial terms used herein may be interpreted in the same way.

[0009] A package comprising an integrated voltage regulator (IVR) and resistive-capacitor (RC) elements is provided, and a method for manufacturing the same. According to some embodiments of this disclosure, the integrated voltage regulator and resistive-capacitor elements are embedded within the package. The integrated voltage regulator and resistive-capacitor elements may be embedded in the core of the package substrate, an add-on structure of the package substrate, an underfill, a redistribution structure, a layer for forming local silicon interconnect (LSI) dies, and / or other similar structures. The resistive-capacitor elements are located close to the integrated voltage regulator. Furthermore, the resistive-capacitor elements may be located in the path between the integrated voltage regulator and a powered device supplied with the regulated voltage, thereby reducing the resistance of the connection lines. By incorporating the integrated voltage regulator and resistive-capacitor elements, transient overshoot of the integrated voltage regulator can be reduced.

[0010] The embodiments described in this disclosure will provide examples of how the subject matter of this disclosure can be implemented or used, and those skilled in the art to which this application pertains will readily understand the modifications that may be made within the considerations of different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be described as being performed in a particular order, other method embodiments may be performed in any logical order.

[0011] Figures 1 through 9 illustrate schematic diagrams of intermediate stages in the manufacture of a package including an integrated voltage regulator and resistive-capacitive elements according to some embodiments of the present disclosure. The corresponding process is also schematically shown in the process flow shown in Figure 22.

[0012] Figure 1 illustrates a carrier 20 and a release film 22 formed on the carrier 20. The release film 22 may be formed of a polymer-based material (e.g., a light-to-heat-conversion (LTHC) material) that is capable of decomposition under heat-carrying radiation, such as a laser beam, so that the carrier 20 can be debonded from the overlay structure to be formed in subsequent processes.

[0013] An add-in structure 24 (also known as a redistribution structure 24 or interconnect structure 24) is formed above the carrier 20. The corresponding process is illustrated in process 202 of process flow 200 shown in Figure 22. The add-in structure 24 includes a plurality of dielectric layers 26 and a plurality of redistribution lines (RDLs) 28 formed above the release film 22. The dielectric layers 26 may be formed of polymers, or they may be photosensitive materials, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which can be patterned using a lithography process including exposure and development processes.

[0014] The redistribution line 28 can be formed by electroplating. The formation of the redistribution line 28 may include forming a metal seed layer (not shown), forming a patterned mask (not shown), such as photoresist, over the metal seed layer, and performing a metal plating process on the exposed seed layer. Subsequently, the patterned mask and the portion of the metal seed layer covered by the patterned mask are removed, leaving the redistribution line 28. The metal seed layer can be formed using, for example, physical vapor deposition (PVD) or a similar process. Plating can be performed using, for example, electrochemical plating or chemical plating processes. The plating material may include copper.

[0015] Next, as shown in Figure 2, a metal pillar 30 is formed. The corresponding process is illustrated as process 204 in process flow 200 shown in Figure 22. The manufacturing process may include forming a metal seed layer, forming a plating mask (not shown, e.g., photoresist) over the metal seed layer, patterning the plating mask to expose the underlying metal seed layer, and then plating a metal material in the openings of the plating mask. The plating mask is then removed, followed by an etching process to remove portions of the metal seed layer previously covered by the plating mask.

[0016] The metal pillar 30 is optionally referred to as a through-hole because it will penetrate the subsequently formed encapsulation material (which may also be a molding compound). The plated metal material may be copper or a copper alloy. The metal pillar 30 may have generally vertical and straight edges. According to an alternative embodiment, a conductive tube (also referred to as a plated through-hole (PTH)) is formed. The formation of the plated through-hole can be substantially the same as the formation of the metal pillar 30.

[0017] Figure 2 further illustrates the placement / attachment of the integrated regulator die 32. The corresponding process is illustrated as process 206 in process flow 200 as shown in Figure 22. The integrated regulator die 32 may be attached to the redistribution structure 24, for example, through a die attachment film 34 (which is an adhesive film). The integrated regulator die 32 includes electrical connectors 36A and 36B (collectively referred to as electrical connectors 36), which may include input nodes and output nodes. According to some embodiments, electrical connectors 36A and 36B may be metal pillars.

[0018] Figure 19 illustrates a circuit diagram of an exemplary integrated voltage regulator die 32 according to some embodiments. The input node 36A of the integrated voltage regulator die 32 is used to receive a high input voltage Vi, such as 15V, 9V, etc. According to some embodiments, the switching voltage VSW and the output voltage Vo are also illustrated in Figure 19. Other supply voltages, such as 5V, 3.3V, 1.2V, 0.9V, and 0.75V, are generated at the output node 36B (according to some embodiments, also the electrical connector 36B in Figure 2) through a driver integrated circuit (IC) and other circuitry.

[0019] Next, referring to Figure 3, the integrated voltage regulator chip 32 and the metal pillar 30 are encapsulated in encapsulating adhesive 38. The corresponding process is illustrated as process 208 in process flow 200 shown in Figure 22. The encapsulating adhesive 38 fills the gaps between adjacent metal pillars 30 and the integrated voltage regulator chip 32. The encapsulating adhesive 38 includes glass fiber, prepreg (which includes epoxy resin, resin and / or glass fiber), resin-coated copper foil (RCC), glass, plastics (e.g., polyvinyl chloride (PVC), acrylonitrile, butadiene & styrene (ABS), polypropylene (PP), polyethylene (PE), polystyrene (PS), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonates (PC), polyphenylene sulfide (PPS), flexible materials (e.g., polyimide), molding compounds, molding underfills, epoxy resin, resin or combinations thereof.

[0020] When formed from a molding compound, the encapsulating adhesive 38 may include a substrate material and filler particles in the substrate material. The substrate material may be a polymer, resin, epoxy resin, etc. The filler particles may be dielectric particles such as SiO2, Al2O3, and silicon dioxide, and may have a spherical shape. Furthermore, the spherical filler particles may have a variety of different diameters.

[0021] Next, a planarization process, such as chemical mechanical polishing (CMP) or mechanical abrasion, is performed to thin the encapsulant 38 until the metal pillar 30 and the integrated voltage regulator die 32 are exposed. Due to the planarization process, the top of the via 30 is substantially flush with (coplanar with) the top surface of the electrical connector 36 and substantially coplanar with the top surface of the encapsulant 38. Throughout this specification, the metal pillar 30 is also referred to as the via 30 because it penetrates the encapsulant 38. The encapsulant 38 serves as the dielectric core (and is also referred to as the dielectric core 38) in the corresponding encapsulation substrate.

[0022] Figure 4 illustrates the formation of a redistribution structure 40 (also referred to as an interconnect structure), which includes a dielectric layer 42 and redistribution lines 44. The corresponding process is illustrated as process 210 in process flow 200 as shown in Figure 22. The redistribution structure 40 is alternatively referred to as an add-on structure 40 or an interconnect structure 40. The formation of the redistribution structure 40 can be substantially the same as the formation of the redistribution structure 24. The dielectric layer 42 can be formed of an organic material, such as PBO, polyimide, etc.

[0023] Referring to Figure 5, an opening 46 is formed in the dielectric layer 42 of the redistribution structure 40. The corresponding process is illustrated as process 212 in process flow 200 as shown in Figure 22. According to some embodiments, the forming process may include an etching process in which an etch mask (e.g., photoresist) is formed to define the size and location of the opening 46. The metal pad 48 may be formed as an etch stop layer (or a laser ablation stop layer). The metal pad 48 is also formed in the same process as the corresponding layer forming the redistribution line 44. The metal pad 48 may be electrically floating or may have an electrically connected function, such as current flowing through it.

[0024] According to an alternative embodiment, the opening 46 penetrates the dielectric layer 42, exposing the top surface of the encapsulant 38 and serving as an etch stop layer.

[0025] Figure 5 also illustrates the placement of the resistive-capacitive element 50 within the opening 46. The corresponding process is illustrated as process 214 in process flow 200 as shown in Figure 22. According to some embodiments, placement is achieved using a die attachment film 54, which attaches the resistive-capacitive element 50 to the metal pad 48. According to an alternative embodiment, the opening 46 is formed such that the resistive-capacitive element 50 can fit snugly within the opening 46, wherein the sidewalls of the resistive-capacitive element 50 are in physical contact with the sidewalls of the dielectric layer 42. According to some embodiments, the sidewalls of the resistive-capacitive element 50 may be separated from or in physical contact with the redistribution line 44. For example, the resistive-capacitive element 50 may include an electrical connector 52 (which includes electrical connectors 52A and 52B).

[0026] The resistive-capacitive element 50 can have various structures. For example, Figure 19 illustrates that the resistive-capacitive element 50 may include a plurality of resistors 58 and a plurality of capacitors 60. The resistors 58 and capacitors 60 may form a unit, and the resistive-capacitive element 50 may include a plurality of units connected in parallel.

[0027] Figure 20 illustrates a resistive-capacitive element 50 comprising a single resistor 58 and a single capacitor 60 according to some embodiments. It should be understood that the integrated regulator die 32 and the resistive-capacitive element 50 may have many application forms other than those shown in Figures 19 and 20, and the corresponding integrated regulator die 32 and resistive-capacitive element 50 are also within the scope of this disclosure.

[0028] According to some embodiments, as shown in Figure 6, a gap-filling region 56 is formed to fill the remainder of the opening 46. The corresponding process is illustrated as process 216 in process flow 200 as shown in Figure 22. According to some embodiments, the gap-filling region 56 is formed of or includes materials such as an underfill, polymer, resin, epoxy resin, etc. The gap-filling region 56 is dispensed into the opening 46, then cured into a solid after dispensing, and subsequently planarized so that its top surface is flush with the top surface of the redistribution structure 40 and the electrical connector 52. The gap-filling region 56 is in physical contact with the dielectric layer 42 and may or may not be in physical contact with some redistribution lines 44 on the opposite side of the gap-filling region 56. According to some embodiments, the gap-filling region 56 may also be in physical contact with the top surface of the metal pad 48.

[0029] According to some embodiments, the structure above the release film 22 is referred to as a (wafer-level) packaging substrate 61, which may include one or more packaging substrates. According to some embodiments, the packaging substrate 61 may be debonded from the carrier 20. The corresponding process is illustrated as process 218 in process flow 200 as shown in Figure 22. The separation process may include projecting radiation (e.g., a laser beam) onto the release film 22, the laser beam penetrating the carrier 20. The release film 22 thus decomposes, and the packaging substrate 61 may be debonded from the carrier 20.

[0030] According to some embodiments, as shown in Figure 7, under-bump metal 63 and solder regions 62 may be formed on the bottom side of the package substrate 61. One of the solder regions 62 is electrically connected to the integrated regulator die 32 to provide an input voltage to the integrated regulator die 32. The package substrate 61 may include a plurality of identical package substrates 61', each package substrate 61' including the integrated regulator die 32 and resistive-capacitive elements 50.

[0031] According to an alternative embodiment, the debonding of the encapsulation substrate 61 from the carrier 20 can be performed in a subsequent process, for example, after the encapsulation element 82 (also referred to as the encapsulation body) has been bonded to the carrier 20.

[0032] According to some embodiments, the package substrate 61 can be monolithized during the dicing process, such that the plurality of individual package substrates 61' are separated from each other. According to an alternative embodiment, the dicing of the package substrate 61 into individual package substrates 61' can be performed in a subsequent process, for example, after the plurality of package elements 82 have been bonded to the package substrate 61'.

[0033] Figure 7 further illustrates a package element 82 (also referred to as a package body) according to some embodiments. The formation of the package element 82 may include forming a redistribution structure 64, which includes a plurality of dielectric layers 66 and redistribution lines 68. The materials and forming processes of the dielectric layers 66 and redistribution lines 68 may be substantially the same as those of the dielectric layer 26 and redistribution lines 28 in the redistribution structure 24, respectively. Solder regions 63 may be formed below and electrically connected to the redistribution lines 68.

[0034] A via 70 is formed above and electrically connected to the redistribution line 68. The forming process can be substantially the same as that of the via 30, and may include plating the via 70 directly from a metal pad in the redistribution line 68.

[0035] According to some embodiments, device die 72 is bonded to redistribution structure 64. Device die 72 may include local silicon interconnect dies for electrically interconnecting the packaged elements 84 above. Device die 72 may also include passive device dies, such as deep trench capacitor dies. According to some embodiments, the local silicon interconnect die includes a semiconductor substrate 78 and a through-silicon via (TSV, also known as a silicon via) 76. The through-silicon via 76 and via 70 electrically connect redistribution line 68 to the redistribution line 80 above.

[0036] The through-hole 70 and the device die 72 are encapsulated in an encapsulating adhesive 74, which may include a molding compound, a molding underfill, or may include an inorganic material, such as a silicon nitride layer and a silicon oxide region above the silicon nitride layer.

[0037] The package element 82 may further include a redistribution structure 76 located above the device die 72. The redistribution structure 76 may include a plurality of dielectric layers 78 and a plurality of redistribution lines 80. The materials and forming processes of the dielectric layers 78 and the redistribution lines 80 may be substantially the same as those of the redistribution structure 24.

[0038] Packaged elements 84 (including packaged elements 84A and 84B) are bonded to the redistribution structure 76. The corresponding process is illustrated as process 216 in process flow 200 as shown in Figure 22. The bonding of packaged elements 84 to the redistribution structure 76 can be performed by solder bonding, metal-to-metal direct bonding, hybrid bonding (including metal-to-metal direct bonding and fusion bonding), etc.

[0039] Package element 84A (also referred to as device die when it includes a device die) may be a high-bandwidth memory (HBM) stack. Package element 84B may be an independent device die, a system-on-chip (SoC) die, etc. Package element 84B may also include a deep-trench capacitor (DTC), an active device die, or an independent passive device (IPD).

[0040] According to some embodiments, the encapsulation element 84 may be encapsulated in an encapsulating adhesive 86, which may include a molding compound, a molding underfill, etc. An underfill may also be present in the gap between the encapsulation element 84 and the underlying redistribution structure 76.

[0041] Figure 8 illustrates the bonding of a package element 82 (also referred to as a package body) to a package substrate 61' according to some embodiments. This forms a package body 90. The bonding can be achieved by solder bonding using solder areas 63. Underfill 88 is also distributed in the gap between the package substrate 61' and the package element 82.

[0042] According to some embodiments where the package substrate 61' has been cut into package substrate 61, die-on-die bonding is performed, and a single package element 82 can be bonded to an individual package substrate 61'. According to these embodiments, the edge of the single package element 82 may extend laterally beyond the corresponding edge of the package substrate 61', be perpendicularly aligned with the corresponding edge of the package substrate 61', or be laterally recessed from the corresponding edge of the package substrate 61'.

[0043] According to an alternative embodiment, a wafer-level die bonding process is performed, wherein a plurality of package elements 82 are bonded to a package substrate 61 (including a plurality of uncut package substrates 61'), which is wafer-level. After the plurality of package elements 82 are bonded to the package substrate 61, an additional packaging process can be performed to encapsulate the plurality of package elements 82 in an additional encapsulating adhesive 86, which is located above the wafer-level package substrate and in physical contact with the wafer-level package substrate 61. Next, a dicing process is performed to dic the resulting package into a plurality of identical packages, each package including a package substrate 61' and a package element 82.

[0044] According to the embodiment of wafer-on-die bonding, the edge of the package element 82 is laterally recessed from the corresponding edge of the underlying package substrate 61'. The outer edge of the additional encapsulant 86 is vertically aligned with the edge of the underlying package substrate 61'.

[0045] Figure 9 illustrates the bonding of package 90 to package element 92 to form package 94. In the resulting package 94, an input voltage (which may be a relatively high voltage) can be provided from package element 92 to package substrate 61'. According to some embodiments, the voltage input path from package element 92 to integrated regulator die 32 is shown by arrow 96.

[0046] Arrow 98 illustrates the voltage conduction path from the integrated regulator die 32 to the output voltage of the powered device. According to some embodiments, the powered device includes a package element 84. The output voltage, which may be 3.3V, 1.2V, 0.9V, 0.75V, etc., is conducted via redistribution line 44 to the resistive-capacitive element 50, and further to the solder area 63 and redistribution line 68. The output voltage is further conducted to the redistribution line 80 and the package element 84 through vias 70 and / or substrate vias 76 in the device die 74.

[0047] According to some embodiments, the transient overshoot of the integrated regulator output is reduced because the resistor-capacitor element 50 is located in the path between the integrated regulator die 32 and the package element 84. For example, Figure 21 illustrates the output voltage of the integrated regulator as a function of time. Line 102 illustrates the voltage transient before the integrated regulator die 32 reaches a steady state when it is not connected to the resistor-capacitor element 50. Line 104 illustrates the voltage transient before the integrated regulator die 32 reaches a steady state when it is connected to the resistor-capacitor element 50. Transient overshoot can damage the powered device, leading to serious reliability problems. Therefore, the package according to the embodiments of this disclosure is more reliable.

[0048] Additionally, as shown in Figures 19 and 20, inductors LP1 and LP2 represent the parasitic inductance of the metal wires in the conduction path 98 (Figure 9). The parasitic inductance is also reduced by placing the resistor-capacitor element 50 in the path between the integrated regulator die 32 and the package element 84 (which is represented as the load resistor Rload).

[0049] Figure 10 shows an enlarged view of a portion of the package 94 in Figure 9, wherein the portion shown includes the integrated voltage regulator die 32 and the resistor-capacitor element 50. The redistribution line 44 is shown as including metal lines and metal vias connecting the metal lines.

[0050] Figure 11 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of this disclosure. Unless otherwise stated, the materials, structures, and forming processes of the elements in these embodiments (and the subsequent embodiments shown in Figures 13 through 18) are substantially the same as those of similar elements indicated by similar reference numerals in the foregoing embodiments. The details regarding materials, structures, and forming processes described in each embodiment throughout the specification apply to all other applicable embodiments and will not be repeated.

[0051] In Figure 11, the integrated voltage regulator die 32 is not located in the dielectric core 38, but in the redistribution structure 40, and may or may not be in contact with the dielectric layer 42. The placement of the integrated voltage regulator die 32 can be approximately the same as that of the resistor-capacitor elements 50 shown in Figures 5 and 6, and will not be described again here. The integrated voltage regulator die 32 can be encapsulated in encapsulant 56, or it can be tightly fitted into an opening in the redistribution structure 40, thus making physical contact with the dielectric layer 42. The integrated voltage regulator die 32 may or may not be in physical contact with the redistribution line 44.

[0052] The resistive-capacitive element 50 is located in the redistribution structure 64. According to some embodiments, after the redistribution structure 64 is formed, an opening is formed in the redistribution structure 64, and the resistive-capacitive element 50 is placed in the opening and flip-chip bonded to the redistribution line 68. Next, an encapsulating adhesive (not shown in Figure 11, see Figure 12) such as underfill 56 is dispensed to encapsulate the resistive-capacitive element 50. The underfill 56 may have portions located directly above the resistive-capacitive element 50, as shown in Figure 12, or it may be removable from the area directly above the resistive-capacitive element 50.

[0053] As shown in voltage conduction path 98, resistor-capacitor element 50 is also located in the path used to conduct the output voltage from integrated regulator die 32 to package element 84, and thus reduces transient overshoot.

[0054] Figure 12 shows an enlarged view of a portion of the package 94 in Figure 11, wherein the portion shown includes resistive and capacitive elements 50. The redistribution line 68 is shown as including metal lines and metal through-holes connecting the metal lines.

[0055] Figure 13 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. An integrated voltage regulator die 32 is located within the redistribution structure 64 and may or may not be in contact with the dielectric layer 66. The placement of the integrated voltage regulator die 32 may be substantially the same as the placement of the resistive-capacitive elements 50 shown in Figures 5 and 6, and will not be repeated here. The integrated voltage regulator die 32 may be encapsulated in encapsulant 56 (Figure 14), or it may fit tightly into an opening in the redistribution structure 64, thus making physical contact with the dielectric layer 66. The integrated voltage regulator die 32 may or may not be in physical contact with the redistribution line 68. According to some embodiments, the integrated voltage regulator die 32 may be flip-chip bonded to the redistribution line 68.

[0056] The resistive-capacitor element 50 is located within the packaging material 74. According to some embodiments, the resistive-capacitor element 50 is placed above the redistribution structure 64 (e.g., through the die attachment film 54), and then the resistive-capacitor element 50, device die 72, and via 70 are encapsulated within the packaging material 74. As shown in the voltage conduction path 98, the resistive-capacitor element 50 is also located in the path that conducts the voltage output of the integrated regulator die 32 to the packaging element 94, thus reducing transient overshoot.

[0057] Figure 14 shows an enlarged view of a portion of the package 94 in Figure 13, wherein the portion shown includes the integrated regulator die 32 and the resistive-capacitor elements 50. According to some embodiments, the integrated regulator die 32 is surrounded by encapsulant 33 (e.g., underfill). As shown in Figure 14, the underfill 33 may have a portion located directly above the integrated regulator die 32. Alternatively, the underfill 33 may not have any portion located directly above the integrated regulator die 32.

[0058] Figure 15 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. Both the integrated regulator die 32 and the resistive-capacitor element 50 are located within the encapsulant 74 and are at the same level as the device die 70. The device die 70 may include local silicon interconnect dies 70. As shown in voltage conduction path 98, the resistive-capacitor element 50 is also located in the path used to conduct the output voltage from the integrated regulator die 32 to the package element 90, and thus reduces transient overshoot.

[0059] Figure 16 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. The integrated voltage regulator die 32 is located in the dielectric core 38, and is substantially the same as the structure shown in Figure 9. The placement details of the integrated voltage regulator die 32 are substantially the same as those shown in Figures 2 and 3, and will not be repeated here.

[0060] According to these embodiments, the resistive-capacitive element 50 is located in the underfill 88. The resistive-capacitive element 50 can be bonded to the redistribution structure 64 before the package element 82 is bonded to the package substrate 61'. As shown in the voltage conduction path 98, the resistive-capacitive element 50 is also located in the path for conducting the output voltage from the integrated regulator die 32 to the package element 84, and thus reduces transient overshoot.

[0061] Figure 17 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. Resistive-capacitor elements 50 are located in the dielectric core 38. The placement of the resistive-capacitor elements 50 may be substantially the same as that of the integrated regulator die 32 shown in Figures 2 and 3, and details will not be repeated here.

[0062] The integrated regulator die 32 is bonded to the bottom of the package substrate 61' and can be encapsulated in an underfill that fills the gap between the package substrate 61' and the package element 92. As shown in voltage conduction path 98, the resistor-capacitor element 50 is also in the path for conducting the output voltage from the integrated regulator die 32 to the package element 84, and thus transient overshoot can be reduced.

[0063] Figure 18 illustrates a cross-sectional view of a package 94 according to an alternative embodiment of the present disclosure. Resistive-capacitor elements 50 are located in the dielectric core 38, which is substantially the same as the structure shown in Figure 17. The placement of the resistive-capacitor elements 50 may be substantially the same as the placement of the integrated regulator die 32 shown in Figures 2 and 3, details of which will not be described here.

[0064] On the other hand, the integrated voltage regulator die 32 is located above the resistor-capacitor element 50. According to some embodiments, the integrated voltage regulator die 32 is placed in the redistribution structure 40 and may or may not be located in the bottom filler. The details of placing the integrated voltage regulator die 32 can be substantially the same as the placement of the resistor-capacitor element 50 as shown in Figures 5 and 6, and the details will not be repeated here.

[0065] As shown in voltage conduction path 98, although the resistor-capacitor element 50 is located below the integrated regulator die 32, and therefore the path for conducting the output voltage from the integrated regulator die 32 to the package element 84 is increased, this embodiment increases design flexibility, and the integrated regulator die 32 and resistor-capacitor element 50 have the flexibility to be placed in locations with low feature density and more available space. The length of the conduction path is increased only slightly.

[0066] In the above embodiments, some processes and features are described according to some embodiments of this disclosure to form a three-dimensional (3D) package. Other features and processes may also be included. For example, test structures may be included to assist in verifying and testing 3D packages or three-dimensional integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed on a redistribution layer or substrate, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. In addition, the structures and methods described in this disclosure can be used in conjunction with test methods that incorporate intermediate verification of known good wafers to increase yield and reduce costs.

[0067] The embodiments disclosed herein have several advantageous features. By placing resistive and capacitive elements in the conduction path between the integrated regulator chip and the powered device, voltage transient overshoot can be reduced. Since the resistive and capacitive elements are located in the voltage conduction path, the increase in parasitic inductance is minimal.

[0068] According to some embodiments of the present disclosure, a method of manufacturing a package structure includes placing an integrated voltage regulator in a first package element; placing a resistor-capacitor element in a second package element; electrically connecting the resistor-capacitor element to the integrated voltage regulator; and electrically connecting a first device die to the resistor-capacitor element, wherein the resistor-capacitor element is located in a conductive path connecting the integrated voltage regulator to the first device die.

[0069] In some embodiments, the resistor-capacitor elements are located above the integrated voltage regulator, and the first element die is also located above the integrated voltage regulator.

[0070] In some embodiments, the method further includes forming a first redistribution structure, wherein the integrated voltage regulator is placed above the first redistribution structure; and encapsulating the integrated voltage regulator in a dielectric core, wherein the first redistribution structure and the dielectric core together constitute a first encapsulation element. Furthermore, a second redistribution structure is formed as a second encapsulation element, which is located above the integrated voltage regulator and electrically coupled to the integrated voltage regulator, wherein the first redistribution structure, the encapsulating adhesive, and the second redistribution structure together form an encapsulation substrate.

[0071] In some embodiments, the integrated voltage regulator is attached to the first redistribution structure through a die attachment film, and wherein the integrated voltage regulator is electrically connected to resistive and capacitive elements through a second redistribution structure.

[0072] In some embodiments, the resistive and capacitive elements are placed in the second redistribution structure.

[0073] In some embodiments, forming the second redistribution structure includes forming a plurality of dielectric layers and forming a plurality of redistribution lines in the plurality of dielectric layers, and the method further includes forming openings in the plurality of dielectric layers, wherein resistive and capacitive elements are placed in the openings.

[0074] In some embodiments, the method further includes placing encapsulating adhesive in the opening to encapsulate the resistive and capacitive elements in the opening.

[0075] In some embodiments, this method further includes forming a redistribution structure, including forming a plurality of dielectric layers and forming a plurality of redistribution lines in the plurality of dielectric layers. Furthermore, openings are formed in the plurality of dielectric layers, wherein an integrated voltage regulator is disposed in the openings.

[0076] In some embodiments, the method further includes placing encapsulating adhesive in the opening to encapsulate the integrated voltage regulator in the opening.

[0077] In some embodiments, the method further includes bonding a local silicon interconnect die over a resistive-capacitive element; and bonding a second element die over the local silicon interconnect die, wherein the local silicon interconnect die is configured to electrically bridge the first element die to the second element die.

[0078] According to some embodiments of the present disclosure, a package structure includes an integrated voltage regulator, a resistive-capacitive element located above and electrically coupled to the integrated voltage regulator, a first element die located above the integrated voltage regulator and the resistive-capacitive element, a first electrical connection path connecting the integrated voltage regulator to the input terminal of the resistive-capacitive element, and a second electrical connection path connecting the output terminal of the resistive-capacitive element to the first element die.

[0079] In some embodiments, this package structure further includes a package substrate in which the integrated voltage regulator and the resistor-capacitor elements are embedded.

[0080] In some embodiments, the packaging substrate includes a first redistribution structure, a dielectric core located above the first redistribution structure, and a second redistribution structure located above the dielectric core, wherein the integrated voltage regulator is located in the dielectric core and the resistor-capacitor elements are located in the second redistribution structure.

[0081] In some embodiments, the packaging structure further includes a packaging substrate, the packaging substrate including a first redistribution structure, a dielectric core located above the first redistribution structure, and a second redistribution structure located above the dielectric core and resistive-capacitive elements, wherein the integrated voltage regulator is attached to the bottom surface of the first redistribution structure, and the resistive-capacitive elements are located in the dielectric core.

[0082] In some embodiments, the resistive-capacitive element includes a plurality of resistive-capacitive units, each resistive-capacitive unit including a resistor and a capacitor connected to the resistor.

[0083] In some embodiments, the resistive-capacitive element is a single resistive-capacitive element, which includes a resistor and a capacitor connected to the resistor.

[0084] According to some embodiments of the present disclosure, a packaging structure includes a packaging substrate including a first redistribution structure; a dielectric core located above the first redistribution structure; a second redistribution structure located above the dielectric core; a plurality of vias located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator located in the dielectric core; a resistive-capacitive element located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a packaging element located above the packaging substrate and bonded to the packaging substrate, wherein the packaging element includes a device die electrically connected to the resistive-capacitive element.

[0085] In some embodiments, the resistive and capacitive elements are located in the second redistribution structure.

[0086] In some embodiments, the second redistribution structure includes a plurality of dielectric layers, wherein resistive and capacitive elements are located in the plurality of dielectric layers; and a plurality of redistribution lines located in the plurality of dielectric layers.

[0087] In some embodiments, this package structure further includes an underfill located in a plurality of dielectric layers, wherein resistive and capacitive elements are further located in the underfill.

[0088] The features of many embodiments have been summarized above to enable those skilled in the art to better understand the various embodiments of this disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments of this disclosure without departing from the spirit and scope of the appended claims. [Simplified Explanation of the Diagram]

[0006] The concepts of the embodiments disclosed herein will be better understood by referring to the following detailed description and accompanying drawings. It should be noted that, according to standard industry practice, various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings. Figures 1 to 9 illustrate intermediate stages of the manufacturing process of a package including an integrated voltage regulator (IVR) and resistor-capacitor (RC) elements according to some embodiments of the present disclosure. Figure 10 illustrates an enlarged schematic diagram of a portion of a package according to some embodiments. Figures 11 and 12 illustrate a package and an enlarged portion of a package according to some embodiments, respectively. Figures 13 and 14 illustrate a package and an enlarged portion of a package according to some embodiments, respectively. Figures 15 to 18 illustrate some packages including an integrated voltage regulator and resistor-capacitor elements according to some embodiments. Figures 19 and 20 illustrate circuit diagrams of an integrated voltage regulator and resistive-capacitor elements according to some embodiments. Figure 21 illustrates the effect of the integrated voltage regulator and resistive-capacitor elements in a package according to some embodiments. Figure 22 illustrates the manufacturing process for forming the package according to some embodiments.

Claims

1. A method for manufacturing a packaging structure, comprising: An integrated voltage regulator is placed in a first package element; A resistor-capacitor component is placed in a second package component; The resistor-capacitor element is electrically connected to the integrated voltage regulator; and a first device die is electrically connected to the resistor-capacitor element, wherein the resistor-capacitor element is located in a conductive path connecting the integrated voltage regulator to the first device die, the integrated voltage regulator is connected to an input terminal of the resistor-capacitor element, and an output terminal of the resistor-capacitor element is connected to the first device die.

2. A method for manufacturing the package structure of claim 1, wherein the resistor-capacitor element is located above the integrated voltage regulator, and the first device die is located above the integrated voltage regulator.

3. The method for manufacturing the packaging structure as described in claim 1 further includes: A first redistribution structure is formed, wherein the integrated voltage regulator is placed on top of the first redistribution structure; the integrated voltage regulator is encapsulated in a dielectric core, wherein the first redistribution structure and the dielectric core together constitute the first encapsulation element; and a second redistribution structure is formed as the second encapsulation element, the second encapsulation element being located on top of the integrated voltage regulator and electrically coupled to the integrated voltage regulator, wherein the first redistribution structure, an encapsulant, and the second redistribution structure together form an encapsulation substrate.

4. A method of manufacturing the package structure of claim 3, wherein the integrated voltage regulator is attached to the first redistribution structure through a die attachment film, and the integrated voltage regulator is electrically connected to the resistor-capacitor element through the second redistribution structure.

5. A method for manufacturing the package structure as claimed in claim 3, wherein the resistor-capacitor element is placed in the second redistribution structure.

6. A method for manufacturing a package structure as claimed in claim 3, wherein forming the second redistribution structure includes forming a plurality of dielectric layers and a plurality of redistribution lines located in the dielectric layers, and the method for manufacturing the package structure further includes: An opening is formed in the dielectric layer, and the resistive and capacitive element is placed in the opening; And to place the encapsulant in the opening to encapsulate the resistor-capacitor element in the encapsulant.

7. The method for manufacturing the packaging structure of claim 1 further includes: A redistribution structure is formed, the redistribution structure including forming a plurality of dielectric layers and forming a plurality of redistribution lines in the dielectric layers; an opening is formed in the dielectric layers, wherein the integrated voltage regulator is placed in the opening; and an encapsulant is disposed in the opening to encapsulate the integrated voltage regulator in the encapsulant.

8. The method for manufacturing the packaging structure as described in claim 1 further includes: A partial silicon interconnect die is bonded over the resistor-capacitor element; and a second device die is bonded over the partial silicon interconnect die, wherein the partial silicon interconnect die is configured to electrically bridge the first device die to the second device die.

9. A packaging structure, comprising: An integrated voltage regulator; a resistor-capacitor element located above and electrically coupled to the integrated voltage regulator; a first device die located above the integrated voltage regulator and the resistor-capacitor element; a first electrical connection path connecting the integrated voltage regulator to an input terminal of the resistor-capacitor element; and a second electrical connection path connecting an output terminal of the resistor-capacitor element to the first device die.

10. The packaging structure of claim 9 further includes a packaging substrate, wherein the integrated voltage regulator and the resistive-capacitive element are both embedded in the packaging substrate, wherein the packaging substrate includes: The first redistribution structure; A dielectric core is located above the first redistribution structure, wherein the integrated voltage regulator is located within the dielectric core; And a second redistribution structure, located above the dielectric core, wherein the resistive and capacitive elements are located in the second redistribution structure.

11. The packaging structure of claim 9 further includes a packaging substrate, the packaging substrate comprising: A first redistribution structure, wherein the integrated voltage regulator is attached to a bottom surface of the first redistribution structure; A dielectric core is located above the first redistribution structure, wherein the resistive and capacitive elements are located within the dielectric core; And a second redistribution structure located above the dielectric core and the resistive-capacitive element.

12. A packaging structure, comprising: A package substrate includes: a first redistribution structure; a dielectric core located above the first redistribution structure; a second redistribution structure located above the dielectric core; a plurality of vias located in the dielectric core and electrically connecting the first redistribution structure to the second redistribution structure; an integrated voltage regulator located in the dielectric core; a resistive-capacitive element located above the integrated voltage regulator and electrically connected to the integrated voltage regulator; and a package element located above the package substrate and bonded to the package substrate, wherein the package element includes a device die electrically connected to the resistive-capacitive element, the integrated voltage regulator is connected to an input terminal of the resistive-capacitive element, and an output terminal of the resistive-capacitive element is connected to the device die.

13. The encapsulation structure as described in request item 12, wherein the second redistribution structure includes: A plurality of dielectric layers, wherein the resistive and capacitive element is located in the dielectric layers; Multiple redistribution lines are located in the dielectric layers; And a bottom filler located in the dielectric layers, wherein the resistive and capacitive elements are further located in the bottom filler.

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