Series-fed array system for signal transmission

Abstract

An array system for signal transmission includes a transmission line, N array elements, and N capacitors. The transmission line includes N taps. The N array elements are each driven by N voltage signals fed to N input terminals of the N array elements. Each array element includes a transistor, and the N gates of the N transistors in the N array elements serve as the N input terminals. The N capacitors are used to capacitively couple the N taps to the N gates of the N transistors to provide the N voltage signals. The capacitance value of each capacitor is less than the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled.

Description

[Technical Field]

[0001] This disclosure relates to signal transmission, and more particularly to a sequence feed array system for signal transmission. [Previous Technology]

[0002] A phased array antenna system is an advanced technology that uses the coordinated operation of multiple radiating elements to electronically steer a signal beam. By applying a specific phase offset to each radiating element, the phased array antenna system can dynamically control the beam direction and radiation pattern without physical movement. Phased array antennas are widely used in radar, telecommunications, and satellite communications to provide precise, real-time beam control. In a phased array antenna system, power distribution among the radiating elements is crucial because stable power levels help achieve the optimal radiation pattern and maximum gain in the desired direction. Unbalanced power distribution can lead to signal degradation, reduced efficiency, and unwanted sidelobes, highlighting the importance of careful power management in phased array design. [Summary of the Invention]

[0003] The embodiments disclosed herein provide a sequence feed array system for signal transmission.

[0004] Some embodiments of this disclosure include an array system for signal transmission. The array system includes a transmission line, N array cells, and N capacitors. The transmission line includes N taps. The N array cells are each driven by N voltage signals fed to N input terminals of the N array cells. Each array cell includes a transistor, and the N gates of the N transistors in the N array cells serve as the N input terminals. The N capacitors are used to capacitively couple the N taps to the N gates of the N transistors to provide the N voltage signals. The capacitance value of each capacitor is less than the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled.

[0005] Some embodiments of this disclosure include an array system for signal transmission. The array system includes a transmission line, N array cells, and N capacitors. The transmission line includes N taps. The N array cells are each driven by N voltage signals fed to N input terminals of the N array cells. Each array cell includes a radiating element and an integrated circuit. The integrated circuit is coupled to the radiating element and driven by a corresponding voltage signal to enable the radiating element to emit a radio frequency signal. The gate of a transistor in the integrated circuit serves as the input terminal of the array cell. The N capacitors have N first terminals respectively coupled to the N taps and N second terminals respectively coupled to the N input terminals. The N capacitors are used to provide the N voltage signals.

[0006] By placing capacitors on the feed path between the transmission line tap and the array cell with high input impedance, the sequential feed system disclosed herein can reduce / eliminate the influence of temperature or environmental variations on the input capacitance value of the array cell, thereby achieving good impedance matching design and high-quality signal transmission.

Implementation Method

[0008] [Cross-referencing related applications]

[0009] This application claims priority to U.S. Provisional Application No. 63 / 572,642, filed April 1, 2024, the entire contents of which are incorporated herein by reference.

[0010] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in multiple embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0011] Furthermore, it is understood that if a component is described as being "connected to" or "coupled to" another component, then the two components may be directly connected or coupled, or there may be other intervening components between them.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "above," "left," "right," and similar terms may be used herein to describe the relationship between one element or component and another element(s) shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also used to cover different orientations of the device during use or operation. Furthermore, the device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0013] The antenna array system can adopt a tree-structured power distribution method, which transmits the input power to each antenna element in the antenna array system layer by layer. However, when the input power changes, the power received by each antenna element will also change accordingly.

[0014] This disclosure provides an array system for signal transmission that employs a series-fed power distribution architecture with high-impedance elements. Voltage signals can be fed into the array elements via high-impedance paths. The array system provided in this disclosure can be implemented as an antenna array system, a switch array system, or other array systems with high-impedance elements. The array system provided in this disclosure not only reduces power / signal distribution losses but also improves system stability. Further explanation follows.

[0015] Figure 1 is a schematic diagram of an exemplary array system according to certain embodiments of the present disclosure. The array system 100 may include (but is not limited to) one or more transmission lines TL1 to TLM (M is a positive integer) and multiple array elements AE1,1 to AEM,N (N is an integer greater than 1). The array system 100 employs a sequential feed architecture, feeding the energy transmitted by the transmission line TL1 to the array elements AE1,1 to AE1,N via multiple tap points of the transmission line TL1, thereby driving the array elements AE1,1 to AE1,N, where i = 1, 2, ..., M. Each array element can be driven by a voltage signal fed to its input terminal. For example, the transmission line TL1 for transmitting the input signal SIN may include multiple tap points TP1 to TPN, wherein the energy of the input signal SIN can be accessed / obtained at each tap point. The array units AE1,1 to AE1,N can be driven by voltage signals fed from tap points TP1 to TPN to input terminals TI1 to TIN, respectively.

[0016] Each array unit can be an array unit with a high input impedance value, so that the voltage magnitudes of multiple taps on the same transmission line can be equal or approximately equal to each other. For example, the characteristic impedance of transmission line TL 1 can be much smaller than the input impedance values ​​of array units AE 1,1 to AE 1,N. Therefore, the voltage magnitudes accessed at taps TP 1 to TP N can be equal or approximately equal to each other. In this embodiment, each array unit can include a transistor, the gate of which can be used as the input terminal of the array unit to achieve a high input impedance value. For example, the gates of transistors M 1 to MN can be used as the input terminals TI 1 to TI N of array units AE 1,1 to AE 1,N, respectively.

[0017] The array system 100 may be implemented as (but is not limited to) an antenna array system, a switch array system, or other array system with high-impedance elements. For example (but not limited to this disclosure), each array element may be an antenna element, which includes (but is not limited to) an integrated circuit and a radiating element. The gate of a transistor in the integrated circuit for receiving voltage signals from the tap point may serve as the input terminal of the array element. As another example, each array element may include an amplifier (such as a power amplifier); the gate of a transistor in the amplifier for receiving voltage signals from the tap point may serve as the input terminal of the array element. As another example, each array element may include a switching element; the gate of a transistor in the switching element for receiving voltage signals from the tap point may serve as the input terminal of the array element.

[0018] The array system 100 (or a sequence-feed power distribution system with high-impedance units) can achieve impedance matching design by unifying the inductance-capacitance product (LC product) of each array unit, rather than by using impedance elements that match the characteristic impedance of the transmission line. The array unit 100 can control the inductance-capacitance product within a predetermined value (or a predetermined range) and can set the resonant frequency corresponding to the square root of the inductance-capacitance product to be much higher than the maximum frequency in the operating frequency band, thereby reducing the impact of resonance on the required frequency range and improving the characteristics of return loss (S21) and insertion loss (S21).

[0019] Figure 2 is a schematic diagram of an architecture for extracting return loss (or reflection coefficient) and insertion loss associated with each array cell shown in Figure 1, according to certain embodiments of the present disclosure. The array cell AE shown in Figure 2 may represent one of the array cells AE1,1 to AEM,N shown in Figure 1. In this embodiment, the input and output ends of the transmission line TL are connected to impedance elements Z1 and Z2, respectively, wherein the impedance values ​​of impedance elements Z1 / Z2 are matched to the characteristic impedance value of the transmission line TL. Return loss can be extracted from voltage signal V1 (input to the input end) and voltage signal V3 (reflected back from the input end), while insertion loss can be extracted from voltage signal V1 and voltage signal V2 (output from the output end).

[0020] Furthermore, the tap point TP of the transmission line TL is coupled to the input terminal TI of the array cell AE. The equivalent circuit seen from the input terminal TI (i.e., the gate of the transistor contained in the array cell AE) can be represented by a resistor RP and a capacitor CP connected in parallel. The resistance value of the resistor RP can be much larger than the characteristic impedance value of the transmission line TL. For example (but this disclosure is not limited to this), the resistance value of the resistor RP can be greater than 1000 ohms, while the characteristic impedance value of the transmission line TL can be 50 ohms. However, due to temperature variations, process variations, and / or doping concentration, the parasitic effects of the active components are difficult to control, resulting in an unstable capacitance value of the capacitor CP. That is, the equivalent capacitance values ​​(i.e., the capacitance values ​​of the capacitor CP) of different array cells vary considerably from one another. This leads to significant differences in the inductance-capacitance products of different array cells, and causes the return loss and insertion loss characteristics of the overall system to be less than ideal.

[0021] Figure 3 is a schematic diagram of an exemplary array system according to certain embodiments of the present disclosure. Except for the capacitor disposed between the tap point and the array unit, the structure of the array system 300 is substantially the same as / similar to the structure of the array system 100 shown in Figure 1. In this embodiment, the array system 300 may be implemented as a phase array antenna system. Each array unit may be implemented as an antenna unit, which may include (but is not limited to) integrated circuitry (or a chip) and a radiating element. For example, array unit AE1,i may include a radiating element 310_i and integrated circuitry 320_i, where i = 1, 2, ..., N. Integrated circuitry 320_i is coupled to radiating element 310_i and is driven by a corresponding voltage signal, thereby enabling radiating element 310_i to emit a radio frequency signal. Integrated circuitry 320_i includes a transistor Mi, the gate of which may serve as an input terminal TIi. However, this is not intended to limit the scope of the present disclosure. Each array element can be implemented by other high-input-impedance elements without departing from the scope of this disclosure.

[0022] The array system 300 may further include multiple capacitors, each disposed on the feed path between the tap and the array unit. For example, capacitor C1 may be disposed between tap TP1 and input terminal TI1 (or the gate of transistor M1), capacitor C2 may be disposed between tap TP2 and input terminal TI2 (or the gate of transistor M2), and so on. That is, the first terminal of each of capacitors C1 to CN is coupled to taps TP1 to TPN, and the second terminal of each of capacitors C1 to CN is coupled to input terminals TI1 to TIN. In addition, each capacitor is used to capacitively couple a tap to a corresponding input terminal to provide a voltage signal (such as one of voltage signals VD1 to VDN) fed to that input terminal, thereby driving the corresponding array unit.

[0023] The capacitor placed between the tap point and the gate of the transistor can reduce or eliminate the impact of variations in the input capacitance value at the gate on impedance matching. Please refer to Figure 4, which is a schematic diagram of the architecture used to extract the return loss (or reflection coefficient) and insertion loss associated with each array unit shown in Figure 3 according to certain embodiments of this disclosure. Except for the capacitor CX connected between the tap point TP and the input terminal TI (or the gate of the transistor), the architecture shown in Figure 4 is the same as / similar to the architecture shown in Figure 2. In this embodiment, the capacitor CX (such as one of the capacitors C1 to CN shown in Figure 3) can be a thin-film capacitor or other capacitors with a stable capacitance value. Connecting the capacitor CX between the tap point TP and the input terminal TI can reduce the variation in the equivalent capacitance value seen from the tap point TP, thereby improving the consistency between the inductance-capacitance products of different array units.

[0024] Figure 5A is a frequency response diagram of the return loss (S11) of the architecture shown in Figure 4 according to certain embodiments of the present disclosure under the condition that the capacitor CP has different capacitance values. Referring to Figure 5A, in this embodiment, curves CV11 to CV16 plot the frequency response of the return loss when the capacitor CP is at different capacitance values ​​f1 to f6 (i.e., different input capacitance values ​​of the transistor gate) and the capacitor CX is at the capacitance value f0, where the capacitance values ​​f1 to f6 increase from small to large (e.g., from 100 fF to 500 fF), representing the possible range of variation of the capacitance value of the capacitor CP. In addition, the capacitance value f0 is less than each of the capacitance values ​​f1 to f6. For example (but the present disclosure is not limited to this), the capacitance value f0 can be set to be less than one-fifth of the capacitance value of the capacitor CP. As can be seen from Figure 5A, the variation of the capacitance value of the capacitor CP has little effect on the frequency response of the return loss (corresponding to the characteristics of the reflection coefficient), which means that the capacitor CX effectively stabilizes the equivalent capacitance value seen from the tap point TP. Furthermore, a capacitor CP with a larger capacitance value can exhibit better frequency response characteristics, meaning that the smaller the capacitance value of capacitor CX is relative to the capacitance value of capacitor CP, the better the signal transmission quality. In some embodiments, when the capacitance value of capacitor CX is much smaller than the capacitance value of capacitor CP, the effect of capacitance variation of capacitor CP on impedance matching can be eliminated or substantially eliminated.

[0025] Figure 5B is a frequency response diagram of the insertion loss (S21) of the architecture shown in Figure 4 according to certain embodiments of the present disclosure, under the condition that the capacitor CP has different capacitance values. Referring to Figure 5B, curves CV21 to CV26 illustrate the frequency response of the insertion loss when the capacitor CP is at different capacitance values ​​f1 to f6 (i.e., different input capacitance values ​​of the transistor gate) and the capacitor CX is at the capacitance value f0. As can be seen from Figure 5B, setting the capacitor CX can reduce the influence of the capacitance value variation of the capacitor CP on the frequency response of the insertion loss; the capacitor CX with a capacitance value smaller than that of the capacitor CP can improve the signal transmission quality.

[0026] Referring again to Figure 3, each array element in the array system 300 can be a high-input-impedance array element. Therefore, the voltage amplitudes of adjacent taps on the same transmission line are equal or approximately equal. For example, the input impedance value looking into the corresponding capacitor (i.e., the capacitor coupled to the tap) from each tap is greater than or much greater than the characteristic impedance value of the transmission line; similarly, the input impedance value looking into the array element from the input terminal (i.e., the input impedance value of the array element) is greater than or much greater than the characteristic impedance value of the transmission line. Compared to a sequential power distribution system that uses input impedance values ​​to match transmission line impedance values, the array system 300 using high-impedance array elements can achieve impedance matching design by unifying the inductance-capacitance product of each array element (instead of using the transistor drain as the input terminal of the array element, and not using an inductor-capacitor matching network). In other words, impedance matching can be achieved by setting / designing the product of the equivalent inductance and equivalent capacitance of each of the multiple taps to be the same (or approximately the same).

[0027] Figure 6 is a schematic diagram of an architecture for extracting the return loss (S11) and insertion loss (S21) characteristics of the transmission line TL 1 shown in Figure 3 according to certain embodiments of the present disclosure. For ease of explanation, the transmission line TL 1 shown in Figure 6 is used to distribute the energy of the input signal S IN to eight array cells AE 1,1 to AE 1,8 (i.e., N in Figure 3 equals 8) by sequential feeding. However, this is not intended to limit the scope of the present disclosure. In some embodiments, the architecture shown in Figure 6 can be applied to transmission lines coupled to different numbers of array cells without departing from the scope of the present disclosure. For example, the architecture shown in Figure 6 can be used to extract the return loss and insertion loss characteristics of other transmission lines shown in Figure 3 without departing from the scope of the present disclosure.

[0028] In this embodiment, the transmission line TL 1 can be equivalent to a capacitor-inductor-capacitor (CLC) model to unify the inductance-capacitance product (the product of equivalent inductance and equivalent capacitance) of all array units. For example, the inductance-capacitance product of array unit AE 1,i can be determined by the equivalent input circuit of the transmission line segments TL1_i, TL2_i, and TL3_i and the tap point TP i (which includes capacitance Ci and the equivalent resistance RP i and equivalent capacitance CP i at the input terminal TI i), where i = 1, 2, ..., 8. The equivalent circuit of transmission line segment TL1_i includes inductor Li1, capacitor CiA1, and capacitor CiB1; the equivalent circuit of transmission line segment TL2_i includes inductor Li2, capacitor CiA2, and capacitor CiB2; and the equivalent circuit of transmission line segment TL3_i includes inductor Li3, capacitor CiA3, and capacitor CiB3. Furthermore, the input terminal of transmission line TL1 can be connected to the terminating element ZIN, whose impedance value can be matched to the characteristic impedance value of transmission line TL1; the output terminal of transmission line TL1 can be connected to the terminating element ZOUT, whose impedance value can be matched to the characteristic impedance value of transmission line TL1.

[0029] In some embodiments, the transmission line length between adjacent taps (or adjacent array elements) can be equal to half the wavelength of the input signal SIN propagating along the transmission line TL 1, thereby reducing reflections and phase interference, and improving antenna gain and overall efficiency. Furthermore, in some embodiments, the inductance-capacitance product of the array system 300 can be controlled within a predetermined value (or a predetermined range) to maintain consistency. The resonant frequency (corresponding to the square root of the equivalent inductance and equivalent capacitance) determined by the product of the equivalent inductance and equivalent capacitance of each tap can be higher than or significantly higher than the maximum frequency in the operating frequency band of the array system 300, thereby achieving good S11 and S21 characteristics.

[0030] Figure 7A is a frequency response diagram of the insertion loss (S21) of the sequence feed system of eight array elements shown in Figure 6 according to certain embodiments of this disclosure. Referring to Figure 7A, in this embodiment, the S21 values ​​at operating frequencies m11 and m12 are both close to (or equal to) 0 dB, which represents very small insertion loss. The resonant frequency, determined by the inductor-capacitor product, can be designed at a high frequency m13, which is far from the operating frequency band. As can be seen from Figure 7A, the inductor-capacitor product is consistent within the operating frequency band, thus enabling effective impedance matching or power distribution.

[0031] Figure 7B is a frequency response diagram of the return loss (S11) of the sequence feed system of eight array elements shown in Figure 6 according to certain embodiments of the present disclosure. Referring to Figure 7B, in this embodiment, the local maximum S11 values ​​within the operating frequency band are all significantly different from 0 dB, which indicates that the return loss is very small. For example, the S11 values ​​at operating frequencies m11 and m12 are both much less than 0 dB, therefore, the sequence feed system operating at operating frequencies m11 / m12 can achieve high-efficiency signal transmission.

[0032] Please note that when the taps of the transmission line are directly connected to the input terminals of the corresponding array elements, the frequency response of the insertion loss and return loss will be significantly affected by the variation in the input capacitance value of the array elements. For example, please refer to Figure 8A, which is a frequency response diagram of the insertion loss (S21) when the taps TP1 to TP8 shown in Figure 6 are directly connected to the input terminals TI1 to TI8, respectively. As can be seen from Figure 8A, due to the variation in the input capacitance value (i.e., the input capacitance value at the transistor gate), the S21 value near the operating frequencies m11 and m12 is inconsistent. This means that the inductor-capacitor product is not consistent within the operating frequency band, resulting in poor transmission efficiency within the operating frequency band.

[0033] Furthermore, please refer to Figure 8B, which is a frequency response diagram of the return loss (S11) when the tap points TP1 to TP8 shown in Figure 6 are directly connected to the input terminals TI1 to TI8, respectively. As can be seen from Figure 8B, the S11 value exhibits a large range of variation within the operating frequency band, and some S11 values ​​are even quite close to 0 dB. For example, the S11 values ​​at operating frequencies m11 and m12 are both higher than the maximum S11 value within the operating frequency band in Figure 7B, indicating poor transmission efficiency.

[0034] FIG9 is a schematic diagram of an embodiment of capacitor C1 on a high-impedance feed path as shown in FIG3 according to certain embodiments of the present disclosure. Note that the structure shown in FIG9 can be used to implement other capacitors located on high-impedance feed paths without departing from the scope of the present disclosure.

[0035] In this embodiment, the transmission line TL1 may be formed in the metal layer ML1; the capacitor C1 has electrodes ED1 and ED2, which may be formed in the metal layers ML2 and ML3, respectively. The metal layer ML2 is located between the metal layers ML1 and ML3. In some examples, a thin-film process may be used to integrate the transmission line TL1 and the capacitor C1; the capacitor C1 may be a thin-film capacitor with a stable capacitance value, which may be much smaller than the input capacitance value of the array cell (i.e., the input capacitance value of the array cell AE1,1 shown in FIG. 3). For example (but this disclosure is not limited thereto), the capacitance value of the capacitor C1 may be 0.01 pF, which is much smaller than the input capacitance value of the transistor gate (i.e., the input capacitance value of the gate of the transistor M1 shown in FIG. 3).

[0036] In addition, a conductive via VA1 (which passes through the dielectric layer DL1 between metal layers ML1 and ML2) is used to electrically connect the transmission line TL1 to the electrode ED1. The integrated circuit 320_1 (such as a chip) located above the metal layer ML3 can be coupled to the electrode ED2 via one or more metal interconnect layers (not shown), wire bonding (not shown) or other electrical connections.

[0037] The structure shown in Figure 9 is for illustrative purposes and is not intended to limit the scope of this disclosure. The capacitor located on the feed path between the tap point of the transmission line and the array unit can be implemented using other semiconductor structures or processes without departing from the scope of this disclosure.

[0038] By placing capacitors on the feed path between the tap point of the transmission line and the array cell with high input impedance, the sequential feed system disclosed herein can reduce / eliminate the influence of temperature or environmental variations on the input capacitance value of the array cell, thereby achieving good impedance matching design and high-quality signal transmission.

[0039] The term "approximately" as used in this disclosure is used to describe and indicate minor variations. When these terms are used in conjunction with an event or situation, they can cover examples of an event or situation occurring precisely and examples of an event or situation being very close to occurring. For example, when the term "approximately" is used with a given value or range, it generally means ±10%, ±5%, ±1%, or ±0.5% of that given value or range. In this disclosure, a numerical range is expressed as from one endpoint to another or between two endpoints. Unless otherwise stated, the numerical ranges described in this disclosure may include endpoints. Furthermore, when multiple values ​​or characteristics are mentioned as "approximately" the same, it can cover situations where these values ​​are all within ±10%, ±5%, ±1%, or ±0.5% of the average of these values.

[0040] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various forms of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0007] The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the size of certain features may be arbitrarily enlarged or reduced for clear description. FIG1 is a schematic diagram of an exemplary array system according to certain embodiments of the present disclosure. FIG2 is a schematic diagram of an architecture for extracting return loss and insertion loss associated with each array element shown in FIG1 according to certain embodiments of the present disclosure. FIG3 is a schematic diagram of an exemplary array system according to certain embodiments of the present disclosure. FIG4 is a schematic diagram of an architecture for extracting return loss and insertion loss associated with each array element shown in FIG3 according to certain embodiments of the present disclosure. FIG5A is a frequency response diagram of the return loss of the architecture shown in FIG4 according to certain embodiments of the present disclosure when the capacitor has different capacitance values. FIG5B is a frequency response diagram of the insertion loss of the architecture shown in FIG4 according to certain embodiments of the present disclosure when the capacitor has different capacitance values. FIG6 is a schematic diagram of an architecture for extracting the return loss characteristics and insertion loss characteristics of the transmission line shown in FIG3 according to certain embodiments of the present disclosure. Figure 7A is a frequency response diagram of the insertion loss of the sequential feed system of eight array elements shown in Figure 6 according to certain embodiments of the present disclosure. Figure 7B is a frequency response diagram of the return loss of the sequential feed system of eight array elements shown in Figure 6 according to certain embodiments of the present disclosure. Figure 8A is a frequency response diagram of the insertion loss when the taps shown in Figure 6 are directly connected to the input terminals. Figure 8B is a frequency response diagram of the return loss when the taps shown in Figure 6 are directly connected to the input terminals. Figure 9 is a schematic diagram of an embodiment of the capacitor on the high-impedance feed path shown in Figure 3 according to certain embodiments of the present disclosure.

Claims

1. An array system for signal transmission, comprising: a transmission line including N taps for transmitting an input signal; N array cells, each driven by N voltage signals fed to N input terminals of the N array cells, wherein each array cell includes a transistor, and the N gates of the N transistors of the N array cells serve as the N input terminals; and N capacitors for capacitively coupling the N taps to the N gates of the N transistors to provide the N voltage signals corresponding to the input signal to the N gates of the N transistors, wherein the capacitance value of each capacitor is less than the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled.

2. An array system for signal transmission, comprising: a transmission line having N taps; N array cells, each driven by N voltage signals fed to N input terminals of the N array cells, wherein each array cell includes a transistor, and the N gates of the N transistors of the N array cells serve as the N input terminals; and N capacitors for capacitively coupling the N taps to the N gates of the N transistors to provide the N voltage signals, wherein the capacitance value of each capacitor is less than the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled, wherein the capacitance value of the capacitor is less than one-fifth of the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled.

3. The array system as claimed in claim 1, wherein the transmission line length between adjacent taps is equal to half the wavelength of the input signal propagating along the transmission line.

4. The array system as claimed in claim 1, wherein each of the N taps has a consistent product of equivalent inductance and equivalent capacitance.

5. The array system as claimed in claim 1, wherein the resonant frequency determined by the product of the equivalent inductance and equivalent capacitance of each tap point is higher than the maximum frequency in the operating frequency band of the array system.

6. The array system as claimed in claim 1, wherein the array unit includes an integrated circuit and a radiating element, the transistor being contained within the integrated circuit, and the integrated circuit being driven by a corresponding voltage signal such that the radiating element emits a radio frequency signal.

7. The array system as described in claim 1, wherein the voltage magnitudes of adjacent tap points are equal to each other.

8. The array system as claimed in claim 1, wherein the input impedance value seen from each tap point into the corresponding capacitor coupled to that tap point is greater than the characteristic impedance value of the transmission line.

9. The array system as claimed in claim 1, wherein the transmission line system is formed in a first metal layer, the capacitor system is a thin-film capacitor having a first electrode and a second electrode, the first electrode being formed in a second metal layer, the second electrode being formed in a third metal layer; the second metal layer is located between the first metal layer and the third metal layer.

10. The array system as claimed in claim 1, further comprising: a first terminating element connected to an input end of the transmission line; and a second terminating element connected to an output end of the transmission line, wherein the impedance values ​​of the first terminating element and the second terminating element are both matched to the characteristic impedance value of the transmission line.

11. An array system for signal transmission, comprising: a transmission line having N taps for transmitting an input signal; N array cells, each driven by N voltage signals fed to N input terminals of the N array cells, each array cell comprising: a radiating element; and an integrated circuit coupled to the radiating element and driven by a corresponding voltage signal to enable the radiating element to emit a radio frequency signal, wherein a gate of a transistor in the integrated circuit serves as the input terminal of the array cell; and N capacitors having N first terminals respectively coupled to the N taps and N second terminals respectively coupled to the N input terminals, the N capacitors being used to provide the N voltage signals corresponding to the input signal to the N input terminals of the N array cells.

12. The array system as claimed in claim 11, wherein the capacitance value of each capacitor is less than the input capacitance value of the gate of the corresponding transistor to which the capacitor is coupled.

13. An array system for signal transmission, comprising: a transmission line having N taps; N array cells, each driven by N voltage signals fed to N input terminals of the N array cells, each array cell comprising: a radiating element; and an integrated circuit coupled to the radiating element and driven by a corresponding voltage signal to enable the radiating element to transmit a radio frequency signal, wherein the gate of a transistor in the integrated circuit serves as the input terminal of the array cell; and N capacitors having N first terminals respectively coupled to the N taps and N second terminals respectively coupled to the N input terminals, the N capacitors being used to provide the N voltage signals, wherein the capacitance value of each capacitor is less than one-fifth of the input capacitance value.

14. The array system as claimed in claim 11, wherein the transmission line length between adjacent taps is equal to half the wavelength of the input signal propagating along the transmission line.

15. The array system as claimed in claim 11, wherein each of the N taps has a consistent product of equivalent inductance and equivalent capacitance.

16. The array system as claimed in claim 11, wherein the resonant frequency determined by the product of the equivalent inductance and equivalent capacitance of each tap point is higher than the maximum frequency in the operating frequency band of the array system.

17. The array system as claimed in claim 11, wherein the voltage magnitudes of adjacent tap points are equal to each other.

18. The array system as claimed in claim 11, wherein the input impedance value seen from each tap point into the corresponding capacitor coupled to that tap point is greater than the characteristic impedance value of the transmission line.

19. The array system as claimed in claim 11, wherein the transmission line system is formed in a first metal layer, each capacitor system is a thin-film capacitor having a first electrode and a second electrode, the first electrode being formed in a second metal layer, the second electrode being formed in a third metal layer; the second metal layer is located between the first metal layer and the third metal layer.

20. The array system as claimed in claim 11, further comprising: a first terminating element connected to an input end of the transmission line; and a second terminating element connected to an output end of the transmission line, wherein the impedance values ​​of the first terminating element and the second terminating element are both matched to the characteristic impedance value of the transmission line.

Images