Gate driver and display apparatus including the same

Abstract

A gate driver and a display device including the gate driver are disclosed. The gate driver includes a plurality of stages. The nth stage of the plurality of stages includes: a pull-up transistor configured to control the current flow between an output node and an input for an nth clock signal based on the voltage of a Q node; a pull-down transistor configured to control the current flow between an output node and an input of a first low power supply based on the voltage of a QB node; and a QB node controller configured to control the voltage of the QB node based on the voltage of a control power supply and the voltage of the Q node, wherein the voltage of the control power supply has an on level during a vertical start-up period of a frame and an off level during a vertical blank period of the frame, where n is an integer.

Description

Technical Field

[0001] The present invention relates to a gate driver and a display device comprising the gate driver. Prior Art

[0002] A display device includes a plurality of pixels arranged in a matrix. Image data synchronized with a scanning signal is supplied to the pixels, thereby adjusting the pixel brightness. The display device generates the scanning signal using a gate driver comprising a plurality of gate stages. Each gate stage of the gate driver is connected to a gate line of the display panel. Each gate stage comprises a plurality of transistors and outputs a scanning signal to the gate line of the display panel that oscillates between an on-scan voltage and an off-scan voltage.

[0003] Because the number of gate lines in a display of a given size increases with resolution, the number of gate levels also increases in high-resolution display devices. As the number of gate levels increases, the area of ​​the bezel containing the gate levels inevitably increases, thus limiting the reduction of the bezel in display devices. Summary of the Invention

[0004] In order to overcome the aforementioned problems of the prior art, the present invention provides a gate driver and a display device including the gate driver, wherein the configuration of the gate level can be simplified, thereby achieving a narrow frame.

[0005] To achieve these goals and other advantages, and in accordance with the purposes of the present invention, as embodied and broadly described herein, a gate driver includes a plurality of stages. The nth stage of the plurality of stages includes: a pull-up transistor configured to control the flow of current between an output node and an input terminal for an nth clock signal based on a voltage at a Q node; a pull-down transistor configured to control the flow of current between the output node and an input terminal of a first low power supply based on a voltage at a QB node; and a QB node controller configured to control the voltage of the QB node based on a voltage of a control power supply and a voltage of the Q node, wherein the voltage of the control power supply has an on level during a vertical enable period of a frame and has an off level during a vertical blank period of the frame, where n is an integer.

[0006] On the other hand, a display device is provided, comprising: a display panel including a plurality of gate lines; and a gate driver including a plurality of stages connected to the plurality of gate lines, wherein an nth stage of the plurality of stages comprises: a pull-up transistor configured to control the flow of current between an output node and an input terminal for an nth clock signal based on a voltage at a Q node; a pull-down transistor configured to control the flow of current between the output node and an input terminal of a first low power supply based on a voltage at a QB node; and a QB node controller configured to control the voltage of the QB node based on a voltage of a control power supply and a voltage of the Q node, wherein the voltage of the control power supply has an on level during a vertical start period of a frame and has an off level during a vertical blank period of the frame, where n is an integer. Simple diagram description

[0007] The following drawings are provided to provide a further understanding of the present invention and are incorporated into and constitute a part of this application. They illustrate embodiments of the present invention and together with the specification serve to explain the principles of the present invention. In the drawings: Figure 1 is a diagram illustrating a display device according to an embodiment of the present invention; Figure 2 is a diagram schematically illustrating an equivalent circuit of a pixel provided in a display panel; Figure 3 is a diagram illustrating a gate stage connected to a gate line; Figure 4 is a diagram illustrating an n-th gate stage connected to an n-th gate line; Figure 5 is a diagram illustrating a driving signal for driving the n-th gate stage; Figures 6 and 7 are diagrams illustrating the operation of the n-th gate stage during the first period; Figures 8 and 9 are diagrams illustrating the operation of the n-th gate stage during the second period; Figures 10 and 11 are diagrams illustrating the operation of the n-th gate stage during the third period; 12 and 13 are diagrams illustrating the operation of the n-th gate stage during the fourth period; and 14 and 15 are diagrams illustrating the operation of the n-th gate stage during the fifth period. Implementation Method

[0008] The present invention will be described more fully hereinafter with reference to the accompanying drawings, which illustrate exemplary embodiments of the present invention. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be thorough and complete and will fully convey the concepts of the present invention to those skilled in the art.

[0009] The advantages and features of the present invention, as well as their implementation methods, will be clarified through the embodiments described with reference to the following figures. However, the present invention may be embodied in various forms and should not be construed as limited to the embodiments described herein. Rather, the embodiments are provided to provide a thorough and complete understanding of the present invention and to fully convey the scope of the invention to those skilled in the art. Furthermore, the present invention is defined solely by the scope of the claims.

[0010] In the drawings used to describe various embodiments of the present invention, the shapes, sizes, proportions, angles, quantities, etc. disclosed in describing the embodiments of the present invention are for illustrative purposes only and are not intended to limit the present invention. Throughout this specification, like reference numerals refer to like elements. Throughout this specification, like elements are represented by like reference numerals. As used herein, unless the word "only" is used, the terms "including," "having," "comprising," etc., imply that additional elements may be included. As used herein, unless the context clearly indicates otherwise, the singular also includes the plural.

[0011] Even if not explicitly stated, the document of the various embodiments of the present invention should be interpreted as including the error range.

[0012] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "above," "below," or "beside," one or more other components may be disposed between the two components, unless the term "directly" is used.

[0013] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0014] In the present invention, the pixel circuits and gate drivers provided on the substrate of the display panel can be implemented using, but are not limited to, N-type metal oxide semiconductor field-effect transistors (MOSFETs). A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers may begin to flow from the source. The drain is the electrode that allows carriers to flow out of the transistor. That is, in a MOSFET, carriers flow from the source to the drain. In a P-type MOSFET, because the carriers are holes, the source voltage may be higher than the drain voltage, causing holes to flow from the source to the drain. In an N-type MOSFET, because the carriers are electrons, electrons flow from the source to the drain, and current may flow from the drain to the source. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be interchanged. Therefore, when describing embodiments of the present invention, one of the source and drain may be described as the first electrode, and the other as the second electrode.

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, among electroluminescent display devices, organic light-emitting display devices including organic light-emitting materials will be primarily described. However, it should be noted that the present invention is not limited to organic light-emitting display devices and can also be applied to inorganic light-emitting display devices including inorganic light-emitting materials.

[0016] Fig. 1 is a diagram illustrating a display device according to an embodiment of the present invention. Fig. 2 is a diagram schematically illustrating an equivalent circuit of a pixel provided in the display panel of Fig. 1. Fig. 3 is a diagram illustrating a gate stage connected to a gate line.

[0017] 1 , a display device according to this embodiment may include: a display panel 100; a timing controller 110; a data driver 120; a gate driver 130; and a level shifter 150. The display device according to this embodiment may be implemented as an electroluminescent display device, but is not limited thereto.

[0018] In the display panel 100, as shown in FIG2 , pixels PXL connected to data lines 14 and gate lines 15 may be arranged in a matrix to form a pixel array. The pixel array may include a plurality of horizontal pixel lines, and a plurality of horizontally adjacent pixels PXL commonly connected to gate lines 15 may be arranged in each horizontal pixel line. Here, a horizontal pixel line may refer to a group of pixels in a horizontal line implemented by horizontally adjacent pixels PXL, rather than a physical signal line. The pixel array may include power lines that transmit a high-level source voltage EVDD to the pixels PXL. The pixels PXL may also be connected to a low-level source voltage EVSS.

[0019] As shown in FIG2 , each pixel PXL may include: a light-emitting device (OLED); and a pixel driving circuit (PCC) for driving the light-emitting device (OLED). The pixel driving circuit (PCC) may include: a driving element that generates a driving current to be applied to the light-emitting device (OLED); and a switching circuit connected to the driving element. The switching circuit can set and maintain the gate-source voltage of the driving element. To this end, the switching circuit can obtain a data voltage (Vdata) via a data line 14, a gate signal (Gout) via a gate line 15, and a high-level source voltage (EVDD) via a power line to set the gate-source voltage of the driving element. The gate electrode of the switching element included in the switching circuit can be connected to the gate line 15, and the first electrode (or second electrode) of the switching element included in the switching circuit can be connected to the data line.

[0020] Each pixel PXL can be one of red, green, blue, and white. The red, green, blue, and white pixels together constitute a unit pixel, and can achieve various colors. The color achieved in a unit pixel can be determined based on the emissivity of each red, green, blue, and white pixel. Furthermore, the white pixel can be omitted, and in this case, the unit pixel can be configured with a red, green, and blue pixel. The gate lines 15 connected to the pixel PXL can also be single or multiple.

[0021] Referring to Figure 1 , the data driver 120 receives image data DATA and a source timing control signal DDC from the timing controller 110. In response to the source timing control signal DDC from the timing controller 110, the data driver 120 converts the image data DATA into a gamma compensation voltage to generate a data voltage Vdata. Based on the supply timing of the gate signal Gout, the data driver 120 supplies the data voltage Vdata to the data lines 14 of the display panel 100. The data driver 120 can be connected to the data lines 14 of the display panel 100 via a chip-on-glass (COG) packaging process or a tape automated bonding (TAB) process. The data driver 120 can be configured in a plurality of partitions, but is not limited thereto, and can be configured as a single data driver.

[0022] 1 , the level shifter 150 can generate a gate timing control signal GDC for driving a pixel's switching element based on an on / off control timing signal input from the timing controller 110 and having a transistor-to-transistor logic (TTL) level. The gate timing control signal GDC can include an enable signal and a clock signal, which oscillate between an on level and an off level. The level shifter 150 can supply the gate timing control signal GDC to the gate driver 130.

[0023] 1 to 3 , the gate driver 130 operates based on the gate timing control signal GDC input from the level shifter 150 to generate the gate signal Gout required to drive the pixel PXL. The gate driver 130 may also supply the gate signal Gout to the gate line 15 .

[0024] The gate driver 130 can be directly mounted on the lower substrate of the display panel 100 using a GIP (gate driver in panel) design. The gate driver 130 can be located in the non-display area (i.e., the bezel area BZ) outside the screen (i.e., the active area AA) of the display panel 100. In a GIP-type design, the level shifter 150 can be mounted on a printed circuit board (PCB) 140 along with the timing controller 110.

[0025] The gate driver 130 may include a plurality of gate stages STG connected to each other based on a cascading architecture. Each of the plurality of gate stages STG may be connected to a corresponding gate line 15 and output a gate signal Gout to the corresponding gate line 15 .

[0026] Some of the plurality of gate stages STG can start operating based on a start signal (VST in FIG5 ), and each of the other gate stages except the aforementioned gate stages can start operating based on an output of a previously operated gate stage (i.e., a carry signal).

[0027] The gate driver 130 may be disposed in the side frame regions BZ facing the display panel 100 and may supply a scan signal to each gate line 15 based on a double feeding scheme, thereby minimizing signal distortion caused by load deviation of each gate line.

[0028] Referring to FIG. 1 , a timing controller 110 can be connected to an external host system via various interface types known to those skilled in the art. The timing controller 110 can receive image data DATA from the host system, correct the image data DATA to compensate for brightness variations caused by differences in electronic properties, and transmit the corrected image data to a data driver 120.

[0029] The timing controller 110 may receive timing signals from a host system, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock signal (MCLK), and may generate on / off control timing signals based on a source timing control signal DDC and a gate timing control signal GDC based on the timing signals.

[0030] FIG. 4 is a diagram illustrating an n-th gate stage STG(n) connected to an n-th gate line; and FIG. 5 is a diagram illustrating a driving signal for driving the n-th gate stage STG(n).

[0031] 4 and 5 , in the n-th gate stage STG(n), the control power supply voltage VDD_AC applied to the second block BK2 may use alternating current (AC) instead of direct current (DC), thereby reducing the number of transistors included in the second block BK2 , where n is an integer.

[0032] In the prior art, additional transistors are required for controlling the QB node QB, and these additional transistors are driven based on a VDD voltage (VDD_DC) using a DC voltage and an AC control signal to pre-charge the QB node QB.

[0033] According to this embodiment, the AC control power supply VDD_AC can replace the VDD_DC voltage and the AC control signal. This embodiment eliminates the need for the additional transistor used to pre-charge the QB node QB in the prior art. In this embodiment, the AC control power supply VDD_AC with an on-level can be applied to the QB node QB via transistors T4 and T6.

[0034] According to this embodiment, the voltage of the AC control power source VDD_AC can be input at an on-level Lon during a vertical start period VA of one frame, and can be input at an off-level Loff during a vertical blank period VB of one frame.

[0035] The configuration of the n-th gate stage STG(n) will be described in detail below.

[0036] The n-th gate stage STG(n) may include: a first block BK1; a second block BK2; a third block BK3; and a fourth block BK4.

[0037] The first block BK1 may be a Q-node controller for controlling the voltage of the Q-node Q. The Q-node controller may be configured to control the voltage of the Q-node Q based on a carry signal and the voltage of the QB node QB. The first block BK1 may include: a transistor T1 connected to the Q-node Q and an input terminal for a carry signal Gout(n-4) input from the (n-4)th stage; a transistor T2 connected to the Q-node Q to an input terminal of the second low power supply GVGL based on a sub-carry signal Gout(n+6) input from the (n+6)th stage; and a transistor T3 connected to the Q-node Q to an input terminal of the second low power supply GVGL based on the voltage of the QB node QB. The carry signal Gout(n-4) may be used to charge the Q-node Q to a turn-on voltage, and the sub-carry signal Gout(n+6) may be used to discharge the Q-node Q to a turn-off voltage. In this embodiment, the output of the (n-4)th stage can be set as the carry signal Gout(n-4), and the output of the (n+6)th stage can be set as the sub-carry signal Gout(n+6), but the present invention is not limited to this. However, when the output of the (n+6)th stage is used as the sub-carry signal Gout(n+6) instead of the output of the (n-4)th stage, the charging duration of the Q node Q can be increased, thereby ensuring operational stability.

[0038] The gate electrode and drain electrode of transistor T1 may be connected to an input terminal for carry signal Gout(n-4), and the source electrode of transistor T1 may be connected to the Q-node Q. The gate electrode of transistor T2 may be connected to an input terminal for sub-carry signal Gout(n+6), the drain electrode of transistor T2 may be connected to the Q-node Q, and the source electrode of transistor T2 may be connected to an input terminal of the second low power supply GVGL. The gate electrode of transistor T3 may be connected to the QB node QB, the drain electrode of transistor T3 may be connected to the Q-node Q, and the source electrode of transistor T3 may be connected to the input terminal of the second low power supply GVGL.

[0039] The second block BK2 may be a QB node controller for controlling the voltage of the QB node QB. The second block BK2 may include: a transistor T4 connected to the first control node Nx and the input terminal of the control power supply VDD_AC; a transistor T5 connecting the first control node Nx to the input terminal of the second low power supply GVGL at the voltage of the Q node Q; a transistor T6 applying the control power supply VDD_AC to the QB node QB at the voltage of the first control node Nx; and a transistor T7 connecting the QB node QB to the input terminal of the second low power supply GVGL at the voltage of the Q node Q.

[0040] The gate electrode and drain electrode of transistor T4 may be connected to the input terminal of the control power supply VDD_AC, and the source electrode of transistor T4 may be connected to the first control node Nx. The gate electrode of transistor T5 may be connected to the Q-node Q, the drain electrode of transistor T5 may be connected to the first control node Nx, and the source electrode of transistor T5 may be connected to the input terminal of the second low power supply GVGL. The gate electrode of transistor T6 may be connected to the first control node Nx, the drain electrode of transistor T6 may be connected to the input terminal of the control power supply VDD_AC, and the source electrode of transistor T6 may be connected to the QB node QB. The gate electrode of transistor T7 may be connected to the Q-node Q, the drain electrode of transistor T7 may be connected to the QB node QB, and the source electrode of transistor T7 may be connected to the input terminal of the second low power supply GVGL.

[0041] The third block BK3 may be an output unit for outputting a gate signal Gout(n). The third block BK3 may include a pull-up transistor PU that controls the flow of current between the input terminal for the n-th clock signal CLK(n) and the output node NO based on the voltage at the Q-node Q; and a pull-down transistor PD that controls the flow of current between the input terminal of the first low power supply AVGL and the output node NO based on the voltage at the QB-node QB.

[0042] A gate electrode of the pull-up transistor PU may be connected to the Q-node Q, a drain electrode of the pull-up transistor PU may be connected to the input terminal for the n-th clock signal CLK(n), and a source electrode of the pull-up transistor PU may be connected to the output node NO. A gate electrode of the pull-down transistor PD may be connected to the QB-node QB, a drain electrode of the pull-down transistor PD may be connected to the output node NO, and a source electrode of the pull-down transistor PD may be connected to the input terminal of the first low power supply AVGL.

[0043] The fourth block BK4 may be a reset unit that resets the voltage of the output node NO to the voltage of the first low power source AVGL and resets the voltage of the QB node QB to the voltage of the second low power source GVGL during the vertical blank period VB.

[0044] The fourth block BK4 may include a transistor T8 connecting the QB node QB to the input of the second low power source GVGL based on the reset signal RST, and a transistor T9 connecting the output node NO to the input of the first low power source AVGL based on the reset signal RST.

[0045] The gate electrode of transistor T8 may be connected to the second control node Ny, the drain electrode of transistor T8 may be connected to the QB node QB, and the source electrode of transistor T8 may be connected to the input terminal of the second low power supply GVGL. The gate electrode of transistor T9 may be connected to the second control node Ny, the drain electrode of transistor T9 may be connected to the output node NO, and the source electrode of transistor T9 may be connected to the input terminal of the first low power supply AVGL.

[0046] The QB node QB remains at an on-level longer than the Q node Q, which can easily degrade the pull-down transistor PD. The fourth block BK4 can reset the voltage of the QB node QB to the voltage of the second low power supply GVGL during the vertical blank period VB based on the reset signal RST, thereby reducing degradation in the pull-down transistor PD.

[0047] To this end, the reset signal RST can turn on the level Lon input during part of the vertical blank period VB, and can turn off the level Loff input during the vertical start period VA and the rest of the vertical blank period VB.

[0048] When the pull-down transistor PD degrades, an off-state current may flow through the off-state pull-down transistor PD. This off-state current may distort the waveform of the gate signal Gout(n). To prevent the off-state current in the pull-down transistor PD, the voltage of the first low power supply AVGL can be set to be greater than the voltage of the second low power supply GVGL. When the pull-down transistor PD is off, the second low power supply GVGL can be connected to the gate electrode of the pull-down transistor PD, and the first low power supply AVGL can be connected to the source electrode of the pull-down transistor PD. In this case, when the voltage of the first low power supply AVGL is greater than the voltage of the second low power supply GVGL, an off-state current does not flow into the pull-down transistor PD due to the reverse bias applied between the gate and source electrodes of the pull-down transistor PD.

[0049] The operation of the n-th gate stage STG(n) can be divided into the first to fifth periods (X1 to X5 in Figures 6 to 15). Here, the first to fourth periods (X1 to X4 in Figures 6 to 15) can correspond to the vertical activation period VA, and the fifth period (X5 in Figures 6 to 15) can correspond to the vertical blanking period VB.

[0050] 6 and 7 are diagrams illustrating the operation of the n-th gate stage STG(n) during the first period X1.

[0051] 6 and 7 , during the first period X1, the voltage of the control power supply VDD_AC can be input at a turn-on level Lon, thereby turning on transistors T4 and T6. Based on the voltage of the control power supply VDD_AC at the turn-on level Lon, the voltage of the QB node QB can have a turn-on level Lon. Based on the voltage of the QB node QB at the turn-on level Lon, transistor T3 and the pull-down transistor PD can be turned on. Based on the second low power supply GVGL connected through transistor T3, the voltage of the Q node Q can have an off level Loff. Based on the first low power supply AVGL connected through the pull-down transistor PD, the voltage of the output node NO can have an off level Loff.

[0052] 8 and 9 are diagrams illustrating the operation of the n-th gate stage STG(n) during the second period X2.

[0053] Referring to Figures 8 and 9 , during the second period X2, transistor T1 can be turned on by the carry signal Gout(n-4) having the on-level Lon, and the Q-node Q can be charged at the on-level Lon. Based on the voltage of the Q-node Q having the on-level Lon, transistors T5, T7, and the pull-up transistor PU can be turned on. When transistor T5 is turned on, the second low power source GVGL can be connected to the first control node Nx, thereby turning off transistor T6. Even when the control power source VDD_AC having the on-level Lon is applied to the first control node Nx via transistor T4 during the second period X2, the control power source VDD_AC having the on-level Lon can still be discharged to the voltage of the second low power source GVGL via transistor T5. When transistor T7 is turned on, the voltage of the QB node QB can have the off-level Loff. When the pull-up transistor PU is turned on, the clock signal CLK(n) having the off-level Loff can be output to the output node NO.

[0054] 10 and 11 are diagrams illustrating the operation of the n-th gate stage STG(n) during the third period X3.

[0055] Referring to Figures 10 and 11 , when a clock signal CLK(n) having a turn-on level Lon is input during the third period X3, the voltage at the Q-node Q can shift from the turn-on level Lon to the bootstrap level Lbst due to the coupling of parasitic capacitance between the gate and drain electrodes of the pull-up transistor PU. The bootstrap level Lbst can be higher than the turn-on level Lon. When the voltage at the Q-node Q shifts to the bootstrap level Lbst, the turn-on response of the pull-up transistor PU can be accelerated. When the voltage at the Q-node Q shifts to the bootstrap level Lbst, the gate-source voltage of the pull-up transistor PU can increase, thereby potentially increasing the amount of current flowing through the pull-up transistor PU. At this point, the clock signal CLK(n) having the turn-on level Lon can be output to the output node NO in response to the turn-on of the pull-up transistor PU, thus providing a gate signal Gout(n) having the turn-on level Lon.

[0056] 12 and 13 are diagrams illustrating the operation of the n-th gate stage STG(n) during the fourth period X4.

[0057] Referring to Figures 12 and 13 , during the fourth period X4, transistor T2 can be turned on by the sub-carry signal Gout(n+6) having the on-level Lon, and the Q-node Q can be discharged to the off-level Loff. Based on the voltage of the Q-node Q having the off-level Loff, transistors T5, T7, and the pull-up transistor PU can be turned off. When transistor T5 is turned off, transistor T6 can be turned on, so that the voltage of the QB node QB can have the on-level Lon. Based on the voltage of the QB node QB having the on-level Lon, transistor T3 and the pull-down transistor PD can be turned on. Based on the second low power source GVGL connected through transistor T3, the voltage of the Q-node Q can be maintained at the off-level Loff, while transistor T3 remains on. Based on the first low power source AVGL connected through the pull-down transistor PD, the voltage of the output node NO can have the off-level Loff.

[0058] FIG. 14 and FIG. 15 are diagrams illustrating the operation of the n-th gate stage STG(n) during the fifth period X5.

[0059] Referring to Figures 14 and 15 , during the fifth period X5, the voltage of the control power supply VDD_AC can be input at the off-level Loff, and the reset signal RST can be input at the on-level Lon. Transistors T8 and T9 can be turned on by the reset signal RST at the on-level Lon. Consequently, the voltage of the QB node QB can be reset to the voltage of the second low power supply GVGL, and the output node NO can be reset to the first low power supply AVGL, thereby preventing abnormal operation (i.e., waveform distortion of the gate signal Gout(n)) caused by coupling from an external source voltage during the vertical blank period VB. When the voltage of the QB node QB is reset to the voltage of the second low power supply GVGL during each vertical blank period VB, degradation in transistor T3 and the pull-down transistor PD including the gate electrode connected to the QB node QB can be reduced.

[0060] 5, 6, 8, 10, 12 and 14, the reset signal RST is used to turn on the level Lon input during part of the vertical blank period VB, and to turn off the level Loff input during the vertical start period VA and the rest of the vertical blank period VB.

[0061] In the gate driver and the display device including the gate driver according to the embodiment of the present invention, the configuration of the gate block can be simplified, thereby achieving a thin and narrow frame.

[0062] The effects according to the present invention are not limited to the above-described examples, and other various effects may be included in this specification.

[0063] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

[0064] This application requests the Korean patent application filed on February 13, 2024 No. 10-2024-0020502, the entire contents of which are incorporated herein by reference.

[0065] 14: Data line 15: Gate line 100: Display panel 110: Timing controller 120: Data drive 130: Gate Driver 140:Printed circuit board 150:Level Shifter AA: Active Area AVGL: First Low Power BK1-BK4: first to fourth blocks BZ: Border Zone CLK(n): nth clock signal DATA: Image data DDC: Source timing control signal EVDD: High level source voltage EVSS: Low-level source voltage GDC: Gate timing control signal Gout(n): nth gate-level signal Gout(n+6): next carry signal Gout(n-4): carry signal Gout: gate signal GVGL: Second Lowest Power Lbst: Bootstrap level Loff: Off level Lon: Open level NO: Output node Nx: first control node Ny: Second control node OLED: Light Emitting Device PCC: Pixel Driver Circuit PD: Pull-down transistor PU: Pull-up transistor PXL: Pixel Q:Q node QB:QB node RST: Reset signal STG(n): nth gate stage STG: Gate Level T1 to T9: transistors (first to ninth transistors) VA: Vertical start period VB: Vertical blank period Vdata: data voltage VDD_AC: control power supply VST: Start signal X1~X5: first period to fifth period

Claims

1. A gate driver comprising a plurality of stages, wherein the nth stage comprises: A pull-up transistor configured to control the current flow between an output node and an input for an nth clock signal based on the voltage of a Q node; a pull-down transistor configured to control the current flow between the output node and an input of a first low power supply based on the voltage of a QB node; and a QB node controller configured to control the voltage of the QB node based on the voltage of a control power supply and the voltage of the Q node, wherein the voltage of the control power supply has an on level during a vertical start-up period of a frame and an off level during a vertical blank period of the frame, where n is an integer, and wherein a transition of the voltage of the control power supply between the on level and the off level is synchronized with a transition between the vertical start-up period and the vertical blank period.

2. The gate driver as described in claim 1, wherein, The QB node controller includes: a fourth transistor connected to an input of the control power supply and a first control node; a fifth transistor configured to connect the first control node to an input of a second low power supply based on the voltage of the Q node; a sixth transistor configured to apply the voltage of the control power supply to the QB node based on the voltage of the first control node; and a seventh transistor configured to connect the QB node to the input of the second low power supply based on the voltage of the Q node.

3. The gate driver as claimed in claim 1, further comprising: A Q-node controller is configured to control the voltage of the Q-node based on a carry signal and the voltage of the QB-node.

4. The gate driver as described in claim 3, wherein, The Q-node controller includes: a first transistor connected to the Q-node and an input for a carry signal input from a (n-4)th stage; a second transistor configured to connect the Q-node to an input of a second low power supply based on a carry signal input from a (n+6)th stage; and a third transistor configured to connect the Q-node to the input of the second low power supply based on the voltage of the QB-node.

5. The gate driver as claimed in claim 1, further comprising: An eighth transistor is configured to connect the QB node to an input of a second low power supply based on a reset signal; And a ninth transistor configured to connect the output node to the input of the first low power supply based on the reset signal.

6. The gate driver as described in claim 5, wherein, The reset signal is input at an on level for a portion of the vertical blank period and at a off level for the other portion of the vertical start and vertical blank periods.

7. The gate driver as claimed in any one of claims 2, 4, and 5, wherein, The voltage of the first low power supply is greater than the voltage of the second low power supply.

8. A display device, comprising: A display panel containing a plurality of gate lines; and a gate driver comprising a plurality of stages connected to the plurality of gate lines, wherein the nth stage comprises: a pull-up transistor configured to control the flow of current between an output node and an input for an nth clock signal based on the voltage of a Q node; a pull-down transistor configured to control the flow of current between the output node and an input of a first low power supply based on the voltage of a QB node; and a QB node controller configured to control the voltage of the QB node based on the voltage of a control power supply and the voltage of the Q node, wherein the voltage of the control power supply has an on level during a vertical start-up period of a frame and an off level during a vertical blank period of the frame, wherein n is an integer, and wherein a transition of the voltage of the control power supply between the on level and the off level is synchronized with a transition between the vertical start-up period and the vertical blank period.

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