Power semiconductor device

Abstract

This invention provides a power semiconductor device, which mainly comprises a second conductivity type contact region formed on a first conductivity type highly doped substrate. The contact region has a double-layer doped structure consisting of a highly doped region and a lightly doped region, making the active region of the device a five-layer structure consisting of a second conductivity type highly doped region, a second conductivity type lightly doped region, an intrinsically semiconductor epitaxial layer, a first conductivity type lightly doped layer, and a first conductivity type highly doped substrate, thereby improving the device's breakdown voltage. Furthermore, metal silicides are introduced on the front and back sides of the device, forming ohmic contacts with the metal layers on the front and back sides to shorten the device's reverse recovery time. The metal electrodes on the front side of the device have a plurality of ring-shaped designs, including at least one second conductivity type metal ring and one first conductivity type metal ring.

Description

Technical Field

[0001] This invention relates to a power semiconductor device, and more particularly to a fast recovery diode semiconductor device that can improve breakdown voltage. Prior Technology

[0002] A Fast Recovery Diode (FRD) is a power semiconductor device used in high-speed switching applications. Under forward bias, an FRD allows current to flow like a regular diode, exhibiting a low forward voltage drop, thus reducing power loss. On the other hand, when switching from forward conduction to reverse blocking, it can rapidly remove charge carriers from the active region, reducing the reverse recovery time (trr), which is crucial in high-speed switching applications. Furthermore, under reverse bias, an FRD blocks current flow and can withstand a certain reverse voltage without breaking down or collapsing. Therefore, FRDs are mainly used in switching power supplies, especially in high-frequency rectifiers and freewheeling diodes, providing efficient and stable power conversion.

[0003] However, with the continuous development of power semiconductor devices, modern power electronics and high-frequency switching circuits are increasingly demanding fast recovery diodes with features such as shorter reverse recovery time and higher voltage withstand capability. Therefore, the industry urgently needs an innovative power semiconductor device structure to meet the high-performance requirements of next-generation power semiconductor devices. Summary of the Invention

[0004] The main objective of this invention is to provide an innovative power semiconductor device that reduces the reverse recovery time of the power semiconductor device, has higher voltage resistance, and improves device performance.

[0005] To achieve the above objectives, the present invention provides a power semiconductor device comprising a substrate, a first conductivity type lightly doped epitaxial layer, an intrinsic semiconductor epitaxial layer, a central second conductivity type doped region, at least one annular second conductivity type doped region, and an annular first conductivity type doped region. The substrate has a first conductivity type heavily doped layer, and the first conductivity type lightly doped epitaxial layer is disposed on the substrate. The intrinsic semiconductor epitaxial layer is disposed on the first conductivity type lightly doped epitaxial layer. The central second conductivity type doped region is disposed in the central region of the intrinsic semiconductor epitaxial layer, and at least one annular second conductivity type doped region is disposed at intervals around the central second conductivity type doped region in the peripheral region of the intrinsic semiconductor epitaxial layer. The annular first conductivity type doped region is disposed around the at least one annular second conductivity type doped region in the peripheral region of the intrinsic semiconductor epitaxial layer. The central second conductivity type doped region and the at least one annular second conductivity type doped region each have a second conductivity type lightly doped region adjacent to an intrinsic semiconductor epitaxial layer, a second conductivity type heavily doped region covering the second conductivity type lightly doped region, and a first metal silicide layer disposed on the second conductivity type heavily doped region.

[0006] In one embodiment of the present invention, the power semiconductor device further includes an upper metal layer having a central metal layer, at least one annular metal layer and an outer annular metal layer, wherein the central metal layer is disposed on and electrically connected to a central second conductivity type doped region, the at least one annular metal layer is disposed on and electrically connected to the at least one annular second conductivity type doped region, and the outer annular metal layer is disposed on and electrically connected to an annular first conductivity type doped region.

[0007] In one embodiment of the present invention, the power semiconductor device, wherein the at least one annular metal layer and the outer annular metal layer are one of a rectangular ring, a square ring, an elliptical ring, and a circular ring.

[0008] The power semiconductor device in one embodiment of the present invention further includes a lower metal layer disposed on the back side of a substrate and electrically connected thereto.

[0009] In one embodiment of the present invention, the power semiconductor device further includes a second metal silicide layer sandwiched between the lower metal layer and the substrate.

[0010] In one embodiment of the present invention, the materials of the first metal silicide layer and the second metal silicide layer are selected from one or a combination of the group consisting of platinum silicide (PtSi), nickel silicide (NiSi), titanium silicide (TiSi), chromium silicide (CrSi), palladium silicide (PdSi), molybdenum silicide (MoSi), cobalt silicide (CoSi), and tungsten silicide (WSi).

[0011] In one embodiment of the present invention, the thicknesses of the first metal silicide layer and the second metal silicide layer are 0.01 to 0.5 micrometers (µm).

[0012] In one embodiment of the present invention, the doping elements of the power semiconductor device, the substrate, the first conductivity type lightly doped epitaxial layer, and the annular first conductivity type doped region are selected from one or a combination of the group consisting of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0013] In a power semiconductor device according to an embodiment of the present invention, the doping element of the second conductivity type doped region and the at least one annular second conductivity type doped region is selected from one or a combination of the group consisting of boron (B), gallium (Ga), indium (In), aluminum (Al) and thallium (Tl).

[0014] In one embodiment of the present invention, the doping concentration of the substrate, the annular first conductivity type doped region, and each of the second conductivity type highly doped regions is greater than 1E17cm-3.

[0015] In a power semiconductor device according to an embodiment of the present invention, the doping concentration of the first lightly doped epitaxial layer and the second lightly doped region is 1E15 to 1E17 cm⁻³.

[0016] In one embodiment of the present invention, the doping concentration of the intrinsic semiconductor epitaxial layer 12 of the power semiconductor device is less than 1E15cm-3.

[0017] In one embodiment of the present invention, the power semiconductor device further comprises a first metal silicide layer 23 disposed between the annular first conductivity doped region 15 and the outer annular metal layer (33).

[0018] In a power semiconductor device according to an embodiment of the present invention, the thickness of the second conductivity type highly doped region is 0.5 to 5 micrometers (µm), and the thickness of the second conductivity type lightly doped region is 2 to 10 micrometers (µm).

[0019] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the drawings and the embodiments described below. Simple Explanation of the Diagram

[0020] Figure 1 is a partial schematic diagram of a power semiconductor device according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a power semiconductor device and a top view of the upper metal layer in another embodiment of the present invention; and Figure 3 is a top view schematic diagram of several embodiments of the upper metal layer of the power semiconductor device of the present invention. Implementation

[0021] The present invention will be explained below through embodiments. These embodiments are not intended to limit the implementation of the invention to any specific environment, application, or special method as described in the embodiments. Therefore, the descriptions of the embodiments are for illustrative purposes only and are not intended to limit the invention. It should be noted that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0022] This invention relates to a power semiconductor device, and more particularly, a fast recovery diode semiconductor device capable of rapid switching. Please refer to Figure 1, which shows a partial schematic diagram of a power semiconductor device according to an embodiment of the present invention. The power semiconductor device 1 of the present invention has a substrate 10, which is a silicon substrate with a first conductivity type of high doping and a thickness of 100-300 micrometers (µm). For example, the substrate 10 is a silicon substrate with N-type high doping, and the doping element is selected from one or a combination of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the doping concentration is greater than 1E17 cm⁻³, but is not limited thereto.

[0023] Next, a first conductivity type lightly doped epitaxial layer 11 with a thickness of 5-15 micrometers (µm) is epitaxially grown on the substrate 10 using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). This first conductivity type lightly doped epitaxial layer 11 is an N-type lightly doped epitaxial layer, and the doping element is selected from one or a combination of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), with a doping concentration of 1E15 to 1E17 cm⁻³, but not limited thereto. Then, an intrinsically semiconductor epitaxial layer 12 is formed on the first conductivity type lightly doped epitaxial layer 11 by epitaxial growth, with a thickness of 45-85 micrometers (µm). In a specific embodiment, the intrinsically semiconductor epitaxial layer 12 has a small amount of background doping elements, including phosphorus (P) and arsenic (As), with a doping concentration of less than 1E15 cm⁻³, but not limited thereto.

[0024] Please refer to Figures 1 and 2 together. Figure 2 shows a cross-sectional view of a power semiconductor device and a top view of the upper metal layer of the device in another embodiment of the present invention. The figure shows that a patterned oxide layer 16 is present on the surface of the intrinsic semiconductor epitaxial layer 12. This oxide layer 16 is formed by patterning and etching an entire oxide layer according to the pattern layout of the active region A in the central region of the device and the annular regions R on both sides of the device, as shown in Figure 2. Furthermore, each doped region within the semiconductor layer of the substrate is covered by several ion implantation processes using the patterned oxide layer 16 as a mask, to form a central second conductive doped region 13 in the active region A, and at least one annular second conductive doped region 14 and an annular first conductive doped region 15 in the annular region R. It should be noted that the central second conductive doped region 13 is located within the active region A in the central region of the device. On the other hand, the annular second conductive type doped region 14 can be a single doped region or multiple doped regions depending on the layout design of the device. If it is a multiple doped region, each annular second conductive type doped region 14 is disposed in the annular region R at intervals and surrounds the central second conductive type doped region 13. In addition, the annular first conductive type doped region 15 is similarly disposed in the outermost region of the annular region R and surrounds the annular second conductive type doped region 14.

[0025] One feature of this invention is that the central second conductivity type doped region 13 located in the active region A of the central region of the power semiconductor device 1 is a double-layer doped structure, which has a second conductivity type lightly doped region 21 and a second conductivity type heavily doped region 22. The second conductivity type lightly doped region 21 is adjacent to the intrinsic semiconductor epitaxial layer 12 and covers the second conductivity type heavily doped region 22. Specifically, the second conductivity type lightly doped region 21 is a P-type lightly doped region with a thickness of 2 to 10 micrometers (µm) and a doping concentration of 1E15 to 1E17 cm⁻³. The second conductivity type heavily doped region 22 is a P-type heavily doped region with a thickness of 0.5 to 5 micrometers (µm) and a doping concentration greater than 1E17 cm⁻³. The doping elements in this double-layer doped structure are selected from one or a combination of the group consisting of boron (B), gallium (Ga), indium (In), aluminum (Al), and thallium (Tl). Specifically, the active region A of the power semiconductor device of the present invention has a five-layer structure, comprising a second conductivity type highly doped region 22, a second conductivity type lightly doped region 21, an intrinsic semiconductor epitaxial layer 12, a first conductivity type lightly doped layer 11, and a first conductivity type highly doped substrate 10, as shown by the enlarged block in Figure 1 (shown by the dashed line). The thickness of the intrinsic semiconductor epitaxial layer 12 in the five-layer structure is 40-70 micrometers (µm). This five-layer PN junction structure widens the band gap between each layer, thereby further improving the reverse breakdown voltage of the device. Furthermore, the depth or thickness of each layer in the aforementioned five-layer structure can be individually adjusted and varied according to the voltage withstand requirements of the power semiconductor device, for example: 600 volts (V), 750 volts (V), 850 volts (V), or 1000 volts (V) and above, which will not be elaborated here.

[0026] As shown in Figure 2, the power semiconductor device 1 of the present invention has a plurality of annular second conductivity type doped regions 14 disposed in annular regions R on both sides of the device's outer periphery, with each annular doped region spaced apart from the others. Specifically, each annular second conductivity type doped region 14, like the central second conductivity type doped region 13, is a double-layer doped structure, similarly having a second conductivity type lightly doped region 21 and a second conductivity type heavily doped region 22. The second conductivity type lightly doped region 21 is adjacent to the intrinsic semiconductor epitaxial layer 12 and covers the second conductivity type heavily doped region 22, as shown by the enlarged block indicated by the dashed line in Figure 2. The doping elements and doping concentrations of each doped region are described above and will not be repeated here. Furthermore, the annular region R further includes an annular first conductivity type doped region 15 disposed in the outermost intrinsic semiconductor epitaxial layer 12 on both sides of the device. Specifically, this annular first conductivity type doped region 15 is an N-type highly doped region, and its doping element is selected from one or a combination of the group consisting of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi). The doping concentration is greater than 1E17cm-3, but is not limited thereto.

[0027] As shown in Figures 1 and 2, the power semiconductor device 1 further includes an upper metal layer 30, which has a central metal layer 31, at least one annular metal layer 32, and an outer annular metal layer 33. The central metal layer 31 is disposed on and electrically connected to the central second conductivity type doped region 13 within the active region A. The at least one annular metal layer 32 is disposed on and surrounds the at least one annular second conductivity type doped region 14 within the annular region R, belonging to the second conductivity type metal ring, i.e., a P-type metal ring, and is electrically connected to each annular second conductivity type doped region 14. The outer annular metal layer 33 is disposed on and surrounds the at least one annular metal layer 32 on the outermost annular first conductivity type doped region 15 within the annular region R, belonging to the first conductivity type metal ring, i.e., an N-type metal ring, and is electrically connected to the annular first conductivity type doped region 15.

[0028] As shown in Figures 1 and 2, the intrinsic semiconductor epitaxial layer 12 has a plurality of annular second conductivity type doped regions 14. Therefore, the annular metal layer 32 is correspondingly designed with a multi-ring layout, which is arranged at intervals. However, it is not limited to this. In fact, the annular metal layer 32 can also be designed with a single ring, usually with 1 to 10 rings. Referring to Figure 3, the upper metal layer 30 of the power semiconductor device 1, including the central metal layer 31, the annular metal layer 32, and the outer annular metal layer 33, can be, for example, but not limited to, a rectangular ring, a square ring, an elliptical ring, or a circular ring. In addition, as shown in Figures 1 and 2, the power semiconductor device 1 of the present invention further includes a passivation layer 50 and a protective layer 60 covering the annular metal layer 32 and the outer annular metal layer 33 in the annular region R.

[0029] On the other hand, the power semiconductor device 1 of the present invention further includes a lower metal layer 40 disposed on and electrically connected to one of the back sides of the substrate 10. Another feature of the present invention is that the power semiconductor device 1 has a metal silicide structure disposed between the upper metal layer 30 and the central second conductivity type doped region 13, the plurality of annular second conductivity type doped regions 14, and the annular first conductivity type doped region 15. Specifically, the first metal silicide layer 23 is disposed within the central second conductivity type doped region 13 and between the second conductivity type highly doped region 22 within the plurality of annular second conductivity type doped regions 14 and the upper metal layer 30, and between the upper metal layer 30 and the annular first conductivity type doped region 15, to form an ohmic contact and thereby shorten the reverse recovery time of the power semiconductor device. Preferably, in another embodiment, the power semiconductor device 1 further includes a second metal silicide layer 24 sandwiched between the lower metal layer 40 and the substrate 10, as shown in FIG1, to further shorten the reverse recovery time of the power semiconductor device. Specifically, the thickness of the aforementioned first metal silicide layer 23 and second metal silicide layer 24 is 0.01~0.5 micrometers (µm), and the material is selected from one or a combination of the group consisting of platinum silicide (PtSi), nickel silicide (NiSi), titanium silicide (TiSi), chromium silicide (CrSi), palladium silicide (PdSi), molybdenum silicide (MoSi), cobalt silicide (CoSi), and tungsten silicide (WSi).

[0030] The above embodiments are merely illustrative of the implementation of the present invention and to explain its technical features, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention shall be determined by the scope of the patent application.

[0031] 1: Power semiconductor components 10:Substrate 11: First conductivity type lightly doped epitaxial layer 12: Intrinsic semiconductor epitaxial layer 13: Central second conductivity type doped region 14: Ring-shaped second conductivity type doped region 15: Ring-shaped first conductivity type doped region 16: Oxide layer 21: Lightly doped region of the second conductivity type 22: Second conductivity type highly doped region 23: First metal silicate layer 24: Second metal silicide layer 30: Upper metal layer 31: Central Metal Layer 32: Ring-shaped metal layer 33: Outer ring-shaped metal layer 40: Lower metal layer 50: Passivation layer 60: Protective layer A: Active Area R: Annular region

Claims

1. A power semiconductor device, comprising: a substrate having a first conductivity type heavily doped region; a first conductivity type lightly doped epitaxial layer disposed on the substrate; an intrinsic semiconductor epitaxial layer disposed on the first conductivity type lightly doped epitaxial layer; a central second conductivity type doped region disposed in the central region of the intrinsic semiconductor epitaxial layer; at least one annular second conductivity type doped region disposed at intervals around the central second conductivity type doped region in the peripheral region of the intrinsic semiconductor epitaxial layer; and an annular first conductivity type doped region disposed around the at least one annular second conductivity type doped region in the peripheral region of the intrinsic semiconductor epitaxial layer, wherein... The central second conductivity type doped region and the at least one annular second conductivity type doped region each have: a second conductivity type lightly doped region adjacent to the intrinsic semiconductor epitaxial layer; a second conductivity type heavily doped region covering the second conductivity type lightly doped region; and a first metal silicide layer disposed on the second conductivity type heavily doped region.

2. The power semiconductor device as claimed in claim 1 further includes an upper metal layer having a central metal layer, at least one annular metal layer and an outer annular metal layer, wherein the central metal layer is disposed on and electrically connected to a central second conductivity type doped region, the at least one annular metal layer is disposed on and electrically connected to the at least one annular second conductivity type doped region, and the outer annular metal layer is disposed on and electrically connected to the annular first conductivity type doped region.

3. The power semiconductor device as claimed in claim 2, wherein the at least one annular metal layer and the outer annular metal layer are one of a rectangular ring, a square ring, an elliptical ring, and a circular ring.

4. The power semiconductor device as described in claim 1 further includes a lower metal layer disposed on and electrically connected to one of the back sides of the substrate.

5. The power semiconductor device as described in claim 4 further includes a second metal silicide layer sandwiched between the lower metal layer and the substrate.

6. The power semiconductor device as claimed in claim 5, wherein the materials of the first metal silicide layer and the second metal silicide layer are selected from one or a combination of the group consisting of platinum silicide (PtSi), nickel silicide (NiSi), titanium silicide (TiSi), chromium silicide (CrSi), palladium silicide (PdSi), molybdenum silicide (MoSi), cobalt silicide (CoSi), and tungsten silicide (WSi).

7. The power semiconductor device as claimed in claim 5, wherein the thicknesses of the first metal silicide layer and the second metal silicide layer are 0.01 to 0.5 micrometers (µm).

8. The power semiconductor device as claimed in claim 1, wherein the doping elements of the substrate, the first conductivity type lightly doped epitaxial layer and the annular first conductivity type doped region are selected from one or a combination of the group consisting of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).

9. The power semiconductor device as claimed in claim 1, wherein the doping element of the second conductivity type doped region and the at least one annular second conductivity type doped region is selected from one or a combination of the group consisting of boron (B), gallium (Ga), indium (In), aluminum (Al), and thallium (Tl).

10. The power semiconductor device as claimed in claim 1, wherein the doping concentration of the substrate, the annular first conductivity type doped region, and the second conductivity type highly doped region is greater than 1E17cm⁻³.

11. The power semiconductor device as claimed in claim 1, wherein the doping concentration of the first conductivity type lightly doped epitaxial layer and the second conductivity type lightly doped region is 1E15 to 1E17 cm⁻³.

12. The power semiconductor device as claimed in claim 1, wherein the doping concentration of the intrinsic semiconductor epitaxial layer is less than 1E15cm⁻³.

13. The power semiconductor device as claimed in claim 2, wherein the first metal silicide layer is further disposed between the annular first conductivity type doped region and the outer annular metal layer.

14. The power semiconductor device as claimed in claim 1, wherein the thickness of the second conductivity type highly doped region is 0.5 to 5 micrometers (µm), and the thickness of the second conductivity type lightly doped region is 2 to 10 micrometers (µm).

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