Semiconductor structure and method of manufacturing thereof

Abstract

The embodiment of the semiconductor structure includes a first active region and a second active region extending along a first direction, a functional gate structure and a non-functional gate structure aligned with each other and extending along a second direction, and a metallization layer above the functional and non-functional gate structures. The metallization layer defines the first metallization region, the second metallization region, and one or two intermediate metallization regions between the first and second metallization regions. The functional gate structure overlaps with the first metallization region and with one of the one or two intermediate metallization regions to define an overlapping portion of the one or two intermediate metallization regions. The overlapping portion has a space defined therein, the dimensions of which are adapted for connection features between the functional gate structure and one of the one or two intermediate metallization regions.

Description

[Previous Technology]

[0001] The latest trend of miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power but offer greater functionality at higher speeds. Miniaturization processes have also led to more stringent design and manufacturing specifications and reliability challenges. For example, IC manufacturing is moving towards reducing component size and cell area to increase the number of transistors and other circuit elements within the IC die. However, the reduction in cell area and increase in transistor density within the IC die also makes the wiring of interconnect structures within the IC die more complex and challenging.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "consisting of." In this disclosure, "one of A, B, C" refers to A, B, and / or C (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean one from A, one from B, and one from C, unless otherwise stated.

[0007] In some embodiments, the circuit cell includes three or four conductive tracks for forming signal paths over the lowest metallization layer (also known as the MO layer) above the transistor of the circuit cell. In some embodiments, minimizing wiring resources for implementing cross-coupled transistors is challenging, where some gate structures are configured as non-functional gate structures. In some embodiments, as further illustrated in this disclosure, one or more non-functional gate structures and corresponding one or more aligned functional gate structures are formed based on continuous-poly-on-oxide-diffusion-edge (CPODE) patterns and / or shifted cut-poly (CPO) patterns, providing more options for the placement of gate via structures. Therefore, in some embodiments, one or more advantages of fabricating semiconductor structures based on shortened CPODE patterns and / or shifted CPO patterns include: increased layout and routing flexibility, reduced routing complexity thereby reducing unintended signal coupling, increased number of vias connecting gate structures to the same conductive trace to reduce resistance, reduced number of dummy devices in circuit cells of skewed logic circuits, or any combination thereof.

[0008] FIG1 is a block diagram of a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 corresponds to a portion of an integrated circuit (IC).

[0009] As shown in FIG. 1, the semiconductor device 100 includes at least one circuit macro 110, etc. In some embodiments, the circuit macro 110 corresponds to a set of semiconductor elements configured as memory, controller, one or more logic gates, or similar elements. The circuit macro 110 includes one or more circuit cells, such as circuit cells 112, 114, and 116, etc. In some embodiments, each of the circuit cells 112, 114, and 116 includes a transistor formed based on one or more active regions extending along a first direction (e.g., the X direction) and one or more gate structures extending along a second direction (e.g., the Y direction). In some embodiments, each of the circuit cells 112, 114, and 116 has corresponding cell heights H1, H2, and H3 measurable along the second direction.

[0010] In some embodiments, each of circuit cells 112, 114, and 116 includes a respective conductive track within one or more metallization layers, electrically connecting various transistors within each circuit cell 112, 114, and 116. In some embodiments, semiconductor device 100 defines a plurality of power track regions extending along a first direction, configured to carry a first supply voltage (e.g., VDD) or a second supply voltage (e.g., VSS or ground). In some embodiments, a circuit cell includes a first side extending along a power track region and a second side extending along another power track region. In some embodiments, a circuit cell without any other power track region between the first and second sides is sometimes referred to as having a standard cell height. In some embodiments, based on a more compact design for certain process nodes, a circuit cell with a standard cell height includes up to four metallization regions (in addition to the power track regions) extending along the first direction in the lowest metallization layer (also referred to as the MO layer) above the circuit cell transistor. In some embodiments, any one of the cell heights H1, H2, and H3 has a standard cell height (e.g., 1H cell), two standard cell heights (e.g., 2H cell), or three standard cell heights (e.g., 3H cell). In some embodiments, a cell in the circuit macro 110 corresponds to multiple standard cell heights or less than one standard cell height (e.g., 1 / 2H cell).

[0011] FIG2A is a layout diagram 200A of various layout patterns corresponding to a portion of a first circuit cell example according to some embodiments. In some embodiments, the first circuit cell example is part of a semiconductor device, such as semiconductor device 100 in FIG1.

[0012] Layout diagram 200A depicts a first active region pattern 212, indicating a first active region of a semiconductor device extending along a first direction (e.g., the X direction); and a second active region pattern 214, indicating a second active region of a semiconductor device extending along a first direction (e.g., the X direction). In some embodiments, an isolation region is located between and adjacent to the first and second active regions, as shown in the blank area 216 between the first active region pattern 212 and the second active region pattern 214. In some embodiments, one of the first and second active regions is used to form one or more p-type transistors; while the other of the first and second active regions is used to form one or more n-type transistors.

[0013] Layout 200A further includes a first gate pattern 222, a second gate pattern 224, a third gate pattern 226a, and a fourth gate pattern 226b. The first gate pattern 222 and the second gate pattern 224 each indicate one or more functional or non-functional gate structures extending along a second direction (e.g., the Y direction). The third gate pattern 226a is located between the first gate pattern 222 and the second gate pattern 224, indicating a functional gate structure extending along the second direction (e.g., the Y direction) and overlapping with the first active region (e.g., overlapping at least across the entire width of the first active region along the second direction). The fourth gate pattern 226b is also located between the first gate pattern 222 and the second gate pattern 224, indicating a non-functional gate structure extending along the second direction (e.g., the Y direction), aligned with the functional gate structure indicated by the third gate pattern 226a along the second direction, and overlapping with the second active region (e.g., overlapping at least across the entire width of the second active region along the second direction).

[0014] In some embodiments, a transistor is formed based on one of the active regions and a corresponding gate structure overlapping therewith. For example, one or more channel structures overlapping a functional gate structure (e.g., indicated by a third gate pattern 226a) are formed within a first active region (e.g., indicated by a first active region pattern 212). In some embodiments, one or more channel structures are located below or surrounded by the functional gate structure. In some embodiments, a first drain / source structure is formed within the active region and on a first side of the functional gate structure; and a second drain / source structure is formed within the active region and on a second side of the functional gate structure. In some embodiments, a combination of the functional gate structure, one or more channel structures, the first drain / source structure, and the second drain / source structure corresponds to a planar field-effect transistor (FET), a fin field-effect transistor (FinFET), a nanosheet field-effect transistor (nanosheet FET), a nanowire field-effect transistor (nanowire FET), or a complementary field-effect transistor (CFET).

[0015] In layout diagram 200A, the first circuit cell example has a cell height of H4. In some embodiments, the first circuit cell example includes a metallization layer above a functional gate structure and a non-functional gate structure. In some embodiments, the metallization layer is the lowest metallization layer of one or more metallization layers above the functional gate structure and the non-functional gate structure in the first circuit cell example, sometimes referred to as the M0 layer of the first circuit cell example. As a non-limiting example, the first circuit cell example of layout diagram 200A has three metallization regions in the M0 layer. Layout diagram 200A includes a first metallization trajectory pattern 232, a second metallization trajectory pattern 234, and a third metallization trajectory pattern 236, corresponding to various metallization regions defined in the metallization layer. For example, the first metallization trajectory pattern 232 indicates a first metallization region extending above the first active region along a first direction (e.g., the X direction); the second metallization trajectory pattern 234 indicates a second metallization region extending above the second active region along a first direction (e.g., the X direction); and the third metallization trajectory pattern 236 indicates a third metallization region extending along a first direction (e.g., the X direction) and located between the first and second metallization regions.

[0016] In FIG. 2A, as a non-limiting example, the non-functional gate structure indicated by the fourth gate pattern 226b is formed based on a continuous polysilicon-on-diode (CPODE) process at the diffusion edge to form a non-functional gate structure adjacent to the functional gate structure indicated by the third gate pattern 226a, the non-functional gate structure being a dielectric gate structure. In some embodiments, the fourth gate pattern 226b is also a CPODE pattern used to form the corresponding non-functional gate structure, and the third gate pattern 226a is defined based on subtracting the fourth gate pattern 226b from a gate pattern extending at least the entire cell height H4. In this example, the boundary between the third gate pattern 226a and the fourth gate pattern 226b is arranged approximately in the middle of the first active region indicated by the first active region pattern 212 and the second active region indicated by the second active region pattern 214. In Figure 2A, if the functional gate structure indicated by the third gate pattern 226a is to be electrically connected to the conductive trace of the metallization layer (e.g., the M0 layer), in some embodiments the only option is through a connection feature (e.g., a via structure) indicated by the via pattern 242, which connects the functional gate structure and the conductive trace formed based on the first metallization region indicated by the first metallization trace pattern 232.

[0017] FIG2B is a layout diagram 200B of various layout patterns corresponding to the second circuit cell example portion, conforming to some embodiments. The second circuit cell example is a modification based on the first circuit cell example. Therefore, elements depicted in FIG2B that are the same or similar to those in FIG2A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0018] Compared to layout diagram 200A, layout diagram 200B includes a modified third gate pattern 226c indicating a functional gate structure of an example of a second circuit cell and a modified fourth gate pattern 226d indicating a non-functional gate structure of an example of a second circuit cell. Compared to the example in FIG2A, the length L1 of the modified third gate pattern 226c is greater than the length of the third gate pattern 226a; the length L2 of the modified fourth gate pattern 226d is less than the length of the fourth gate pattern 226b (i.e., the modified fourth gate pattern 226d is a shortened CPODE pattern). Therefore, the functional gate structure indicated by the modified third gate pattern 226c overlaps with the first metallized region indicated by the first metallized trajectory pattern 232 and with the third metallized region indicated by the third metallized trajectory pattern 236. In some embodiments, the measurable length along the second direction of the non-functional gate structure within the cell region of the second circuit cell example (e.g., indicated by the length L2 of the modified fourth gate pattern 226d) is equal to or greater than the measurable width along the second direction of the second active region (e.g., indicated by the width W1 of the second active region pattern 214). In some embodiments, the length of the non-functional gate structure along the second direction (e.g., L2) is less than half of the cell height of the cell region along the second direction (e.g., half of H4).

[0019] In some embodiments, the functional gate structure overlaps with a third metallization region to define an overlapping portion of the third metallization region, the overlapping portion of the third metallization region having a space defined therein, the size of which is adapted for a connection feature between the functional gate structure and the third metallization region (e.g., a space indicated by another via pattern 244). In FIG. 2B, if the functional gate structure indicated by the modified third gate pattern 226c is to be electrically connected to a conductive trace of a metallization layer (e.g., an MO layer), in some embodiments there are two options, including: connecting the functional gate structure to a conductive trace formed based on a first metallization region indicated by a first metallization trace pattern 232 via a connection feature (e.g., a via structure) indicated by a via pattern 242; and connecting the functional gate structure to a conductive trace formed based on a third metallization region indicated by a third metallization trace pattern 236 via a connection feature (e.g., a via structure) indicated by a via pattern 244.

[0020] In some embodiments, the width of the third metallized region (e.g., indicated by the width W2 of the third metallized trajectory pattern 236) is 1.2 to 2 times the width of the first metallized region (e.g., indicated by the width W3 of the first metallized trajectory pattern 232). In some embodiments, the width of the third metallized region (e.g., W2) is 1.2 to 2 times the width of the second metallized region (e.g., indicated by the width W4 of the second metallized trajectory pattern 234). In some embodiments, the widths of the first metallized region (e.g., W3) and the second metallized region (e.g., W4) are substantially the same (e.g., the internal variation is within 10% of the nominal width).

[0021] In some embodiments, compared to the first circuit cell example in FIG2A, the second circuit cell example in FIG2B, having a shortened CPODE pattern (e.g., fourth gate pattern 226b relative to the modified fourth gate pattern 226d), provides additional options for landing vias between the functional gate structure and the conductive traces of the MO layer (e.g., one via pattern 242 in FIG2A relative to two via patterns 242 and 244 in FIG2B). In some embodiments, one or more benefits of implementing the shortened CPODE pattern and increasing the options for landing vias include increased layout and routing flexibility, reduced routing complexity thereby reducing unintended signal coupling, increased number of vias connecting the gate structure to the same conductive trace to reduce resistance, reduced number of dummy devices in the circuit cell of skewed logic circuitry, or any combination thereof.

[0022] FIG2C is a layout diagram 200C of various layout patterns corresponding to the portion of the third circuit cell example, conforming to some embodiments. The third circuit cell example is a variation of the first circuit cell example. Therefore, elements depicted in FIG2C that are the same or similar to those in FIG2A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0023] Compared to layout diagram 200A, layout diagram 200C includes a third circuit cell example with a cell height H4 and a third circuit cell example, comprising four metallized regions in an MO layer, indicated by four metallization trajectory patterns 231, 233, 235, and 237, which indicate four respective metallized regions extending along a first direction (e.g., the X direction). In some embodiments, the widths of the metallized regions indicated by the metallization trajectory patterns 231, 233, 235, and 237 are substantially the same (e.g., internal variations within 10% of the nominal width). In this example, the boundary between the third gate pattern 226a and the fourth gate pattern 226b is arranged approximately midway between the first active region indicated by the first active region pattern 212 and the second active region indicated by the second active region pattern 214.

[0024] As shown in FIG. 2C, if a functional gate structure indicated by a third gate pattern 226a is to be electrically connected to a conductive trace of a metallization layer (e.g., an MO layer), in some embodiments the only feasible option is through a connection feature (e.g., a via structure) indicated by a via pattern 246, which connects the functional gate structure and the conductive trace formed based on a first metallization region indicated by a first metallization trace pattern 231. In some embodiments, as shown in FIG. 2C, although the third gate pattern 226a overlaps with the metallization trace pattern 235, the boundary between the third gate pattern 226a and the fourth gate pattern 226b is too close to the metallization trace pattern 235, thus making the formation of a via structure landing on the conductive trace based on the metallization trace pattern 235 susceptible to process variations. Therefore, a via structure connecting a functional gate structure (e.g., indicated by the third gate pattern 226a) and a conductive trace based on the metallization trace pattern 235 is not feasible or impractical.

[0025] FIG2D is a layout diagram 200D of various layout patterns corresponding to the portion of the fourth circuit cell example, conforming to some embodiments. The fourth circuit cell example is a modification based on the third circuit cell example and with reference to the second circuit cell example. Therefore, the same or similar elements depicted in FIG2D as those in FIG2A-2C are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0026] Compared to layout diagram 200C, layout diagram 200D includes a modified third gate pattern 226c and a modified fourth gate pattern 226d as shown in FIG2B. Compared to the example in FIG2C, the length L1 of the modified third gate pattern 226c is greater than the length of the third gate pattern 226a; and the length L2 of the modified fourth gate pattern 226d is less than the length of the fourth gate pattern 226b. Therefore, in some embodiments, the functional gate structure indicated by the modified third gate pattern 226c overlaps with the first metallized region indicated by the first metallized trajectory pattern 231 and with the third metallized region indicated by the third metallized trajectory pattern 235. In some embodiments, the relationship between the length (e.g., length L2) of the non-functional gate structure within the cell region of the fourth circuit cell example, the width of the second active region, and the cell height (e.g., H4) of the cell region along the second direction is as described in FIG2B.

[0027] In some embodiments, the functional gate structure (e.g., indicated by the modified third gate pattern 226c) overlaps with the metallized region indicated by the metallization trajectory pattern 231 to define the via pattern 246. In some embodiments, the functional gate structure (e.g., indicated by the modified third gate pattern 226c) further overlaps with the metallized region indicated by the metallization trajectory pattern 235 to define an overlapping portion in which a space is defined, the size of which is adapted for a connection feature (e.g., indicated by the via pattern 248) between the functional gate structure and the corresponding metallized region. In some embodiments, as shown in FIG2D, since the boundary between the modified third gate pattern 226c and the modified fourth gate pattern 226d is moved to a position farther away from the first active region indicated by the first active region pattern 212, forming the via structure based on the via pattern 248 is less susceptible to process variations than in the example of FIG2C, and thus becomes a feasible or practical option.

[0028] Therefore, as shown in FIG2D, if a functional gate structure indicated by the modified third gate pattern 226c is to be electrically connected to a conductive trace of a metallization layer (e.g., an MO layer), in some embodiments there are two options, including: connecting the functional gate structure and a conductive trace formed based on a first metallization region indicated by the first metallization trace pattern 231 via a connection feature (e.g., a via structure) indicated by the via pattern 246; and connecting the functional gate structure and a conductive trace formed based on a third metallization region indicated by the third metallization trace pattern 235 via a connection feature (e.g., a via structure) indicated by the via pattern 248. In some embodiments, the fourth circuit cell example in FIG2D with a shortened CPODE pattern (e.g., fourth gate pattern 226b relative to the modified fourth gate pattern 226d) has similar options and benefits as discussed with reference to FIG2B, compared to the third circuit cell example in FIG2C.

[0029] FIG3A is a layout diagram 300A of various layout patterns corresponding to a portion of the fifth circuit cell example, conforming to some embodiments. The fifth circuit cell example is a variation of the first circuit cell example. Therefore, elements depicted in FIG3A that are the same or similar to those in FIG2A are given the same reference numerals, and their detailed descriptions are simplified or omitted. In some embodiments, layout diagram 300A includes a fifth circuit cell example having a cell height of H4, and the fifth circuit cell example having three metallized regions in the MO layer.

[0030] Compared to layout diagram 200A, layout diagram 300A includes a fifth gate pattern 326a and a sixth gate pattern 326b. The fifth gate pattern 326a is located between the first gate pattern 222 and the second gate pattern 224, indicating a functional gate structure that extends along a second direction (e.g., the Y direction) and overlaps with the first active region. The sixth gate pattern 326b is also located between the first gate pattern 222 and the second gate pattern 224, indicating a non-functional gate structure that extends along a second direction (e.g., the Y direction), is aligned with the functional gate structure along the second direction, and overlaps with the second active region.

[0031] As a non-limiting example in FIG3A, the non-functional gate structure indicated by the sixth gate pattern 326b is formed based on a diced polysilicon (CPO) process, wherein the non-functional gate structure is implemented as a dielectric gate structure or a conductive gate structure and is spaced apart from the functional gate structure. In some embodiments, the CPO process is performed based on a CPO pattern 332, which separates the gate pattern extending across the entire cell height H4 into a fifth gate pattern 326a and a sixth gate pattern 326b. In this example, the CPO pattern 332 is arranged approximately midway between the first active region indicated by the first active region pattern 212 and the second active region indicated by the second active region pattern 214.

[0032] In FIG. 3A, if the functional gate structure indicated by the fifth gate pattern 326a is to be electrically connected to the conductive trace of the metallization layer (e.g., the MO layer), in some embodiments the only feasible option is through a connection feature (e.g., a via structure) indicated by the via pattern 242, which connects the functional gate structure and the conductive trace formed based on the first metallization region indicated by the first metallization trace pattern 232. In some embodiments, as shown in FIG. 3A, although the fifth gate pattern 326a overlaps with the metallization trace pattern 236, the corresponding overlap space is insufficient to accommodate the via pattern therein.

[0033] FIG3B is a layout diagram 300B of various layout patterns corresponding to a portion of the sixth circuit cell example, conforming to some embodiments. The sixth circuit cell example is a modification based on the fifth circuit cell example. Therefore, elements depicted in FIG3B that are the same or similar to those in FIG3A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0034] Compared to layout diagram 300A, layout diagram 300B includes a modified fifth gate pattern 326c, indicating a functional gate structure of an example of a sixth circuit cell, and a modified sixth gate pattern 326d, indicating a non-functional gate structure of an example of a sixth circuit cell. In some embodiments, the modified fifth gate pattern 326c and the modified sixth gate pattern 326d are defined based on a CPO pattern 334, which separates a gate pattern extending across the entire cell height H4 into the modified fifth gate pattern 326c and the modified sixth gate pattern 326d. Compared to the example in FIG. 3A, the CPO pattern 334 is moved to a position further away from the first active region pattern 212. In some embodiments, the length L3 of the modified fifth gate pattern 326c is greater than the length of the fifth gate pattern 326a; and the length L4 of the modified sixth gate pattern 326d is less than the length of the sixth gate pattern 226b. Therefore, in some embodiments, the functional gate structure indicated by the modified third gate pattern 226c overlaps with the first metallized region indicated by the first metallized trajectory pattern 232 and with the third metallized region indicated by the third metallized trajectory pattern 236. In some embodiments, the non-functional gate structure within the cell region of the sixth circuit cell example (e.g., indicated by the length L4 of the modified sixth gate pattern 326d) has a measurable length in the second direction equal to or greater than the measurable width in the second direction of the second active region (e.g., indicated by the width W1 of the second active region pattern 214). In some embodiments, the length of the non-functional gate structure in the second direction (e.g., L4) is less than half the cell height of the cell region in the second direction (e.g., half of H4).

[0035] In some embodiments, the functional gate structure overlaps with the third metallization region to define an overlapping portion of the third metallization region, and the overlapping portion of the third metallization region has a space defined therein, the size of which is adapted for connection features between the functional gate structure and the third metallization region (e.g., indicated by another via pattern 244). Referring to FIG2B, in some embodiments, the width of the third metallization region (e.g., W2) is 1.2 to 2 times the width of the first metallization region (e.g., W3). In some embodiments, the width of the third metallization region (e.g., W2) is 1.2 to 2 times the width of the second metallization region (e.g., W4). In some embodiments, the width of the first metallization region (e.g., W3) and the width of the second metallization region (e.g., W4) are substantially the same (e.g., having internal variation within 10% of the nominal width).

[0036] As shown in FIG3B and similarly referring to FIG2B, if a functional gate structure indicated by the modified fifth gate pattern 326c is to be electrically connected to a conductive trace of a metallization layer (e.g., an MO layer), in some embodiments there are two options, including connecting the functional gate structure to a conductive trace formed based on a first metallization region indicated by a first metallization trace pattern 232 via a connection feature (e.g., a via structure) indicated by a via pattern 242, and connecting the functional gate structure to a conductive trace formed based on a third metallization region indicated by a third metallization trace pattern 236 via a connection feature (e.g., a via structure) indicated by a via pattern 244. In some embodiments, the sixth circuit cell example in FIG3B with a shifted CPO pattern (e.g., CPO pattern 334 relative to CPO pattern 332) provides options and benefits similar to those discussed with reference to FIG2B, compared to the fifth circuit cell example in FIG3A.

[0037] FIG3C is a layout diagram 300C of various layout patterns corresponding to the seventh circuit cell example portion, conforming to some embodiments. In some embodiments, the seventh circuit cell example is a variation of the fifth circuit cell example. Therefore, elements depicted in FIG3C that are the same or similar to those in FIG3A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0038] Compared to layout diagram 300A, layout diagram 300C includes a seventh circuit cell example with a cell height H4, and the MO layer of the seventh circuit cell example has four metallized regions, including four metallization trajectory patterns 231, 233, 235, and 237, indicating four respective metallized regions extending along a first direction (e.g., the X direction). In some embodiments, the widths of the metallized regions indicated by the metallization trajectory patterns 231, 233, 235, and 237 are substantially the same (e.g., having internal variations within 10% of the nominal width). In this example, the CPO pattern 332 is arranged approximately midway between the first active region indicated by the first active region pattern 212 and the second active region indicated by the second active region pattern 214.

[0039] As shown in FIG. 3C, if a functional gate structure indicated by the fifth gate pattern 326a is to be electrically connected to a conductive trace of a metallization layer (e.g., the MO layer), in some embodiments, the only option is to connect the functional gate structure to a conductive trace formed based on a first metallization region indicated by the first metallization trace pattern 231 via a connection feature (e.g., a via structure) indicated by the via pattern 246. In some embodiments, as shown in FIG. 3C, although the fifth gate pattern 326a overlaps with the metallization trace pattern 235, the boundary between the fifth gate pattern 326a and the sixth gate pattern 326b is too close to the metallization trace pattern 235, thus making the formation of a via structure falling on a conductive trace based on the metallization trace pattern 235 susceptible to process variations. Therefore, a via structure for connecting a functional gate structure (e.g., indicated by the fifth gate pattern 326a) and a conductive trace based on the metallization trace pattern 235 is not feasible or impractical.

[0040] FIG3D is a layout diagram 300D of various layout patterns corresponding to the eighth circuit cell example section, conforming to some embodiments. The eighth circuit cell example is a modification based on the seventh circuit cell example and referring to the sixth circuit cell example. Therefore, the same or similar elements depicted in FIG3D as those in FIG3A-3C are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0041] Compared to layout diagram 300C, layout diagram 300D includes a modified fifth gate pattern 326c and a modified sixth gate pattern 326d as shown in FIG3B. Compared to the example in FIG3C, the length L3 of the modified fifth gate pattern 326c is greater than the length of the fifth gate pattern 326a; and the length L4 of the modified sixth gate pattern 326d is less than the length of the sixth gate pattern 326b. Therefore, in some embodiments, the functional gate structure indicated by the modified fifth gate pattern 326c overlaps with the first metallized region indicated by the first metallized trajectory pattern 232 and with the third metallized region indicated by the third metallized trajectory pattern 236. In some embodiments, the relationship between the length (e.g., length L4) of the non-functional gate structure within the cell region of the eighth circuit cell example, the width of the second active region, and the cell height (e.g., H4) of the cell region along the second direction is shown in FIG3B.

[0042] In some embodiments, the functional gate structure sufficiently overlaps with the metallized region indicated by the metallization trajectory pattern 231 to define the via pattern 246. In some embodiments, the functional gate structure further overlaps with the metallized region indicated by the metallization trajectory pattern 235 to define an overlapping portion having a space defined therein, the size of which is adapted for connection features (e.g., the space indicated by the via pattern 248) between the functional gate structure and the corresponding metallized region. In some embodiments, as shown in FIG3D, the formation of the via structure based on the via pattern 248 is less susceptible to process variations than in the example of FIG3C because the boundary of the modified fifth gate pattern 326c is moved away from the first active region indicated by the first active region pattern 212 by shifting the position of the CPO pattern 334.

[0043] Therefore, as shown in FIG3D, if a functional gate structure indicated by the modified fifth gate pattern 326c is to be electrically connected to a conductive trace of a metallization layer (e.g., an MO layer), in some embodiments there are two options, including: connecting the functional gate structure to a conductive trace formed based on a first metallization region indicated by a first metallization trace pattern 231 via a connection feature (e.g., a via structure) indicated by a via pattern 246; and connecting the functional gate structure to a conductive trace formed based on a third metallization region indicated by a third metallization trace pattern 235 via a connection feature (e.g., a via structure) indicated by a via pattern 248. In some embodiments, the eighth circuit cell example in FIG3D with a shifted CPO pattern (e.g., CPO pattern 332 relative to CPO pattern 334) has similar options and benefits to those discussed with reference to FIG2B, compared to the seventh circuit cell example in FIG3C.

[0044] The examples in Figures 2A-2D and 3A-3D are non-limiting examples. In some embodiments, the CPODE process illustrated in Figures 2A-2D and the CPO process illustrated in Figures 3A-3D can be combined to define one or more layout patterns for one or more gate structures, whether the gate structure is functional or non-functional. For example, in some embodiments, a sixth gate pattern 326b and / or a modified sixth gate pattern 326d can be used as a CPODE pattern.

[0045] In some embodiments, the examples in Figures 2B, 2D, 3B and 3D are applicable to various types of circuit cells with different cell heights to achieve the improvements and benefits discussed above.

[0046] In some embodiments, according to the examples in Figures 2B, 2D, 3B and 3D, the semiconductor structure includes a first active region (e.g., indicated by a first active region pattern 212) and a second active region (e.g., indicated by a second active region pattern 214) extending along a first direction, an isolation region located between and adjacent to the first and second active regions (e.g., indicated by a blank region 216), a functional gate structure extending along a second direction and overlapping the first active region (e.g., indicated by a modified third gate pattern 226c or a modified fifth gate pattern 326c), a non-functional gate structure aligned with the functional gate structure and overlapping the second active region along the second direction (e.g., indicated by a modified fourth gate pattern 226d or a modified sixth gate pattern 326c), and a metallization layer located above the functional and non-functional gate structures. In some embodiments, the metallization layer defines a first metallization region extending over a first active region along a first direction (e.g., indicated by metallization trajectory pattern 232 or metallization trajectory pattern 231), a second metallization region extending over a second active region along the first direction (e.g., indicated by metallization trajectory pattern 234 or metallization trajectory pattern 233), and one or two intermediate metallization regions extending along the first direction and located between the first and second metallization regions (e.g., indicated by metallization trajectory pattern 236, or metallization trajectory patterns 235 and 237). In some embodiments, a functional gate structure overlaps with the first metallization region and with one of the one or two intermediate metallization regions to define an overlapping portion of one or two intermediate metallization regions. In some embodiments, the overlapping portion of one or two intermediate metallization regions has a space defined therein, the size of which is adapted to accommodate a connection feature between the functional gate structure and one of the one or two intermediate metallization regions (e.g., indicated by via pattern 244 or via pattern 248).

[0047] In some embodiments, the distance between the overlapping portion and the first active region is less than the distance between the overlapping portion and the second active region. In some embodiments, the non-functional gate structure is a first dielectric gate structure adjacent to the functional gate structure (e.g., based on the CPODE process), or the non-functional gate structure is a second dielectric gate structure or a conductive gate structure spaced apart from the functional gate structure (e.g., based on the CPO process).

[0048] In some embodiments, one or two intermediate metallized regions include a third metallized region located between the first metallized region and the second metallized region. In some embodiments, the width of the third metallized region is 1.2 to 2 times the width of the first metallized region; or the width of the third metallized region is 1.2 to 2 times the width of the second metallized region. In some embodiments, one or two intermediate metallized regions further include a fourth metallized region located between the third metallized region and the second metallized region.

[0049] In some embodiments, the semiconductor structure with reference to the examples in Figures 2B, 2D, 3B, and 3D includes a first active region (e.g., indicated by a first active region pattern 212) and a second active region (e.g., indicated by a second active region pattern 214) extending along a first direction, an isolation region located between and adjacent to the first and second active regions (e.g., indicated by a blank region 216), a functional gate structure extending along a second direction and overlapping the first active region (e.g., indicated by a modified third gate pattern 226c or a modified fifth gate pattern 326c), and a non-functional gate structure aligned with the functional gate structure and overlapping the second active region along the second direction (e.g., indicated by a modified fourth gate pattern 226d or a modified sixth gate pattern 326c). In some embodiments, the semiconductor structure includes a first conductive trace of a metallization layer extending along the first direction, overlapping the functional gate structure, and overlapping the isolation region (e.g., formed based on a metallization region indicated by metallization trace pattern 236 or metallization trace pattern 235). In some embodiments, the semiconductor structure further includes a connection feature (e.g., a via structure formed based on via pattern 244 or via pattern 248) connecting the functional gate structure and the first conductive trace.

[0050] In some embodiments, the semiconductor structure includes one or more channel structures located within a first active region, wherein the one or more channel structures are located below or surrounded by a functional gate structure. In some embodiments, the semiconductor structure includes a first drain / source structure located within the first active region and on a first side of the functional gate structure, and a second drain / source structure located within the first active region and on a second side of the functional gate structure. In some embodiments, the combination of the functional gate structure, one or more channel structures, the first drain / source structure, and the second drain / source structure corresponds to a planar field-effect transistor (FET), a fin field-effect transistor (FinFET), a nanosheet FET, a nanowire FET, or a complementary field-effect transistor (CFET).

[0051] Figures 4A-8D include various examples of semiconductor structures based on continuous on-polysilicon (CPODE) patterns with shortened diffusion edges, shifted diced polysilicon (CPO) patterns, or combinations thereof, similar to Figures 2B, 2D, 3B and 3D.

[0052] Figure 4A is a circuit diagram 400A of two transmission gates operating according to complementary control signals, conforming to some embodiments. Circuit diagram 400A includes two p-type transistors 402 and 404 and two n-type transistors 406 and 408. The first source / drain terminals of p-type transistor 402 and n-type transistor 406 are electrically coupled to signal path 411. The first source / drain terminals of p-type transistor 404 and n-type transistor 408 are electrically coupled to signal path 413. The second source / drain terminals of p-type transistor 402, p-type transistor 404, n-type transistor 406, and n-type transistor 408 are electrically coupled to signal path 415. The gate terminals of n-type transistor 406 and p-type transistor 404 are electrically coupled to control path 417. The gate terminals of n-type transistor 408 and p-type transistor 402 are electrically coupled to control path 419. In some embodiments, the combination of p-type transistor 402 and n-type transistor 406 forms a transmission gate; while the combination of p-type transistor 404 and n-type transistor 408 forms another transmission gate. In some embodiments, control paths 417 and 419 are configured to transmit two complementary control signals.

[0053] FIG4B is a layout diagram 400B corresponding to various layout patterns of circuit cell portions including two transmission gates (e.g., an example of circuit diagram 400A in FIG4A) operating based on complementary control signals, conforming to some embodiments. In some embodiments, the circuit cell in FIG4B is part of a semiconductor device, such as semiconductor device 100 in FIG1.

[0054] Layout 400B includes a first active region pattern 422 indicating a first active region of a semiconductor device extending along a first direction (e.g., the X direction); and a second active region pattern 424 indicating a second active region of a semiconductor device extending along a first direction (e.g., the X direction). Layout 400B further includes a first gate pattern 431, a second gate pattern 433, a third gate pattern 435, a first functional gate pattern 427a, a first non-functional gate pattern 427b, a second functional gate pattern 429a, and a second non-functional gate pattern 429b. The first functional gate pattern 427a and the first non-functional gate pattern 427b are aligned with each other and located between the first gate pattern 431 and the third gate pattern 435. The second functional gate pattern 429a and the second non-functional gate pattern 429b are aligned with each other and located between the second gate pattern 433 and the third gate pattern 435.

[0055] In some embodiments, the first gate pattern 431 and the second gate pattern 433 indicate two non-functional gate structures extending along a second direction (e.g., the Y direction). In some embodiments, the first gate pattern 431 and the second gate pattern 433 represent two cell boundaries and do not correspond to any physical gate structure. The first functional gate pattern 427a indicates a first functional gate structure extending along the second direction (e.g., the Y direction) and overlapping with the first active region. The second functional gate pattern 429a indicates a second functional gate structure extending along the second direction (e.g., the Y direction) and overlapping with the second active region. The first non-functional gate pattern 427b indicates a first non-functional gate structure extending along the second direction (e.g., the Y direction) and overlapping with the second active region. The second non-functional gate pattern 429b indicates a second non-functional gate structure extending along the second direction (e.g., the Y direction) and overlapping with the first active region. In some embodiments, the third gate pattern 435 indicates a third functional gate structure extending along a second direction (e.g., the Y direction) and overlapping with the first and second active regions. As shown in FIG4B as a non-limiting example, the non-functional gate structure indicated by the non-functional gate pattern 427b and the non-functional gate pattern 429b is formed based on a continuous on-polysilicon process at the diffusion edge, wherein, in some embodiments, the non-functional gate pattern 427b and the non-functional gate pattern 429b are also referred to as CPODE patterns.

[0056] In some embodiments, the first functional gate structure and the first active region define the first p-type transistor of p-type transistor 402 in FIG4A; and the third functional gate structure and the first active region define the second p-type transistor of p-type transistor 404 in FIG4A. In some embodiments, the third functional gate structure and the second active region define the first n-type transistor of n-type transistor 406 in FIG4A; and the second functional gate structure and the second active region define the second n-type transistor of n-type transistor 408 in FIG4A.

[0057] In some embodiments, the circuit cell in FIG4B includes a metallization layer (e.g., an MO layer) located above the functional gate structure and the non-functional gate structure. As a non-limiting example, layout 400B includes a circuit cell having three metallization regions in the MO layer. Layout 400B includes a first metallization trajectory pattern 442, a second metallization trajectory pattern 444, and a third metallization trajectory pattern 446, corresponding to the three metallization regions defined in the metallization layer. For example, the first metallization trajectory pattern 442 indicates a first metallization region extending along a first direction (e.g., the X direction) and located above a first active region; the second metallization trajectory pattern 444 indicates a second metallization region extending along a first direction (e.g., the X direction) and located above a second active region; and the third metallization trajectory pattern 446 indicates a third metallization region extending along a first direction (e.g., the X direction) and located between the first and second metallization regions.

[0058] In some embodiments, the gate terminals of p-type transistor 404 and n-type transistor 406 in FIG. 4A correspond to the third functional gate structure indicated by the third gate pattern 435 in FIG. 4B and are electrically coupled based on the shared third functional gate structure. In some embodiments, the gate terminal of p-type transistor 402 corresponds to the first functional gate structure indicated by the first functional gate pattern 427a in FIG. 4B and is electrically coupled to a conductive trajectory formed based on a metallization region indicated by the third metallization trajectory pattern 446 via a connection feature (e.g., a via structure) indicated by the via pattern 452. In some embodiments, the gate terminal of n-type transistor 408 corresponds to the second functional gate structure indicated by the second functional gate pattern 429a in FIG. 4B and is also electrically coupled to the conductive trajectory via a connection feature (e.g., a via structure) indicated by the via pattern 454, thereby electrically coupling to the gate terminal of p-type transistor 402.

[0059] FIG4B is an example of implementing the example in FIG4A based on the example in FIG2B. In some embodiments, the relationship between the length of the non-functional gate structure, the width of the active region, and the circuit cell height along the second direction in FIG4B is similar to that in FIG2B. In some embodiments, the relationship between the width of the third metallization region of the MO layer along the second direction in FIG4B is similar to that in FIG2B.

[0060] In some embodiments, by limiting the lengths of the first nonfunctional gate pattern 427b and the second nonfunctional gate pattern 429b in the manner discussed in FIG2B, and by having the third metallization trace pattern 446 wider than the first metallization trace pattern 442 or the second metallization trace pattern 444, the gate terminals of the p-type transistor 402 and the n-type transistor 408 can achieve electrical coupling without using any wiring resources corresponding to the first metallization trace pattern 442, the second metallization trace pattern 446, and any other metallization layer above the M0 layer. Therefore, in some embodiments, implementing the circuit of FIG4A based on the example of a continuous on-polysilicon pattern with shortened diffusion edges in FIG4B (e.g., referring to the example of FIG2B) frees up more wiring resources and reduces the resistance of the conductive paths compared to another implementation of the circuit of FIG4A with a continuous on-polysilicon pattern without shortened diffusion edges (e.g., referring to the example of FIG2A).

[0061] FIG4C is a layout diagram 400C, showing various layout patterns corresponding to circuit cell portions including two transmission gates operating based on complementary control signals (e.g., the circuit example in circuit diagram 400A of FIG4A), conforming to some embodiments. The circuit cells in FIG4C are variations of the circuit cells in FIG4B. Therefore, elements depicted in FIG4C that are the same or similar to those in FIG4B are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0062] Compared to layout diagram 400B, layout diagram 400C includes a circuit cell with four metallized regions in the MO layer, including four metallization trajectory patterns 462, 464, 466, and 468, indicating four respective metallized regions extending along a first direction (e.g., the X direction). In some embodiments, the widths of the metallized regions indicated by the metallization trajectory patterns 462, 464, 466, and 468 are substantially the same (e.g., internal variations within 10% of the nominal width).

[0063] In some embodiments, the gate terminal of the p-type transistor 402 corresponds to a first functional gate structure indicated by a first functional gate pattern 427a and is electrically coupled to a first conductive trace formed based on a metallization region indicated by a metallization trace pattern 462 via a connection feature (e.g., a via structure) indicated by a via pattern 455. In some embodiments, the gate terminal of the n-type transistor 408 corresponds to a second functional gate structure indicated by a second functional gate pattern 429a and is electrically coupled to a second conductive trace formed based on a metallization region indicated by a metallization trace pattern 468 via a connection feature (e.g., a via structure) indicated by a via pattern 456. In some embodiments, as shown in FIG4C, the first conductive trace and the second conductive trace are electrically coupled together through a third conductive trace (indicated by metallization trace pattern 472) in a metallization layer above the M0 layer and along a second direction (e.g., the Y direction), a via structure (indicated by via pattern 482) connecting the first conductive trace (based on the metallization region indicated by metallization trace pattern 462) and the third conductive trace, and a via structure (indicated by via pattern 484) connecting the second conductive trace (based on the metallization region indicated by metallization trace pattern 468) and the third conductive trace.

[0064] FIG4D is a layout diagram 400D, showing various layout patterns corresponding to circuit cell portions including two transmission gates operating based on complementary control signals (e.g., the circuit example of circuit diagram 400A in FIG4A), conforming to some embodiments. The circuit cells in FIG4D are variations of the circuit cells in FIG4C. Therefore, elements depicted in FIG4D that are the same or similar to those in FIG4B and FIG4C are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0065] Similar to layout diagram 400C, layout diagram 400D also includes a circuit cell having four metallized regions in the MO layer, including four metallization trajectory patterns 462, 464, 466, and 468, indicating four metallization regions extending respectively along a first direction (e.g., the X direction). Compared to layout diagram 400C, in some embodiments, the gate terminal of p-type transistor 402 corresponds to a first functional gate structure indicated by a first functional gate pattern 427a, electrically coupled to a fourth conductive trajectory formed based on the metallization region indicated by metallization trajectory pattern 466 via a connection feature (e.g., a via structure) indicated by via pattern 457. In some embodiments, the gate terminal of n-type transistor 408 corresponds to a second functional gate structure indicated by a second functional gate pattern 429a, electrically coupled to a second conductive trajectory formed based on the metallization region indicated by metallization trajectory pattern 468 via a connection feature (e.g., a via structure) indicated by via pattern 456. In some embodiments, as shown in FIG4D, the fourth conductive trace and the second conductive trace are electrically coupled together through a fifth conductive trace (indicated by metallization trace pattern 474) in a metallization layer above the M0 layer and along a first direction (e.g., the Y direction), a via structure (indicated by via pattern 486) connecting the fifth conductive trace (based on the metallization region indicated by metallization trace pattern 466) and the fourth conductive trace, and a via structure (indicated by via pattern 484) connecting the second conductive trace (based on the metallization region indicated by metallization trace pattern 468) and the fifth conductive trace.

[0066] In some embodiments, Figures 4C and 4D are two examples that implement the example of Figure 4A based on the example in Figure 2D. In some embodiments, the length of the non-functional gate structure, the width of the active region, and the cell height of the circuit cell along the second direction in Figures 4C and 4D have a similar relationship to that in Figure 2D. In some embodiments, the width of the third metallization region of the MO layer along the second direction in Figures 4C and 4D has a similar relationship to that in Figure 2D.

[0067] In some embodiments, by limiting the lengths of the first non-functional gate pattern 429a and the second non-functional gate pattern 429b, and by providing four metallization regions in the MO layer of the circuit cell as discussed in FIG. 2D, a variety of wiring options for electrically connecting the gate terminals of the p-type transistor 402 and the n-type transistor 408 can be obtained. Therefore, in some embodiments, implementing the circuit of FIG. 4A based on the examples in FIG. 4C and 4D and having a continuous on-polysilicon pattern with shortened diffusion edges (e.g., referring to the example in FIG. 2D) provides more wiring options and thus improves wiring flexibility compared to another implementation of the circuit of FIG. 4A without a continuous on-polysilicon pattern with shortened diffusion edges (e.g., referring to the example in FIG. 2C).

[0068] FIG. 5A is a layout diagram 500A corresponding to various layout patterns of circuit cell portions including two transmission gates operating based on complementary control signals (e.g., the circuit example 400A in FIG. 4A), conforming to some embodiments. The circuit cells in FIG. 5A are variations of the circuit cells in FIG. 4B. Therefore, elements depicted in FIG. 5A that are the same or similar to those in FIG. 4B are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0069] Compared to layout diagram 400B in FIG4B, layout diagram 500A includes a third functional gate pattern 527a, a third non-functional gate pattern 527b, a fourth functional gate pattern 529a, and a fourth non-functional gate pattern 529b. The third functional gate pattern 527a represents a fourth functional gate structure extending along a second direction (e.g., the Y direction) and overlapping with the first active region. The fourth functional gate pattern 529a represents a fifth functional gate structure extending along a second direction (e.g., the Y direction) and overlapping with the second active region. The third non-functional gate pattern 527b represents a fourth non-functional gate structure extending along a second direction (e.g., the Y direction) and overlapping with the second active region. The fourth non-functional gate pattern 529b represents a fifth non-functional gate structure extending along a second direction (e.g., the Y direction) and overlapping with the first active region. As shown in the non-limiting example in Figure 5A, the fourth functional gate structure represented by the third functional gate pattern 527a and the fourth non-functional gate structure represented by the third non-functional gate pattern 527b are formed based on the CPO process of CPO pattern 542; the fifth functional gate structure represented by the fourth functional gate pattern 529a and the fifth non-functional gate structure represented by the fourth non-functional gate pattern 529b are formed based on the CPO process of CPO pattern 544.

[0070] In some embodiments, the fourth functional gate structure and the first active region boundary correspond to the first p-type transistor of p-type transistor 402 in FIG. 4A; the third functional gate structure and the first active region boundary correspond to the second p-type transistor of p-type transistor 404 in FIG. 4A. In some embodiments, the third functional gate structure and the second active region boundary correspond to the first n-type transistor of n-type transistor 406 in FIG. 4A; the fifth functional gate structure and the second active region boundary correspond to the second n-type transistor of n-type transistor 408 in FIG. 4A.

[0071] In some embodiments, the gate terminal of the p-type transistor 402 corresponds to the fourth functional gate structure represented by the third functional gate pattern 427a in FIG. 5A, and is electrically coupled to the conductive trajectory formed based on the metallization region represented by the via pattern 552 (e.g., via structure) through the connection feature represented by the via pattern 552. In some embodiments, the gate terminal of the n-type transistor 408 corresponds to the fifth functional gate structure represented by the fourth functional gate pattern 529a in FIG. 5A, and is also electrically coupled to the conductive trajectory through the connection feature represented by the via pattern 554 (e.g., via structure), and thus electrically coupled to the gate terminal of the p-type transistor 402.

[0072] In some embodiments, FIG5A is an example of implementing the example of FIG4A based on the example of FIG3B. In some embodiments, the length of the non-functional gate structure, the width of the active region, and the height of the circuit cell along the second direction in FIG5A have a similar relationship to that in FIG3B. In some embodiments, the width of the third metallization region of the MO layer along the second direction in FIG5A has a similar relationship to that in FIG3B.

[0073] In some embodiments, by shifting the CPO patterns 542 and 544 in the manner discussed in FIG3B to extend the length of the third functional gate pattern 527a and the fourth functional gate pattern 529a, and in addition, by making the third metallization trace pattern 446 wider than the first metallization trace pattern 442 or the second metallization trace pattern 444, the gate terminals of the p-type transistor 402 and the n-type transistor 408 can be electrically coupled without using any wiring resources corresponding to the first metallization trace pattern 442, the second metallization trace pattern 446, and any other metallization layer above the MO layer. Therefore, in some embodiments, implementing the circuit of FIG4A based on the example of FIG5A with the shifted CPO pattern (e.g., referring to the example of FIG3B) can free up more wiring resources and reduce the resistance of the conductive path compared to another circuit implementation of FIG4A with the CPO pattern located between the first active region pattern 422 and the second active region pattern 424 (e.g., referring to the example of FIG3A).

[0074] FIG5B is a layout diagram 500B, showing various layout patterns corresponding to circuit cell portions including two transmission gates operating based on complementary control signals (e.g., the circuit example of circuit diagram 400A in FIG4A), conforming to some embodiments. The circuit cells in FIG5B are variations of the circuit cells in FIG5A. Therefore, elements depicted in FIG5B that are the same or similar to those in FIG5A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0075] Compared to layout diagram 500A, layout diagram 500B includes a circuit cell with four metallized regions in the MO layer, including four metallization trajectory patterns 462, 464, 466, and 468, indicating four respective metallized regions extending along a first direction (e.g., the X direction). In some embodiments, the widths of the metallized regions indicated by the metallization trajectory patterns 462, 464, 466, and 468 are substantially the same (e.g., internal variations within 10% of the nominal width).

[0076] In some embodiments, the gate terminal of the p-type transistor 402 corresponds to a fourth functional gate structure indicated by a third functional gate pattern 527a, and is electrically coupled to a first conductive trace formed based on a metallization region indicated by a via pattern 555 (e.g., a via structure). In some embodiments, the gate terminal of the n-type transistor 408 corresponds to a fifth functional gate structure indicated by a fourth functional gate pattern 529a, and is electrically coupled to a second conductive trace formed in a metallization region indicated by a via pattern 556 (e.g., a via structure). In some embodiments, as shown in FIG5B, the first conductive trace and the second conductive trace are electrically coupled together through a third conductive trace (indicated by metallization trace pattern 472) located above the MO layer and along a second direction (e.g., the Y direction), a via structure (indicated by via pattern 482) connecting the first conductive trace (based on the metallization region indicated by metallization trace pattern 462) and the third conductive trace, and a via structure (indicated by via pattern 484) connecting the second conductive trace (based on the metallization region indicated by metallization trace pattern 468) and the third conductive trace.

[0077] FIG5C is a layout diagram 500C, showing various layout patterns corresponding to circuit cell portions including two transmission gates operating based on complementary control signals (e.g., the circuit example 400A in FIG4A), conforming to some embodiments. The circuit cells in FIG5C are variations of the circuit cells in FIG5B. Therefore, elements depicted in FIG5C that are the same or similar to those in FIG5A and FIG5B are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0078] Similar to layout diagram 500B, layout diagram 500C further includes a circuit cell having four metallized regions in the MO layer, including four metallization trajectory patterns 462, 464, 466, and 468, indicating four respective metallized regions extending along a first direction (e.g., the X direction). Compared to layout diagram 500B, in some embodiments, the gate terminal of the p-type transistor 402 corresponds to a fourth functional gate structure indicated by a third functional gate pattern 527a, electrically coupled to a fourth conductive trajectory formed based on the metallized region indicated by the metallization trajectory pattern 468 via a connection feature (e.g., a via structure) indicated by a via pattern 557. In some embodiments, the gate terminal of the n-type transistor 408 corresponds to a fifth functional gate structure indicated by a fourth functional gate pattern 529a, electrically coupled to a second conductive trajectory formed based on the metallized region indicated by the metallization trajectory pattern 468 via a connection feature (e.g., a via structure) indicated by a via pattern 556. In some embodiments, as shown in FIG5C, the fourth conductive trace and the second conductive trace are electrically coupled together through a fifth conductive trace (indicated by metallization trace pattern 474) located above the M0 layer and along the second direction, a via structure (indicated by via pattern 486) connecting the fifth conductive trace (based on the metallization region indicated by metallization trace pattern 466) and the fourth conductive trace, and a via structure (indicated by via pattern 484) connecting the second conductive trace (based on the metallization region indicated by metallization trace pattern 468) and the third conductive trace.

[0079] In some embodiments, Figures 5B and 5C are two examples of the example of Figure 4A implemented based on the example of Figure 3D. In some embodiments, the length of the non-functional gate structure, the width of the active region, and the height of the circuit cell along the second direction in Figures 5B and 5C have a similar relationship to that in Figure 3D. In some embodiments, the width of the third metallization region of the MO layer along the second direction in Figures 5B and 5C has a similar relationship to that in Figure 3D.

[0080] In some embodiments, by arranging CPO patterns 542 and 544 at shifted positions in the manner discussed in FIG3D, various wiring options for electrically connecting the gate terminals of p-type transistor 402 and n-type transistor 408 become available. Therefore, in some embodiments, implementing the circuit of FIG4A based on the examples of shifted CPO patterns in FIG5B and FIG5C (e.g., referring to the example in FIG3D) provides more wiring options and thus improves wiring flexibility compared to implementing the circuit of FIG4A with another CPO pattern without shifting (e.g., referring to the example in FIG3A).

[0081] The examples in Figures 4A-4D and 5A-5C are non-limiting examples. In some embodiments, there is no limitation on whether the gate pattern defined based on the shortened CPODE pattern corresponds to a functional gate structure or a non-functional gate structure. In some embodiments, the gate pattern may be converted into two shortened CPODE patterns and correspond to a non-functional gate structure. Furthermore, in some embodiments, the CPODE process and the CPO process may be combined to define one or more layout patterns for one or more gate structures, regardless of whether the gate structure is functional or non-functional.

[0082] In some embodiments, referring to the examples of Figures 2B, 2D, 3B and 3D and Figures 4A-5C, the semiconductor structure includes a first active region (e.g., indicated by a first active region pattern 422) and a second active region (e.g., indicated by a second active region pattern 424) extending along a first direction, an isolation region located between and adjacent to the first and second active regions, a first functional gate structure (e.g., indicated by a first functional gate pattern 427a or a third functional gate pattern 527a) extending along a second direction and overlapping the first active region, and an isolation region extending along the second direction and overlapping the first active region. The semiconductor structure comprises a first non-functional gate structure aligned with and overlapping the second active region (e.g., indicated by a first non-functional gate pattern 427b or a third non-functional gate pattern 527b), a second functional gate structure extending along a second direction and overlapping the second active region (e.g., indicated by a second functional gate pattern 429a or a fourth functional gate pattern 529a), and a second non-functional gate structure aligned along the second direction with the second functional gate structure and overlapping the first active region (e.g., indicated by a second non-functional gate pattern 429b or a fourth non-functional gate pattern 529b). In some embodiments, the semiconductor structure further includes a first conductive trace (e.g., indicated by a metallization trace pattern 446, a metallization trace pattern 462, or a metallization trace pattern 466), a second conductive trace (e.g., indicated by a metallization trace pattern 468), or both, of a metallization layer extending along a first direction and overlapping the isolation region. In some embodiments, the semiconductor structure further includes a first connection feature (e.g., indicated by contact pattern 452, contact pattern 455, contact pattern 552 or contact pattern 555) connecting the first functional gate structure and the first conductive trace, or a second connection feature (e.g., indicated by contact pattern 454, contact pattern 456, contact pattern 554 or contact pattern 556) connecting the second functional gate structure and the first conductive trace.

[0083] In some embodiments, the distance between the first connection feature and the first active region is less than the distance between the first connection feature and the second active region. In some embodiments, the distance between the second connection feature and the second active region is less than the distance between the second connection feature and the first active region.

[0084] In some embodiments, the semiconductor structure further includes a third conductive trace (e.g., indicated by metallization trace pattern 442 or metallization trace pattern 462). In some embodiments, the third conductive trace overlaps with the first active region and is further away from the second active region than the first conductive trace (e.g., indicated by metallization trace pattern 446 or metallization trace pattern 466). In some embodiments, a second connection feature connects the second functional gate structure and the first conductive trace, and the width of the first conductive trace is 1.2 to 2 times the width of the third conductive trace.

[0085] In some embodiments, the second connection feature connects the second functional gate structure and the second conductive trace. In some embodiments, the semiconductor structure further includes a third conductive trace (e.g., indicated by metallization trace pattern 472 or metallization trace pattern 474) of another metallization layer extending along a second direction, a third connection feature (e.g., indicated by via pattern 482 or via pattern 486) connecting the first conductive trace and the third conductive trace, and a fourth connection feature (e.g., indicated by via pattern 484) connecting the second conductive trace and the third conductive trace.

[0086] In some embodiments, the first non-functional gate structure is a first dielectric gate structure adjacent to the first functional gate structure (e.g., based on the CPODE process), or the first non-functional gate structure is a second dielectric gate structure or a first conductive gate structure spaced apart from the first functional gate structure (e.g., based on the CPO process). In some embodiments, the second non-functional gate structure is a third dielectric gate structure adjacent to the second functional gate structure (e.g., based on the CPODE process), or the second non-functional gate structure is a fourth dielectric gate structure or a second conductive gate structure spaced apart from the second functional gate structure (e.g., based on the CPO process).

[0087] In some embodiments, the semiconductor structure includes one or more channel structures within a first active region, wherein the one or more channel structures are below or surrounded by a first functional gate structure. In some embodiments, the semiconductor structure includes a first drain / source structure within the first active region and on a first side of the first functional gate structure, and a second drain / source structure within the first active region and on a second side of the first functional gate structure. In some embodiments, the combination of the first functional gate structure, one or more channel structures, the first drain / source structure, and the second drain / source structure corresponds to a planar field-effect transistor, a fin field-effect transistor (FinFET), a nanosheet field-effect transistor, a nanowire field-effect transistor, or a complementary field-effect transistor (CFET).

[0088] FIG6A is a circuit diagram 600A of an example flip-flop circuit according to some embodiments. In some embodiments, circuit diagram 600A includes elements of a flip-flop circuit example as a simplified, non-limiting example. In FIG6A, the flip-flop circuit includes a 2:1 multiplexer (MUX) circuit 602, a transmission gate 604, two clock inverters 606 and 608, and three inverters 612, 614, and 616.

[0089] In FIG. 6A, the output terminal of multiplexer 602, the output terminal of clock inverter 606, and the input terminal of inverter 612 are electrically coupled together. The output terminal of inverter 612 and the input terminal of clock inverter 606 are electrically coupled to the first terminal of transmission gate 604. The output terminal of clock inverter 608 and the input terminal of inverter 614 are electrically coupled to the second terminal of transmission gate 604. The output terminal of inverter 614 and the input terminal of clock inverter 608 are electrically coupled to the input terminal of inverter 616. In some embodiments, multiplexer 602 includes a first input terminal configured to receive a first input signal (labeled "D"), a second input terminal configured to receive a second input signal (labeled "SI"), and a selection terminal configured to receive a selection signal (labeled "SE"). The output terminal of inverter 616 is configured to output the output signal (labeled "Q") of the flip-flop circuit.

[0090] In some embodiments, the operation of various elements of the flip-flop circuit is based on two complementary clock signals (labeled "CLK" and " / CLK"). For example, clock inverter 606 is configured to operate as an inverter when clock signal CLK is at a high voltage level (also referred to as "HIGH") and clock signal / CLK is at a low voltage level (also referred to as "LOW"); and to operate as an open circuit when clock signal CLK is LOW and clock signal / CLK is HIGH. Conversely, clock inverter 608 is configured to operate as an inverter when clock signal CLK is LOW and clock signal / CLK is HIGH; and to operate as an open circuit when clock signal CLK is HIGH and clock signal / CLK is LOW. Furthermore, transmission gate 604 is configured to operate as a short circuit when clock signal CLK is HIGH and clock signal / CLK is LOW; and to operate as an open circuit when clock signal CLK is LOW and clock signal / CLK is HIGH. In some embodiments, the control signal paths of clock signals CLK and / or CLK and the corresponding transistors controlled by them may include cross-coupled gate terminals of different types of transistors.

[0091] FIG6B is a layout diagram 600B of various layout patterns corresponding to the circuit cell portion of the flip-flop circuit example of FIG6A, conforming to some embodiments. In FIG6B, layout diagram 600A includes layout patterns for forming an active region (labeled "OD"), forming a conductive structure connected to the source / drain structure (labeled "MD"), defining a CPO pattern for the CPO process (labeled "CPO"), defining a CPODE pattern for the CPODE process (labeled "CPODE"), and defining the location of the gate structure (labeled "Poly"). FIG6B identifies a portion 620 of layout diagram 600B, which will be further described in FIG6C. In some embodiments, portion 620 corresponds to the element formation of the transmission gate 604, the clock inverter 608, and inverters 614 and 616.

[0092] FIG6C is a layout diagram 600C of various layout patterns corresponding to the example portion of the flip-flop circuit in FIG6A, the portion corresponding to portion 620 identified in FIG6B, conforming to some embodiments. As shown in FIG6C, layout diagram 600C includes layout patterns for forming an active region (labeled "OD"), forming a conductive structure connected to the source / drain structure (labeled "MD"), defining a CPO pattern for the CPO process (labeled "CPO"), defining a CPODE pattern for the CPODE process (labeled "CPODE"), and defining the location of the gate structure (labeled "Poly"). In FIG6B, layout diagram 600B further includes layout patterns for forming via structures (labeled "VG" and "VIA0") and forming conductive traces (labeled "M0" and "M1").

[0093] In Figures 6A and 6C, the circuit cell includes elements corresponding to clock inverter 608 and transmission gate 604, wherein various transistors operate based on complementary control signals. In some embodiments, layout pattern 632a represents the gate terminal of the p-type transistor forming clock inverter 608; layout pattern 636 represents the gate terminal of the p-type transistor forming transmission gate 604 and the n-type transistor forming clock inverter 608; layout pattern 634a represents the gate terminal of the n-type transistor forming transmission gate 604. In some embodiments, the dimensions of layout patterns 632a and 634a are determined based on CPODE pattern 632b, CPO pattern 642, CPODE pattern 634b and / or CPO pattern 644, in a manner similar to the examples in Figures 2B, 3B, 4A-4D and 5A-5C. Therefore, in some embodiments, the flip-flop circuit example of FIG6A is implemented based on the layout diagrams of FIG6B and 6C with shortened CPODE patterns and / or shifted CPO patterns, which increases more routing options and thus improves routing flexibility compared to another implementation without shortened CPODE patterns and without shifted CPO patterns.

[0094] Figure 7A is a circuit diagram 700A of an example 4:1 multiplexer circuit, conforming to some embodiments. Circuit diagram 700A includes elements of the example multiplexer circuit as a simplified, non-limiting example. In Figure 7A, the multiplexer circuit includes four clock inverters 702, 704, 706, and 708, two transmission gates 712 and 714, and one inverter 722.

[0095] In Figure 7A, the output terminals of clock inverters 702 and 704 are electrically coupled to the first terminal of the transmission gate 712; the output terminals of clock inverters 706 and 708 are electrically coupled to the first terminal of the transmission gate 714. Furthermore, the second terminals of the transmission gate 712 and the second terminals of the transmission gate 714 are electrically coupled to the input terminals of inverter 722. The input terminals of clock inverters 702, 704, 706, and 708 are configured to receive four corresponding input signals (labeled "I0", "I1", "I2", and "I3"). The output terminal of inverter 722 is configured to output the output signal of the multiplexer circuit (labeled "Z").

[0096] In some embodiments, the operation of each element of the multiplexer circuit is based on two sets of complementary selection signals (labeled "S0", " / S0", "S1", and " / S1"). For example, clock inverters 702 and 706 are configured to operate as inverters when selection signal S0 is low and selection signal / S0 is high; clock inverters 704 and 708 are configured to operate as inverters when selection signal S0 is high and selection signal / S0 is low. Transmission gate 712 is configured to operate as a short circuit when selection signal S1 is low and selection signal / S1 is high; and as an open circuit when selection signal S1 is high and selection signal / S1 is low. Furthermore, the transmission gate 714 is configured to operate as a short circuit when the selection signal S1 is high and the selection signal / S1 is low; and to operate as an open circuit when the selection signal S1 is low and the selection signal / S1 is high. In some embodiments, the control signal paths for the selection signals S0 and / S0, or the control signal paths for the selection signals S1 and / S1, and the corresponding transistors controlled thereby include cross-coupled gate terminals of different types of transistors.

[0097] FIG7B is a layout diagram 700B of various layout patterns of the circuit cell portion corresponding to the 4:1 multiplexer circuit example of FIG7A, conforming to some embodiments. In FIG7B, layout diagram 700B includes layout patterns for forming active regions (labeled "OD"), forming conductive structures connected to source / drain structures (labeled "MD"), defining CPO patterns for CPO processes (labeled "CPO"), defining CPODE patterns for CPODE processes (labeled "CPODE"), and defining the location of gate structures (labeled "Poly").

[0098] In FIG. 7B, the circuit cell includes elements corresponding to two transmission gates (e.g., transmission gates 712 and 714) operating based on complementary control signals. In some embodiments, layout pattern 732a indicates the gate terminal of the p-type transistor forming transmission gate 712, layout pattern 734a indicates the gate terminal of the n-type transistor forming transmission gate 714, and layout pattern 736 indicates the gate terminal of the p-type transistor forming transmission gate 714 and the gate terminal of the n-type transistor forming transmission gate 712. In some embodiments, the dimensions of layout patterns 732a and 734a are determined based on CPODE pattern 732b, CPO pattern 742, CPODE pattern 734b and / or CPO pattern 744, which are based on the examples in FIG. 2B, 3B, 4A-4D and 5A-5C. Therefore, in some embodiments, the 4:1 multiplexer circuit of FIG7A implemented based on FIG7B has a shortened CPODE pattern and / or a shifted CPO pattern, which increases more routing options and thus improves routing flexibility compared to another implementation without a shortened CPODE pattern and without a shifted CPO pattern.

[0099] Figure 8A is a layout diagram 800A of various layout patterns corresponding to the example portion of the first circuit cell of a skew logic circuit, conforming to some embodiments. In some embodiments, the skew logic circuit corresponds to a logic circuit (e.g., a logic gate or combination of logic gates) that has a greater driving force at a certain stage to pull a signal to one supply voltage rather than another (e.g., to pull high to VDD, or to pull low to VSS or ground potential). Therefore, the skew logic circuit may include more transistors of a certain type (e.g., p-type transistors for pulling high or n-type transistors for pulling low) and leave some unused gate structures and corresponding source / drain structures (which may be configured as dummy transistors) in the circuit cell.

[0100] As a non-limiting example, layout diagram 800A includes active region patterns 822 and 824 indicating active regions extending along a first direction (e.g., the X direction); gate patterns 831, 833, 835, 837, and 839 indicating gate structures or one or more cell boundaries; and metallization trajectory patterns 841, 842, 845, 846, and 847 indicating metallization regions of a metallization layer (e.g., an MO layer). In some embodiments, metallization trajectory pattern 841 corresponds to a metallization region for forming a first power rail configured to carry a first supply voltage (e.g., VDD). In some embodiments, metallization trajectory pattern 842 corresponds to a metallization region for forming a second power rail configured to carry a second supply voltage (e.g., VSS or ground potential).

[0101] In Figure 8A, two contact patterns 852 and 854 overlap with the active regions indicated by the active region pattern 822 on both sides of the gate pattern 839, indicating the formation of corresponding source / drain terminals. Furthermore, two contact patterns 856 and 858 overlap with the active regions indicated by the active region pattern 824 on both sides of the gate pattern 839, indicating the formation of two additional corresponding source / drain terminals. In this example, since the metallized region indicated by the metallized track pattern 847 may be reserved for connection to the source / drain terminal indicated by the contact pattern 858, the metallized regions indicated by the metallized track patterns 845 and 846 can still be used for via structures to land and connect the gate structure to M0 (e.g., via pattern 872 indicating the via structure overlapping with the metallized track pattern 845).

[0102] In some embodiments, the gate structure indicated by gate pattern 839 and the source / drain terminals under contact patterns 852 and 854 form a dummy transistor (as shown in reference numeral 862), wherein the source / drain terminals are electrically connected to a first power rail (e.g., indicated by metallization track pattern 841) through two through-hole structures indicated by two through-hole patterns (unmarked). In some embodiments, although the dummy transistor 862 is not logically functional, it still introduces parasitic capacitance between the gate structure and the source / drain terminals (indicated by contact patterns 852 and 854).

[0103] FIG8B is a layout diagram 800B of various layout patterns corresponding to a portion of a second circuit cell example of a skewed logic circuit, conforming to some embodiments. The second circuit cell example is a variation of the first circuit cell example. Elements in FIG8B that are the same as or similar to those in FIG8A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0104] In FIG8B, by converting the gate structure indicated by gate pattern 839 to a functional gate structure indicated by functional gate pattern 839a and a dielectric gate structure indicated by non-functional gate pattern 839b based on the CPODE process, the dummy transistor 862 in FIG8A is replaced by a non-functional device 864 having a dielectric gate structure (indicated by non-functional gate pattern 839b), which is electrically isolated from the functional gate structure (indicated by functional gate pattern 839a). In some embodiments, the non-functional device 864 further reduces the parasitic capacitance caused by the dummy transistor 862 compared to the dummy transistor 862. As described similarly with reference to FIG2B, even if it is no longer possible to connect to the metallization region indicated by the metallization trajectory pattern 845 due to the formation of the non-functional device 864, the functional gate structure (indicated by the functional gate pattern 839a) can still be connected to the metallization region of the M0 layer through the through-hole structure indicated by the through-hole pattern 874, wherein the through-hole pattern 874 has a shortened CPODE pattern (e.g., the non-functional gate pattern 839b).

[0105] FIG8C is a layout diagram 800C of various layout patterns corresponding to a portion of the third circuit cell example of the skew logic circuit, conforming to some embodiments. The third circuit cell example is a variation of the first circuit cell example. Therefore, elements depicted in FIG8C that are the same as or similar to those in FIG8A are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0106] Compared to layout diagram 800A, layout diagram 800C includes a third circuit cell example having six metallized regions in the MO layer of the third circuit cell example, indicated by six metallized trace patterns 881, 882, 884, 885, 886, and 887. In some embodiments, metallized trace pattern 881 corresponds to a metallized region for forming a first power rail configured to carry a first supply voltage (e.g., VDD). In some embodiments, metallized trace pattern 882 corresponds to a metallized region for forming a second power rail configured to carry a second supply voltage (e.g., VSS or ground potential). In this example, since the metallized region indicated by metallized trace pattern 887 may reserve space for connection to the source / drain terminals indicated by contact pattern 858, the metallized regions indicated by metallized trace patterns 884, 885, and 886 are still available for via structures to fall upon to connect gate structures to MO (e.g., via pattern 876 indicates a via structure overlapping with metallized trace pattern 884). As shown in Figure 8C and similarly illustrated with reference to Figure 8A, the virtual transistor 862 still introduces parasitic capacitance between the gate structure and the source / drain terminals (indicated by contact patterns 852 and 854).

[0107] FIG8D is a layout diagram 800D of various layout patterns corresponding to a portion of the fourth circuit cell example of the skew logic circuit, conforming to some embodiments. The fourth circuit cell example is a variation of the third circuit cell example. Elements in FIG8D that are the same as or similar to those in FIG8C are given the same reference numerals, and their detailed descriptions are simplified or omitted.

[0108] In FIG8D, by converting the gate structure indicated by gate pattern 839 to a functional gate structure indicated by functional gate pattern 839a and a dielectric gate structure indicated by non-functional gate pattern 839b based on the CPODE process, the dummy transistor 862 in FIG8C is replaced by a non-functional device 864 having a dielectric gate structure (indicated by non-functional gate pattern 839b), which is electrically isolated from the functional gate structure (indicated by functional gate pattern 839a). In some embodiments, the non-functional device 864 further reduces parasitic capacitance compared to the dummy transistor 862. As illustrated similarly with reference to FIG2D, even if the metallization region indicated by metallization trajectory patterns 884 and 885 can no longer be connected due to the formation of non-functional device 864, the functional gate structure (indicated by functional gate pattern 839a) can still be connected to the metallization region of the M0 layer through the through-hole structure indicated by through-hole pattern 878, wherein through-hole pattern 878 has a shortened CPODE pattern (e.g., non-functional gate pattern 839b).

[0109] The examples in Figures 6A-8D are non-limiting examples. In some embodiments, the CPODE process and the CPO process may be combined to define one or more layout patterns of the corresponding gate structure, whether the gate structure is functional or non-functional.

[0110] FIG9 is a flowchart of a method 900 for manufacturing a semiconductor structure according to some embodiments. In some embodiments, the semiconductor structure manufactured based on method 900 may include circuit cells as shown in the layout diagrams of FIG2B, 2D, 3B, 3D, 4A-7B, 8B, and 8D. In some embodiments, method 900 corresponds to one or more operations performed, in whole or in part, based on the semiconductor device manufacturing system shown in FIG11 combined with the electronic design automation (EDA) system shown in FIG10. As shown in FIG9, method 900 includes blocks 910-950.

[0111] In block 910, a first active region and a second active region extending along a first direction are formed. In some embodiments, as a non-limiting example, the first active region and the second active region correspond to any active region indicated by active region patterns 212 and 214 in FIG2A-3D, and the active region indicated by active region patterns 422 and 424 in FIG4B-5C.

[0112] In block 920, an isolation region (e.g., indicated by blank area 216) is formed between and adjacent to the first active region and the second active region. In some embodiments, the isolation region is formed by shielding a portion of the semiconductor substrate as an isolation region during the formation of the first active region and the second active region. In some embodiments, the isolation region is formed between the first active region and the second active region after the first active region and the second active region have been formed.

[0113] In block 930, a functional gate structure extending along the second direction and overlapping with the first active region is formed. In some embodiments, as a non-limiting example, the functional gate structure corresponds to any functional gate structure indicated by functional gate pattern 226c in Figures 2B and 2D, the functional gate structure indicated by functional gate pattern 326c in Figures 3B and 3D, the functional gate structure indicated by functional gate patterns 427a and 429a in Figures 4B-4D, and the functional gate structure indicated by functional gate patterns 527a and 529a in Figures 5B-5C.

[0114] In block 940, a non-functional gate structure is formed that is aligned with the functional gate structure along the second direction and overlaps with the second active region. In some embodiments, as a non-limiting example, the non-functional gate structure corresponds to any non-functional gate structure indicated by non-functional gate pattern 226d in Figures 2B and 2D, the non-functional gate structure indicated by non-functional gate pattern 326d in Figures 3B and 3D, the non-functional gate structure indicated by non-functional gate patterns 427b and 429b in Figures 4B-4D, and the non-functional gate structure indicated by non-functional gate patterns 527b and 529b in Figures 5B-5C.

[0115] In block 950, a metallization layer is formed over the functional gate structure and the non-functional gate structure. In some embodiments, the metallization layer defines a first metallization region extending along a first direction and located above a first active region, a second metallization region extending along a first direction and located above a second active region, and one or two intermediate metallization regions extending along a first direction and located between the first and second metallization regions. In some embodiments, as a non-limiting example, various metallization regions correspond to any metallization region indicated by metallization trajectory patterns 232, 234, and 236 in Figures 2B and 3B, metallization regions indicated by metallization trajectory patterns 231, 233, 235, and 237 in Figures 2D and 3D, metallization regions indicated by metallization trajectory patterns 442, 444, and 446 in Figures 4B and 5A, and metallization regions indicated by metallization trajectory patterns 462, 464, 466, and 468 in Figures 4C, 4D, 5B, and 5C.

[0116] In some embodiments, the functional gate structure overlaps with a first metallization region and with one of one or two intermediate metallization regions to define an overlapping portion of one of the intermediate metallization regions. In some embodiments, the overlapping portion of one of the intermediate metallization regions has a space defined therein, the size of which is adapted to accommodate a connection feature between the functional gate structure and one of the intermediate metallization regions.

[0117] In some embodiments, the distance between the overlapping portion and the first active region is less than the distance between the overlapping portion and the second active region. In some embodiments, the non-functional gate structure is formed based on a continuous polysilicon-on-dimer (CPODE) process at the diffusion edge to form a first dielectric gate structure adjacent to the functional gate structure as a non-functional gate structure. In some embodiments, the non-functional gate structure is formed based on a diced polysilicon (CPO) process to form a second dielectric gate structure or a conductive gate structure spaced apart from the functional gate structure as a non-functional gate structure.

[0118] In some embodiments, the length of the non-functional gate structure along the second direction within the cell region of the semiconductor structure is equal to or greater than the width of the second active region along the second direction. In some embodiments, the length of the non-functional gate structure along the second direction is less than half of the cell height of the cell region along the second direction.

[0119] In some embodiments, one or two intermediate metallized regions include a third metallized region located between the first metallized region and the second metallized region. In some embodiments, the width of the third metallized region is 1.2 to 2 times the width of the first metallized region. In some embodiments, the width of the third metallized region is 1.2 to 2 times the width of the second metallized region. In some embodiments, one or two intermediate metallized regions further include a fourth metallized region located between the third metallized region and the second metallized region.

[0120] In some embodiments, method 900 further includes forming one or more channel structures within a first active region, the one or more channel structures being located below or surrounded by a functional gate structure; forming a first drain / source structure within the first active region, the first drain / source structure being located on a first side of the functional gate structure; and forming a second drain / source structure within the first active region, the second drain / source structure being located on a second side of the functional gate structure. In some embodiments, the combination of the functional gate structure, the one or more channel structures, the first drain / source structure, and the second drain / source structure corresponds to a planar field-effect transistor, a fin field-effect transistor (FinFET), a nanosheet field-effect transistor, a nanowire field-effect transistor, or a complementary field-effect transistor (CFET).

[0121] In some embodiments, block 950 includes a first conductive trace forming a metallization layer, extending along a first direction, overlapping with a functional gate structure, and overlapping with an isolation region. In some embodiments, method 900 further includes forming a connection feature connecting the functional gate structure and the first conductive trace. In some embodiments, block 950 includes a second conductive trace forming a metallization layer, extending along the first direction. In some embodiments, the second conductive trace overlaps with a first active region and is further away from the second active region than the first conductive trace. In some embodiments, the width of the first conductive trace is 1.2 to 2 times the width of the second conductive trace.

[0122] In some embodiments, method 900 can be modified for manufacturing a semiconductor structure. In some embodiments, the modified method for manufacturing a semiconductor structure includes forming a first active region and a second active region extending along a first direction, forming an isolation region located between and adjacent to the first active region and the second active region, forming a first functional gate structure extending along a second direction and overlapping the first active region, forming a first non-functional gate structure aligned with the first functional gate structure along the second direction and overlapping the second active region, forming a second functional gate structure extending along the second direction and overlapping the second active region, and forming the second functional gate structure extending along the second direction and overlapping the second active region. In some embodiments, the modified method further includes forming a first conductive trace, a second conductive trace, or both of a metallization layer extending along the first direction and overlapping the isolation region, and forming a first connection feature connecting the first functional gate structure and the first conductive trace. In some embodiments, the modified method further includes forming a second connection feature connecting the second functional gate structure and the first conductive trace, or connecting the second functional gate structure and the second conductive trace.

[0123] In some embodiments, according to the modified method, the distance between the first connection feature and the first active region is less than the distance between the first connection feature and the second active region, and the distance between the second connection feature and the second active region is less than the distance between the second connection feature and the first active region.

[0124] FIG10 is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments. In some embodiments, the EDA system 1000 includes an automatic placement and routing (APR) system. The design layout methods described herein represent wiring arrangements according to one or more embodiments, which may be implemented, for example, using the EDA system 1000 according to some embodiments.

[0125] In some embodiments, the EDA system 1000 is a general-purpose computing device, including a processor 1002 and a non-transitory computer-readable storage medium 1004. The storage medium 1004 (among others) is encoded with (i.e., stored) computer program code 1006, i.e., a set of executable instructions. The processor 1002 executes the instructions 1006 (at least partially) representing an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the processes and / or methods).

[0126] Processor 1002 is electrically coupled to non-transitory computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and non-transitory computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in non-transitory computer-readable storage medium 1004 so that EDA system 1000 can be used to perform some or all of the said processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0127] In one or more embodiments, the computer-readable storage medium 1004 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1004 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0128] In one or more embodiments, storage medium 1004 stores computer program code 1006, which enables EDA system 1000 (wherein the execution representation (at least partially) EDA tools) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1004 also stores information that facilitates the execution of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1004 stores a library 1007 of standard cells, including such standard cells or any circuit cells corresponding to the cells disclosed herein.

[0129] The EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to an external circuit. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 1002.

[0130] The EDA system 1000 further includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the EDA system 1000 to communicate with a network 1014, to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the process and / or method are implemented in two or more systems 1000.

[0131] The EDA system 1000 receives information via the I / O interface 1010. The information received via the I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 1002. The information is transmitted to the processor 1002 via the bus 1008. The EDA system 1000 also receives UI-related information via the I / O interface 1010. This information is stored as a user interface (UI) 1042 in the computer-readable medium 1004.

[0132] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a hardware processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 1000. In some embodiments, a layout diagram containing standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

[0133] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards; and the like.

[0134] FIG11 is a block diagram of a semiconductor device (e.g., integrated circuit (IC)) manufacturing system 1100 and associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1100 is used to manufacture at least one of the following: (i) one or more semiconductor photomasks or (ii) at least one component in the layers of a semiconductor device.

[0135] In Figure 11, manufacturing system 1100 includes entities that interact with each other during the design, development, and manufacturing cycles, such as design company 1120, photomask fab 1130, and IC wafer fab (IC manufacturer / manufacturer, also referred to as "fab") 1150, and / or services related to manufacturing IC devices 1160. Entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 1120, photomask fab 1130, and IC wafer fab 1150 are owned by a single larger company. In some embodiments, two or more of design company 1120, photomask fab 1130, and IC wafer fab 1150 coexist in a shared facility and use shared resources.

[0136] A design company (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for an IC device 1160. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1160 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout 1122 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metallized traces or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers will be disposed on the semiconductor substrate. The design company 1120 implements appropriate design procedures to form the IC design layout 1122. The design procedures include one or more of logic design, physical design, or place-and-route. The IC design layout 1122 is presented in one or more data files containing geometric pattern information. For example, the IC design layout 1122 may be represented in GDSII file format or DFII file format.

[0137] The photomask factory 1130 includes data preparation 1132 and photomask fabrication 1144. The photomask factory 1130 uses an IC design layout 1122 to fabricate one or more photomasks 1145 for fabricating layers of an IC device 1160 according to the IC design layout 1122. The photomask factory 1130 performs photomask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file ("RDF"). The photomask data preparation 1132 provides the RDF to the photomask fabrication 1144. The photomask fabrication 1144 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask 1145 or a semiconductor wafer 1153. The design layout 1122 is manipulated by the photomask data preparation 1132 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC wafer fab 1150. In Figure 11, the photomask data preparation 1132 and photomask fabrication 1144 are depicted as separate elements. In some embodiments, the photomask data preparation 1132 and photomask fabrication 1144 may be collectively referred to as photomask data preparation.

[0138] In some embodiments, the data preparation 1132 of the photomask includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can produce self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1122. In some embodiments, the data preparation 1132 of the photomask includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer photomasks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0139] In some embodiments, the photomask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout 1122, which has been processed in the OPC, using a set of photomask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during photomask fabrication 1144, which may undo some modifications performed by the OPC to conform to the photomask creation rules.

[0140] In some embodiments, the data preparation 1132 of the photomask includes lithography process checking (LPC), which is simulated by the IC wafer fab 1150 to manufacture the IC device 1160. The LPC simulates this process based on the IC design layout 1122 to create a simulated manufactured device, such as the IC device 1160. The processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and similar or combinations thereof. In some embodiments, after the LPC has created the simulated manufactured device, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further improve the IC design layout 1122.

[0141] It should be understood that, for clarity, the above description of the photomask data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify the IC design layout 1122 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0142] After the photomask data preparation 1132 and during photomask fabrication 1144, a photomask 1145 or a set of photomasks 1145 is fabricated based on a modified IC design layout 1122. In some embodiments, photomask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam or multiple electron beam mechanisms are used to form a pattern on the photomask (photomask or intermediate photomask) 1145 based on the modified IC design layout 1122. The photomask 1145 is formed using various techniques. In some embodiments, a binary technique is used to form the photomask 1145. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmits through the transparent areas. In one example, the binary version of photomask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary photomask. In another example, photomask 1145 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of photomask 1145, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask may be an attenuated PSM or an alternating PSM. Photomask fabrication 1144 generates one or more photomasks for various processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0143] IC wafer fab 1150 includes wafer fabrication 1152. IC wafer fab 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 1150 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of a plurality of IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services to the foundry enterprise.

[0144] IC wafer fab 1150 uses a photomask 1145 manufactured by photomask fab 1130 to manufacture IC device 1160. Therefore, IC wafer fab 1150 uses IC design layout 1122 at least indirectly to manufacture IC device 1160. In some embodiments, semiconductor wafer 1153 is manufactured by IC wafer fab 1150 using photomask 1145 to form IC device 1160. In some embodiments, IC manufacturing includes performing one or more photolithography exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1153 further includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0145] It will be readily apparent to those skilled in the art that one or more of the disclosed embodiments achieve one or more of the advantages described above. Upon reading the foregoing specification, those skilled in the art will be able to influence the various modifications, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalents.

[0146] In some embodiments, the semiconductor structure includes a first active region and a second active region extending along a first direction, an isolation region between and adjacent to the first and second active regions, a functional gate structure extending along a second direction and overlapping the first active region, a non-functional gate structure aligned with the functional gate structure along the second direction and overlapping the second active region, and a metallization layer located above the functional and non-functional gate structures. In some embodiments, the metallization layer defines a first metallization region extending along the first direction and located above the first active region, a second metallization region extending along the first direction and located above the second active region, and one or two intermediate metallization regions extending along the first direction and located between the first and second metallization regions. In some embodiments, the functional gate structure overlaps with the first metallization region and with one of the one or two intermediate metallization regions to define an overlapping portion of the one or two intermediate metallization regions. In some embodiments, the overlapping portion of the one or two intermediate metallization regions has a space defined therein, the size of which is adapted for connection features between the functional gate structure and one or two intermediate metallization regions.

[0147] In some embodiments, the semiconductor structure includes a first active region and a second active region extending along a first direction, an isolation region between and adjacent to the first and second active regions, a functional gate structure extending along a second direction and overlapping the first active region, and a non-functional gate structure aligned with the functional gate structure along the second direction and overlapping the second active region. In some embodiments, the semiconductor structure includes a first conductive trace of a metallization layer extending along the first direction, overlapping the functional gate structure, and overlapping the isolation region. In some embodiments, the semiconductor structure includes a connection feature connecting the functional gate structure and the first conductive trace.

[0148] In some embodiments, the semiconductor structure includes a first active region and a second active region extending along a first direction, an isolation region between and adjacent to the first active region and the second active region, a first functional gate structure extending along a second direction and overlapping the first active region, a first non-functional gate structure aligned with the first functional gate structure along the second direction and overlapping the second active region, a second functional gate structure extending along the second direction and overlapping the second active region, and a second non-functional gate structure aligned with the second functional gate structure along the second direction and overlapping the first active region. In some embodiments, the semiconductor structure includes a first conductive trace, a second conductive trace, or both of a metallization layer extending along the first direction and overlapping the isolation region. In some embodiments, the semiconductor structure includes a first connection feature connecting the first functional gate structure and the first conductive trace. In some embodiments, the semiconductor structure includes a second connection feature connecting the second functional gate structure and the first conductive trace, or connecting the second functional gate structure and the second conductive trace.

[0149] In some embodiments, a method of manufacturing a semiconductor structure includes forming a first active region and a second active region extending along a first direction, forming an isolation region between and adjacent to the first active region and the second active region, forming a functional gate structure extending along a second direction and overlapping the first active region, forming a non-functional gate structure aligned with the functional gate structure along the second direction and overlapping the second active region, and forming a metallization layer on the functional gate structure and the non-functional gate structure. In some embodiments, the metallization layer defines a first metallization region extending along the first direction and located above the first active region, a second metallization region extending along the first direction and located above the second active region, and one or two intermediate metallization regions extending along the first direction and located between the first metallization region and the second metallization region. In some embodiments, the functional gate structure overlaps with the first metallization region and overlaps with one of the one or two intermediate metallization regions to define an overlapping portion of the one or two intermediate metallization regions. In some embodiments, the overlapping portion of one of the one or two intermediate metallization regions has a space defined therein, the size of which is adapted for a connection feature between a functional gate structure and one of the one or two intermediate metallization regions.

[0150] In some embodiments, a method of manufacturing a semiconductor structure includes forming a first active region and a second active region extending along a first direction, forming an isolation region between and adjacent to the first and second active regions, forming a functional gate structure extending along a second direction and overlapping the first active region, and forming a non-functional gate structure aligned with the functional gate structure along the second direction and overlapping the second active region. In some embodiments, a method of manufacturing a semiconductor structure includes forming a first conductive trace of a metallization layer, the first conductive trace extending along the first direction, overlapping the functional gate structure, and overlapping the isolation region. In some embodiments, a method of manufacturing a semiconductor structure includes forming a connection feature connecting the functional gate structure and the first conductive trace.

[0151] In some embodiments, a method of manufacturing a semiconductor structure includes forming a first active region and a second active region extending along a first direction, forming an isolation region between and adjacent to the first active region and the second active region, forming a first functional gate structure extending along a second direction and overlapping the first active region, forming a first non-functional gate structure aligned with the first functional gate structure along the second direction and overlapping the second active region, forming a second functional gate structure extending along the second direction and overlapping the second active region, and forming a second non-functional gate structure aligned with the second functional gate structure along the second direction and overlapping the first active region. In some embodiments, a method of manufacturing a semiconductor structure includes forming a first conductive trace, a second conductive trace, or both of a metallization layer extending along the first direction and overlapping the isolation region. In some embodiments, a method of manufacturing a semiconductor structure includes forming a first connection feature connecting the first functional gate structure and the first conductive trace. In some embodiments, a method of manufacturing a semiconductor structure includes forming a second connection feature connecting the second functional gate structure and the first conductive trace, or connecting the second functional gate structure and the second conductive trace.

[0152] The features of several embodiments or examples have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity. FIG1 is a block diagram of a semiconductor device according to some embodiments. FIG2A-2D are layout diagrams of various layout patterns corresponding to various circuit cell examples according to some embodiments. FIG3A-3D are layout diagrams of various layout patterns corresponding to various circuit cell examples according to some embodiments. FIG4A is a circuit diagram of two transmission gates operating based on complementary control signals according to some embodiments. FIG4B-4D are layout diagrams of various layout patterns corresponding to circuit cells including two transmission gates operating based on complementary control signals according to some embodiments. FIG5A-5C are layout diagrams of various layout patterns corresponding to circuit cells including two transmission gates operating based on complementary control signals according to some embodiments. FIG6A is a circuit diagram of a trigger circuit example according to some embodiments. FIG6B-6C are layout diagrams of various layout patterns of circuit cells corresponding to the trigger circuit example of FIG6A according to some embodiments. Figure 7A is a circuit diagram of an example 4:1 multiplexer circuit according to some embodiments. Figure 7B is a layout diagram of various layout patterns of circuit cells corresponding to the 4:1 multiplexer of Figure 7A according to some embodiments. Figures 8A-8D are layout diagrams of various layout patterns of circuit cells corresponding to examples of skew logic circuits according to some embodiments. Figure 9 is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments. Figure 10 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 11 is a block diagram of a semiconductor device (e.g., integrated circuit (IC)) manufacturing system and the associated IC manufacturing process according to some embodiments.

Claims

1. A semiconductor structure, comprising: A first active region and a second active region extending along a first direction; An isolation region located between and adjacent to the first active region and the second active region; A functional gate structure extending along a second direction and overlapping with the first active region; a non-functional gate structure aligned with the functional gate structure and overlapping with the second active region along the second direction; and a metallization layer located above the functional gate structure and the non-functional gate structure, the metallization layer defining a first metallization region extending along the first direction and located above the first active region, a second metallization region extending along the first direction and located above the second active region, and one or two intermediate metallization regions extending along the first direction and located between the first metallization region and the second metallization region, wherein the functional gate structure overlaps with the first metallization region and overlaps with one of the one or two intermediate metallization regions to define an overlapping portion of one of the one or two intermediate metallization regions, the overlapping portion of one of the one or two intermediate metallization regions having a space defined therein, the size of which is adapted for a connection feature between the functional gate structure and one of the one or two intermediate metallization regions. The length of the non-functional gate structure along the second direction within the cell region of the semiconductor structure is equal to or greater than the width of the second active region along the second direction, and the length of the non-functional gate structure along the second direction is less than half of the cell height of the cell region along the second direction.

2. The semiconductor structure of claim 1, wherein the distance between the overlapping portion and the first active region is less than the distance between the overlapping portion and the second active region.

3. The semiconductor structure as claimed in claim 1, wherein the one or two intermediate metallization regions include a third metallization region located between the first metallization region and the second metallization region.

4. The semiconductor structure as claimed in claim 3, wherein the one or two intermediate metallization regions further include a fourth metallization region located between the third metallization region and the second metallization region.

5. The semiconductor structure as described in claim 1, further comprising: One or more channel structures located within the first active region, the one or more channel structures being located below or surrounded by the functional gate structure; A first drain / source structure located within the first active region and on a first side of the functional gate structure; and a second drain / source structure located within the first active region and on a second side of the functional gate structure, wherein the combination of the functional gate structure, the one or more channel structures, the first drain / source structure, and the second drain / source structure corresponds to a planar field-effect transistor (FET), a fin field-effect transistor (FinFET), a nanosheet field-effect transistor, or a nanowire field-effect transistor.

6. A semiconductor structure, comprising: A first active region and a second active region extending along a first direction; An isolation region located between and adjacent to the first active region and the second active region; A functional gate structure extending along a second direction and overlapping with the first active region; a non-functional gate structure aligned with the functional gate structure and overlapping with the second active region along the second direction; a first conductive trace of a metallization layer extending along the first direction, overlapping with the functional gate structure, and overlapping with the isolation region; and a connection feature connecting the functional gate structure and the first conductive trace, wherein the length of the non-functional gate structure along the second direction within the cell region of the semiconductor structure is equal to or greater than the width of the second active region along the second direction, and the length of the non-functional gate structure along the second direction is less than half of the cell height of the cell region along the second direction.

7. The semiconductor structure of claim 6, wherein the non-functional gate structure is a first dielectric gate structure adjacent to the functional gate structure, or the non-functional gate structure is a second dielectric gate structure or a conductive gate structure spaced apart from the functional gate structure.

8. A method for manufacturing a semiconductor structure, comprising: A first active region and a second active region are formed, extending along a first direction; An isolation region is formed between and adjacent to the first active region and the second active region; A functional gate structure is formed that extends along the second direction and overlaps with the first active region; a non-functional gate structure is formed that is aligned with the functional gate structure along the second direction and overlaps with the second active region; The non-functional gate structure is formed above the functional gate structure and the non-functional gate structure, the metallization layer defining a first metallization region extending along the first direction and located above the first active region, a second metallization region extending along the first direction and located above the second active region, and one or two intermediate metallization regions extending along the first direction and located between the first metallization region and the second metallization region, wherein the functional gate structure overlaps with the first metallization region and overlaps with one of the one or two intermediate metallization regions to define an overlapping portion of one of the one or two intermediate metallization regions, the overlapping portion of one of the one or two intermediate metallization regions having a space defined therein, the size of which is adapted for connection features between the functional gate structure and one of the one or two intermediate metallization regions, the length of the non-functional gate structure along the second direction within the cell region of the semiconductor structure is equal to or greater than the width of the second active region along the second direction, and the length of the non-functional gate structure along the second direction is less than half of the cell height of the cell region along the second direction.

9. The method of claim 8, wherein the nonfunctional gate structure is formed by a continuous polysilicon-on-dimer (CPODE) process based on a diffusion edge, wherein the nonfunctional gate structure is a first dielectric gate structure adjacent to the functional gate structure, or by a diced polysilicon (CPO) process, wherein the nonfunctional gate structure is a second dielectric gate structure or a conductive gate structure spaced apart from the functional gate structure.

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