Driving structure for display panel

Abstract

This invention provides a driving architecture for a display panel, comprising a controller, at least one driver, and a data detection circuit. The controller is disposed on the display panel and generates a data signal and a display clock signal. The at least one driver is disposed on the display panel and receives the data signal and the display clock signal. The data detection circuit detects the content of the data signal.

Description

Display panel driver architecture The present invention relates to a driving structure, and more particularly to a driving structure for a display panel. In a display panel having a plurality of drivers, a controller of the display panel sends a plurality of clock signals to the drivers, so that the drivers operate according to the timing of the clock signals to drive the light-emitting elements. Under normal circumstances, the controller continuously sends display clock signals to multiple drivers. Each driver contains a counter and comparator. Each counter in each driver is constantly counting, and each corresponding comparator is constantly comparing data. Therefore, regardless of whether a pixel is displaying, the dynamic power consumption of the driver remains constant. Display panels with multiple drivers typically have a large number of drivers and light-emitting elements. Even when the image is not displayed, these numerous drivers continue to operate and consume a large amount of power. This large number of drivers can lead to high power consumption for the entire display panel. Based on the above, the present invention provides a driving structure for a display panel, which can solve the technical problem of high power consumption and reduce the power consumption of the display panel according to the display image, thereby saving power. An object of the present invention is to provide a driving structure for a display panel, which includes a controller, at least one driver, and a data detector. The data detector controls the controller or at least one driver to selectively send a display clock signal according to the content of a data signal. One object of the present invention is to provide a display panel driving architecture in which, when a data detector detects that the contents of a data signal are all non-display values, a controller stops generating or sending a display clock signal, causing the driver to stop driving the light-emitting element to achieve power saving. One object of the present invention is to provide a display panel driving architecture, wherein when a data detector detects that the contents of a data signal are all non-display values, at least one driver stops sending a display clock signal, turning off light-emitting elements to achieve power saving. The present invention provides a display panel driver architecture comprising a controller, at least one driver, and a data detector. The controller and at least one driver are disposed on the display panel. The controller generates a data signal and a display clock signal, while the at least one driver receives the data signal and the clock signal. The data detector controls the controller or at least one driver to transmit the clock signal based on the data signal. Using the present invention's driver architecture to drive the display panel, the display panel can be operated without generating or without transmitting the clock signal based on the data signal, thereby achieving power savings while the display panel displays images. To help you, the review committee, gain a deeper understanding of the features and effects of the present invention, we would like to provide examples and accompanying explanations as follows: Certain terms are used in the specification and claims to refer to specific components. However, those skilled in the art will understand that manufacturers may use different terms to refer to the same component. Furthermore, this specification and claims do not distinguish components by name, but rather by overall technical differences. Throughout the specification and claims, the term "including" is an open-ended term and should be interpreted as meaning "including, but not limited to." Furthermore, the term "coupled" encompasses any direct and indirect means of connection. Therefore, if a first device is described as being coupled to a second device, this means that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or other means of connection. Please refer to Figure 1, which is a schematic diagram of a display panel drive architecture according to the present invention. The drive architecture of the present invention is used to drive a display panel 100 to display images. The display panel 100 includes a controller 110 and at least one driver 120. In this embodiment, a plurality of drivers 120 are used as an example. The controller 110 is disposed on the display panel 100 and coupled to the at least one driver 120. The at least one driver 120 is disposed on the display panel 100, and the plurality of drivers 120 in the same row are connected in series. Please refer to FIG. 2 , which is a partial schematic diagram of a driver architecture according to an embodiment of the present invention. The driver architecture of the present invention further includes a data detection circuit 130 . A controller 110 generates a data signal Din, a data clock signal DCK, a display clock signal PWMCK, and an enable signal ENRD. The controller 110 transmits the data signal Din, the data clock signal DCK, the display clock signal PWMCK, and the enable signal ENRD to at least one driver 120 . In this embodiment, these signals are transmitted to a plurality of drivers 120 . In this embodiment, data signal Din represents display data, which can be a serial data stream containing multiple pixel data and is used by display panel 100 to display images. While one data line is used to transmit data signal Din, any number of data lines can be used depending on panel size or application. Data clock signal DCK is a timing signal, and driver 120 receives data signal Din according to the timing of data clock signal DCK. Display clock signal PWMCK is a timing signal, and driver 120 drives the light-emitting elements on or off according to the timing of display clock signal PWMCK. The enable signal ENRD is a timing signal. The driver 120 is activated according to the enable signal ENRD. For example, when the driver 120 receives the enable signal ENRD, it indicates that it is selected to drive the light-emitting element to display an image. After the driver 120 of the current stage completes the transmission of display data, it outputs another enable signal to the driver 120 of the next stage, so that the driver 120 of the next stage receives the enable signal ENRD and begins operation. The driver 120 of the current stage and the driver 120 of the next stage are coupled to each other in series, as shown in the first figure. In this embodiment, a data detection circuit 130 is provided in the controller 110. There may be a plurality of data detection circuits 130, corresponding to the number of longitudinal rows of drivers 120. For example, if there are N rows of drivers 120, N data detection circuits 130 may be provided for each row of drivers 120, where N is an integer greater than 0. The data signal Din is transmitted to the plurality of drivers 120 via the data detection circuits 130. The data detection circuit 130 detects the contents of the data signal Din. The controller 110 determines whether to generate or transmit the display clock signal PWMCK based on the detection result of the data detection circuit 130. When the data detection circuit 130 detects that the contents of the data signal Din are all non-display values, this indicates that none of the light-emitting elements in the corresponding row of drivers 120 in the display panel 100 are emitting light. The non-display value is, for example, 0, meaning that the displayed image is black. The controller 110 then stops generating the display clock signal PWMCK or stops transmitting the display clock signal PWMCK to the corresponding driver 120. Consequently, the entire row of drivers 120 will not receive the display clock signal PWMCK, and the drivers 120 will stop driving the light-emitting elements, thereby eliminating dynamic current and achieving power conservation. In one embodiment, the non-display value is 1. When the data detection circuit 130 detects that the content of the data signal Din is not entirely non-display value, for example, when the data signal Din includes 1, it indicates that at least one light-emitting element corresponding to this row of drivers 120 in the display panel 100 will emit light and display an image. In this case, the controller 110 sends a display clock signal PWMCK to at least one driver 120 to perform subsequent display driving operations. In one embodiment, a data detection circuit 130 is provided within the controller 110. The data detection circuit 130 detects the contents of the data signal Din and transmits the data signal Din. For example, when the data detection circuit 130 detects that the contents of the data signal Din are not all zeros, the data detection circuit 130 transmits the data signal Din to at least one driver 120. This embodiment simplifies the overall circuit architecture by integrating various functions into the data detection circuit 130, thereby achieving the technical benefit of reducing circuit size. Please refer to FIG. 3, which is a partial schematic diagram of a driver architecture according to another embodiment of the present invention. In this embodiment, a data detection circuit 130 is provided in at least one driver 120. In this embodiment, the data detection circuit 130 is provided in each driver 120 as an example. When the controller 110 sends an enable signal ENRD to the driver 120, the driver 120 is enabled and ready to receive data and drive the light-emitting element. The driver 120 receives the data clock signal DCK and, according to the timing of the data clock signal DCK, receives the data signal Din. The data detection circuit 130 of the driver 120 detects the contents of the data signal Din. When the data detection circuit 130 detects that the contents of the data signal Din are all non-display values, the driver 120 stops receiving the display clock signal PWMCK. For example, the driver 120 stops operating. For example, the driver 120 stops operating. Even if the internal circuit elements receive the display clock signal PWMCK, they will not operate, thereby ceasing to drive the corresponding light-emitting elements. In one embodiment, when the data detection circuit 130 detects that the contents of the data signal Din are all non-display values, the data detection circuit 130 sends a control signal to other circuit elements within the driver 120, causing the other circuit elements to stop receiving the display clock signal PWMCK or to stop operating, thereby refraining from subsequently driving the light-emitting elements. In one embodiment, the driver 120 includes a counter. When the data detection circuit 130 detects that the data signal Din contains all non-display values, the data detection circuit 130 sends a control signal to the driver 120 counter to stop receiving the display clock signal PWMCK or to disable the counter. Since the counter counts based on the display clock signal PWMCK, when it does not receive the display clock signal PWMCK, it does not continue counting, causing the corresponding light-emitting element to be undriven and turned off. Furthermore, when the counter is not operating, it does not count even if it receives the display clock signal PWMCK. When the data detection circuit 130 detects that the data signal Din contains less than all non-display values, for example, when the data signal Din contains 1, at least one driver 120 drives the corresponding light-emitting element. After the driver 120 in the current stage receives the data signal Din, it sends an enable signal to the driver 120 in the next stage, and so on until the last driver 120 in the current stage. Please refer to FIG. 4 , which is a partial schematic diagram of a driving architecture according to another embodiment of the present invention. In this embodiment, the data detection circuit 130 is disposed in the controller 110 and the driver 120 . Therefore, the operation of detecting the content of the data signal Din by the data detection circuit 130 can be performed in the controller 110 , the driver 120 , or both the controller 110 and the driver 120 . For example, when the amount of information in the data signal Din is large, the operation of detecting the content of the data signal Din can be performed simultaneously in the controller 110 and the driver 120 to ensure that the content of the data signal Din is accurately detected. This simultaneous detection by both sides ensures the accuracy of data content detection. Please refer to Figure 5, which is a circuit diagram of one embodiment of a driver according to the present invention. In this embodiment, the driver 120 includes a data receiver / detector 121, a counter 122, at least one memory circuit 123, at least one comparator 124, at least one current source circuit 125, and at least one light-emitting element 126. In this embodiment, three memory circuits 123, three comparators 124, three current source circuits 125, and three light-emitting elements 126 are used as an example. In other words, the driver 120 is coupled to and drives three light-emitting elements 126, but the present invention is not limited to this. The data receiver / detector 121 receives an enable signal ENRD generated by the controller 110 or sent by the previous driver 120, as well as a data signal Din and a data clock signal DCK generated by the controller 110. In one embodiment, after receiving the data signal Din, the driver 120 transmits another enable signal to the next driver 120 as the enable signal ENRD for the next driver 120. After the data receiver / detector 121 receives the enable signal ENRD, the driver 120 prepares to receive the data signal Din and drive the corresponding light-emitting element 126. The data receiver / detector 121 receives the data signal Din according to the timing of the data clock signal DCK. The data receiver / detector 121 distributes the data signal Din to the memory circuit 123 based on the display image of the display panel 100. The memory circuit 123 stores the received data signal Din and sends it to the comparator 124. Counter 122 receives the display clock signal PWMCK generated by controller 110. Counter 122 generates a count signal based on the display clock signal PWMCK and transmits it to comparator 124. Comparator 124 receives data signal Din from memory circuit 123 and the count signal from counter 122. Comparator 124 compares the two signals and transmits the comparison result to current source circuit 125. Current source circuit 125 then turns light-emitting element 126 on or off based on the comparison result. For example, comparator 124 compares the grayscale value of data signal Din with the count signal. When the count signal is greater than or equal to the grayscale value of data signal Din, comparator 124 transmits the comparison result to current source circuit 125, which then turns light-emitting element 126 on based on the comparison result. In another embodiment, when the grayscale value of data signal Din is greater than or equal to the count signal, comparator 124 transmits the comparison result to current source circuit 125 to drive light-emitting element 126. In one embodiment, the data detection circuit 130 is disposed within the data receiver / detector 121. When the data receiver / detector 121 of the driver 120 receives the data signal Din, the data detection circuit 130 detects the contents of the data signal Din. When the contents of the data signal Din are all non-display values, the data receiver / detector 121 transmits a control signal Ctrl to the counter 122, causing the counter 122 to stop receiving the display clock signal PWMCK or to stop operating. When the counter 122 does not receive the display clock signal PWMCK, it does not count. When the counter 122 stops operating, it does not count even if it receives the display clock signal PWMCK. This stops the subsequent operation of driving the light-emitting element 126, thereby saving power consumption of the display panel 100. Please refer to Figure 6, which is a circuit diagram of another embodiment of a driver according to the present invention. In this embodiment, the driver 120 includes a data receiver / detector 121, a counter 122, at least one memory circuit 123, at least one current source circuit 125, and at least one light-emitting element 126. For ease of explanation, this embodiment uses three memory circuits 123, three current source circuits 125, and three light-emitting elements 126 as an example. In other words, the driver 120 is coupled to and drives three light-emitting elements 126, but the present invention is not limited to this. The data receiver / detector 121 receives an enable signal ENRD generated by the controller 110 or sent by the previous driver 120, as well as a data signal Din and a data clock signal DCK generated by the controller 110. In one embodiment, after receiving the data signal Din, the driver 120 transmits another enable signal to the next driver 120 as the enable signal ENRD for the next driver 120. After the data receiver / detector 121 receives the enable signal ENRD, the driver 120 prepares to receive the data signal Din and drive the corresponding light-emitting element 126. The data receiver / detector 121 receives the data signal Din according to the timing of the data clock signal DCK. The data receiver / detector 121 distributes the data signal Din to the memory circuit 123 based on the display image of the display panel 100. The memory circuit 123 stores the received data signal Din and sends it to the counter 122. Counter 122 receives data signal Din sent from memory circuit 123 and display clock signal PWMCK generated by controller 110. Counter 122 generates a count signal based on the display clock signal PWMCK and the grayscale value of data signal Din. Current source circuit 125 drives light-emitting element 126 on or off based on the count signal. For example, if the grayscale value of data signal Din is 50, counter 122 generates a count signal corresponding to the grayscale value of 50 based on the timing of display clock signal PWMCK and sends it to current source circuit 125. Current source circuit 125 activates light-emitting element 126 based on the count signal, causing light-emitting element 126 to produce a brightness corresponding to the grayscale value of 50 of data signal Din. In one embodiment, the data detection circuit 130 is disposed within the data receiver / detector 121. When the data receiver / detector 121 of the driver 120 receives the data signal Din, the data detection circuit 130 detects the contents of the data signal Din. When the contents of the data signal Din are all non-display values, the data receiver / detector 121 transmits a control signal Ctrl to the counter 122, causing the counter 122 to stop receiving the display clock signal PWMCK or to stop operating. When the counter 122 does not receive the display clock signal PWMCK, it does not count. When the counter 122 stops operating, it does not count even if it receives the display clock signal PWMCK. This stops the subsequent operation of driving the light-emitting element 126, thereby saving power consumption of the display panel 100. The light-emitting element 126 of the present invention can be a micro LED, a sub-millimeter LED, or other light-emitting element. The display panel 100 can be a micro LED panel, a sub-millimeter LED panel, or other light-emitting element display panel. The data detection circuit 130 of the present invention is not limited to being located in the controller 110 or the driver 120. It can be located anywhere in the display panel 100 according to actual needs, and can also be located in part of the driver 120. Through the display panel driving architecture of this case, the display panel controller and driver can selectively generate display clock signals according to the content of the data signal. When the light-emitting element does not need to display, the overall power consumption of the display panel can be greatly reduced, saving electricity. Therefore, this invention is novel, progressive and can be used in industry. It should undoubtedly meet the patent application requirements of my country's Patent Law. Therefore, I have filed an invention patent application in accordance with the law and pray that the patent office will be approved as soon as possible. I am deeply grateful. However, the above is only one embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications based on the structure, characteristics and spirit described in the scope of the patent application of the present invention should be included in the scope of the patent application of the present invention. 100: Display panel 110: Controller 120: Driver 121: Data receiver / detector 122: Counter 123: Memory circuit 124: Comparator 125: Current source circuit 126: Light-emitting element 130: Data detection circuit Din: Data signal DCK: Data clock signal PWMCK: Display clock signal ENRD: Enable signal Ctrl: Control signal Figure 1 is a schematic diagram of the driving structure of a display panel of the present invention; Figure 2 is a partial schematic diagram of the driving structure of one embodiment of the present invention; Figure 3 is a partial schematic diagram of the driving structure of another embodiment of the present invention; Figure 4 is a partial schematic diagram of the driving structure of another embodiment of the present invention; Figure 5 is a circuit block diagram of one embodiment of the driver of the present invention; Figure 6 is a circuit block diagram of another embodiment of the driver of the present invention. 100: Display panel 110: Controller 120:Drive

Claims

1. A driving architecture for a display panel, comprising: a controller disposed on the display panel for generating a data signal and a display clock signal; at least one driver disposed on the display panel for receiving the data signal and the display clock signal; and a data detection circuit for detecting the content of the data signal to control the transmission of the display clock signal.

2. The drive architecture as described in claim 1, wherein the data detection circuit is disposed in the controller, and when the data detection circuit detects that the content of the data signal is all non-display values, the controller stops generating the display clock signal.

3. The drive architecture as described in claim 1, wherein the data detection circuit is disposed in the controller, and when the data detection circuit detects that the content of the data signal is all non-display values, the controller stops sending the display clock signal to the at least one driver.

4. The drive architecture as described in claim 1, wherein the data detection circuit is disposed in the at least one driver, and when the data detection circuit detects that the content of the data signal is all non-display values, the at least one driver stops receiving the display clock signal or stops operating.

5. The drive architecture as described in claim 1, wherein the data detection circuit is disposed in the at least one driver, the at least one driver including a counter, wherein when the data detection circuit detects that the content of the data signal is all non-display values, the data detection circuit sends a control signal to the counter to stop operation, or causes the counter to stop receiving the display clock signal.

6. The drive architecture as described in claim 1, wherein the data detection circuitry is disposed in the controller and the at least one driver.

7. The drive architecture as described in claim 1, wherein the controller generates a consistent enable signal and sends it to the at least one driver, the at least one driver starting to receive the data signal and the display clock signal based on the enable signal.

8. The drive architecture as described in claim 7, wherein the at least one driver includes a first driver and a second driver, the first driver being connected in series with the second driver, and the first driver receiving the enable signal and then sending another enable signal to the second driver.

9. The drive architecture as described in claim 1, wherein the controller generates a data clock signal and sends it to the at least one driver, the at least one driver receiving the data signal based on the data clock signal.

10. The drive architecture as described in claim 9, wherein the at least one driver includes a first driver and a second driver, the first driver being connected in series with the second driver, and the first driver and the second driver simultaneously receiving the data clock signal.

11. The driving architecture as described in claim 1, wherein the at least one driver comprises: a data receiver / detector for detecting the content of the data signal and allocating the data signal; a memory circuit for storing the data signal; a counter for generating a counting signal based on the display clock signal; a comparator for receiving the data signal and the counting signal and generating a comparison result; and a current source circuit for driving a light-emitting element based on the comparison result.

12. The drive architecture as described in claim 11, wherein the data receiver / detector includes the data detection circuitry that, when the content of the data signal is entirely non-display values, the data receiver / detector sends a control signal to the counter to stop the operation of the counter, or causes the counter to stop receiving the display clock signal.

13. The driving architecture as described in claim 1, wherein the at least one driver comprises: a data receiver / detector for detecting the content of the data signal and allocating the data signal; a memory circuit for storing the data signal; a counter for generating a counting signal based on the content of the data signal and the display clock signal; and a current source circuit for driving a light-emitting element based on the counting signal.

14. The drive architecture as described in claim 13, wherein the data receiver / detector includes the data detection circuitry that, when the content of the data signal is entirely non-display values, the data receiver / detector sends a control signal to the counter to stop the operation of the counter, or causes the counter to stop receiving the display clock signal.

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