Semiconductor devices and methods for forming the same

Abstract

A GAA device is provided. The GAA device is manufactured from a substrate having a (551) / <110> top surface. Choosing a (551) / <110> substrate enables channel miniaturization while improving hole mobility without sacrificing electron mobility.

Description

[Technical Field]

[0001] The present invention relates to an apparatus and a method of forming the same, and particularly to a semiconductor apparatus and a method of forming the same. [Previous Technology]

[0002] The semiconductor industry has experienced sustained and rapid growth due to the increasing integration of various electronic components. To a large extent, the increase in integration density comes from the continuous reduction in the minimum component size, which allows more components to be integrated into a given wafer area. As the minimum component size decreases, the trade-off between holes and electron mobility in the channel region becomes a challenge affecting device performance. [Summary of the Invention]

[0003] Some embodiments of the present invention provide a semiconductor device, including: a first source / drain region; a second source / drain region; two or more semiconductor layers disposed between the first source / drain region and the second source / drain region and coupled to the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure wrapping around the two or more semiconductor layers.

[0004] Other embodiments of the present invention provide a semiconductor device, comprising: two or more semiconductor layers, each of the two or more semiconductor layers including a first end, a second end, and a central portion connecting the first end and the second end, the first end having a first surface roughness, and the central portion having a second surface roughness different from the first surface roughness; a gate structure surrounding the central portion of the two or more semiconductor layers; a first source / drain region disposed on the first end of the two or more semiconductor layers; and a second source / drain region disposed on the second end of the two or more semiconductor layers.

[0005] Some embodiments of the present invention provide a method of forming a semiconductor device, comprising: selecting a substrate having a top surface having a (551) surface orientation; epitaxially growing a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack includes two or more first semiconductor layers and two or more second semiconductor layers, the two or more first semiconductor layers and the two or more second semiconductor layers being stacked alternately; forming a fin structure from the semiconductor stack and the substrate; forming a sacrificial gate structure on the fin structure; etching back the fin structure along the sidewalls of the sacrificial gate structure; epitaxially growing a source / drain region from the two or more second semiconductor layers; depositing a contact etch stop layer (CESL) on the source / drain region; depositing an interlayer dielectric (ILD) layer on the CESL; removing the sacrificial gate structure to expose the fin structure; removing the two or more first semiconductor layers; and forming an alternative gate structure around the two or more second semiconductor layers.

Implementation Method

[0007] The following provides many different embodiments or examples to achieve different features of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the following description mentions forming a first component on or above a second component, which may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0008] Spatial relative terms, such as "below," "below," "lower," "above," "above," "top," "upper," etc., may be used here to facilitate the description of the relationship between one or more components or features in the diagram and another component or feature(s). Spatial relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 64 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0009] The foregoing description summarizes some aspects of the embodiments disclosed herein. While some embodiments of this disclosure are described in the context of nanosheet channel FETs, implementations of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices. Those skilled in the art will understand that other modifications are also possible and are covered within the scope of this disclosure. Furthermore, although method embodiments may be described in a specific order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. In this disclosure, source / drain refers to the source and / or drain. Source and drain are used interchangeably.

[0010] Fins can be patterned using any suitable method. For example, one or more lithography processes (including dual patterning or multiple patterning processes) can be used to pattern the fins. Generally, dual patterning or multiple patterning processes combine lithography with a self-aligned process, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins.

[0011] Fully wound gate (GAA) transistor structures can be patterned using any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine lithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0012] The horizontally stacked GAA nanosheet channel structure provides excellent short-channel control and increases the effective channel width (Wff) per unit area. As technology nodes continue to miniaturize, further miniaturization of nanosheet height and performance improvement are urgently needed.

[0013] In the prior art, GAA nanosheet channels are formed on the (100) substrate surface direction with the channel along the <110> direction (hereinafter referred to as (100) / <110> channels), or formed on the (110) substrate surface direction with the channel along the <110> direction (hereinafter referred to as (110) / <110> channels). As the channel height decreases, the (100) / <110> channels suffer a significant loss in hole mobility, while the electron mobility increases slightly. On the other hand, the (110) / <110> channels suffer a certain degree of loss in electron mobility as the channel height decreases, while the hole mobility increases. Therefore, further miniaturization of the channel height under the prior art inevitably faces a trade-off between loss of hole mobility or loss of electron mobility.

[0014] In addition, it has been observed that various other factors, such as surface roughness scattering (SRS), remote phonon scattering (RPS), acoustic deformation potential (ADP), and remote coulomb scattering (RCS), also lead to a loss of electron mobility, especially when the channel width is reduced. Among these factors, surface roughness scattering dominates the electron mobility performance for (110) / <110>.

[0015] This disclosure provides a thin-channel nanosheet device and a method for forming the device by selecting a (551) / <110> substrate as the starting material. The (551) surface is inclined at 8 degrees from the (110) surface to the (100) surface and has a similar band structure and other scattering factors as the (110) surface. Therefore, the (551) surface provides the same high hole mobility as the (110) surface when the sheet height is reduced. In addition, the (551) / <110> channel exhibits a similar electron mobility to the (100) / <110> channel, i.e., it does not suffer a loss of electron mobility as the channel height is reduced.

[0016] Therefore, the GAA device with (551) / <110> channel according to the present disclosure provides improved hole mobility compared to (110) / <110> channel without loss of electron mobility.

[0017] Furthermore, the (551) silicon surface can achieve a lower surface roughness. In some embodiments, the (551) surface is roughened to reduce the SRS factor and improve electron mobility. In summary, the (551) / <110> channel according to this disclosure provides hole mobility gain without sacrificing electron mobility as the channel height decreases.

[0018] According to some embodiments of the present disclosure, Figure 1 is a flowchart of a method 100 for manufacturing a semiconductor device. According to some embodiments of the present disclosure, Figures 2, 2A, 3, 4, 4A and 5 to 10 schematically illustrate various stages of manufacturing an example semiconductor device 200. In detail, the semiconductor device 200 can be manufactured according to the method 100 of Figure 1.

[0019] In operation 102 of method 100, a substrate 202 having a (551) surface orientation is selected for forming a semiconductor device 200 thereon. Figure 2A is a schematic top view of the substrate 202 according to the present disclosure. The top surface 202t of the substrate 202 is a facet surface in the (551) direction. Specifically, the (551) surface is inclined at 8 degrees from the (110) surface in the <100> direction. As shown in Figures 2 and 2A, the substrate 202 has a <110> direction along the x-direction.

[0020] In some embodiments, the substrate 202 may include a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP.

[0021] Depending on the circuit design, substrate 202 may include various doping configurations. For example, substrate 202 may include p-doped regions or p-wells and n-doped regions or n-wells. One or more n-type devices, such as nFETs, will be formed on and / or within the p-wells. One or more p-type devices, such as pFETs, will be formed on and / or within the n-wells.

[0022] In operation 104 of method 100, a semiconductor stack including alternating first semiconductor layer 206 and second semiconductor layer 208 is formed on substrate 202 to facilitate the formation of nanosheet channels, such as nanosheet channel FETs, in a multi-gate n-type device. The first semiconductor layer 206 and the second semiconductor layer 208 can be epitaxially grown from the top surface 202b of substrate 202. Due to the characteristics of epitaxial growth, the first and second semiconductor layers 206, 208 also have a (551) surface orientation.

[0023] The first semiconductor layer 206 and the second semiconductor layer 208 have different compositions. In some embodiments, semiconductor layers 206 and 208 provide different oxidation rates and / or different etch selectivity. In subsequent fabrication stages, portions of the second semiconductor layer 208 form nanosheet channels in a multi-gate device. As shown in Figure 2, an example is an alternating arrangement of three first semiconductor layers 206 and three second semiconductor layers 208. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer semiconductor layers 206 and 208 may be included. In some embodiments, the number of semiconductor layers 206 and 208 is between 1 and 10.

[0024] For an n-type device or nFET, the first semiconductor layer 206 may include silicon germanium (SiGe). The first semiconductor layer 206 may be a SiGe layer comprising Ge with a molar ratio exceeding 25%. For example, the first semiconductor layer 206 may be a SiGe layer comprising Ge with a molar ratio between 25% and 50%. For an n-type device or nFET, the second semiconductor layer 208 may include silicon. In some embodiments, the second semiconductor layer 208 is a silicon layer.

[0025] For a p-type device or pFET, the first semiconductor layer 206 may include silicon germanium (SiGe). The first semiconductor layer 206 may be a SiGe layer comprising Ge with a molar ratio exceeding 25%. For example, the first semiconductor layer 206 may be a SiGe layer comprising Ge with a molar ratio between 25% and 50%. For a p-type device or pFET, the second semiconductor layer 208 may include silicon, Ge, compound semiconductors (e.g., SiC, GeAs, GaP, InP, InAs, and / or InSb), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof). In some embodiments, the second semiconductor layer 208 is a silicon layer.

[0026] Semiconductor layers 206 and 208 can be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. The semiconductor stacks of n-type and p-type devices can be formed separately using patterning techniques.

[0027] In operation 106 of method 100, a fin structure 210 is formed by etching a portion of the semiconductor stack and the underlying substrate 202, as shown in Figure 3, which is a schematic diagram of the semiconductor device 200. As shown in Figure 3, the fin structure 210 is formed along the x-direction. In other words, the fin structure 210 is formed along the <110> direction.

[0028] As shown in Figure 3, after forming the fin structure 210, each semiconductor layer 208 has two horizontal channel surfaces 208xys parallel to the top surface 202t of the substrate 202. The horizontal channel surfaces 208xys have a (551) surface orientation. Each semiconductor layer 208 also has two vertical channel surfaces 208xzs along the x-direction. At the end of the fin structure 210, the semiconductor layer 208 has two channel end faces 208yzs. In some embodiments, the channel end faces 208yzs have a (110) surface orientation.

[0029] In some embodiments, each fin structure 210 has a width W1 along the y-direction. The width W1 can be selected according to the circuit design. In some embodiments, the width W1 can be between about 10 nm and about 200 nm. A portion of the semiconductor layer 208 serves as a channel region connecting the source / drain components in the semiconductor device to be formed. Each semiconductor layer 208 may have a channel height CH along the z-direction. In some embodiments, the channel height CH is between about 2 nm and about 10 nm. The semiconductor layer 206 is used to define the vertical distance between adjacent channel regions formed by the semiconductor layers 208 of the subsequently formed device. Each semiconductor layer 206 may have a gate height GH along the z-direction. In some embodiments, the gate height GH of the semiconductor layer 206 is equal to or greater than the channel height CH of the semiconductor layer 208. In some embodiments, the gate height GH is between about 2 nm and about 10 nm. The channel spacing CS (the combined distance of the gate height GH and the channel height CH) can be between 4 nm and 20 nm. It should be noted that since a portion of semiconductor layer 206 can be removed along with semiconductor layer 208 during the subsequent gate replacement process, the channel height CH will decrease and the gate height GH will increase. However, the channel spacing CS will remain substantially unchanged.

[0030] After forming the fin structures, an isolation layer 212 is formed, as shown in Figure 4, which is a schematic diagram of the semiconductor device 200. The isolation layer 212 fills the trenches between the fin structures 210 and is then etched back to the semiconductor stack beneath the fin structures 210. The isolation layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flow CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 212 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or combinations thereof. In some embodiments, the isolation layer 212 is formed by a suitable deposition process to cover the fin structures 210 to fill the trenches between the fin structures 210, and then etched using a suitable anisotropic etching process to expose the active portions of the fin structures 210.

[0031] In operation 108, as shown in Figure 4, a sacrificial gate structure 214 is formed on the isolation layer 212 and on the exposed portion of the fin structure 210, which is a schematic diagram of the semiconductor device 200. The sacrificial gate structure 214 is formed on the portion of the fin structure 210 that will serve as a channel region. Figure 4A is a schematic top view of the substrate 202 showing the orientation of the fin structure 210 and the sacrificial gate structure 214. As shown in Figure 4A, the fin structure 210 is formed along the <110> direction, and the sacrificial gate structure 214 is perpendicular to the fin structure 210.

[0032] The sacrificial gate structure 214 may include a sacrificial gate dielectric layer 218, a sacrificial gate electrode layer 220, a pad layer 222, and a shielding layer 224.

[0033] The sacrificial gate dielectric layer 218 can be compliantly formed on the fin structures 210a, 210b and the isolation layer 212. In some embodiments, the sacrificial gate dielectric layer 218 can be deposited through a CVD process, a subatmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process or other suitable processes. The sacrificial gate dielectric layer 218 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material and / or other suitable dielectric material.

[0034] The sacrificial gate electrode layer 220 may be deposited on the sacrificial gate dielectric layer 218 as a blanket. The sacrificial gate electrode layer 220 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is between about 42 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer 220 is planarized. The sacrificial gate electrode layer 220 may be deposited using CVD (including LPCVD and PECVD, PVD, ALD or other suitable processes).

[0035] Subsequently, a pad layer 222 and a mask layer 224 are formed on the sacrificial gate electrode layer 220. The pad layer 222 may include silicon nitride. The mask layer 224 may include silicon oxide. Next, the mask layer 224, the pad layer 222, the sacrificial gate electrode layer 220, and the sacrificial gate dielectric layer 218 are patterned to form a sacrificial gate structure 214.

[0036] Subsequently, gate sidewall spacers 216 are formed on the sidewalls of the sacrificial gate structure 214. Gate sidewall spacers 216 are formed on the sidewalls of each sacrificial gate structure 214, as shown in Figure 4. Gate sidewall spacers 216 are formed by blanket deposition of one or more layers of insulating material. The insulating material can be deposited using any suitable deposition method. In some embodiments, gate sidewall spacers 216 can be formed by ALD or CVD. In some embodiments, the insulating material of the gate sidewall spacers 216 may include one or more dielectric materials. In some embodiments, the insulating material of the gate sidewall spacers 216 may include a dielectric material selected from silicon oxide, silicon nitride (e.g., Si3N4), carbon-doped silicon oxide, nitrogen-doped silicon oxide, porous silicon oxide, or combinations thereof.

[0037] The gate sidewall spacer 216 has a thickness of about 3 nm and about 12 nm along the x-direction and covers a portion of the fin structure 210. In some embodiments, the gate sidewall spacer 216 is anisotropically etched to remove the gate sidewall spacer 216 from horizontal surfaces (e.g., the top surface of the masking layer 224 and the top surface of the isolation layer 212). In other embodiments, the gate sidewall spacer 216 on the horizontal surface may be removed during the fin structure etchback process in operation 108 discussed below.

[0038] In operation 110, the fin structures 210 not covered by the sacrificial gate structure 214 are etched back, as shown in Figure 5, which is a cross-sectional view of the semiconductor device 200 along line AA in Figure 4. The fin structures 210 not covered by the sacrificial gate structure 214 and the gate sidewall spacers 216 are etched to expose the well portion of each fin structure 210 and form the source / drain cavity 205. In some embodiments, suitable dry etching and / or wet etching may be used to remove the semiconductor layers 206, 208 together or separately.

[0039] In operation 112, an inner spacer 226 is formed, as shown in Figures 5 and 6. To form the inner spacer 226, the semiconductor layer 206 exposed to the source / drain cavity 205 is etched from the semiconductor layer 208 along the horizontal or x-direction to form an inner spacer cavity under the gate sidewall spacer 216, as shown in Figure 5. In some embodiments, the semiconductor layer 206 may be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0040] After forming the inner spacer cavity, the inner spacer 226 is formed by conformally depositing an insulating layer in the inner spacer cavity and then partially removing it through an anisotropic etching process. The insulating layer can be formed by ALD or any other suitable method. The subsequent etching process removes most of the insulating layer except inside the cavity, thereby forming the inner spacer 226. In some embodiments, the inner spacer 226 may include one or more dielectric materials. In some embodiments, the inner spacer 226 may include a dielectric material, such as a dielectric material based on SiO2, SiON, SiOC, or SiOCN, an air gap, or a combination thereof.

[0041] The inner spacer 226 and the gate sidewall spacer 216 may be formed of the same material or different materials to achieve the desired performance. In some embodiments, the inner spacer 226 may have a lower dielectric constant k than the gate sidewall spacer 216 to obtain the desired performance, such as low capacitance. In some embodiments, the inner spacer 226 may have a higher dielectric constant k than the gate sidewall spacer 216 to obtain the desired performance, such as increased device reliability.

[0042] The thickness of the inner spacer 226 along the x-direction is about 3 nm to about 12 nm. In some embodiments, the thickness of the inner spacer 226 is approximately similar to the thickness of the gate sidewall spacer 216.

[0043] In operation 114, an epitaxial source / drain region 232 is formed, as shown in Figure 7. In some embodiments, a bottom epitaxial layer 229 may be formed at the bottom of the source / drain cavity 205. The bottom epitaxial layer 229 may be an epitaxial semiconductor layer grown from the substrate 202, and therefore has the same crystal orientation as the substrate 202. The bottom epitaxial layer 229 may be a transition layer between the crystal structure of the semiconductor substrate 202 and the epitaxial source / drain region 232. In some embodiments, the bottom epitaxial layer 229 may serve as an alignment member for forming a back-side source / drain contact.

[0044] The bottom isolation layer 230 may be formed on the bottom epitaxial layer 229. The bottom isolation layer 230 may include one or more dielectric materials. The bottom isolation layer 230 may be formed by a deposition process followed by an etching process. The bottom isolation layer 230 can prevent leakage current between the source / drain region 232 and the high plateau region under the sacrificial gate structure 214.

[0045] The epitaxial source / drain region 232 can be epitaxially grown from exposed surfaces, such as the semiconductor layer 208 and the substrate 202, in the source / drain cavity 205. The epitaxial source / drain region 232 of the N-type device and the epitaxial source / drain region 232 of the P-type device are typically formed using patterning techniques, respectively.

[0046] The epitaxial source / drain region 232 for an n-type device may include one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain region 232 may also include an n-type dopant, such as phosphorus (P), arsenic (As), etc. In some embodiments, the epitaxial source / drain region 232 may be a Si layer including a phosphorus (P) dopant. The epitaxial source / drain region 232 for a p-type device may include one or more layers of Si, SiGe, or Ge having a p-type dopant (e.g., boron (B)). In some embodiments, the epitaxial source / drain region 232 may be a SiGe material containing boron as a dopant.

[0047] The epitaxial source / drain region 232 grows from the channel end face 208yzs, so the sidewall 232s portion of the source / drain region has the same surface orientation as the channel end face 208yzs. In some embodiments, the portion of the sidewall 232s that contacts the semiconductor layer 208 has a (110) surface orientation.

[0048] In operation 116, a contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are compliantly formed on the semiconductor substrate, as shown in Figure 7.

[0049] CESL 236 can be uniformly formed on the exposed surface of semiconductor device 200. CESL 236 is formed on the exposed surface 232f of epitaxial source / drain region 232, the exposed surface of gate sidewall spacer 216, and the exposed surface of isolation layer 212. CESL 236 serves as an etch stop layer to provide protection for source / drain region 232 during the formation of source / drain contact components. CESL 236 may include Si3N4, SiON, SiCN, or any other suitable material and may be formed by CVD, PVD, or ALD.

[0050] An ILD layer 238 is formed on a CESL 236. The material of the ILD layer 238 includes compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may be used for the ILD layer 238. In some embodiments, the ILD layer 238 may be formed by flow-through CVD (FCVD). The ILD layer 238 protects the epitaxial source / drain region 232 during the removal of the sacrificial gate structure 214. A planarization process, such as a CMP process, may be performed after the deposition of the material for the ILD layer 238 to expose the sacrificial gate structure 214 for subsequent processes.

[0051] In operation 118, the sacrificial gate structure 214 and semiconductor layer 206 are removed to expose semiconductor layer 208, as shown in Figure 8. The sacrificial gate dielectric layer 218 and sacrificial gate electrode layer 220 are removed by dry etching, wet etching, or a combination thereof. Semiconductor layer 206 is exposed and subsequently removed to form a gate cavity 240 surrounding the nanosheet of semiconductor layer 208. As shown in Figure 8, the central portion 208c of each semiconductor layer 208 is exposed to the gate cavity 240, while the end portion 208e of each semiconductor layer 208 is covered by inner spacers 226 and gate sidewall spacers 216.

[0052] In operation 120, a roughness treatment process is performed to reduce the surface roughness of the central portion of the semiconductor layer 208, as shown in Figure 9.

[0053] In some embodiments, a roughening process can be performed by processing the semiconductor device 200 in a process gas. In some embodiments, a roughening process can be performed by Xe / H2 plasma, H2 annealing, H radicals, etc.

[0054] The roughening process improves the surface smoothness of the exposed portion of the semiconductor layer 208 (i.e., the central portion 208c of the semiconductor layer 208). Figure 9A is a partially enlarged cross-sectional view of the semiconductor layer 208 exposed to the gate cavity 240. As shown in Figure 9A, the horizontal channel surface 208xys and the vertical channel surface 208xzs are exposed to process chemicals.

[0055] As described above, the horizontal channel surface 208xys has a (551) surface orientation, which is stable in alkaline solutions and is beneficial for maintaining surface flatness and reducing surface roughness. In some embodiments, after roughening treatment, the horizontal channel surface 208xys of the central portion 208c of the semiconductor layer 208 can achieve a roughness Δrms of less than about 3.0 Å, for example, about 1.1 Å, while the unexposed end 208e has a roughness Δrms of about 5.2 Å.

[0056] The vertical channel surface 208xzs can have a (1 1 10) surface. Roughening treatment also improves the smoothness of the vertical channel surface 208xzs, but to a lesser extent than the horizontal channel surface 208xys. In some embodiments, after roughening treatment, the vertical channel surface 208xzs of the central portion 208c of the semiconductor layer 208 can achieve a roughness Δrms of less than about 5.0 Å, for example, between about 4.2 Å and about 4.8 Å, while the roughness Δrms of the unexposed end 208e is between about 5.0 Å and 6.6 Å. Since the channel height CH is smaller than the channel width W1, the area of ​​the vertical channel surface 208xzs is smaller than the area of ​​the horizontal channel surface 208xys, and the roughness reduction effect from the vertical channel surface 208xzs is less than the roughness reduction effect from the horizontal channel surface 208xys.

[0057] In operation 122, a replacement gate structure 248 is formed on the central portion 208c of the semiconductor layer 208 and fills the gate cavity 240, as shown in Figure 10. The replacement gate structure 248 includes a gate dielectric layer 242 and a gate electrode layer 244. In some embodiments, an interface layer 243 (as shown in Figures 11A to 11D) may be formed on the semiconductor layer 208 before the gate dielectric layer 242 is formed.

[0058] A gate dielectric layer 242 is formed on the exposed surface in the gate cavity. For N-type and P-type devices, the gate dielectric layer 242 can have different compositions and sizes, and can be formed individually using patterned masking layers and different deposition formulations. The gate dielectric layer 242 may include one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, and other suitable high-k dielectric materials. The gate dielectric layer 242 can be formed by CVD, ALD, or any suitable method.

[0059] A gate electrode layer 244 is formed on the gate dielectric layer 242 to fill the gate cavity. The gate electrode layer 244 may include one or more layers of conductive materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 244 may be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, the gate electrode layer 244 may include different conductive materials and be formed in different processes. Alternatively, the gate electrode layer 244 may include the same conductive material and be formed in the same process. After the gate electrode layer 244 is formed, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer 238.

[0060] Subsequently, source / drain contact components 254 are formed. Contact holes can be formed through ILD layers 238 and CESL 236 to expose the epitaxial source / drain regions 232, and the contact holes are subsequently filled with a conductive material. Suitable lithography and etching techniques are used to form the contact holes through the layers. After forming the contact holes, a silica layer 252 is selectively formed on the surface of the epitaxial source / drain regions 232 exposed by the contact holes. The silica layer 252 can be formed by depositing a metal source layer to cover the exposed surfaces (including the exposed surfaces of the epitaxial source / drain regions 232) and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After forming the metal source layer, a rapid thermal annealing process is performed. During the rapid annealing process, a portion of the metal source layer located on the epitaxial source / drain region 232 reacts with silicon in the epitaxial source / drain region 232 to form a silicate layer 252. The unreacted portion of the metal source layer is then removed. In some embodiments, the silicate layer 252 may include one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0061] After forming the silicate layer 252, a conductive material is deposited to fill the contact holes and form the source / drain contact components 254. Optionally, a barrier layer (not shown) may be formed in the contact holes before forming the source / drain contact components 254. In some embodiments, the conductive material layer of the gate contact may be formed by CVD, PVD, electroplating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact components 254 includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove a portion of the conductive material layer on the top surface of the ILD layer 238.

[0062] This disclosure provides a solution for improving hole mobility without sacrificing electron mobility during miniaturization. According to this disclosure, Figures 11A to 11E illustrate the gate region of a GAA device. According to this disclosure, Figure 11A is a schematic enlarged view of an NFET device. According to this disclosure, Figure 11B is a schematic enlarged view of a PFET device. Figure 11C is an enlarged view of the NFET device in Figure 11A, showing details around a channel. Figure 11D is a schematic cross-sectional view of Figure 11C along line DD. As shown in Figures 11A and 11B, the channel regions of the NFET and PFET devices have similar channel compositions. In some embodiments, both the NFET and PFET devices have a semiconductor layer 208 serving as a nanosheet channel. The semiconductor layer 208 (or channel) is formed of epitaxial silicon and has a horizontal channel surface 208xys on the (551) plane along the <110> direction and a channel end face 208yzs on the (110) plane along the <110> direction. In some embodiments, the source / drain region 232n of the NFET device is formed of SiP. In some embodiments, the source / drain region 232p of the PFET device is formed of SiGe.

[0063] In some embodiments, the central portion 208c of the semiconductor layer 208 (or channel layer) and the end portion 208e of the semiconductor layer 208 have different surface roughnesses. The central portion 208c is smoother or has a lower roughness than the end portion 208e.

[0064] Figure 11E is an XRD pattern (X-ray diffraction pattern) of the interface in region 11E of Figure 11C. The XRD pattern shows that the (551) silicon surface at 208xys of the horizontal channel surface can be clearly observed.

[0065] Figure 12A is a graph showing the electron mobility along the channel height of the (110) channel surface and the (100) surface channel. As shown in Figure 12A, the electron carriers on the (110) channel surface are farther away from the interface, such as the interface between semiconductor layer 208 and interface layer 243, than the electron carriers on the (100) channel surface. In other words, the electron carriers on the (110) channel surface are more concentrated at the center of the channel layer or semiconductor layer 208 or channel sheet than the electron carriers on the (100) channel surface. Compared to the (100) channel surface, the (110) channel surface is less sensitive to the surrounding gate stack (i.e., RCS factor) but more sensitive to surface roughness (i.e., SRS factor).

[0066] According to an embodiment of this disclosure, Figure 12B shows that after roughening, the (551) / <110> channel surface has a similar electron mobility to the (100) channel surface. In Figure 12B, curves 301, 302, and 303 represent the electron mobilities of the (110) channel surface, the (551) channel surface, and the (100) channel surface, respectively. The (100) channel surface has the highest electron mobility. Curve group 304 shows the SRS factor of electron mobility for the (100), (551), and (110) surfaces. Curve group 305 shows the RCS factor of electron mobility for the (100), (551), and (110) surfaces. According to an embodiment of this disclosure, curve 306 shows the electron mobility of the (551) surface after roughening. Curve 306 shows that the (551) / <110> channel surface has a similar electron mobility to the (100) channel surface.

[0067] According to an embodiment of this disclosure, Figure 13 is a schematic cross-sectional view of semiconductor device 200a. Semiconductor device 200a is similar to semiconductor device 200 except that it includes a portion of the bottom isolation layer 230a. Therefore, the bottom of the epitaxial source / drain region 232a grows from a bottom epitaxial layer 229 having a (551) surface. Therefore, a portion of the bottom surface 232abs of the epitaxial source / drain region 232a has a (551) surface.

[0068] According to an embodiment of this disclosure, Figure 14 is a schematic cross-sectional view of semiconductor device 200b. Semiconductor device 200b is similar to semiconductor devices 200 and 200a, except that it does not include any bottom isolation layer. Therefore, the epitaxial source / drain region 232b also grows from the bottom epitaxial layer 229 having a (551) surface. Thus, the bottom surface 232bbs of the epitaxial source / drain region 232b has a (551) surface.

[0069] The various embodiments or examples described in this disclosure provide several advantages over the prior art. By selecting a (551) / <110> substrate as the starting material, the embodiments of this disclosure enable highly miniaturized channels while having improved hole mobility without sacrificing electron mobility.

[0070] This disclosure provides a semiconductor device in some embodiments, including: a first source / drain region; a second source / drain region; two or more semiconductor layers disposed between the first source / drain region and the second source / drain region and coupled to the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure wrapping around the two or more semiconductor layers.

[0071] In some embodiments, two or more semiconductor layers each have a <110> crystal orientation that extends along a direction from the first source / drain region to the second source / drain region.

[0072] In some embodiments, each of the two or more semiconductor layers includes: a top surface; a bottom surface opposite to the top surface; and a vertical surface connecting the top surface to the bottom surface, wherein the vertical surface extends from a first source / drain region to a second source / drain region, wherein the top surface has a (551) surface orientation and the vertical surface has a (110) surface orientation.

[0073] In some embodiments, the distance between the top surface and the bottom surface is about 2 nanometers to 10 nanometers.

[0074] In some embodiments, each of the two or more semiconductor layers further includes: a first end face connecting the top surface and the bottom surface, wherein the first end face contacts the sidewall of the first source / drain region and the first end face has a (110) surface orientation.

[0075] In some embodiments, two or more semiconductor layers each include a first end face adjacent to a first end face; and a central portion that contacts a gate structure, the first end face having a first surface roughness, and the central portion having a second surface roughness different from the first surface roughness.

[0076] In some embodiments, the first surface roughness is greater than the second surface roughness.

[0077] Other embodiments of this disclosure provide a semiconductor device, including: two or more semiconductor layers, each of the two or more semiconductor layers including a first end, a second end, and a central portion connecting the first end and the second end, the first end having a first surface roughness, and the central portion having a second surface roughness different from the first surface roughness; a gate structure surrounding the central portion of the two or more semiconductor layers; a first source / drain region disposed on the first end of the two or more semiconductor layers; and a second source / drain region disposed on the second end of the two or more semiconductor layers.

[0078] In some other embodiments, the first surface roughness is greater than the second surface roughness.

[0079] In other embodiments, two or more semiconductor layers each include a horizontal channel surface having a (551) surface orientation.

[0080] In some other embodiments, the horizontal channel surface has a <110> crystal orientation that extends from the first source / drain region to the second source / drain region.

[0081] In some other embodiments, two or more semiconductor layers each include a vertical channel surface having a (110) surface orientation.

[0082] In some other embodiments, the vertical channel surface has a third surface roughness that is greater than the second surface roughness.

[0083] In some other embodiments, the first source / drain region has a bottom surface formed in the (551) surface direction.

[0084] Some embodiments of this disclosure provide a method of forming a semiconductor device, comprising: selecting a substrate having a top surface having a (551) surface orientation; epitaxially growing a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack includes two or more first semiconductor layers and two or more second semiconductor layers, the two or more first semiconductor layers and the two or more second semiconductor layers being stacked alternately; forming a fin structure from the semiconductor stack and the substrate; forming a sacrificial gate structure on the fin structure; etching back the fin structure along the sidewalls of the sacrificial gate structure; epitaxially growing a source / drain region from the two or more second semiconductor layers; depositing a contact etch stop layer (CESL) on the source / drain region; depositing an interlayer dielectric (ILD) layer on the CESL; removing the sacrificial gate structure to expose the fin structure; removing the two or more first semiconductor layers; and forming an alternative gate structure around the two or more second semiconductor layers.

[0085] In some other embodiments, forming the fin structure includes forming the fin structure along the <110> crystal direction.

[0086] In some other embodiments, it further includes performing a roughening process to reduce the surface roughness of the second semiconductor layer before forming the replacement gate structure.

[0087] In some other embodiments, performing the roughening process includes processing two or more second semiconductor layers with plasma.

[0088] In some other embodiments, the plasma contains H radicals.

[0089] In some other embodiments, the epitaxial growth source / drain region includes a bottom surface grown from the (551) surface of the substrate.

[0090] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0006] The various aspects of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the cells may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure. According to some embodiments of this disclosure, Figure 1 is a flowchart of a method for manufacturing a semiconductor device. According to some embodiments of this disclosure, Figures 2, 2A, 3, 4, 4A, and 5 to 10 schematically illustrate various stages in the manufacturing of a semiconductor device. According to some embodiments of this disclosure, Figures 11A, 11B, 11C, 11D, and 11E illustrate the gate region of a GAA device. According to some embodiments of this disclosure, Figures 12A and 12B illustrate the electron mobility of a GAA device. According to some embodiments of this disclosure, Figure 13 schematically illustrates a semiconductor device. According to some embodiments of this disclosure, Figure 14 schematically illustrates a semiconductor device.

Claims

1. A semiconductor device, comprising: First source / drain region; A second source / drain region; Two or more semiconductor layers are disposed between the first source / drain region and the second source / drain region and coupled to the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure surrounds the two or more semiconductor layers.

2. The semiconductor device as claimed in claim 1, wherein each of the two or more semiconductor layers has a <110> crystal orientation extending along a direction from the first source / drain region to the second source / drain region.

3. The semiconductor device as claimed in claim 2, wherein each of the two or more semiconductor layers comprises: A top surface; A bottom surface, relative to the top surface; And a vertical surface connecting the top surface to the bottom surface, wherein the vertical surface extends from the first source / drain region to the second source / drain region, wherein the top surface has a (551) surface direction and the vertical surface has a (110) surface direction.

4. The semiconductor device as claimed in claim 3, wherein the distance between the top surface and the bottom surface is about 2 nanometers to 10 nanometers.

5. The semiconductor device as claimed in claim 3, wherein each of the two or more semiconductor layers further comprises: A first end face connects the top surface and the bottom surface, wherein the first end face contacts a sidewall of the first source / drain region, and the first end face has a (110) surface orientation.

6. The semiconductor device as claimed in claim 5, wherein each of the two or more semiconductor layers includes a first end face adjacent to the first end face; and a central portion contacting the gate structure, the first end face having a first surface roughness, and the central portion having a second surface roughness different from the first surface roughness.

7. The semiconductor device as claimed in claim 6, wherein the first surface roughness is greater than the second surface roughness.

8. A semiconductor device, comprising: Two or more semiconductor layers, each of the two or more semiconductor layers including a first end, a second end, and a central portion connecting the first end and the second end, the first end having a first surface roughness, and the central portion having a second surface roughness different from the first surface roughness; a gate structure surrounding the central portion of the two or more semiconductor layers; a first source / drain region disposed on the first end of the two or more semiconductor layers; and a second source / drain region disposed on the second end of the two or more semiconductor layers.

9. The semiconductor device as claimed in claim 8, wherein each of the two or more semiconductor layers includes a horizontal channel surface having a (551) surface orientation.

10. The semiconductor device as claimed in claim 9, wherein the horizontal channel surface has a <110> crystal orientation extending from the first source / drain region to the second source / drain region.

11. The semiconductor device as claimed in claim 10, wherein each of the two or more semiconductor layers includes a vertical channel surface having a (110) surface orientation.

12. The semiconductor device as claimed in claim 9, wherein the first source / drain region has a bottom surface formed in a (551) surface direction.

13. A method of forming a semiconductor device, comprising: Select a substrate having a top surface having a (551) surface orientation; epitaxially grow a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack includes two or more first semiconductor layers and two or more second semiconductor layers, the two or more first semiconductor layers and the two or more second semiconductor layers being stacked alternately; form a fin structure from the semiconductor stack and the substrate; form a sacrificial gate structure on the fin structure; etch back the fin structure along the sidewalls of the sacrificial gate structure; epitaxially grow a plurality of source / drain regions from the two or more second semiconductor layers; deposit a contact etch stop layer (CESL) on the source / drain regions; deposit an inter-dielectric layer (ILD) on the CESL; remove the sacrificial gate structure to expose the fin structure; remove the two or more first semiconductor layers; and form a replacement gate structure around the two or more second semiconductor layers.

14. The method of forming a semiconductor device as described in claim 13, wherein forming the fin structure comprises: The fin structure is formed along a <110> crystallization direction.

15. The method of forming a semiconductor device as described in claim 14, further comprising: Before forming the replacement gate structure, a roughening process is performed to reduce the surface roughness of the second semiconductor layers.

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