Semiconductor memory devices and methods for manufacturing semiconductor memory devices

Abstract

A semiconductor memory device according to one embodiment of the present invention includes a first wafer and a second wafer bonded to the first wafer. The second wafer includes a stacked body, a pillar, a semiconductor layer, a first wiring, and a second wiring. The pillar includes a first end portion extending at least to a first end of the stacked body. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion disposed along the first end of the stacked body and a second portion covering the first end portion of the pillar. The first and second semiconductor portions include impurities forming p-type semiconductors. The third semiconductor portion includes impurities forming n-type semiconductors. A first gate electrode layer includes a portion that overlaps with the first semiconductor portion when viewed from a first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Prior Technology

[0002] NAND flash memory with memory cells arranged in a three-dimensional configuration is known (for example, see Japanese Patent Application Publication No. 2022-41054). Summary of the Invention

[0003] In one embodiment, a semiconductor memory device includes a first wafer and a second wafer. The second wafer is bonded to the first wafer. The second wafer has a stacked body, a pillar, a semiconductor layer, a first wiring, and a second wiring. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are stacked alternately layer by layer in a first direction. The stacked body has a first end, which is the opposite side of the first wafer, i.e., the first side end in the first direction. The pillar extends in the stacked body in the first direction. The pillar has a first end portion that reaches at least the first end of the stacked body. The semiconductor layer has a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion disposed along the first end of the stacked body and a second portion covering the first end portion of the pillar. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first and second semiconductor portions contain impurities forming p-type semiconductors. The third semiconductor portion contains impurities forming n-type semiconductors. The first gate electrode layer among the plurality of gate electrode layers closest to the first end of the laminate includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. Simple Explanation of the Diagram

[0004] Figure 1 is a block diagram showing a portion of the semiconductor memory device according to the first embodiment. Figure 2 is a diagram showing the equivalent circuit of a portion of the memory cell array of the first embodiment. Figure 3 is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment. Figure 4 is an enlarged cross-sectional view of the area enclosed by line F4 of the semiconductor memory device shown in Figure 3. Figure 5 is a cross-sectional view of the semiconductor memory device shown in Figure 4 along line F5-F5. Figure 6 is a cross-sectional view of the semiconductor memory device shown in Figure 3 along line F6-F6. Figure 7 is a cross-sectional view illustrating the semiconductor layer of the first embodiment. Figure 8 is a cross-sectional view of the structure shown in Figure 7 along line F8-F8. Figure 9 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 10 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 11 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 12 is a diagram illustrating the readout operation of the semiconductor memory device according to the first embodiment. Figure 13 is a cross-sectional view illustrating the readout operation of the semiconductor memory device according to the first embodiment. Figure 14 is a diagram illustrating the writing operation of the semiconductor memory device according to the first embodiment. Figure 15 is a diagram illustrating the erasure operation of the semiconductor memory device according to the first embodiment. Figure 16 is a cross-sectional view illustrating the erasure operation of the semiconductor memory device according to the first embodiment. Figure 17 is a cross-sectional view of a portion of the semiconductor memory device according to the second embodiment. Figure 18 is a cross-sectional view of a portion of the semiconductor memory device according to the third embodiment. Figure 19 is a cross-sectional view of the structure shown in Figure 18 along line F19-F19. Figure 20 is a top view showing a portion of the semiconductor memory device according to the fourth embodiment. Figure 21 is a top view showing a portion of the semiconductor memory device according to the fifth embodiment. Implementation

[0005] Hereinafter, with reference to the drawings, the semiconductor memory device according to the embodiments and the method for manufacturing the semiconductor memory device will be described. In the following description, components having the same or similar functions are marked with the same symbols. Moreover, repeated descriptions of these components may be omitted at times. In the following description, reference symbols ending with numbers or letters for distinction may also be omitted if there is no need to distinguish them.

[0006] In this application, the terms are defined as follows. "Parallel," "orthogonal," or "identical" may include "generally parallel," "generally orthogonal," or "generally identical," respectively. "Connection" is not limited to mechanical connections and may include electrical connections. That is, "connection" is not limited to the direct connection of multiple elements and may include the connection of multiple elements with other elements interspersed in between. "Overlapping" is not limited to the contact of multiple elements and may include the separation of multiple elements (where the projections of multiple elements overlap when viewed from a certain direction).

[0007] The definitions of +X, -X, +Y, -Y, +Z, and -Z directions are as follows: +X direction is the extension direction of the character line WL (see Figure 3). -X direction is the opposite direction of +X direction. When there is no need to distinguish between +X and -X directions, it is simply referred to as the X direction. +Y direction is the direction that intersects (e.g., orthogonal) the X direction. +Y direction is the extension direction of the bit line BL (see Figure 6). -Y direction is the opposite direction of +Y direction. When there is no need to distinguish between +Y and -Y directions, it is simply referred to as the Y direction. +Z direction is the direction that intersects (e.g., orthogonal) both the X and Y directions. +Z direction is the direction from the bit line BL towards the stack 40 (see Figure 3). -Z direction is the opposite direction of +Z direction. When there is no need to distinguish between +Z and -Z directions, it is simply referred to as the Z direction. In this application, the +Z direction side is sometimes referred to as "upper," and the -Z direction side as "lower." However, these expressions are for illustrative purposes only and are not intended to specify the direction of gravity. The Z direction is an example of the "first direction." The X direction is an example of the "second direction." Furthermore, in the diagrams described below, sometimes illustrations of components unrelated to the explanation are omitted.

[0008] (First Embodiment) <1. Composition of Semiconductor Memory Devices> Figure 1 is a block diagram showing a portion of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device. The semiconductor memory device 1 is a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device. The semiconductor memory device 1 serves as the memory space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a column decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 11 contains a plurality of blocks BLK0 to BLK(k-1) (where k is an integer greater than or equal to 1). A block BLK is a collection of memory cell transistors. Block BLK is used as the unit for data erasure. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0010] Instruction register 12 stores the instruction CMD received by semiconductor memory device 1 from the host device. Address register 13 stores the address information ADD received by semiconductor memory device 1 from the host device. The address information ADD is used for the selection of block BLK, word lines, and bit lines. Control circuit 14 controls various operations of semiconductor memory device 1. For example, based on the instruction CMD stored in instruction register 12, control circuit 14 performs data write operations, read operations, or erase operations.

[0011] The driver module 15 includes a voltage generation circuit that generates the voltages required for various operations of the semiconductor memory device 1. The column decoder module 16 transmits the voltage applied to the signal lines corresponding to the select word lines to the select word lines. During the write operation, the sense amplifier module 17 applies the desired voltage to each bit line. During the read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line. In this operation, the sense amplifier module 17 transmits the determination result as read data DAT to the host device.

[0012] <2. Electrical Configuration of Memory Cell Array> Figure 2 is a diagram showing the equivalent circuit of a portion of the memory cell array 11. Figure 2 shows one block BLK contained in the memory cell array 11. The block BLK contains a plurality of strings STR (e.g., 5 strings STR0~STR4).

[0013] Each STR string contains a plurality of NAND strings NS that are associated with bit lines BL0~BLm (m is an integer greater than or equal to 1). Each NAND string NS contains a plurality of memory cell transistors MT0~MTn (n is an integer greater than or equal to 1), one or more drain-side select transistors STD and one or more source-side select transistors STS.

[0014] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is stored in the charge storage section according to the voltage applied to the control gate via the word line WL, thus non-volatilely preserving data.

[0015] The drain-side select transistor STD has its drain connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the memory cell transistors MT0~MTn connected in series. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0~SGD4. The drain-side select transistor STD is electrically connected to the column decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.

[0016] The drain of the source-side select transistor (STS) is connected to the other end of the series-connected memory cell transistors MT0~MTn. The source of the source-side select transistor (STS) is connected to the source line SL. The control gate of the source-side select transistor (STS) is connected to the source-side select gate line SGS. When a specified voltage is applied to the source-side select gate line SGS, the source-side select transistor (STS) connects the NAND string NS to the source line SL.

[0017] Within the same BLK, the control gates of memory cell transistors MT0~MTn are all connected to their respective word lines WL0~WLn. Within the same STR string, the control gates of drain-side select transistors STD are all connected to their corresponding drain-side select gate line SGD. The control gates of source-side select transistors STS are all connected to their respective source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by multiple NAND strings NS that are assigned the same row address within the STR strings.

[0018] <3. Structure of Semiconductor Memory Devices> Next, the structure of semiconductor memory device 1 will be explained. Figure 3 is a cross-sectional view of a portion of a semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first wafer 2 and a second wafer 3. The second wafer 3 is a wafer bonded to the first wafer 2.

[0019] <3.1 First Chip> The first chip 2 is a circuit chip that includes peripheral circuitry. The first chip 2 includes, for example, a semiconductor substrate 21, peripheral circuitry 22, insulating portion 23, and a plurality of solder pads 24.

[0020] The semiconductor substrate 21 is, for example, a substrate serving as the base of the first wafer 2. At least a portion of the semiconductor substrate 21 is plate-shaped along the X and Y directions. The semiconductor substrate 21 is, for example, formed of a semiconductor material such as silicon.

[0021] The peripheral circuitry 22 is used to enable the memory cell array 11 to function. The peripheral circuitry 22 includes a plurality of transistors 22a and a plurality of wirings 22b. The peripheral circuitry 22 includes one or more of the following: instruction register 12, address register 13, control circuitry 14, driver module 15, column decoder module 16, and sense amplifier module 17. An insulating portion 23 covers the peripheral circuitry 22. A plurality of solder pads 24 are disposed on the surface of the insulating portion 23. Each solder pad 24 is electrically connected to the peripheral circuitry 22.

[0022] <3.2 Second Chip> The second chip 3 is an array chip that includes a memory cell array 11. The second chip 3, for example, has a memory cell array 11, an insulating portion 31, a plurality of solder pads 32, and an insulating portion 33. Here, the insulating portion 31, the plurality of solder pads 32, and the insulating portion 33 will be described. The memory cell array 11 will be described below.

[0023] An insulating portion 31 covers the memory cell array 11 from the -Z direction side. A plurality of solder pads 32 are disposed on the surface of the insulating portion 31. Each solder pad 32 is electrically connected to wiring (e.g., wiring 71 or wiring 72) included in the wiring portion 70 of the memory cell array 11. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the plurality of solder pads 24 of the first chip 2 and the plurality of solder pads 32 of the second chip 3 together. An insulating portion 33 covers the memory cell array 11 from the +Z direction side.

[0024] <4. Memory Cell Array> Next, the memory cell array 11 will be explained. As shown in Figure 3, the memory cell array 11 includes an array region AR and a wiring region FR. In the array region AR, a plurality of memory pillars MH are provided. The array region AR is the area capable of storing data. In the wiring region FR, a plurality of contacts CC are provided. The wiring region FR is the area that connects the plurality of conductive layers 41 to the wiring portion 70. The wiring region FR is, for example, located on both sides of the array region AR in the X direction. No memory pillars MH are provided in the wiring region FR. In the wiring region FR, for example, the ends of the plurality of conductive layers 41 are arranged in a stepped manner. Alternatively, the wiring region FR may also have through contacts penetrating the conductive layers 41 as contacts CC. Furthermore, in the wiring region FR, a support HR is provided to support the plurality of insulating layers 42 in the following replacement step.

[0025] As shown in Figure 3, the memory cell array 11 includes, for example, a stacked layer 40, a semiconductor layer 50, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for memory pillars, a plurality of contacts VY for memory pillars, contacts CC for conductive layers, a wiring section 70, a support body HR, and a plurality of break sections 80 (see Figure 6).

[0026] <4.1 Laminated Body> First, let’s explain the laminate 40. Figure 4 is an enlarged cross-sectional view of the area enclosed by line F4 of the semiconductor memory device 1 shown in Figure 3. The laminate 40 has a first end 40e1. The first end 40e1 is the end opposite to the first wafer 2, i.e., the end in the +Z direction. For example, the first end 40e1 is the end opposite to the semiconductor substrate 21, i.e., the end in the +Z direction. Furthermore, the laminate 40 includes, for example, a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating layer 43. The plurality of conductive layers 41 and the plurality of insulating layers 42 are deposited alternately layer by layer in the Z direction.

[0027] The conductive layer 41 extends along both the X and Y directions. Each conductive layer 41 is formed, for example, from a conductive material such as tungsten or molybdenum. The conductive layer 41 is an example of a "gate electrode layer".

[0028] Of the plurality of conductive layers 41, one or more (e.g., a plurality of) of the lower conductive layers 41 function as drain-side selected gate lines (SGDs). The drain-side selected gate lines (SGDs) are provided commonly relative to the plurality of memory pillars (MHs) arranged in the X or Y direction. The intersection of the drain-side selected gate lines (SGDs) with the channel layers 62 (described below) of each memory pillar (MH) functions as the drain-side selected transistor (STD).

[0029] Of the plurality of conductive layers 41, one or more (e.g., a plurality of) conductive layers 41 located at the top function as source-side gate select lines (SGS). The source-side gate select lines (SGS) are disposed commonly relative to the plurality of memory pillars (MH) arranged in the X or Y direction. The intersection of the source-side gate select lines (SGS) with the channel layers 62 of each memory pillar (MH) functions as the aforementioned source-side select transistor (STS).

[0030] Of the plurality of conductive layers 41, at least a portion of the remaining conductive layers 41 disposed between the conductive layers 41 that function as drain-side select gate line (SGD) and source-side select gate line (SGS) functions as word lines WL. The word lines WL are conventionally disposed relative to the plurality of memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection of the word lines WL with the channel layers 62 of each memory pillar MH functions as memory cell transistors MT. The memory cell transistors MT will be described in detail below.

[0031] In this embodiment, the plurality of conductive layers 41 include conductive layer 41A, conductive layer 41B and conductive layer 41C.

[0032] Conductive layer 41A is the uppermost conductive layer 41 among a plurality of conductive layers 41. Conductive layer 41A is the conductive layer 41 closest to the first end 40e1 of the laminate 40 among a plurality of conductive layers 41. Conductive layer 41A is an example of a "first gate electrode layer".

[0033] Conductive layer 41B is one of a plurality of conductive layers 41. Conductive layer 41B may function as the uppermost word line WL among a plurality of word lines WL. Conductive layer 41B may also be the conductive layer 41 closest to the source-side select gate line SGS among a plurality of word lines WL. Furthermore, conductive layer 41B may also function as the drain-side select gate line SGD, or it may function as the source-side select gate line SGS. Conductive layer 41B is an example of a "second gate electrode layer".

[0034] Conductive layer 41C is a conductive layer 41 adjacent to conductive layer 41B in the Z direction. Conductive layer 41C is, for example, the next conductive layer 41 located below conductive layer 41B. Conductive layer 41C may function as a word line WL. Furthermore, conductive layer 41C may also function as a drain-side selected gate line SGD, or as a source-side selected gate line SGS. Conductive layer 41C is an example of a "third gate electrode layer".

[0035] An insulating layer 42 is disposed between two adjacent conductive layers 41 in the Z direction. The insulating layer 42 is an interlayer insulating film that insulates the two conductive layers 41. The insulating layer 42 extends along both the X and Y directions. The insulating layer 42 is, for example, formed of a film containing silicon and oxygen. The insulating layer 42 is formed by supplying a raw material gas, causing a chemical reaction on one side and deposition on the other. The insulating layer 42 is, for example, formed by chemical vapor deposition (CVD). The insulating layer 42 contains carbon and other substances mixed in due to the chemical reaction during the film formation process.

[0036] The plurality of insulating layers 42 includes an insulating layer 42A. The insulating layer 42A is disposed between the conductive layer 41B (the second gate electrode layer) and the conductive layer 41C (the third gate electrode layer). The insulating layer 42A is an interlayer insulating film that insulates the two conductive layers 41B and 41C. The insulating layer 42A is an example of a "first insulating layer".

[0037] The insulating layer 43 is disposed above the conductive layer 41A (first gate electrode layer). The insulating layer 43 is positioned between the conductive layer 41A (first gate electrode layer) and the first end 40e1 of the laminate 40. The +Z direction side end of the insulating layer 43 forms the first end 40e1 of the laminate 40. The insulating layer 43 extends along both the X and Y directions. The insulating layer 42 is, for example, formed of a film containing silicon and oxygen.

[0038] Insulating layer 43 is, for example, a thermally oxidized film. Insulating layer 43 is formed by heating a silicon layer in an oxygen environment, causing partial or complete oxidation of the silicon layer. Compared to insulating layer 42, insulating layer 43 has a lower content of materials other than silicon and oxygen (e.g., carbon). The composition (e.g., film type) of insulating layer 43 differs from that of insulating layer 42. Insulating layer 43 is a film with higher withstand voltage than insulating layer 42. Insulating layer 43 is an example of a "second insulating layer".

[0039] In this embodiment, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness (e.g., minimum thickness) T1 of the insulating layer 42 in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half of the thickness (e.g., minimum thickness) T1 of the insulating layer 42 in the Z direction. In this embodiment, "the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction" corresponds to the distance (e.g., shortest distance) in the Z direction between the conductive layer 41A and the first semiconductor portion 51 described below.

[0040] In another viewpoint, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness T3 of the conductive layer 41A in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half of the thickness T3 of the conductive layer 41A in the Z direction. In yet another viewpoint, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness T4 of the conductive layer 41B in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half of the thickness T4 of the conductive layer 41B in the Z direction.

[0041] <4.2 Semiconductor Layer (Source Line)> A semiconductor layer 50 is disposed on the first end 40e1 of the laminate 40. The semiconductor layer 50 extends in the X and Y directions. The semiconductor layer 50 is formed of a silicon-containing material. The semiconductor layer 50 functions as the source line SL. The semiconductor layer 50 will be described in detail below.

[0042] <4.3 Memory Columns> A plurality of memory columns MH are arranged in the X and Y directions (see Figure 3). Each memory column MH extends in the Z direction within the laminate 40, penetrating the laminate 40. The memory column MH is an example of a "column".

[0043] Figure 5 is a cross-sectional view of the semiconductor memory device 1 shown in Figure 4 along line F5-F5. The memory column MH has, for example, a memory film (multilayer film) 61, a channel layer 62, an insulating portion 63, a hole portion (air gap) 64, and a cap portion 65 (see Figure 4).

[0044] A memory film 61 is disposed on the outer periphery of the channel layer 62. The memory film 61 is located between the plurality of conductive layers 41 and the channel layer 62. The memory film 61 includes, for example, a block insulating film 61a, a charge trapping film 61b, and a tunnel insulating film 61c.

[0045] A block insulating film 61a is disposed between a plurality of conductive layers 41 and a charge trapping film 61b. The block insulating film 61a is an insulating film that suppresses reverse tunneling. Reverse tunneling refers to the phenomenon of charge returning from the character line WL to the charge trapping film 61b. The block insulating film 61a is formed in a ring shape and extends in the Z direction. The block insulating film 61a is disposed, for example, across the entire Z-direction length of the memory column MH except for the first end MHe1 of the memory column MH described below. The block insulating film 61a is, for example, a laminated structure film composed of a plurality of insulating films including silicon and oxygen films, or films including metal and oxygen films. An example of a film including metal and oxygen is aluminum oxide. The block insulating film 61a may also contain high dielectric constant materials (high k materials) such as silicon nitride or hafnium oxide.

[0046] A charge trapping film 61b is located between the block insulating film 61a and the tunnel insulating film 61c. The charge trapping film 61b is formed in a ring shape and extends in the Z direction. For example, the charge trapping film 61b is disposed across the entire Z-direction length of the memory column MH, excluding the first end MHe1 of the memory column MH. The charge trapping film 61b is a functional film that has many crystal defects (trapping energy levels) and can trap charge at the crystal defects. The charge trapping film 61b is formed, for example, from a film containing silicon and nitrogen. The portion of the charge trapping film 61b adjacent to each character line WL is an example of a "charge storage section" that can store information by storing charge.

[0047] A tunnel insulating film 61c is disposed between the channel layer 62 and the charge trapping film 61b. The tunnel insulating film 61c is, for example, annular along the outer peripheral surface of the channel layer 62 and extends along the channel layer 62 in the Z direction. The tunnel insulating film 61c, for example, spans the entire Z-direction length of the memory pillar MH, except for the first end MHe1 of the memory pillar MH. The tunnel insulating film 61c acts as a potential barrier between the channel layer 62 and the charge trapping film 61b. The tunnel insulating film 61c is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0048] A channel layer 62 is disposed inside the memory film 61. The channel layer 62 is formed in a ring shape. The channel layer 62 extends in the Z direction. The channel layer 62 is disposed, for example, spanning the entire length of the memory pillar MH in the Z direction. The channel layer 62 is formed of a semiconductor material such as polysilicon. The channel layer 62 may also be doped with impurities. When a voltage is applied to the word line WL, the channel layer 62 forms a channel to electrically connect the bit line BL and the source line SL.

[0049] Therefore, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the memory column MH, a block insulating film 61a, a charge trapping film 61b, a tunnel insulating film 61c, and a channel layer 62. Furthermore, regarding the charge storage section, the memory film 61 may also have a floating gate type charge storage section (floating gate electrode) instead of a charge trapping film 61b. The floating gate electrode, for example, is formed of polycrystalline silicon containing impurities.

[0050] An insulating portion 63 is disposed inside the channel layer 62. At least a portion of the interior of the channel layer 62 is embedded in the insulating portion 63. The insulating portion 63 is formed of a film comprising silicon and oxygen. In this embodiment, the insulating portion 63 is formed in a ring shape along the inner circumferential surface of the channel layer 62, such that a cavity (air gap) 64 is formed inside. Alternatively, the cavity 64 may not be present. The insulating portion 63 extends in the Z direction. For example, the insulating portion 63 is disposed across most of the Z direction of the memory column MH, except for the lower end of the memory column MH (see Figure 4).

[0051] The following description, referring back to Figure 4, focuses on the cover portion 65. The cover portion 65 is located below the insulating portion 63. The cover portion 65 is a semiconductor portion formed from a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 65 may also be doped with impurities. The cover portion 65 is disposed on the inner periphery of the lower end of the memory film 61, forming an integral part with the channel layer 62. The cover portion 65 and the lower end of the channel layer 62 together form the lower end of the memory pillar MH. The contact CH is connected to the cover portion 65 from the -Z direction side.

[0052] Next, the first end MBhe1 of the memory column MH will be described. In this embodiment, the first end MBhe1 of the memory column MH protrudes from the first end 40e1 of the laminate 40 towards the +Z direction. The first end MBhe1 of the memory column MH is in contact with the semiconductor layer 50. At the first end MBhe1 of the memory column MH, there is no memory film 61, and the channel layer 62 is exposed outside the memory column MH. The channel layer 62 of the memory column MH is in contact with the semiconductor layer 50 at a position on the first end MBhe1 that is closer to the +Z direction than the first end 40e1 of the laminate 40. The first end MBhe1 of the memory column MH is an example of "first end". Furthermore, the first end MBhe1 of the memory column MH does not necessarily need to protrude from the first end 40e1 of the laminate 40 towards the +Z direction. The first end MBhe1 of the memory column MH only needs to reach at least the first end 40e1 of the laminate 40. For example, the first end MHe1 of the memory column MH can also be connected to the semiconductor layer 50 at the same position as the first end 40e1 of the laminate 40.

[0053] <4.4-bit line> Next, returning to Figure 3, we will explain the bit lines BL. The bit lines BL are used for routing the memory cylinder MH selected from a plurality of memory cylinders MH. The plurality of bit lines BL are positioned on the lower side (-Z direction side) relative to the stack 40. The plurality of bit lines BL are spaced apart in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends beneath its corresponding plurality of memory cylinders MH.

[0054] Each word line BL is connected to the channel layer 62 of the memory column MH via contact VY and contact CH. Thus, by combining word lines WL and bit lines BL, memory cell transistors MT can be arbitrarily selected from a plurality of memory cell transistors MT arranged in a three-dimensional configuration.

[0055] <4.5 Conductive layer for contacts> As shown in Figure 3, the contact CC is an electrical connection portion that electrically connects the conductive layer 41 to the wiring 72 (hereinafter) included in the wiring portion 70. A plurality of contacts CC are configured, for example, corresponding to the wiring area FR of the memory cell array 11. The plurality of contacts CC extend in the Z direction and are respectively connected to different conductive layers 41.

[0056] <4.6 Cabling Section> Next, the wiring section 70 will be described. The wiring section 70 is disposed, for example, between the laminate 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, a plurality of wirings 72, a plurality of wirings 75 (only one is shown in FIG. 6), and a plurality of wirings 76 (only one is shown in FIG. 6). Wirings 75 and wirings 76 will be described below.

[0057] Wiring 71 is an electrical connection portion that electrically connects the bit line BL to the pad 32. A plurality of wirings 71 are arranged below, for example, relative to a plurality of bit lines BL. Each wiring 71 extends, for example, in the X or Y direction. A through-hole V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0058] Wiring 72 is an electrical connection that electrically connects the conductive layer contact CC to the solder pad 32. Wiring 72 is electrically connected to the conductive layer 41 via the conductive layer contact CC. Wiring 72 is energized with voltage to select the conductive layer 41 (word line WL, drain-side gate select line SGD, or source-side gate select line SGS).

[0059] <4.7 Support> The support body HR is described below. The support body HR is disposed in the wiring area FR. The support body HR penetrates the laminate 40 in the wiring area FR along the Z direction. The support body HR is, for example, a columnar body having the same structure as the memory column MH. Alternatively, the support body HR may be formed of an insulating portion. The support body HR supports a plurality of insulating layers 42 in the following replacement steps.

[0060] <5.Breaking part> Next, the section 80 will be explained. Figure 6 is a cross-sectional view of the semiconductor memory device 1 shown in Figure 3 along line F6-F6. In this embodiment, a plurality of break portions 80 are provided on the laminate 40. The plurality of break portions 80 are arranged separately in the Y direction. The plurality of break portions 80 extend in the laminate 40 in the Z direction, and break one or more conductive layers 41, including the bottommost layer, in the Y direction. The plurality of break portions 80 include, for example, a plurality of break portions ST and a plurality of break portions SHE.

[0061] <5.1 Breaking part ST> The segment ST is a wall portion that divides the laminate 40 in the Y direction. A plurality of segment STs are arranged separately in the Y direction. The segment STs extend in the Z direction, penetrating the laminate 40, and also extend in the X direction. That is, the segment STs are wall portions along both the Z and X directions. The segment STs divide all conductive layers 41 contained in the laminate 40 in the Y direction. The segment STs, for example, include insulating portions STa and conductive portions STb.

[0062] The insulating portion STa extends in the Z direction and penetrates the laminate 40. The insulating portion STa divides the plurality of conductive layers 41 contained in the laminate 40 in the Y direction. The insulating portion STa is formed, for example, from a film containing silicon and oxygen.

[0063] A conductive portion STb is disposed inside an insulating portion STa. The conductive portion STb extends in the Z direction and penetrates the laminate 40. The upper end of the conductive portion STb is connected to the semiconductor layer 50 (source line SL). The conductive portion STb is formed of a conductive material such as tungsten or molybdenum. The conductive portion STb can also function as an electrical connection portion connecting the semiconductor layer 50 (source line SL) to wiring within the memory cell array 11.

[0064] Furthermore, the break section ST may be formed solely from either the insulating section STa or the conductive section STb. For example, the break section ST may be formed solely from an insulator or solely from a conductor.

[0065] <5.2 Breaking part SHE> The segmented portion SHE is a shallower segment in the Z direction than the segmented portion ST, and it is a wall portion that segments the lower end of the laminate 40 in the Y direction. A plurality of segmented portions SHE are arranged separately in the Y direction. In this embodiment, there are a plurality of (e.g., 4) segmented portions SHE between two adjacent segmented portions ST in the Y direction. The segmented portion SHE is provided at the lower end of the laminate 40, extends in the Z direction to the middle of the laminate 40, and extends in the X direction. That is, the segmented portion SHE is a wall portion along both the Z and X directions.

[0066] The interruption section SHE penetrates a portion of the plurality of conductive layers 41, including the lowest layer, and interrupts this portion of conductive layer 41 in the Y direction. For example, the interruption section SHE penetrates all conductive layers 41 that function as drain-side selected gate (SGD). On the other hand, the interruption section SHE does not reach the conductive layer 41 that functions as a word line (WL). The interruption section SHE only interrupts the conductive layer 41 that functions as a drain-side selected gate (SGD) in the Y direction. The interruption section SHE is formed, for example, from a film containing silicon and oxygen.

[0067] <6. Structure related to the semiconductor layer (source line)> Next, the structure related to semiconductor layer 50 will be explained. Figure 7 is a cross-sectional view illustrating the semiconductor layer 50. For ease of explanation, only two memory pillars MH are shown between two adjacent segments ST (ST1, ST2) in the Y direction in Figure 7. In reality, as shown in Figure 6, among the plurality of segments ST, there are a plurality of memory pillars MH between two adjacent segments ST (ST1, ST2) in the Y direction. Segment ST1 is an example of the "first segment". Segment ST2 is an example of the "second segment".

[0068] As shown in FIG7, the semiconductor layer 50 is disposed along the first end 40e1 of the laminate 40. In this embodiment, the semiconductor layer 50 is disposed on the first end 40e1 of the laminate 40. The semiconductor layer 50 includes, for example, a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53.

[0069] <6.1 Semiconductor Division 1> The first semiconductor portion 51 is the portion connected to the first end MBe1 of a plurality of memory cylinders MH. The first semiconductor portion 51 extends in the Y direction, for example, covering the first end MBe1 of the plurality of memory cylinders MH. In this embodiment, the first semiconductor portion 51 extends linearly in the X direction (see Figure 8). The first semiconductor portion 51 includes, for example, a first portion 51a and a plurality of second portions 51b.

[0070] The first portion 51a is disposed along the first end 40e1 of the laminate 40. For example, the first portion 51a is disposed on the first end 40e1 of the laminate 40. For example, the first portion 51a is in a layered form along the X and Y directions on the first end 40e1 of the laminate 40. The first portion 51a is disposed between a plurality of second portions 51b in the X and Y directions, connecting the plurality of second portions 51b. Furthermore, the end of the first portion 51a on the +Y direction side is connected to the second semiconductor portion 52 in the Y direction. The end of the first portion 51a on the -Y direction side is connected to the third semiconductor portion 53 in the Y direction.

[0071] When viewed from the Z direction, each of the plurality of second portions 51b corresponds one-to-one with a plurality of memory columns MH (see Figure 8). Each second portion 51b covers the first end MBhe1 of the memory column MH from the +Z direction side. In this embodiment, the first end MBhe1 of the plurality of memory columns MH protrudes from the first end 40e1 of the stack 40 towards the +Z direction side. In this embodiment, each second portion 51b bulges from the first portion 51a towards the +Z direction side and covers the first end MBhe1 of the memory column MH from the +Z direction side.

[0072] The first semiconductor section 51 includes impurities that form a p-type semiconductor (acting as acceptors), and has a p-type (e.g., p-type) conductivity. "Acceptor" refers to an element with fewer valence electrons than a tetravalent element, such as a trivalent element. An example acceptor is boron (B).

[0073] <6.2 Semiconductor Division 2> The second semiconductor portion 52 is connected to the wiring 75 of the wiring portion 70. The second semiconductor portion 52 is located on the +Y direction side relative to the first semiconductor portion 51. The second semiconductor portion 52 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the second semiconductor portion 52 is disposed on the first end 40e1 of the laminate 40. The second semiconductor portion 52 includes, for example, a first portion 52a and a second portion 52b.

[0074] The first part 52a is disposed along the first end 40e1 of the laminate 40. For example, the first part 52a is disposed on the first end 40e1 of the laminate 40. The thickness of the first part 52a in the Z direction is the same as the thickness of the first part 51a in the Z direction of the first semiconductor portion 51.

[0075] Part 2 52b covers the first end portion STe1 of the first segment ST1 from the +Z direction side. In this embodiment, the first end portion STe1 of the first segment ST1 protrudes from the first end 40e1 of the laminate 40 towards the +Z direction side. In this embodiment, part 2 52b bulges from part 52a towards the +Z direction side and covers the first end portion STe1 of the first segment ST1 from the +Z direction side.

[0076] In this embodiment, when viewed from the Z direction, the second semiconductor portion 52 overlaps with at least a portion of the break portion ST1. The second semiconductor portion 52 extends linearly along the break portion ST1 in the X direction, for example (see Figure 8).

[0077] The second semiconductor portion 52 contains impurities that form a p-type semiconductor (impurities that act as acceptors) and has a p-type (e.g., p+) conductivity. In this embodiment, the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51. The impurities forming the second semiconductor portion 52 may be the same as or different from the impurities forming the first semiconductor portion 51.

[0078] <6.3 Semiconductor Division 3> The third semiconductor portion 53 is connected to the wiring 76 of the wiring portion 70. The third semiconductor portion 53 is located on the -Y direction side relative to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the third semiconductor portion 53 is disposed on the first end 40e1 of the laminate 40. The third semiconductor portion 53, for example, has a first portion 53a and a second portion 53b.

[0079] The first part 53a is disposed along the first end 40e1 of the laminate 40. For example, the first part 53a is disposed on the first end 40e1 of the laminate 40. The thickness of the first part 53a in the Z direction is the same as the thickness of the first part 51a of the first semiconductor portion 51 in the Z direction.

[0080] Part 2 53b covers the first end STe1 of the second segment ST2 from the +Z direction side. In this embodiment, the first end STe1 of the second segment ST2 protrudes from the first end 40e1 of the laminate 40 towards the +Z direction side. In this embodiment, part 53b bulges from part 53a towards the +Z direction side and covers the first end STe1 of the second segment ST2 from the +Z direction side.

[0081] In this embodiment, when viewed from the Z direction, the third semiconductor portion 53 overlaps with at least a portion of the break portion ST2. The third semiconductor portion 53 extends linearly along the break portion ST2 in the X direction, for example (see Figure 8).

[0082] The third semiconductor section 53 includes impurities that form an n-type semiconductor (acting as donor impurities) and has an n-type (e.g., n+ type) conductivity. "Donor" refers to an element with more valence electrons than a tetravalent element, such as a pentavalent element. An example donor is phosphorus (P).

[0083] <6.4 Inverted Layer> In this embodiment, the conductive layer 41A (the uppermost conductive layer 41 among a plurality of conductive layers 41) overlaps with the semiconductor layer 50 when viewed from the Z direction. The conductive layer 41A includes, for example, a first portion 41Aa, a second portion 41Ab, and a third portion 41Ac. When viewed from the Z direction, the first portion 41Aa overlaps with the first semiconductor portion 51 of the semiconductor layer 50. When viewed from the Z direction, the second portion 41Ab overlaps with the second semiconductor portion 52 of the semiconductor layer 50. When viewed from the Z direction, the third portion 41Ac overlaps with the third semiconductor portion 53 of the semiconductor layer 50. Furthermore, the phrase "overlapping with XX" in this application is not limited to overlapping with the entire area of ​​XX, but may include overlapping with at least a portion of the area of ​​XX.

[0084] In this embodiment, when a voltage is applied to the conductive layer 41A, an inversion layer 50r is formed on a portion of the semiconductor layer 50. The inversion layer 50r is formed, for example, at the end of the first semiconductor portion 51 on the -Z direction side. The inversion layer 50r extends along the first end 40e1 of the stack 40 in both the X and Y directions. The inversion layer 50r is connected to the channel layer 62 of the memory pillar MH and to the third semiconductor portion 53. After the inversion layer 50r is formed, electrons can move between the channel layer 62 of the memory pillar MH and the third semiconductor portion 53.

[0085] <6.5 First Wiring> The wiring 75 will now be described. For ease of explanation, wiring 75 will be referred to as "first wiring 75". First wiring 75 is a wiring electrically connected to the second semiconductor portion 52. In this embodiment, first wiring 75 is disposed on the second semiconductor portion 52 and connected to the second semiconductor portion 52 in the +Z direction. For example, first wiring 75 is connected to the first portion 52a and the second portion 52b of the second semiconductor portion 52.

[0086] Figure 8 is a cross-sectional view along line F8-F8 of the configuration shown in Figure 7. Similarly, in Figure 8, for ease of explanation, only a portion of the memory column MH is shown between two adjacent segments ST (ST1, ST2) in the Y direction. Furthermore, for ease of explanation, the insulating portion 33 is omitted in Figure 8, and solid lines are used to represent the schematic diagram of the first semiconductor section 51, the second semiconductor section 52, the third semiconductor section 53, wiring 75, and wiring 76. This definition is also present in Figures 19, 20, and 21.

[0087] As shown in Figure 8, the first wiring 75 extends in a straight line along the second semiconductor portion 52 in the X direction. Furthermore, the arrangement of the first wiring 75 is not limited to the example described above. For example, the first wiring 75 may also be disposed below the laminate 40 and electrically connected to the second semiconductor portion 52 via the conductive portion STb of the interruption portion ST1.

[0088] <6.6 Second Wiring> Next, wiring 76 will be described. For ease of explanation, wiring 76 will be referred to as "second wiring 76". Second wiring 76 is electrically connected to the wiring of the third semiconductor portion 53. In this embodiment, second wiring 76 is electrically insulated from first wiring 75. In this embodiment, second wiring 76 is disposed on the third semiconductor portion 53 and is connected to the third semiconductor portion 53 in the +Z direction. For example, second wiring 76 is connected to the first portion 53a and the second portion 53b of the third semiconductor portion 53. Second wiring 76 extends linearly along the third semiconductor portion 53 in the X direction.

[0089] Furthermore, the configuration of the second wiring 76 is not limited to the example described above. For example, the second wiring 76 may also be disposed below the laminate 40 and electrically connected to the third semiconductor section 53 via the conductive portion STb of the interruption portion ST2.

[0090] <6.7 Insulation Section> Returning to Figure 7, the insulating portion 33 will be described. The insulating portion 33 is disposed between the first wiring 75 and the second wiring 76, thereby electrically isolating the first wiring 75 and the second wiring 76. Furthermore, the insulating portion 33 is disposed between the second semiconductor portion 52 and the third semiconductor portion 53, thereby electrically isolating the second semiconductor portion 52 and the third semiconductor portion 53.

[0091] <7. Manufacturing Method> Next, the manufacturing method of semiconductor memory device 1 will be explained. Figures 9 to 11 are cross-sectional views illustrating the manufacturing method of the semiconductor memory device 1. First, a semiconductor substrate 101 is prepared. The semiconductor substrate 101 is formed of silicon. Next, an insulating layer 43 is formed on the surface of the semiconductor substrate 101 (see Figure 9(a)). In this embodiment, an insulating layer 43 as a thermal oxide film is formed on the surface of the semiconductor substrate 101 by supplying an oxidant to the surface of the semiconductor substrate 101 and heating it simultaneously.

[0092] Then, insulating layers 111 and 42 are alternately deposited on insulating layer 43 (see Figure 9(b)). This forms a laminate 40A. Insulating layer 111 is a sacrificial layer that will be replaced by conductive layer 41 in a subsequent step. Insulating layer 111 is formed, for example, from a material containing silicon and nitrogen.

[0093] Next, memory pillars MH and interrupted portions ST are formed on the laminate 40A (see Figure 9(c)). The first end MHe1 of the memory pillar MH and the first end STe1 of the interrupted portion ST are formed inside the semiconductor substrate 101. In this embodiment, the insulating layer 111 is replaced with the conductive layer 41 by a replacement step performed through the trenches provided when forming the interrupted portion ST. Thereby, the laminate 40 is formed from the laminate 40A.

[0094] Through the above steps, the second chip 3 is formed. Then, through other steps, the first chip 2 is formed. Furthermore, the second chip 3 is positioned upside down and attached to the first chip 2. For example, by bonding the pads 32 of the second chip 3 to the pads 24 of the first chip 2, the first chip 2 and the second chip 3 become a single unit.

[0095] Then, at least a portion of the semiconductor substrate 101 is removed from the second wafer 3 (see (d) in FIG10). Here, for example, etching is performed. Alternatively, other processing methods besides etching may be performed. Also, etching may be performed along with the other steps described above. In this embodiment, the entire semiconductor substrate 101 except for the insulating layer 43 is removed. Furthermore, by etching, the memory film 61 is removed at the first end MHe1 of the memory pillar MH. Hereby, the channel layer 62 is exposed at the first end MHe1 of the memory pillar MH. Furthermore, by etching, the insulating portion STa is removed at the first end STe1 of the break portion ST. Hereby, the conductive portion STb is exposed at the first end STe1 of the break portion ST.

[0096] Next, a semiconductor layer 120 is formed on the insulating layer 43 (see Figure 10(e)). The semiconductor layer 120 contains impurities that form a p-type semiconductor. In this embodiment, the semiconductor layer 120 is formed as a p-type semiconductor. The semiconductor layer 120 is formed, for example, from silicon doped with impurities. Alternatively, the semiconductor layer 120 can also be formed by implanting impurities after film formation.

[0097] Semiconductor layer 120 includes a first portion 121, a second portion 122, and a third portion 123. The first portion 121 corresponds to the first semiconductor portion 51 of semiconductor layer 50. The second portion 122 corresponds to the second semiconductor portion 52 of semiconductor layer 50. The third portion 123 corresponds to the third semiconductor portion 53 of semiconductor layer 50.

[0098] Then, for example, by photolithography, a mask M1 is formed covering the first portion 121 and the third portion 123 of the semiconductor layer 120 (see Figure 10(f)). Next, with the mask M1 provided, impurities for forming a p-type semiconductor are implanted into the second portion 122 of the semiconductor layer 120. Thereby, the second portion 122 of the semiconductor layer 120 is formed as a p+ type semiconductor.

[0099] Then, for example, by photolithography, a mask M2 is formed covering the first portion 121 and the second portion 122 of the semiconductor layer 120 (see (g) in Figure 11). Next, with the mask M2 provided, impurities for forming an n-type semiconductor are implanted into the third portion 123 of the semiconductor layer 120. Thereby, the third portion 123 of the semiconductor layer 120 is formed as an n+ type semiconductor.

[0100] Then, annealing for activation (e.g., laser annealing) is performed. Here, the first portion 121 of semiconductor layer 120 becomes the first semiconductor section 51. The second portion 122 of semiconductor layer 120 becomes the second semiconductor section 52. The third portion 123 of semiconductor layer 120 becomes the third semiconductor section 53.

[0101] Next, a conductive material (e.g., a metal material) is supplied to the semiconductor layer 50, and a conductive layer 130 is formed on the semiconductor layer 50 (see Figure 11(h)). Then, by patterning, unused portions are removed from the conductive layer 130, and a first wiring 75 and a second wiring 76 are formed from the conductive layer 130 (see Figure 11(i)). Next, an insulating portion 33 is provided between the first wiring 75 and the second wiring 76. Afterward, the wiring portion 70 is formed to include the wiring of the upper layer. At this point, the semiconductor memory device 1 is completed.

[0102] Furthermore, the manufacturing method of the semiconductor memory device 1 is not limited to the above example. For example, the insulating layer 43 may be formed after the first wafer 2 and the second wafer 3 are bonded together and the semiconductor substrate 101 is removed from the second wafer 3. Also, a portion or all of the semiconductor layer 50 may be formed before the first wafer 2 and the second wafer 3 are bonded together. For example, a portion or all of the semiconductor layer 50 may be formed as part of the semiconductor substrate 101 earlier than the formation of the insulating layer 43. In this case, for example, the semiconductor layer 50 may be formed from the remaining portion of the semiconductor substrate 101 by bonding the first wafer 2 and the second wafer 3 together and removing the unused portion of the semiconductor substrate 101.

[0103] <8. Action Examples> Next, an example of the operation of the semiconductor memory device 1 will be explained. Furthermore, unless otherwise specified, the following control is performed by the control circuit (sequencer) 14.

[0104] <8.1 Reading Actions> First, let's explain the act of reading aloud. Figure 12 is a diagram illustrating the readout operation. Here, the memory cell transistor MT that is the data readout target is referred to as the "select memory cell transistor MT". The word line WL corresponding to the select memory cell transistor MT is referred to as the "select word line WL". On the other hand, the memory cell transistor MT that is not the data readout target is referred to as the "non-select memory cell transistor MT". The word line WL corresponding to the non-select memory cell transistor MT is referred to as the "non-select word line WL". Furthermore, the bit line BL refers to the bit line BL corresponding to the select memory cell transistor MT.

[0105] As shown in Figure 12, at time t10, the first wiring 75, the second wiring 76, the source-side select gate line SGS, the select word line WL, the non-select word line WL, the drain-side select gate line SGD, and the bit line BL have a ground potential Vss (e.g., 0 V) ​​under the control of the control circuit 14.

[0106] Starting from time t11, control circuit 14 maintains the voltage of bit line BL at voltage Vbl. Voltage Vbl is higher than voltage Vss. Also, starting from time t11, control circuit 14 maintains the voltage of the second wiring 76 at voltage Vcelsrc. Voltage Vcelsrc is lower than voltage Vbl. The application of voltages Vbl and Vcelsrc continues, for example, until time t15.

[0107] Starting from time t12, control circuit 14 applies a voltage Vsgs to the source-side select gate line SGS. The voltage Vsgs is the voltage that turns the source-side select transistor STS on (conducting state). Furthermore, the voltage Vsgs is the voltage that forms the inversion layer 50r on the semiconductor layer 50 (see Figure 13) by applying this voltage Vsgs to the conductive layer 41A.

[0108] Furthermore, a higher voltage can be applied to the conductive layer 41A than the voltage applied to the other conductive layers 41 that serve as the source-side selected gate line SGS, to form an inversion layer 50r on the semiconductor layer 50. In this embodiment, the insulating layer 43 is relatively thin, so even if a lower voltage is applied to the conductive layer 41A, an inversion layer 50r can still be formed on the semiconductor layer 50. Therefore, the voltage Vsgs applied to the conductive layer 41A is the same as the voltage Vsgs applied to the other conductive layers 41 that serve as the source-side selected gate line SGS.

[0109] Furthermore, starting from time t12, control circuit 14 applies a voltage Vsgd to the drain-side select gate line SGD. Voltage Vsgd is the voltage that turns the drain-side select transistor STD into the ON (conducting) state. Also, starting from time t12, control circuit 14 applies a voltage Vpass_read to the non-select word line WL. Voltage Vpass_read is the voltage that turns the non-select memory cell transistor MT into the ON (conducting) state regardless of the threshold state of the non-select memory cell transistor MT. The application of voltages Vsgs, Vsgd, and Vpass_read continues, for example, until time t15.

[0110] Between time t13 and time t14, control circuit 14 applies a voltage Vcgr to the select word line WL. Due to the application of voltage Vcgr, the select memory cell transistor MT having a threshold voltage greater than Vcgr remains in an off state (non-conducting state). The select memory cell transistor MT having a threshold voltage less than Vcgr becomes in an on state (conducting state). Then, in this state, sense amplifier module 17 determines whether current flows in the channel layer 62 of memory pillar MH based on the voltage of bit line BL. This allows for data readout.

[0111] Figure 13 is a cross-sectional view illustrating the readout operation of the semiconductor memory device 1. During the readout operation, as described above, a voltage Vsgs is applied to the conductive layer 41A, forming an inversion layer 50r on the semiconductor layer 50. Therefore, when the select memory cell transistor MT is in the ON state (conduction state), electrons move between the channel layer 62 and the second wiring 76 of the memory pillar MH via the inversion layer 50r and the third semiconductor portion 53. This allows current to flow between the bit line BL and the second wiring 76.

[0112] <8.2 Write Action> Secondly, the writing action will be explained. Figure 14 is a diagram illustrating the write operation. Here, the memory cell transistor MT that is the object of data writing is referred to as the "select memory cell transistor MT". The word line WL corresponding to the select memory cell transistor MT is referred to as the "select word line WL". On the other hand, the memory cell transistor MT that is not the object of data writing is referred to as the "non-select memory cell transistor MT". The word line WL corresponding to the non-select memory cell transistor MT is referred to as the "non-select word line WL". Furthermore, the bit line BL refers to the bit line BL corresponding to the select memory cell transistor MT.

[0113] As shown in Figure 14, at time t20, the first wiring 75, the second wiring 76, the source-side select gate line SGS, the select word line WL, the non-select word line WL, the drain-side select gate line SGD, and the bit line BL have a ground potential Vss (e.g., 0 V) ​​under the control of the control circuit 14.

[0114] Starting at time t21, control circuit 14 applies a voltage Vsgd to the drain-side selector gate line SGD. Voltage Vsgd is the voltage that turns the drain-side selector transistor STD into the ON (conducting) state. The application of voltage Vsgd continues, for example, until time t25.

[0115] Starting at time t22, control circuit 14 applies a voltage Vpass to the select word line WL and the non-select word line WL. Vpass is high enough to turn on the memory cell transistor MT, and low enough not to perform a write operation on the memory cell transistor MT. The application of voltage Vpass to the non-select word line WL continues, for example, until time t25.

[0116] Between time t23 and time t24, control circuit 14 applies a voltage Vpgm to the select word line WL. Voltage Vpgm is higher than voltage Vpass. Voltage Vpgm is the voltage used to write data to the memory transistor MT (causing a change in the threshold state of the memory transistor MT). By applying voltage Vpgm, a large potential difference is formed between the select word line WL and the channel layer 62 of the memory transistor MT, resulting from voltages Vpgm and Vss. As a result, electrons are injected into the select memory transistor MT, thereby writing data.

[0117] <8.3 Erasure Action> The following is an explanation of the erasure action. Figure 15 illustrates the erasure operation. As shown in Figure 15, at time t30, the first wiring 75 and the word line WL, controlled by the control circuit 14, have a ground potential Vss (e.g., 0 V). Furthermore, the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL, controlled by the control circuit 14, become floating (floating).

[0118] Between time t31 and time t32, control circuit 14 applies voltage Vera to the first wiring 75. Voltage Vera is greater than voltage Vss. As a result, the voltages of the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL rise to near voltage Vera (≒Vera). This generates holes in the second semiconductor section 52, and these holes are supplied to the memory cell transistor MT. Electrons are then stolen from the memory cell transistor MT, erasing the data.

[0119] Starting from time t32, control circuit 14 discharges the first wiring 75. As a result, the voltage of the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL, which had previously risen to a voltage close to voltage Vera (≒Vera), decreases to voltage Vss.

[0120] Figure 16 is a cross-sectional view illustrating the erasure operation of the semiconductor memory device 1. During the erasure operation, as described above, holes are generated by the second semiconductor section 52, and these holes are supplied to the memory cell transistor MT via the channel layer 62 between the first semiconductor section 51 and the memory pillar MH. This process steals electrons from the memory cell transistor MT, erasing the data.

[0121] <9. Advantages> As a comparative example, one could envision a configuration where GIDL (Gate Induced Drain Leakage) current is used to supply the holes during the erase operation. In this configuration, impurities such as phosphorus need to be implanted into the deeper portion of the channel layer 62 of the memory pillar MH, and amorphization is achieved through annealing. However, implanting impurities into the deeper portion of the channel layer 62 and achieving amorphization through annealing is not easy. Therefore, the GIDL current may be insufficient during the erase operation. As a result, the electrical characteristics of the semiconductor memory device may sometimes degrade.

[0122] On the other hand, the semiconductor memory device 1 of this embodiment includes a semiconductor layer 50, a first wiring 56, and a second wiring 57. The semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53. The first semiconductor portion 51 includes a first portion 51a disposed along the first end 40e1 of the laminate 40, and a second portion 51b covering the first end MHe1 of the memory pillar MH. The second semiconductor portion 52 is connected to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51. The first wiring 56 is electrically connected to the second semiconductor portion 52. The second wiring 57 is electrically connected to the third semiconductor portion 53. The first semiconductor portion 51 and the second semiconductor portion 52 contain impurities forming p-type semiconductors. The third semiconductor portion 53 contains impurities forming n-type semiconductors. The conductive layer 41A includes a portion 41Aa that overlaps with the first semiconductor portion 51 when viewed from the Z direction.

[0123] With this configuration, during the erase operation, holes can be generated by the second semiconductor section 52, which is a p-type semiconductor, and supplied to the memory cell transistor MT. Therefore, insufficient erasure can be suppressed, and the electrical characteristics of the semiconductor memory device 1 can be improved.

[0124] In this embodiment, the third semiconductor portion 53 is disposed on the first end 40e1 of the stacked layer 40. With this configuration, electrons can easily move between the inversion layer 50r formed near the first end 40e1 of the stacked layer 40 in the first semiconductor portion 51 and the third semiconductor portion 53. This further enhances the electrical characteristics of the semiconductor memory device 1.

[0125] In this embodiment, the second semiconductor section 52 contains more impurities that form p-type semiconductors compared to the first semiconductor section 51. With this configuration, holes are easily generated in the second semiconductor section 52 and supplied to the memory cell transistor MT. For example, if the second semiconductor section 52 contains more impurities that form p-type semiconductors compared to the first semiconductor section 51, the contact resistance between the second semiconductor section 52 and the wiring 75 becomes smaller, thus making it easier to generate holes. Therefore, the electrical characteristics of the semiconductor memory device 1 can be further improved. Furthermore, considering only the operational case, the impurity concentration of the second semiconductor section 52 does not necessarily need to be higher than the impurity concentration of the first semiconductor section 51.

[0126] In this embodiment, the distance in the Z direction between the conductive layer 41A and the first semiconductor portion 51 is less than the thickness T1 in the Z direction of the insulating layer 42A. With this configuration, even with a relatively low voltage applied to the conductive layer 41A, it is easy to form an inversion layer 50r in the semiconductor layer 50. This further enhances the electrical characteristics of the semiconductor memory device 1.

[0127] In this embodiment, the shortest distance between the conductive layer 41A and the first semiconductor portion 51 is less than half the thickness T1 of the insulating layer 42A in the Z direction. With this configuration, even with a low voltage applied to the conductive layer 41A, an inversion layer 50r can be easily formed in the semiconductor layer 50. This further enhances the electrical characteristics of the semiconductor memory device 1.

[0128] In this embodiment, the insulating layer 43 and the insulating layer 42 have different compositions. Due to this configuration, even when the insulating layer 43 is thinner, the required withstand voltage can be easily ensured. This further enhances the electrical characteristics of the semiconductor memory device 1.

[0129] In this embodiment, when viewed from the Z direction, the second semiconductor section 52 overlaps with at least a portion of the segment ST1. With this configuration, the second semiconductor section 52 is formed using a region where the memory pillar MH is not disposed. This facilitates at least one advantage of miniaturization and high-density mounting of the semiconductor memory device 1.

[0130] In this embodiment, when viewed from the Z direction, the third semiconductor section 53 overlaps with at least a portion of the segment ST2. With this configuration, the third semiconductor section 53 is formed in a region where the memory pillar MH is not disposed. This facilitates at least one advantage of miniaturization and high-density mounting of the semiconductor memory device 1.

[0131] (Second Implementation) Next, the second embodiment will be described. The difference between the second embodiment and the first embodiment is that the breaking portion ST does not have a conductive portion STb. Furthermore, except for the configuration described below, the other configurations are the same as those in the first embodiment.

[0132] Figure 17 is a cross-sectional view showing a portion of the semiconductor memory device 1A according to the second embodiment. In this embodiment, the interrupted portion ST does not have a conductive portion STb. The interrupted portion ST is entirely formed by an insulating portion STa. The +Z direction side end of the interrupted portion ST coincides with the first end 40e1 of the laminate 40. Therefore, the second semiconductor portion 52 does not have a second portion 52b. The second semiconductor portion 52 is layered along the X and Y directions. Similarly, the third semiconductor portion 53 does not have a second portion 53b. The third semiconductor portion 53 is layered along the X and Y directions.

[0133] Based on this configuration, the movement paths of electrons and holes can be formed by the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1A.

[0134] (Third Implementation) Next, the third embodiment will be described. The difference between the third embodiment and the second embodiment is that the second semiconductor portion 52 is disposed in a region that does not overlap with the segment ST in the Z direction. Furthermore, except for the configuration described below, the other configurations are the same as those in the second embodiment.

[0135] Figure 18 is a cross-sectional view showing a portion of the semiconductor memory device 1B according to the second embodiment. In this embodiment, the semiconductor layer 50 includes a first semiconductor section 51, a second semiconductor section 52 (see Figure 19), a semiconductor section 53A, and a semiconductor section 53B.

[0136] In this embodiment, semiconductor portions 53A and 53B each include impurities that form n-type semiconductors (acting as donor impurities) and have an n-type (e.g., n+ type) conductivity. Both semiconductor portions 53A and 53B are examples of a "third semiconductor portion". Semiconductor portion 53A, when viewed from the Z direction, overlaps with at least a portion of the break section ST1. Semiconductor portion 53A extends linearly along the break section ST1 in the X direction (see Figure 19). Semiconductor portion 53B, when viewed from the Z direction, overlaps with at least a portion of the break section ST2. Semiconductor portion 53B extends linearly along the break section ST2 in the X direction (see Figure 19).

[0137] In this embodiment, the wiring section 70 includes wiring 76A and wiring 76B. Wiring 76A is disposed away from the semiconductor section 53A in the Z direction. For example, wiring 76A is disposed at a height that will not affect the bit line BL. A through-hole 202A is provided between wiring 76A and the semiconductor section 53A. Through-hole 202A is a conductive portion extending in the Z direction. In this embodiment, through-hole 202A extends in the Z direction and extends linearly in the X direction along the break section ST1. Wiring 76A is electrically connected to the semiconductor section 53A via through-hole 202A. Furthermore, in addition to the above example, through-hole 202A may not be provided. Wiring 76A may also be provided on the semiconductor section 53A.

[0138] Similarly, wiring 76B is disposed away from semiconductor portion 53B in the Z direction. For example, wiring 76B is disposed at a height that does not affect the bit line BL. A through-hole 202B is provided between wiring 76B and semiconductor portion 53B. Through-hole 202B is a conductive portion extending in the Z direction. In this embodiment, through-hole 202B extends in the Z direction and extends linearly in the X direction along the break portion ST2. Wiring 76B is electrically connected to semiconductor portion 53B via through-hole 202B. Furthermore, in addition to the above example, through-hole 202B may not be provided. Wiring 76B may also be provided on semiconductor portion 53B.

[0139] Figure 19 is a cross-sectional view along line F19-F19 of the configuration shown in Figure 18. In this embodiment, regarding the array region AR, the memory cell array 11 includes a first array region AR1 and a second array region AR2. The memory cell array 11 has a non-array region NAR between the first array region AR1 and the second array region AR2. The non-array region NAR is the region where no memory pillars MH are disposed. For example, the non-array region NAR is a region where no memory pillars MH exist beyond the arrangement interval of the memory pillars MH in the array region AR. The memory cell array 11 may also have a plurality of non-array regions NAR arranged at fixed intervals.

[0140] In this embodiment, the semiconductor layer 50 has a second semiconductor portion 52 in at least a portion of the non-array region NAR. Wiring 75 is disposed away from the second semiconductor portion 52 in the Z direction. For example, wiring 75 is disposed at a height that does not affect the bit line BL. A via 201 is provided between wiring 75 and the second semiconductor portion 52. The via 201 is a conductive portion extending in the Z direction. Wiring 75 is electrically connected to the semiconductor portion 53A via the via 201. In addition to the above example, via 201 may not be provided. Wiring 75 may also be disposed on the second semiconductor portion 52.

[0141] Based on this configuration, the movement paths of electrons and holes can be formed by the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1B. Furthermore, in the third embodiment described above, the third semiconductor portion (semiconductor portions 53A and 53B) is disposed in the array region AR, and the second semiconductor portion 52 is disposed in the non-array region NAR. Alternatively, the second semiconductor portion 52 may be disposed in the array region AR, and the third semiconductor portion 53 may be disposed in the non-array region NAR. Also, both the second semiconductor portion 52 and the third semiconductor portion 53 may be disposed in the non-array region NAR.

[0142] (Fourth implementation) Next, the fourth embodiment will be described. The difference between the fourth embodiment and the third embodiment is that the second semiconductor section 52 is disposed in the wiring area FR. Furthermore, except for the configuration described below, the other configurations are the same as those in the third embodiment.

[0143] Figure 20 is a top view showing a portion of the semiconductor memory device 1C according to the fourth embodiment. In this embodiment, the semiconductor layer 50 includes a first semiconductor section 51, a second semiconductor section 52, a semiconductor section 53A, and a semiconductor section 53B.

[0144] At least a portion of semiconductor section 53A is disposed in array region AR. At least a portion of semiconductor section 53B is disposed in array region AR. On the other hand, a second semiconductor section 52 is disposed in wiring region FR. Wiring region FR is a region where memory pillars MH are not disposed. For example, the second semiconductor section 52 is disposed between two supports HR.

[0145] Based on this configuration, the movement paths of electrons and holes can be formed by the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1C. Furthermore, in this embodiment, the second semiconductor section 52 is formed in a region where memory pillars MH are not disposed. This easily achieves at least one advantage in miniaturization and high-density mounting of the semiconductor memory device 1C. Moreover, in addition to the above example, the third semiconductor section 53 can also be disposed in the wiring region FR, or both the second semiconductor section 52 and the third semiconductor section 53 can be disposed in the wiring region FR.

[0146] (Fifth Embodiment) Next, the fifth embodiment will be described. The difference between the fifth embodiment and the third embodiment is that the second semiconductor section 52 overlaps with the dummy memory column DMH in the Z direction. Furthermore, except for the configuration described below, the other configurations are the same as those in the third embodiment.

[0147] Figure 21 is a top view showing a portion of the semiconductor memory device 1D according to the fifth embodiment. In this embodiment, the second semiconductor unit 52 is disposed in the array region AR in a region overlapping with the dummy memory column DMH. The dummy memory column DMH is a memory column MH that is not used for storing valid data. For example, the dummy memory column DMH is disposed at a position that overlaps with the breakpoint SHE in the Z direction and is not connected to the bit line BL.

[0148] Based on this configuration, the movement paths of electrons and holes can be formed by the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1D. Furthermore, in this embodiment, the second semiconductor section 52 is formed in a region where no memory pillar MH is disposed. This easily achieves at least one advantage in miniaturization and high-density mounting of the semiconductor memory device 1D. Moreover, in addition to the above example, the third semiconductor section 53 can also be disposed in a region overlapping with the dummy memory pillar DMH, or both the second semiconductor section 52 and the third semiconductor section 53 can be disposed in a region overlapping with the dummy memory pillar DMH.

[0149] The above describes several implementation methods, but the implementation methods are not limited to the examples described above. For example, multiple implementation methods can be combined with each other to achieve the same result.

[0150] According to at least one embodiment described above, a semiconductor memory device includes a first wafer and a second wafer. The second wafer has a stacked body, a pillar, a semiconductor layer, a first wiring, and a second wiring. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are stacked alternately layer by layer in a first direction. The stacked body has a first end, which is the opposite side of the first wafer, i.e., the first side end in the first direction. The pillar extends within the stacked body in the first direction. The pillar has a first end portion that reaches at least the first end of the stacked body. The semiconductor layer has a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion disposed along the first end of the stacked body and a second portion covering the first end portion of the pillar. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first and second semiconductor portions contain impurities that form p-type semiconductors. The third semiconductor portion contains impurities that form n-type semiconductors. The first gate electrode layer, which is closest to the first end of the stacked body among the plurality of gate electrode layers, includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. With this configuration, the electrical characteristics of the semiconductor memory device can be improved.

[0151] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents.

[0152] 1: Semiconductor memory devices 1A: Semiconductor memory device 1B: Semiconductor memory device 1C: Semiconductor memory device 1D: Semiconductor memory device 2: First chip 3: Second chip 11: Memory Cell Array 12: Instruction Register 13: Address Register 14: Control Circuit 15: Driver Module 16: Column Decoder Module 17: Sensing Amplifier Module 21: Semiconductor substrate 22: Peripheral Circuits 22a: Transistor 22b: Wiring 23: Insulation section 24: Solder pad 31: Insulation section 32: Solder pad 33: Insulation section 40: Laminated body 40A:Laminated body 40e1: First end of the laminate 41: Conductive layer (gate electrode layer) 41A: Conductive layer (first gate electrode layer) 41Aa: Part 1 41Ab: Part 2 41Ac: Part 3 41B: Conductive layer (second gate electrode layer) 41C: Conductive layer (3rd gate electrode layer) 42: Insulation layer 42A: First Insulation Layer 43: Insulation layer (second insulation layer) 50: Semiconductor layer 50r: Invert layer 51: Semiconductor Division 1 51a: Part 1 51b: Part 2 52: Semiconductor Division 2 52a: Part 1 52b: Part 2 53: Third Semiconductor Division 53a: Part 1 53b: Part 2 53A: Semiconductor Division 53B: Semiconductor Division 56: First wiring 57: Second wiring 61: Memory film (multilayer film) 61a: Block insulating film 61b: Charge trapping membrane 61c: Tunnel insulation film 62: Channel Layer 63: Insulation section 64: Cavity (Air Gap) 65: Cover 70: Wiring Department 71: Wiring 72: Wiring 75: First wiring 76: Second wiring 76A: Wiring 76B: Wiring 80:Breaking part 101: Semiconductor substrate 111: Insulation layer 120: Semiconductor layer 121: Part 1 122: Part 2 123: Part 3 130: Conductive layer 201: Through hole 202A: Through hole 202B: Through hole ADD: Address Information AR: Array Area AR1: Array Area 1 AR2: Second Array Region BL, BL0~BLm: Bit lines BLK, BLK0~BLK(k-1): Blocks CC: Contact CH: contact CMD command DAT: Read data DMH: Virtual Memory Column FR: Wiring Area HR: Supporter M1: Mask M2: Mask MH: Memory Column (Columnar Structure) MHe1: The first end of the memory column MT, MT0~MTn: Memory cell transistors NAR: Non-array region NS: NAND string SGD, SGD0~SGD4: Drain-side gate selection line SGS: Source-side gate selection SHE: breaking part SL: Source Line ST: Breaking part ST1: The first breaking part ST2: 2nd breaking part STa: Insulation part STb: Conductive part STe1: The first end of the first segment STD: Drain-side selective transistor STR, STR0~STR4: strings STS: Source-Side Selective Transistor t10~t15, t20~t25, t30~t33: Time points T1: Thickness T2: Thickness T3: Thickness T4: Thickness V1: Through hole Vb: Voltage Vcelsrc: Voltage Vcgr: Voltage Vera: Voltage Vpass: Voltage Vpass_read: Voltage Vpgm: Voltage Vsgd: Voltage Vsgs: Voltage Vss: Voltage VY: Contact Point WL, WL0~WLn: Character lines

Claims

1. A semiconductor memory device comprising: a first wafer; and a second wafer bonded to the first wafer; wherein the second wafer comprises: a stack comprising a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked in a first direction, and the stack comprising having a first end opposite to the first wafer, i.e., an end on a first side in the first direction; a columnar body extending in the stack comprising in the first direction and having a first end portion reaching at least the first end portion of the stack comprising; and a semiconductor layer comprising a first semiconductor portion, a second semiconductor portion connected to the first semiconductor portion, and a third semiconductor portion connected to the first semiconductor portion, the first semiconductor portion comprising a first portion disposed along the first end portion of the stack comprising and a second portion covering the first end portion portion of the columnar body. The first wiring is electrically connected to the second semiconductor portion; and the second wiring is electrically connected to the third semiconductor portion; the first semiconductor portion and the second semiconductor portion contain impurities forming p-type semiconductors, the third semiconductor portion contains impurities forming n-type semiconductors, and the first gate electrode layer among the plurality of gate electrode layers closest to the first end of the stacked body includes a portion that overlaps with the first semiconductor portion when viewed from the first direction.

2. The semiconductor memory device of claim 1, wherein the third semiconductor portion is disposed on the first end of the stack.

3. The semiconductor memory device of claim 1 or 2, wherein the second semiconductor portion contains more impurities forming a p-type semiconductor compared to the first semiconductor portion described above.

4. The semiconductor memory device of claim 1 or 2, wherein the plurality of gate electrode layers includes a second gate electrode layer and a third gate electrode layer adjacent to the second gate electrode layer in the first direction, the plurality of insulating layers includes a first insulating layer disposed between the second gate electrode layer and the third gate electrode layer, and the distance between the first gate electrode layer and the first semiconductor portion in the first direction is less than the thickness of the first insulating layer in the first direction.

5. The semiconductor memory device of claim 4, wherein the distance between the first gate electrode layer and the first semiconductor portion in the first direction is less than half the thickness of the first insulating layer in the first direction.

6. The semiconductor memory device of claim 4, wherein the stacked body includes a second insulating layer disposed between the first gate electrode layer and the first end of the stacked body, and the composition of the second insulating layer is different from that of the first insulating layer.

7. The semiconductor memory device of claim 6, wherein the first insulating layer is an insulating layer formed by supplying raw material gas, and the second insulating layer is a thermally oxidized film.

8. The semiconductor memory device according to claim 1 or 2, further comprising: a first segment extending in the stacked body in the first direction, segmenting the plurality of gate electrode layers in a second direction intersecting the first direction; and the second semiconductor portion overlapping at least a portion of the first segment when viewed from the first direction.

9. The semiconductor memory device of claim 1 or 2 further comprises: a second segment extending in the stacked body in the first direction, which segments the plurality of gate electrode layers in a second direction intersecting the first direction; and the third semiconductor portion overlapping at least a portion of the second segment when viewed from the first direction.

10. A method for manufacturing a semiconductor memory device, comprising: alternately depositing a first layer and a second layer on a semiconductor substrate in a first direction to form a stacked body; forming a columnar body extending in the stacked body in the first direction and including a first end reaching the semiconductor substrate; removing at least a portion of the semiconductor substrate; supplying an impurity for forming a p-type semiconductor to a portion of the semiconductor layer covering the first end of the columnar body; and supplying an impurity for forming an n-type semiconductor to another portion of the semiconductor layer.

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