A method of forming an interfacial layer of a gate structure of a semiconductor device, a method of forming a structure of a semiconductor device, and a structure of a semiconductor device

Abstract

This disclosure relates to a method for improving the quality of an interface layer of a gate structure in a semiconductor device. The method includes: forming a channel region on a substrate; and oxidizing a surface of the channel region to form an interface layer comprising silicon oxide. The method further includes: depositing a metal oxide (e.g., yttrium oxide) layer on the interface layer; performing an annealing process to convert the silicon oxide in the interface layer into silicon dioxide by reducing the density of oxygen vacancies in the interface layer; and removing the metal oxide layer. The method further includes forming a high-k dielectric layer and a gate electrode on the interface layer to form the gate structure.

Description

Technical Field

[0001] This disclosure relates to a method for forming an interface layer for a gate structure of a semiconductor device, a method for forming a structure of a semiconductor device, and a structure of a semiconductor device. Prior Technology

[0002] With the development of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, finFETs, and gate-all-around MOSFETs (GAA FETs). This shrinkage has increased the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a method for forming an interface layer of a gate structure of a semiconductor device is provided. The method includes: forming a channel region in a fin structure on a substrate; forming a source / drain (S / D) region adjacent to the channel region; forming an interface layer (IL) on the channel region, wherein forming the IL includes: forming a silicon oxide layer on the channel region; depositing a yttrium oxide layer on the silicon oxide layer; annealing the yttrium oxide layer and the silicon oxide layer to reduce the density of oxygen vacancies in the silicon oxide layer; removing the yttrium oxide layer; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.

[0004] According to some embodiments of the present disclosure, a method for forming a structure of a semiconductor device is provided. The method includes: forming a nanostructure in a fin structure; forming a source / drain (S / D) region adjacent to the nanostructure; and forming a gate structure surrounding the nanostructure. The formation of the gate structure includes: forming an interface layer (IL) comprising oxygen and silicon on the nanostructure; increasing the oxygen-to-silicon ratio in the IL; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.

[0005] According to some embodiments of this disclosure, a structure for a semiconductor device is provided, the structure comprising: a substrate; a fin structure on the substrate, wherein the fin structure includes a channel region; a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region, wherein the gate structure comprises: an interface layer (IL) on the channel region, wherein the IL comprises silicon dioxide, wherein the oxygen-to-silicon ratio in the IL is approximately 2:1; a high-k dielectric layer on the IL; a work function layer on the high-k dielectric layer; and a gate electrode on the work function layer. Simple Explanation of the Diagram

[0006] The nature of this disclosure is best understood in conjunction with the accompanying drawings and the following detailed description. It should be noted that, in accordance with common industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0007] Figure 1 is an isometric view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0008] Figure 2 is a cross-sectional view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0009] Figure 3 is an X-ray photoelectron spectrum (XPS) of an interface layer of a semiconductor transistor according to one of some embodiments.

[0010] Figures 4A and 4B are flowcharts of a method for forming a semiconductor transistor according to some embodiments.

[0011] Figures 5 and 6 are isometric views of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0012] Figure 7-19 is a cross-sectional view of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally indicate the same, functionally similar, and / or structurally similar elements. Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, a first feature formed over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition itself does not specify a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, this document may use spatial relative terms such as "under," "below," "below," "above," "on," and similar terms to describe the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. Besides the orientations shown in the figures, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related terms used herein may be interpreted accordingly.

[0016] In some embodiments, the terms “about” and “substantially” may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to be limiting. It should be understood that the terms “about” and “substantially” may refer to a percentage of the value as interpreted by someone skilled in the art in accordance with the teachings herein.

[0017] It should be noted that references to "an embodiment," "an exemplary embodiment," "exemplary," etc., in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used in this document is for illustrative rather than restrictive purposes, and that the wording or terminology used in this instruction should be interpreted by someone skilled in the art in light of the teachings herein.

[0019] As an example, and not a limitation, nanostructured transistors with nanosheet (NS) or nanowire (NW) channel regions, such as GAA nanosheet (NS) or nanowire (NW) FETs (collectively referred to as "GAAFETs"), can be formed as follows: A type of fin structure having alternating silicon-germanium (SiGe) and silicon (Si) NS or NW layers is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed on one of the middle portions of the type of fin structure to cover the top and sidewall surfaces of the type of fin structure, such that the edge portions of the type of fin structure are not covered by the sacrificial gate structure. The edge portions of the type of fin structure not covered by the sacrificial gate structure are removed. Subsequently, the edge portions of the SiGe NS or NW layers are recessed relative to the edge portions of the SiGe NS or NW layers, and an inner spacer structure is formed by depositing a dielectric material to fill the space formed by the etched portions of the SiGe NS or NW layers. Next, a source / drain (S / D) epitaxial structure is formed to abut (or contact) the edge portion of the fin-like structure, such that the S / D epitaxial structure contacts the Si NS or NW layer and is isolated (or separated) from the SiGe NS or NW layer by an inner spacer structure. The source / drain may refer individually or collectively to a source or a drain, depending on the context. In a subsequent operation, a sacrificial gate structure is removed to expose the top and sidewall surfaces of the fin-like structure. The SiGe NS or NW layer is selectively removed from the fin-like structure. During the selective removal procedure, the Si NS or NW layer and the inner spacer structure are not removed. Subsequently, a gate structure is formed to surround the Si NS or NW layer. Similar to the SiGe NS or NW layer, the gate structure is isolated (or separated) from the S / D epitaxial structure by an inner spacer structure before their selective removal. The gate structure includes an interface layer (IL) above a Si NS or NW layer, a gate dielectric layer on the IL, and a gate electrode including a metal of suitable work function on the gate dielectric layer.

[0020] The structure of a GAAFET can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual or multiple patterning procedures. Dual or multiple patterning procedures combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be constructed compared to those achievable using a single direct photolithography process in other ways. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0021] As semiconductor devices continue to shrink, in exemplary GAAFETs formed using the processes described above, the critical dimensions of the GAAFET (such as the length / width of the Si NS or NW layer serving as the channel and the metal gate structure) are reduced. Highly sensitive to the shrinkage process, the quality of the interphase (IL) becomes increasingly critical to the electrical performance and reliability of the GAAFET. The IL may include silicon oxide (e.g., SiOx, where x < 2) by oxidizing the surface of the Si NS or NW layer. Since the ratio of oxygen (O) atoms to Si atoms in SiOx can be less than 2, the IL may include oxygen vacancies as defects, which can act as tunneling aid traps for leakage current between the channel and gate structures, thereby affecting electrical performance and causing GAAFET degradation. As an alternative to shrinkage, increasing the thickness of the IL can suppress leakage current, but still compromises the gate structure's ability to modulate channel conductivity. Furthermore, it is difficult to control the growth rate of the IL during processes that increase its thickness (e.g., a thermal process using oxygen radicals), thus affecting the uniformity and quality of the IL.

[0022] The embodiments described herein relate to overcoming the challenges mentioned above. In some embodiments, a structure of a semiconductor device may include a gate structure and a channel layer. The gate structure may include an IL on the channel layer. The IL may include silicon dioxide (SiO₂) having a stoichiometric ratio of O atoms to Si atoms of about 2. When SiO₂ is used in the IL instead of SiOₓ, the integrity of the IL can be improved due to the absence of oxygen vacancies, and leakage current between the channel layer and the gate structure can be effectively suppressed. In some embodiments, a method of forming the structure may include forming the channel layer and forming the gate structure. Forming the gate structure may include forming the IL on the channel layer, and forming a high-k dielectric layer and a gate electrode on the IL. Forming the IL may include forming a SiOₓ layer on the channel layer, depositing a metal oxide layer (e.g., yttrium oxide (Y₂O₃)) on the SiOₓ layer, annealing the metal oxide layer and the SiOₓ layer to reduce the density of oxygen vacancies in the silicon oxide layer, and removing the metal oxide layer. Specifically, during the annealing of the metal oxide layer and the SiO x layer, oxygen atoms in the metal oxide layer can diffuse into the SiO x layer to replace oxygen vacancies, thereby transforming the SiO x layer into a SiO 2 layer and improving the quality of the leakage current (IL). Furthermore, due to the reaction between the metal atoms in the metal oxide layer and the Si atoms in the SiO x layer, the annealing process can also promote the formation of a silicate layer between the metal oxide layer and the SiO x layer. After removing the metal oxide layer, the silicate layer can then be removed, thereby reducing the thickness of the IL. This is consistent with the shrinkage process and contrasts with the aforementioned approach of increasing the thickness of the IL to suppress leakage current. This method of forming the IL can also be applied to the fabrication processes of other semiconductor transistors, such as planar MOSFETs and FinFETs.

[0023] According to some embodiments, a semiconductor device 100 having a plurality of transistors 105 formed above a substrate 102 is described with reference to FIG1 and 2. The semiconductor device 100 may be included in a microprocessor, memory cell or other integrated circuit (IC). FIG1 illustrates an isometric view of the semiconductor device 100. FIG2 illustrates a cross-sectional view (e.g., along the xz plane) of the semiconductor device 100 taken along line AB of FIG1.

[0024] Referring to Figure 1, the substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include: (i) a basic semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium arsenide phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Furthermore, the substrate 102 may be doped depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, one of the crystal orientations of the substrate 102 may be (100), (110), or (111).

[0025] Although Figures 1 and 2 show a fin structure 110 accommodating two transistors 105, any number of transistors 105 may be arranged along the fin structure 110. In some embodiments, the transistor 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in the x-direction) and a gate structure 115 traversing the plurality of fin structures 110 along a second horizontal direction (e.g., in the y-direction). In some embodiments, the crystal orientation of one of the fin structures 110 may be the same as the crystal orientation of the substrate 102.

[0026] Referring to Figures 1 and 2, one or more nanosheet (NS) layers 120 may be disposed above the fin structure 110. Each NS layer 120 may be covered by a gate structure 115 to serve as a channel for the transistor 105. For example, a top surface, a side surface, and a bottom surface of each NS layer 120 may be surrounded by and in contact with the gate structure 115. The fin structure 110 and the NS layer 120 may be made of a material similar to (e.g., within about 5% lattice mismatch) the substrate 102. In some embodiments, the crystal orientation of one of the NS layers 120 may be the same as the crystal orientation of the fin structure 110. In some embodiments, each of the fin structure 110 and the NS layer 120 may be made of Si or SiGe. Each of the fin structure 110 and the NS layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the NS layer 120 may be doped together with a p-type dopant or an n-type dopant. In some embodiments, the thickness of the NS layer 120 may be between about 5 nm and about 10 nm. Although FIG1 shows that each transistor 105 includes four NS layers 120, and FIG2 shows that each transistor 105 includes three NS layers 120, any number of NS layers 120 may be included in each transistor 105. For example, each transistor 105 may include one, two, five, or six NS layers 120.

[0027] Referring to Figures 1 and 2, the gate structure 115 may be a multilayer structure that surrounds each NS layer 120 to adjust the transistor 105. The gate structure 115 may have a length Lc, which represents the channel length of the transistor 105. The length Lc may have any suitable horizontal (e.g., in the x-direction) dimension, such as about 3 nm to about 200 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 along a straight direction (e.g., in the z-direction) may be between about 10 nm and about 20 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 may be greater than about 20 nm. In some embodiments, the thickness of the gate structure 115 between adjacent NS layers 120 may be between about 5 nm and about 15 nm, corresponding to the spacing between adjacent NS layers 120. By way of example and not limitation, each gate structure 115 may include a dielectric stack formed of an IL 115a and a gate dielectric layer 115b. Furthermore, each gate structure 115 may include a gate electrode 115c having a capping layer, one or more work function metal layers, and a metal filler, which are not individually shown in FIG1 for simplicity. The gate dielectric layer 115b may include any suitable dielectric material having any suitable thickness that provides channel tuning for the transistor 105. In some embodiments, the gate dielectric layer 115b may be made of a high-k dielectric material. For example, high-k dielectric materials may include hafnium oxide (HfO 2), aluminum oxide (Al 2O 3), scandium oxide (ScO 2), zirconium oxide (ZrO 2), calcium oxide (CaO), magnesium oxide (MgO), zirconium silicate (ZrSiO 4), or a combination thereof. In some embodiments, the gate dielectric layer 115b may include lanthanum oxide (La 2O 3) on a high-k dielectric to form an N-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the concentration of carbon atoms in the gate dielectric layer 115b may be less than about 0.2%. In some embodiments, the gate dielectric layer 115b may have a thickness ranging from about 1 nm to about 5 nm. Other materials and thicknesses of the gate dielectric layer 115b are within the scope and spirit of this disclosure. The gate electrode 115c may serve as a gate terminal of the transistor 105. The gate electrode 115c may include any suitable conductive material that provides a suitable work function to modulate the transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Other materials of the gate electrode 115c are within the scope and spirit of this disclosure.

[0028] In some embodiments, the thickness of IL 115a may be between about 0.2 nm and about 2 nm. For example, the thickness of IL 115a may be about 1 nm. In some embodiments, IL 115a may include a SiO 2 layer having an O atom to Si atom ratio of about 2. As explained below, the SiO 2 layer may be formed by forming a SiO x layer on the NS layer 120 and then removing and / or reducing oxygen vacancies in the SiO x layer to transform it into a SiO 2 layer. In some embodiments, IL 115a may be free of oxygen vacancies. In some embodiments, IL 115a may be free of Si dangling bonds, such that the Si atoms in IL 115a are in the Si 4+ valence state. In some embodiments, the difference in material composition between the SiO 2 layer and the SiO x layer can be examined by X-ray photoelectron spectroscopy (XPS), as shown in FIG3. Figure 3 shows a graph including a real curve and a dashed curve representing the signal (in counts per second) of photoemitted electrons from the SiO2 and SiOx layers as a function of binding energy. In Figure 3, both the real and dashed curves include a main peak 310, corresponding to photoemission from a SiO state. Furthermore, both the real and dashed curves include satellite peaks 330 and 320, respectively, with satellite peak 330 blue-shifted by an energy Es from satellite peak 320. Specifically, satellite peak 320 corresponds to photoemission from Si3+, Si2+, and / or Si1+ states, indicating that the SiOx layer includes Si atoms with dangling bonds. On the other hand, satellite peak 330 corresponds to photoemission from a fully covalent Si4+ state, which has a deeper potential energy than the Si3+, Si2+, or Si1+ states, resulting in a higher energy for satellite peak 330 than satellite peak 320, indicating that the SiO2 layer does not contain Si dangling bonds or oxygen vacancies. In some embodiments, the energy Es can be between about 0.2 eV and about 0.8 eV. For example, the energy Es can be about 0.5 eV. In some embodiments, the energy difference Ed between satellite peak 330 and main peak 310 can be about 3 eV. In some embodiments, satellite peak 330 can have an amplitude that is smaller than that of satellite peak 320 by a difference Δ, indicating that the thickness of the SiO2 layer is smaller than that of the SiOx layer. In some embodiments, the ratio of the difference Δ of satellite peaks 330 to the amplitude can be about 10%.

[0029] Referring to Figures 1 and 2, the S / D epitaxial structure 125 may be disposed above each opposite side (e.g., along the x-direction) of the NS layer 120 to serve as the source and drain terminals of the transistor 105. The S / D epitaxial structure 125 may be disposed on the fin structure 110. The S / D epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch of about 5%) one of the NS layers 120. In some embodiments, the S / D epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The S / D epitaxial structure 125 may be doped with a p-type dopant, an n-type dopant, or an intrinsic dopant. In some embodiments, the S / D epitaxial structure 125 may have a doping type different from that of the NS layer 120. In some embodiments, the n-type dopant in the S / D epitaxial structure 125 may include P, As, Sb, or a combination thereof. In some embodiments, a crystal orientation of the S / D epitaxial structure 125 may be the same as the crystal orientation of the NS layer 120.

[0030] Referring to Figure 2, the semiconductor device 100 may include a dielectric layer 166 disposed above the top surface of the S / D epitaxial structure 125. As described below, the dielectric layer 166 may be formed in the same process as forming IL 115a, whereby the top surface of the S / D epitaxial structure 125 and the surface of the NS layer 120 are exposed to be oxidized to form a SiO x layer, and subsequently undergo the same treatment as IL 115a to transform into a SiO 2 layer. In some embodiments, the dielectric layer 166 may have the same or similar properties as IL 115a as described above, and will not be repeated for simplicity.

[0031] Referring to Figures 1 and 2, the semiconductor device 100 may include an inner spacer structure 130 that abuts (or contacts) a side surface of the gate structure 115. The inner spacer structure 130 separates the gate structure 115 from the S / D epitaxial structure 125. For example, the inner spacer structure 130 may be formed on opposite sides of the gate structure 115 along the channel direction of the transistor 105 (e.g., along the x-direction) to separate the gate structure 115 from the S / D epitaxial structure 125. In some embodiments, the inner spacer structure 130 may be formed between two orthogonally (e.g., in the z-direction) adjacent NS layers 120. In some embodiments, the inner spacer structure 130 may be formed between the fin structure 110 and the NS layer 120. In some embodiments, the inner spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon oxy-carbon-nitride (SiOCN), silicon carbon-nitride (SiCN), or silicon oxy-nitride (SiON). In some embodiments, the inner spacer structure 130 may include a low-k material, such as a porous material, and a silicon oxide-based dielectric.

[0032] Referring to Figures 1 and 2, the semiconductor device 100 may further include a gate spacer 135, which is formed between the gate structure 115 and the S / D epitaxial structure 125, and which can provide structural support during the formation of the gate structure 115. Additionally, the gate spacer 135 can provide electrical isolation and protection for the gate structure 115 during the formation of the S / D contact. The gate spacer 135 can be made of any suitable dielectric material. In some embodiments, the gate spacer 135 can be made of silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9. In some embodiments, the gate spacer 135 can have any suitable thickness, such as between about 5 nm and about 15 nm. Other materials and thicknesses of the gate spacer 135 are within the scope and spirit of this disclosure based on the present disclosure.

[0033] Referring to Figure 1, the semiconductor device 100 may further include shallow trench isolation (STI) regions 138, which are configured to provide electrical isolation between fin structures 110. STI regions 138 may also provide electrical isolation between transistor 105 and adjacent active and passive components integrated with or disposed on substrate 102. STI regions 138 may include one or more dielectric material layers, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Other dielectric materials for STI regions 138 are within the scope and spirit of this disclosure.

[0034] Referring to Figures 1 and 2, the semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation for structural elements it surrounds or covers, such as gate structure 115 and S / D epitaxial structure 125. In some embodiments, a gate spacer 135 may be disposed between gate structure 115 and ILD layer 165. In some embodiments, ILD layer 165 may be disposed on S / D epitaxial structure 125 and dielectric layer 166. ILD layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon carbide, silicon oxynitride, silicon oxycarbonide, and silicon carbonitride. ILD layer 165 may have any suitable thickness, such as about 50 nm to about 200 nm, to provide electrical insulation. Other insulating materials and thicknesses of ILD layer 165 are within the scope and spirit of this disclosure.

[0035] Referring to Figures 1 and 2, the semiconductor device 100 may further include dielectric layers 152, 154, and 156 on the transistor 105. In some embodiments, dielectric layers 152, 154, and 156 may include silicon oxide and / or silicon nitride. For example, dielectric layers 152 and 156 may be silicon oxide layers, and dielectric layer 154 may be a silicon nitride layer. In some embodiments, dielectric layers 152, 154, and 156 may be etch stop layers.

[0036] Referring to Figures 1 and 2, the semiconductor device 100 may further include an S / D contact 163 that contacts the S / D epitaxial structure 125. The S / D contact 163 may be disposed on the S / D epitaxial structure 125 and surrounded by an ILD layer 165. In some embodiments, the S / D contact 163 may be disposed through a dielectric layer 166. In some embodiments, the S / D contact 163 may be disposed through one or more of dielectric layers 152, 154, and 156. In some embodiments, a silicon layer 164 may be disposed between the S / D contact 163 and the S / D epitaxial structure 125. In some embodiments, the height of one of the S / D contacts 163 may be between about 10 nm and about 50 nm. The S / D contact 163 may include any suitable conductive material that provides low contact resistance with the S / D epitaxial structure 125. In some embodiments, the S / D contact 163 may be made of polycrystalline silicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, nickel, or a combination thereof. Other materials for the S / D contact 163 are within the scope and spirit of this disclosure, based on the information disclosed herein.

[0037] Referring to Figures 1 and 2, the semiconductor device 100 may further include one or more gate contact vias 167 that contact gate electrodes 115c. The gate contact vias 167 may be disposed on the gate structure 115 and pass through one or more of dielectric layers 152, 154, and 156. In some embodiments, an interface between the gate contact via 167 and the gate electrode 115c may be substantially flat. In some embodiments, the interface between the gate contact via 167 and the gate electrode 115c may be curved. In some embodiments, a horizontal cross-section of the gate contact via 167 may have a rectangular shape or a cylindrical shape. In some embodiments, the gate contact via 167 may have a push-out shape, wherein the width of a top surface is greater than the width of a bottom surface. In some embodiments, the gate contact via 167 may have a uniform width from its top surface to its bottom surface. In some embodiments, the width of the top surface of the gate contact via 167 may be between about 2 nm and about 40 nm. In some embodiments, the width of the bottom surface of the gate contact via 167 may be between about 1 nm and about 40 nm. In some embodiments, the ratio of the width of the top surface of the gate contact via 167 to the width of the bottom surface of the gate contact via 167 may be between about 1 and about 3. In some embodiments, the height of one of the gate contact vias 167 may be between about 10 nm and about 50 nm. In some embodiments, the aspect ratio of one of the gate contact vias 167 may be between about 5:1 and about 20:1.

[0038] Although the transistor 105 illustrated in Figures 1 and 2 is an embodiment of a GAAFET, it should be understood that the IL 115a illustrated in Figures 1 and 2 can be applied to other types of transistors, such as MOSFETs, FinFETs, complementary fin field-effect transistors (CFETs) or vertical fin field-effect transistors (VFETs).

[0039] According to some embodiments, FIG4 illustrates a flowchart of a method 400 for forming the transistor 105 shown in FIG1 and 2. FIG4B illustrates a flowchart detailing one operation 440 of the manufacturing method 400, and particularly with respect to the formation of the IL 115a of the transistor 105. This disclosure is not limited to this description of operations, and additional operations may be performed. Other manufacturing operations may be performed among the various operations of method 400, and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously, or in a sequence different from that shown in FIG4A and 4B. In some embodiments, one or more other operations may be performed in addition to or in lieu of the operations currently described. For illustrative purposes, method 400 is described with reference to the structures shown in FIG5-19. Unless otherwise noted, the description of the elements in FIG1 and 2 with the same annotations applies to FIG5-19.

[0040] Referring to FIG4A, method 400 begins with operation 410 and procedure of forming a fin structure having a channel region on a substrate (e.g., substrate 102). In some embodiments, forming the fin structure may include forming a stack of alternating first and second NS layers on the substrate. FIG5 is an isometric view of substrate 102 and a stack 520 of alternating first and second NS layers 520a and 520b. In some embodiments, the first and second NS layers 520a and 520b are formed on an exposed top surface of substrate 102. In some embodiments, the first NS layer 520a is a sacrificial NS layer to be subsequently removed, and the second NS layer 520b corresponds to NS layer 120 shown in FIG1. ​​In some embodiments, the material of the first NS layer 520a in the stack 520 is selected such that the first NS layer 520a can be selectively removed from the stack 520 by etching without removing the second NS layer 520b. For example, the first NS layer 520a can be a SiGe NS layer and the second NS layer 520b can be a Si NS layer.

[0041] The first and second NS layers 520a and 520b can be grown using any suitable method. For example, the first and second NS layers 520a and 520b can be grown using a chemical vapor deposition (CVD) process with a precursor gas such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first NS layer 520a may include Ge at a concentration between about 20% and about 30%, while the second NS layer 120 is substantially free of germanium—for example, having a Ge concentration of less than about 1%. In some embodiments, the second NS layer 520b, which corresponds to the NS layer 120 of FIG. 1, forms the channel region of transistor 105 and may be lightly doped or intrinsically (e.g., undoped). If lightly doped, the doping level of the second NS layer 520b is less than about 10¹³ atoms / cm³. The first and second NS layers 520a and 520b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any interposer layer. In some embodiments, in a subsequent etch operation, the first NS layer 520a may be doped to increase its etch selectivity compared to the second NS layer 520b.

[0042] In some embodiments, the thickness of one of the first NS layers 520a controls the spacing between each interval of the second NS layers 520b in the stack 520. The thicknesses of the first and second NS layers 520a and 520b can range, for example, from about 3 nm to about 15 nm. Since the first and second NS layers 520a and 520b are grown individually, the thickness of each NS layer can be adjusted independently, for example, based on the deposition time. In some embodiments, additional or fewer numbers of the first and second NS layers 520a and 520b can be formed in the stack 520. In some embodiments, the total number of NS layers can be 2^n, where n is the number of first NS layers 520a or the number of second NS layers 520b in the stack 520. In some embodiments, n can be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0043] Referring to Figure 4A, operation 410 may further include a process of patterning stack 520 to form one of the fin structures. In some embodiments, stack 520 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The fin structure can be formed by patterning using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be constructed compared to those achievable using a single direct photolithography process in other ways. In some embodiments, a sacrificial layer is formed on stack 520 and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask structure to pattern the fin structure.

[0044] As an example and not a limitation, FIG6 is an isometric view of a fin structure 620 formed from a stack 520 using the aforementioned patterning process. In some embodiments, the fin structure 620 may be formed by etching first and second NS layers 520a and 520b into first and second NS layers 620a and 620b. In some embodiments, the aforementioned patterning process does not terminate on the top surface of the substrate 102, but continues to etch a top portion of the substrate 102 to form a fin structure 110 from the substrate 102 under the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed using the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the xz plane and the yz plane are substantially aligned with the individual sidewall surfaces of the fin structure 110, as shown in FIG6.

[0045] Additional fin structures, such as fin structure 620, may be formed on the substrate 102 in the same or different regions of the substrate 102. For simplicity, these additional fin structures are not shown in Figure 6. As an example and not a limitation, each fin structure 620 has a width along the y-direction between approximately 15 nm and approximately 150 nm.

[0046] In some embodiments, NS layers 620a and 620b are referred to as "nanosheets" when their width along the y-direction is substantially different from their height along the z-direction—for example, when their width is greater than / narrower than their height. In some embodiments, NS layers 620a and 620b may also be referred to as "nanolines" when their width along the y-direction is substantially equal to their height along the z-direction. In some embodiments, NS layers 620a and 620b are deposited as nanosheets and subsequently patterned to form nanolines with substantially equal height and width. By way of example and not limitation, NS layers 620a and 620b will be illustrated in the context of nanosheet (NS) layers. For the purposes of this disclosure, nanolines (NW) are within the spirit and scope of this disclosure. Furthermore, for illustrative purposes and without limiting the scope of this disclosure, the first and second NS layers 620a and 620b in method 400 will be illustrated in the context of SiGe and Si NS layers, respectively.

[0047] In some embodiments, after the formation of the fin structure 620, an STI region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the STI region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. By way of example and not limitation, the STI region 138 may be formed as follows: An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket-deposited over the fin structure 620 and the substrate 102. The deposited isolation structure material is planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 620. The planarized isolation structure material is then etched back so that the resulting STI region 138 has a height substantially similar to that of the fin structure 110, as shown in FIG6. In some embodiments, the fin structure 620 protrudes from the STI region 138 such that the STI region 138 does not cover the sidewall portion of the fin structure 620, as shown in FIG6.

[0048] Referring to FIG4A, operation 410 may further include a process of forming a sacrificial gate structure on the fin structure. For example, a sacrificial gate structure 700 may be formed on the fin structure 620, as illustrated with FIG7. In some embodiments, the sacrificial gate structures 700 are formed such that their length is along the y-direction—for example, perpendicular to the fin structure 620 shown in the isometric view of FIG6—and their width is along the x-direction. By way of example and not limitation, FIG7 is a cross-sectional view of FIG6 taken along the cutting line AB. FIG7 shows the sacrificial gate structure 700 formed on a portion of the fin structure 620. Because FIG7 is a cross-sectional view and not an isometric view, the portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Also, in the cross-sectional view of FIG7, only one of the fin structures 620 of FIG6 is shown. In some embodiments, portions of the sacrificial gate structure 700 are formed between the fin structures 620 and on the STI region 138 shown in FIG6.

[0049] In some embodiments, the sacrificial gate structure 700 may cover the top and sidewall portions of the fin structure 620. During a subsequent gate replacement procedure, the sacrificial gate structure 700 is subsequently replaced with the gate structure 115 shown in FIG. 1. The sacrificial gate structure 700 may include a sacrificial gate electrode 700a formed on a sacrificial gate dielectric (not shown in FIG. 7 for simplicity). The sacrificial gate structure 700 may also include a capping layer 705, etc., formed on the top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 may protect the sacrificial gate electrode 700a from subsequent etching operations. During this fabrication stage, gate spacers 135 may be formed on the side surfaces of the sacrificial gate structure 700. As discussed above, the gate spacers 135 are not removed during the gate replacement procedure; rather, the gate spacers 135 facilitate the formation of the gate structure 115 shown in FIG. 1.

[0050] By way of example and not limitation, the sacrificial gate structure 700 can be formed by depositing and patterning a sacrificial gate electrode 700a over the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed over a plurality of fin structures 620. As shown in FIG7, portions of the fin structures 620 are not covered by the sacrificial gate structure 700. This is because the width of the sacrificial gate structure 700 is narrower than the length of the fin structures 620 along the x-direction. In some embodiments, the sacrificial gate structure 700 is used as a mask structure in subsequent etching operations to define the channel region of the transistor 105 shown in FIG1. ​​For this reason, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0051] Referring to FIG4A, operation 410 may further include a procedure for removing portions of the fin structure exposed by the sacrificial gate structure, as illustrated with FIG8. Referring to FIG8, portions of the fin structure 620 not covered by the sacrificial gate structure 700 may be removed. In some embodiments, the removal procedure involves a dry etching procedure, a wet etching procedure, or a combination thereof. The removal procedure is selective for the first NS layer 620a and the second NS layer 620b, shaping them into a first NS layer 820a and an NS layer 120, respectively. The removal procedure may further remove portions of the fin structure 110. In some embodiments, the dry etching process includes: an etchant having an oxygen-containing gas, a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); an iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemistry may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; a solution containing one of hydrofluoric acid (HF), nitric acid (HNO3), or acetic acid (CH3COOH); or combinations thereof.

[0052] In some embodiments, the etchant used in the aforementioned etching process substantially does not etch the sacrificial gate structure 700—which is protected by the capping layer 705 and the gate spacer 135—and the STI region 138 shown in FIG. 6. This is because the capping layer 705, the gate spacer 135, and the STI region 138 comprise materials with low etch selectivity, such as a silicon nitride-based material (e.g., silicon nitride, silicon carbon nitride, and silicon carbon oxy-nitride), or a silicon oxide-based material. In some embodiments, the STI region 138 shown in FIG. 6 is used as an etch stop layer for the aforementioned etching process.

[0053] After removing portions of the fin structure 620 not covered by the sacrificial gate structure 700, an opening 840 is formed in each fin structure 620, as shown in FIG8. The opening 840 divides each fin structure 620 into separate portions, each of which is covered by a sacrificial gate structure 700. Each portion may include a stack of a first NS layer 820a as a sacrificial layer and an NS layer 120 as a channel region.

[0054] Referring to Figure 4A, method 400 can proceed to operation 420, wherein an inner spacer structure is formed between the channel regions. For example, as illustrated with reference to Figures 9 and 10, an inner spacer structure 130 may be formed in the opening 840. The procedure for forming the inner spacer may include (i) selectively etching an edge portion of the first NS layer 820a to form a recessed structure 945, as illustrated with reference to Figure 9, and (ii) forming the inner spacer structure 130 in the recessed structure 945, as illustrated with reference to Figure 10. According to some embodiments, Figure 9 shows the structure of Figure 8 after the exposed edge of the first NS layer 820a is laterally etched (e.g., recessed) along the x-direction and becomes the first NS layer 920a. According to some embodiments, the exposed edge of the first NS layer 820a is recessed (e.g., partially etched) along the x-direction as shown in Figure 9 by an amount ranging from about 3 nm to about 10 nm to form the recessed structure 945.

[0055] In some embodiments, selective etching of the first NS layer 820a can be achieved using a dry etching process selective for SiGe. For example, halogen-based chemicals exhibit high etching selectivity for Ge and low etching selectivity for Si. Therefore, a halogen gas system etches Ge-containing layers, such as the first NS layer 820a, at a higher etching rate than a substantially Ge-free layer (such as NS layer 120). In some embodiments, halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, a wet etching chemical with high selectivity for SiGe can be used. By way of example and not limitation, a wet etching chemical may include a mixture of sulfuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂) (SPM), or a mixture of ammonium hydroxide, H₂O₂, and water (APM). The aforementioned etching process is timed to remove the desired amount of SiGe.

[0056] In some embodiments, the first NS layer 820a with a higher Ge atom concentration has a higher etch rate than the NS layer 120 with a lower or zero Ge atom concentration. Therefore, the etch rate of the aforementioned etching process can be adjusted by regulating the Ge atom concentration (e.g., Ge content) in the first NS layer 820a. As discussed above, the Ge content in the first NS layer 820a can be in the range of about 20% to about 30%. A SiGe nanosheet with about 20% Ge can be etched more slowly than a SiGe nanosheet with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve the desired etch rate and selectivity between the first NS layer 820a and the NS layer 120.

[0057] Referring to Figures 9 and 10, once the recessed structure 945 is formed, a dielectric layer can be deposited over the entire structure in Figure 9 in a blanket manner, and a portion of the dielectric layer on the outside of the recessed structure 945 can be removed, leaving the inner spacer structure 130 that fills the recessed structure 945, as illustrated with reference to Figure 10.

[0058] Referring to Figure 4A, method 400 can proceed to operation 430, wherein a source / drain (S / D) region is formed adjacent to the channel region. For example, as illustrated with reference to Figure 11, the S / D epitaxial structure 125 can be formed by epitaxially growing a semiconductor material in the opening 840 and adjacent to the N / S layer 120.

[0059] In some embodiments, as illustrated with FIG11, the S / D epitaxial structure 125 can be epitaxially grown using a CVD process similar to that used in operation 410 to form the first and second NS layers 520a and 520b, as illustrated with FIG5. In some embodiments, the S / D epitaxial structure 125 can be epitaxially grown on the side surface of the second NS layer 120 in a horizontal direction (e.g., along the x-axis). In some embodiments, the S / D epitaxial structure 125 can be epitaxially grown on the top surface of the fin structure 110 in a vertical direction (e.g., along the z-axis). In some embodiments, the S / D epitaxial structure 125 can be grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, or a combination thereof) can be used to grow a semiconductor material (e.g., Si) having a crystal structure that is the same as or similar to the crystal structure of the NS layer 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) can be used to selectively remove semiconductor material having an amorphous structure formed on a dielectric surface (e.g., the side surfaces of the inner spacer structure 130 and the gate spacer 135). Removing the semiconductor material with an amorphous structure ensures that the crystal structure of the S / D epitaxial structure 125 is crystalline. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsine (AsH3), antimonyane (SbH3), or a combination thereof, can be used in a CVD or PECVD process to dope the S / D epitaxial structure 125.

[0060] Referring to Figure 4A, method 400 can proceed to operation 440, wherein an IL is formed on the channel region. Prior to the formation of the IL, the surface of the channel region can be exposed by removing the sacrificial gate structure 700 and the first NS layer 920a, as illustrated with reference to Figure 12. In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a, and subsequently removing the sacrificial gate electrode 700a to expose the fin structure 620 between the S / D epitaxial structures 125. In some embodiments, removing the first NS layer 920a may include selectively etching the first NS layer 920a without removing the NS layer 120, as illustrated with reference to Figure 12.

[0061] After the surface of the channel region is exposed, an IL can be formed on the channel region. For example, as illustrated with reference to FIG13, an IL 115a can be formed on the exposed surface of the NS layer 120. Accompanying the formation of the IL 115a, a dielectric layer 166 can be formed on the exposed top surface of the S / D epitaxial structure 125. Operation 440 is further described in detail with reference to FIG14-17 regarding one of the magnified regions 1300 shown in FIG13, as shown in FIG4B.

[0062] Referring to Figure 4B, operation 440 begins with operation 442, which involves forming a SiO x layer on the channel region. For example, as illustrated with reference to Figure 14, a SiO x layer 1415 may be formed on the NS layer 120. In some embodiments, the SiO x layer 1415 may be formed by exposing the surface of the NS layer 120 to a chemical solution, such as deionized water (DI water), carbonated DI water (DICO 2), ozonated DI water (DIO 3), hydrogen peroxide (H 2O 2), sulfuric acid (H 2SO 4), chloric acid (HCl), ammonia (NH 4OH), or a combination thereof. In some embodiments, the chemical solution may be heated to a temperature above room temperature. For example, the temperature of the chemical solution may be about 50 °C. In some embodiments, Si atoms at the surface of the NS layer 120 may be oxidized by the chemical solution to form the SiO x layer 1415. By exposing the surface of the NS layer 120 to a chemical solution, the oxidation of Si atoms at the surface of the NS layer 120 is incomplete, such that the SiO x layer 1415 comprises Si atoms in the Si 3+, Si 2+, or Si 1+ states, having dangling bonds corresponding to oxygen vacancies 1470. In some embodiments, the oxidation of Si atoms at the surface of the NS layer 120 can form a SiO x layer 1415 with a thickness d1 between about 0.2 nm and about 2 nm. The presence of the SiO x layer 1415 above the surface of the NS layer 120 prevents further oxidation into the NS layer 120. In some embodiments, the top surface of the S / D epitaxial structure 125 can also be exposed to a chemical solution, and the Si atoms at the top surface of the S / D epitaxial structure 125 can also be oxidized to form a dielectric layer 1425 on the S / D epitaxial structure 125, similar to the procedure for forming the SiO x layer 1415. In some embodiments, dielectric layer 1425 may have a chemical composition that is the same as or similar to that of SiO x layer 1415. For example, dielectric layer 1425 may also include SiO x. In some embodiments, dielectric layer 1425 may have a thickness that is the same as or similar to that of SiO x layer 1415.

[0063] Referring to Figure 4B, operation 440 continues with operation 444, which involves depositing a metal oxide layer on the SiO x layer. For example, as illustrated with Figure 15, a metal oxide layer 1515 may be deposited on the SiO x layer 1415. In some embodiments, depositing the metal oxide layer 1515 may include depositing a metal oxide material having a metal element from Group III of the periodic table, such as yttrium (Y), scandium (Sc), argon (Lu), lanthanum (La), lanthanides, strontium (Sr), zinc (Zn), and / or a combination thereof. For example, depositing the metal oxide layer 1515 may include depositing yttrium oxide (Y₂O₃). In some embodiments, the metal oxide material may also include zinc (Zn). In some embodiments, the metal oxide layer 1515 may be deposited using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process to conformally cover the exposed surface of the SiO x layer 1415. In some embodiments, during the deposition process, the thickness of the metal oxide layer 1515 can be controlled to be between about 5 nm and about 20 nm. In some embodiments, along with the deposition of the metal oxide layer 1515, a metal oxide layer 1525 may also be deposited on the dielectric layer 1425. The metal oxide layers 1515 and 1525 may have the same or similar chemical composition and thickness.

[0064] Referring to Figure 4B, operation 440 continues with operation 446 and a process for annealing the metal oxide layer and the SiO x layer. This annealing process can transform the SiO x layer into a SiO 2 layer. The annealing process can also form a silicate layer between the SiO 2 layer and the metal oxide layer. For example, as illustrated with Figure 16, an annealing process 1650 can promote the diffusion of oxygen atoms from the metal oxide layer 1515 into the SiO x layer 1415, and replace oxygen vacancies 1470 by bonding with Si atoms in the Si 3+, Si 2+, or Si 1+ states. By controlling the parameters of the annealing process 1650, such as temperature and duration, oxygen vacancies 1470 in the SiO x layer 1415 can be sufficiently reduced or removed, so that the SiO x layer 1415 is transformed into IL 115a with SiO 2, thereby improving the quality of IL 115a. In some embodiments, the temperature of the annealing process 1650 may be between about 450 °C and about 700 °C. In some embodiments, the duration of the annealing process 1650 may be between about 10 seconds and about 60 seconds.

[0065] In some embodiments, the metal oxide layer 1515 may react with Si atoms 1675 (or a transformation of SiO2) near the surface of the SiOx layer 1415 to form a silicate layer 1615. For example, the Y2O3 of the metal oxide layer 1515 can react with SiOx according to the equation Y2O3 + SiOx → Y2(SiOx) + 3O, releasing approximately 53 ± 5 kJ / mol of energy. The energy released in the reaction can further promote the diffusion of additional oxygen atoms generated in the reaction into the SiOx layer 1415 and reduce the total number of oxygen vacancies 1470. The SiOx consumed in the reaction can reduce the thickness of the SiOx layer 1415 to d2. In some embodiments, a thickness reduction Δd (a difference between thicknesses d1 and d2) may be approximately 0.1 nm. In some embodiments, a ratio between the thickness reduction Δd and the thickness d1 may be between approximately 5% and approximately 20%. In some embodiments, the annealing process 1650 may also be applied to the dielectric layer 1425 and the metal oxide layer 1525 on the S / D epitaxial structure 125. For example, similar to the formation of the silicate layer 1615, the silicate layer 1625 may be formed between the dielectric layer 1425 and the metal oxide layer 1525, and oxygen vacancies in the dielectric layer 1425 may be reduced or removed, transforming SiO₂ in the dielectric layer 1425 into SiO₂.

[0066] Referring to Figure 4B, operation 440 continues with operation 448 and a procedure for removing the metal oxide layer and silicate layer. For example, metal oxide layers 1515 and 1525 and silicate layers 1615 and 1625 as shown in Figure 16 can be removed, leaving IL 115a and dielectric layer 166, as illustrated with Figure 17. In some embodiments, removing the metal oxide layer and silicate layer may include performing a wet etching procedure in a chemical solution. In some embodiments, the chemical solution may include DI water, H₂O₂, HCl, DiCO₂, or a combination thereof. For example, the chemical solution may include a mixture of H₂O₂, HCl, and DI water. In some embodiments, the temperature of the chemical solution may be at or above room temperature. For example, the temperature of the chemical solution may be about 50 °C. In some embodiments, after removing the silicate layer, a small amount of residual metal elements (e.g., Y) may be present in IL 115a. In some embodiments, the properties of IL 115a as shown in FIG. 17 and SiO x layer 1415 as shown in FIG. 14 can be compared by XPS as shown in FIG. 3. After operations 442-448, IL 115a formed on NS layer 120 may have: (i) its Si atoms are in the Si 4+ state, with robust thermal stability; and (ii) its thickness is reduced.

[0067] Referring to Figure 4A, method 400 may continue with operations 450 and procedures including depositing a gate dielectric layer on the IL and depositing a gate electrode on the gate electrode layer to form a metal gate structure. For example, as illustrated with reference to Figure 18, a gate dielectric layer 115b may be deposited on the IL 115a, and a gate electrode 115c may be deposited on the gate dielectric layer 115b to form a metal gate structure 115. As described above, the metal gate structure 115 is electrically isolated from the S / D epitaxial structure 125 by an inner spacer structure 130 and a gate spacer 135. In some embodiments, depositing the gate dielectric layer 115b may include depositing a high-k dielectric material (e.g., HfO 2, Al 2O 3, ScO 2, ZrO 2, CaO, MgO, and / or ZrSiO 4) in a CVD or ALD process. In some embodiments, the deposited gate dielectric layer 115b may further include the deposition of a lanthanum oxide (La₂O₃) layer to form an N-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the deposited gate electrode 115c may include the deposition of one or more work function metal layers and an electrode contact layer (e.g., titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel) in a CVD or ALD process. In some embodiments, after forming the metal gate structure 115, an ILD layer 165 may be formed to fill the space above the S / D epitaxial structure 125, as illustrated with reference to FIG19. In some embodiments, one or more of dielectric layers 152, 154, and 156 may be formed above the metal gate structure 115 and the ILD layer 165 by sequentially depositing dielectric layers such as silicon oxide and silicon nitride, as illustrated with reference to FIG19.

[0068] Referring to Figure 4A, method 400 can continue with operation 460 and procedure for forming contact structures on the gate electrode and S / D region. For example, gate contact via 167 can be formed on gate electrode 115c, and S / D contact 163 can be formed on S / D epitaxial structure 125, as illustrated with reference to Figure 2.

[0069] In some embodiments, forming the gate contact via 167 may include: (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 to expose the gate electrode 115c; and (ii) depositing a metallic material (e.g., W, Cu and / or Mo) in the opening.

[0070] In some embodiments, forming the S / D contact 163 may include: (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 and through the ILD layer 165 and the dielectric layer 166 to expose the S / D epitaxial structure 125; (ii) forming a silicon layer 164 on the S / D epitaxial structure 125; and (iii) depositing a metallic material (e.g., W, Cu and / or Mo) in the opening.

[0071] The embodiments described herein pertain to a structure of a semiconductor device and a method for forming the structure. The structure may include a transistor on a substrate. The transistor may include a channel region, a source / drain region adjacent to the channel region, and a gate structure on the channel region. The gate structure may include an IL on a surface of the channel region, a gate dielectric layer on the IL, and a gate electrode on the gate dielectric layer. The IL may include SiO₂ with an O-to-Si ratio of approximately 2 and may be free of dangling bonds and oxygen vacancies. The method for forming the structure may include forming a SiOₓ layer on the channel region, depositing a metal oxide layer on the SiOₓ layer, and performing an annealing process to promote the diffusion of oxygen atoms from the metal oxide layer into the SiOₓ layer, thereby reducing and removing oxygen vacancies in the SiOₓ layer. The annealing process may improve the quality of the IL by transforming the SiOₓ layer into a SiO₂ layer. The method may further include removing the metal oxide layer and depositing the gate dielectric layer and the gate electrode on the IL to form the gate structure on the channel region.

[0072] In some embodiments, a method includes: forming a channel region in a fin structure on a substrate; forming a source / drain (S / D) region adjacent to the channel region; forming an interface layer (IL) on the channel region; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer. In some embodiments, forming the IL includes: forming a silicon oxide layer on the channel region; depositing a yttrium oxide layer on the silicon oxide layer; annealing the yttrium oxide layer and the silicon oxide layer to reduce a density of oxygen vacancies in the silicon oxide layer; and removing the yttrium oxide layer.

[0073] In some embodiments, the annealed yttrium oxide layer and the silicon oxide layer comprise a silicate layer formed between the yttrium oxide layer and the silicon oxide layer.

[0074] In some embodiments, forming the IL further includes removing the silicate layer after removing the yttrium oxide layer.

[0075] In some embodiments, annealing the yttrium oxide layer and the silicon oxide layer includes converting the silicon oxide layer into a silicon dioxide layer.

[0076] In some embodiments, the annealed yttrium oxide layer and silicon oxide layer include increasing the oxygen-to-silicon ratio in the IL.

[0077] In some embodiments, depositing a yttrium oxide layer includes depositing the yttrium oxide layer by an atomic layer deposition process.

[0078] In some embodiments, forming a silica layer involves using a chemical solution of one of deionized water (DI water), carbonated DI water (DICO 2), ozonated DI water (DIO 3), hydrogen peroxide (H 2O 2), sulfuric acid (H 2SO 4), chloric acid (HCl), or ammonia (NH 4OH) to form the silica layer.

[0079] In some embodiments, a method includes forming a nanostructure in a fin structure, forming a source / drain (S / D) region adjacent to the nanostructure, and forming a gate structure surrounding the nanostructure. In some embodiments, forming the gate structure includes: forming an interface layer (IL) on the nanostructure, wherein the IL comprises oxygen and silicon; increasing the oxygen-to-silicon ratio in the IL; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.

[0080] In some embodiments, increasing the oxygen-to-silicon ratio in the IL includes: depositing a yttrium oxide layer on the IL; annealing the yttrium oxide layer and the IL; and removing the yttrium oxide layer.

[0081] In some embodiments, the annealed yttrium oxide layer and the IL are included in forming a silicate layer between the yttrium oxide layer and the IL.

[0082] In some embodiments, increasing the oxygen-to-silicon ratio in the IL includes reducing the thickness of the IL.

[0083] In some embodiments, reducing the thickness of the IL includes reducing the thickness of the IL by about 5% to about 20%.

[0084] In some embodiments, increasing the oxygen-to-silicon ratio in the IL includes removing oxygen vacancies in the IL.

[0085] In some embodiments, increasing the oxygen-to-silicon ratio in the IL includes increasing the oxygen-to-silicon ratio in the IL to approximately 2:1.

[0086] In some embodiments, a structure includes a substrate and a fin structure on the substrate, wherein the fin structure includes a channel region. The structure further includes: a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region. The gate structure includes an interface layer (IL) on the channel region, a high-k dielectric layer on the IL, a work function layer on the high-k dielectric layer, and a gate electrode on the work function layer. The IL comprises silicon dioxide. The oxygen-to-silicon ratio in the IL is approximately 2:1.

[0087] In some embodiments, the IL is in contact with the top, bottom, and side surfaces of the channel region.

[0088] In some embodiments, the thickness of the IL is approximately 1 nm.

[0089] In some embodiments, IL comprises yttrium, scandium, lanthanum, zinc, or diurethane.

[0090] In some embodiments, the structure further includes an oxide layer on the S / D region, wherein the oxide layer and the IL have substantially the same thickness.

[0091] In some embodiments, the structure further includes an oxide layer on the S / D region, wherein another ratio of oxygen to silicon in the oxide layer is about 2:1.

[0092] It will be understood that Section B, which describes the implementation methods, rather than the summary section of the disclosure, is intended to explain the scope of the claims. This summary section of the disclosure may illustrate one or more, but not all, possible embodiments of the disclosure as conceived by the inventors, and is therefore not intended to limit the scope of the appended claims in any way.

[0093] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as the basis for designing or modifying other programs and structures to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0094] 100: Semiconductor devices 102: Matrix 105: Transistor 110,620: Fin structure 115: Gate Structure 115a:IL 115b: Gate dielectric layer 115c: Gate electrode 120: Nanosheets, NS layer 125: S / D epitaxial structure 130: Inner spacer structure 135: Gate spacer 138: Shallow trench isolation zone, STI zone 152, 154, 156, 166, 1425: Dielectric layer 163:S / D contact 164: Silicon layer 165: Interlayer dielectric layer, ILD layer 167: Gate contact via 310: Main Peak 320, 330: Satellite peaks 400: Manufacturing Method 400: Method 410, 420, 430, 440, 442, 444, 446, 448, 450, 460: Operations 520: Stacking 520a, 820a, 920a: First NS layer 520b: Second NS layer 620a: First NS layer, NS layer 620b: Second NS layer, NS layer 700: Sacrificial gate structure 700a: Sacrificial gate electrode 705: Covering layer 840: Opening 945: Recessed structure 1300: Magnified area 1415: SiOx layer 1470: Oxygen Deficiency 1515, 1525: Metal oxide layer, metal oxide 1615, 1625: Silicate layer 1650: Annealing Procedure 1675: Si atom AB: Cutting line AB: Line d1, d2: Thickness Ed: Energy difference Es: Energy Lc: Length Δ: difference Δd: Thickness reduction

Claims

1. A method for forming an interface layer of a gate structure of a semiconductor device, comprising: forming a channel region in a fin structure on a substrate; forming a source / drain (S / D) region adjacent to the channel region; forming an interface layer (IL) on the channel region, wherein forming the IL comprises: forming a silicon oxide layer on the channel region; depositing a yttrium oxide layer on the silicon oxide layer; annealing the yttrium oxide layer and the silicon oxide layer to reduce the density of oxygen vacancies in the silicon oxide layer; and removing the yttrium oxide layer; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.

2. The method of claim 1, wherein annealing the yttrium oxide layer and the silicon oxide layer comprises forming a silicate layer between the yttrium oxide layer and the silicon oxide layer.

3. The method of claim 1 or 2, wherein annealing the yttrium oxide layer and the silicon oxide layer includes converting the silicon oxide layer into a silicon dioxide layer.

4. The method of claim 1 or 2, wherein annealing the yttrium oxide layer and the silicon oxide layer comprises increasing the oxygen-to-silicon ratio in the IL.

5. A method of forming a structure of a semiconductor device, comprising: forming a nanostructure in a fin structure; forming a source / drain (S / D) region adjacent to the nanostructure; and forming a gate structure surrounding the nanostructure, wherein forming the gate structure comprises: forming an interface layer (IL) comprising oxygen and silicon on the nanostructure; increasing the oxygen-to-silicon ratio in the IL; depositing a high-k dielectric layer on the IL; and depositing a gate electrode on the high-k dielectric layer.

6. The method of claim 5, wherein increasing the oxygen-to-silicon ratio in the IL comprises: depositing a yttrium oxide layer on the IL; annealing the yttrium oxide layer and the IL layer; and removing the yttrium oxide layer.

7. The method of claim 5 or 6, wherein increasing the oxygen-to-silicon ratio in the IL comprises reducing the thickness of the IL.

8. A structure of a semiconductor device comprising: a substrate; a fin structure on the substrate, wherein the fin structure includes a channel region; a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region, wherein the gate structure includes: an interface layer (IL) on the channel region, wherein the IL comprises silicon dioxide, wherein the oxygen-to-silicon ratio in the IL is approximately 2:1; a high-k dielectric layer on the IL; a work function layer on the high-k dielectric layer; and a gate electrode on the work function layer.

9. The structure of claim 8, wherein the IL is in contact with the top, bottom and side surfaces of the channel area.

10. The structure of request item 8 or 9, wherein the IL contains yttrium, scandium, lanthanum, zinc or diurethane.

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