Magnetic memory device

Abstract

This invention provides a magnetic memory device capable of improving operational performance. The magnetic memory device of this embodiment includes a memory cell MC, a constant current source CS, switches S1, S2, and S3, a peak detection circuit 51, and a sensing amplifier SA. The memory cell includes a variable resistor element VR and a selector element SE. The constant current source CS supplies current Ipc to the memory cell. Switch S1 is connected between the memory cell and the constant current source CS. Switch S2 is connected between a ground voltage node and the memory cell. The peak detection circuit 51 includes a comparator CP and a diode D1. The voltage Vm charged into the memory cell is input to the first input terminal of the comparator via the diode, and the voltage Vm is also input to the second input terminal of the comparator. The sensing amplifier SA compares the voltage Vm with a reference voltage Vref. Switch S3 is connected between the memory cell and the sensing amplifier SA.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to a magnetic memory device. [Previous Technology]

[0002] It is known that there is a magnetic memory device (MRAM: Magnetoresistive Random Access Memory) that uses a magnetoresistive element as a memory element. [Summary of the Invention]

[0003] The present invention provides a magnetic memory device that can improve motion performance.

[0004] The magnetic memory device according to the embodiment includes a memory cell, a current source, a first switch, a second switch, a detection circuit, a sensing amplifier, and a third switch. The memory cell includes a variable resistor element and a selector element. The current source supplies a first current to the memory cell. The first switch is connected between the memory cell and the current source. The second switch is connected between a ground voltage node supplied with a ground voltage and the memory cell. The detection circuit includes a comparator and a diode. The first voltage charged into the memory cell is input to the first input terminal of the comparator via the diode, and the first voltage is also input to the second input terminal of the comparator. The sensing amplifier compares the first voltage charged into the memory cell with the second voltage. The third switch is connected between the memory cell and the sensing amplifier.

Implementation Method

[0006] Hereinafter, embodiments will be described with reference to the drawings. In the following description, common reference numerals are used to mark constituent elements having the same function and structure. Furthermore, the embodiments shown below illustrate apparatus or methods for embodying the technical concept of the embodiments, and do not specify the material, shape, structure, and arrangement of the constituent parts as described below.

[0007] 1. First Embodiment First, an example of a memory system including the magnetic memory device of the first embodiment will be described. FIG1 is a block diagram showing the configuration of a memory system MS including the magnetic memory device of the first embodiment.

[0008] As shown in Figure 1, the memory system MS includes a magnetic memory device 1 and a memory controller 2. The magnetic memory device 1 performs actions based on the control of the memory controller 2. The memory controller 2 can respond to requests (or commands) from an external host machine, commanding the magnetic memory device 1 to perform read and write operations, etc.

[0009] 1.1 Configuration of the magnetic memory device Next, referring to FIG1, the configuration of the magnetic memory device 1 of the first embodiment will be described.

[0010] The magnetic memory device 1 is a type of resistance-varying memory. The magnetic memory device 1 is a memory device that uses an MTJ (Magnetic Tunnel Junction) element in the memory cell. The MTJ element utilizes the magnetoresistance effect of the magnetic tunnel junction. The MTJ element is also known as a magnetoresistance effect element.

[0011] The magnetic memory device 1 includes, for example, a memory cell array 11, an input / output circuit 12, a control circuit 13, a column selection circuit 14, a row selection circuit 15, a write circuit 16, and a read circuit 17.

[0012] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Figure 1 shows a set of memory cells MC, word lines WL, and bit lines BL. Memory cells MC can non-volatilely store data. Memory cells MC are connected between one word line WL and one bit line BL, establishing a correspondence with groups of columns. Column addresses are assigned to word lines WL. Row addresses are assigned to bit lines BL. One or more memory cells MC can be specified by selecting one column and one or more rows.

[0013] Input / output circuit 12 is connected to memory controller 2 and manages the communication between magnetic memory device 1 and memory controller 2. Input / output circuit 12 transmits the control signal CNT and instruction CMD received from memory controller 2 to control circuit 13. Furthermore, input / output circuit 12 transmits the column address and row address contained in the address signal ADD received from memory controller 2 to column selection circuit 14 and row selection circuit 15, respectively. Input / output circuit 12 transmits the data DAT (write data) received from memory controller 2 to write circuit 16. Input / output circuit 12 transmits the data DAT (read data) received from read circuit 17 to memory controller 2.

[0014] The control circuit 13 controls the overall operation of the magnetic memory device 1. For example, the control circuit 13 performs read or write operations based on the control signal CNT and the control command CMD. For example, during a write operation, the control circuit 13 supplies the voltage and control signal for writing data to the write circuit 16. Similarly, during a read operation, the control circuit 13 supplies the voltage and control signal for reading data to the read circuit 17.

[0015] Column selection circuit 14 is connected to a plurality of word lines WL. Column selection circuit 14 selects one word line WL specific to the column address. The selected word line WL is electrically connected, for example, to a drive circuit omitted in the figure.

[0016] The row selection circuit 15 is connected to a plurality of bit lines BL. The row selection circuit 15 selects one or a plurality of bit lines BL that are specific to the row address. The selected bit line BL is electrically connected, for example, to a drive circuit that is omitted in the figure.

[0017] The write circuit 16, based on the control of the control circuit 13 and the data DAT (write data) received from the input / output circuit 12, supplies the voltage for data writing to the row selection circuit 15. When the current based on the write data flows through the memory cell MC, the required data is written into the memory cell MC.

[0018] The readout circuit 17 includes a sense amplifier. Based on the control of the control circuit 13, the readout circuit 17 supplies a voltage for data readout to the column selection circuit 14 and the row selection circuit 15. The sense amplifier determines the data stored in the memory cell MC based on the voltage or current of the selected memory cell MC and the word line WL. Then, the readout circuit 17 transmits the data DAT (readout data) corresponding to the determination result to the input / output circuit 12. Details regarding the readout circuit 17 will be described below.

[0019] 1.1.1 Circuit Configuration of Memory Cell Array Referring to FIG2, an example of the circuit configuration of the memory cell array 11 provided in the magnetic memory device 1 of the first embodiment will be described. FIG2 is a circuit diagram showing the configuration of the memory cell array 11 provided in the magnetic memory device 1. FIG2 shows WL0 and WL1 of a plurality of word lines WL and BL0 and BL1 of a plurality of bit lines BL.

[0020] As shown in Figure 2, one memory cell MC is connected between WL0 and BL0, between WL0 and BL1, between WL1 and BL0, and between WL1 and BL1. A plurality of memory cells MC are arranged in a matrix, for example, within the memory cell array 11.

[0021] Each memory cell MC includes a variable resistor element VR and a selector element SE. The variable resistor element VR and the selector element SE are connected in series between the associated bit line BL and word line WL. For example, one end of the variable resistor element VR is connected to the bit line BL. The other end of the variable resistor element VR is connected to one end of the selector element SE. The other end of the selector element SE is connected to the word line WL. Alternatively, the connection relationship between the variable resistor element VR and the selector element SE between the bit line BL and the word line WL can also be reversed. That is, one end of the variable resistor element VR is connected to the word line WL, and the other end of the variable resistor element VR is connected to one end of the selector element SE. The other end of the selector element SE can also be connected to the bit line BL.

[0022] The variable resistor element VR corresponds to an MTJ element (i.e., a magnetoresistive element). The variable resistor element VR can non-volatilely store data based on its resistance value. For example, the memory cell MC of the variable resistor element VR, which contains a high resistance state, stores "1" data. The memory cell MC of the variable resistor element VR, which contains a low resistance state, stores "0" data. The allocation of data associated with the resistance value of the variable resistor element VR can also be otherwise set. The resistance state of the variable resistor element VR can change according to the current flowing through the variable resistor element VR.

[0023] The selector element SE is, for example, a bidirectional diode with a sudden return characteristic. The selector element SE functions as a selector that controls the supply of current to the associated variable resistor element VR.

[0024] Specifically, a selector element SE included in a memory cell MC is in an off state (or non-conducting state) when the voltage applied to the memory cell MC is lower than the threshold voltage of the selector element SE, and in an on state (or conducting state) when the voltage rises above the threshold voltage of the selector element SE. In the off state, the selector element SE functions as an insulator with a higher resistance. When the selector element SE is in the off state, current flow between the word line WL and the bit line BL connected to the memory cell MC is suppressed. In the on state, the selector element SE functions as a conductor with a lower resistance. When the selector element SE is in the on state, current flows between the word line WL and the bit line BL connected to the memory cell MC. That is, the selector element SE can switch whether current flows based on the magnitude of the voltage applied to the memory cell MC, regardless of the direction of current flow. The backflow characteristic of the selector element SE will be described below. Furthermore, other components such as transistors can also be used as selector elements (SE).

[0025] 1.1.2 Structure of Memory Cell Array Referring to FIG3, an example of the structure of the memory cell array 11 provided in the magnetic memory device 1 of the first embodiment will be described. FIG3 is a perspective view showing the structure of the memory cell array 11 provided in the magnetic memory device 1. In the following description, the XYZ orthogonal coordinate system is used. The X direction corresponds to the extension direction of the character line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used to form the magnetic memory device 1. The term "down" and its derivatives and related terms indicate the position of a smaller coordinate on the Z-axis. The term "up" and its derivatives and related terms indicate the position of a larger coordinate on the Z-axis. Shading lines are appropriately added to the perspective view. The shading lines added to the perspective view are not necessarily related to the material or characteristics of the constituent elements to which the shading lines are added. In the perspective view and cross-sectional view, the illustrations of the structure such as the interlayer insulating film are omitted.

[0026] As shown in Figure 3, the memory cell array 11 includes a plurality of conductive layers 20, a plurality of conductive layers 21, and a plurality of memory cells MC.

[0027] Each of the plurality of conductive layers 20 has a portion extending in the X direction. The plurality of conductive layers 20 are arranged side by side and separated from each other in the Y direction. Each conductive layer 20 serves as a character line WL.

[0028] Each of the plurality of conductive layers 21 has a portion extending in the Y direction. The plurality of conductive layers 21 are arranged side by side and separated from each other in the X direction. Each conductive layer 21 serves as a bit line BL.

[0029] A wiring layer comprising a plurality of conductive layers 21 is disposed above a wiring layer comprising a plurality of conductive layers 20. A memory cell MC is disposed at the intersection of the plurality of conductive layers 20 and the plurality of conductive layers 21. In other words, each memory cell MC is disposed between the associated word line WL and bit line BL. Each memory cell MC has a columnar structure. In this example, a selector element SE is disposed above the conductive layer 20. A variable resistor element VR is disposed above the selector element SE. A conductive layer 21 is disposed above the variable resistor element VR.

[0030] Furthermore, although the example shown is of the variable resistor element VR being positioned above the selector element SE, it is not limited to this. Depending on the circuit configuration of the memory cell array 11, the variable resistor element VR can also be positioned below the selector element SE. Additionally, other components or conductive layers can be inserted between the memory cell MC and the conductive layer 20. Similarly, other components or conductive layers can be inserted between the memory cell MC and the conductive layer 21. Both conductive layers 20 and 21 can also be referred to as "wiring".

[0031] 1.1.3 Cross-sectional structure of memory cells Referring to FIG4, an example of the memory cells MC included in the memory cell array 11 of the magnetic memory device 1 of the first embodiment will be described. FIG4 is a cross-sectional view of the memory cells MC included in the memory cell array 11.

[0032] As shown in Figure 4, the memory cell MC has, for example, the following structure: from the conductor layer 20 upward (Z direction), a lower electrode 30, a selector material layer 31, an upper electrode 32, a ferromagnetic layer 40, a nonmagnetic layer 41, and a ferromagnetic layer 42 are sequentially stacked.

[0033] That is, the lower electrode 30 is disposed above the conductive layer 20 (in the Z direction). The selector material layer 31 is disposed above the lower electrode 30. The upper electrode 32 is disposed above the selector material layer 31. The ferromagnetic layer 40 is disposed above the upper electrode 32. The non-magnetic layer 41 is disposed above the ferromagnetic layer 40. The ferromagnetic layer 42 is disposed above the non-magnetic layer 41. The conductive layer 21 is disposed above the ferromagnetic layer 42.

[0034] In other words, the non-magnetic layer 41 is disposed between the ferromagnetic layer 40 and the ferromagnetic layer 42. The ferromagnetic layer 40 is disposed between the non-magnetic layer 41 and the upper electrode 32. The upper electrode 32 is disposed between the ferromagnetic layer 40 and the selector material layer 31. The selector material layer 31 is disposed between the upper electrode 32 and the lower electrode 30. The lower electrode 30 is disposed between the selector material layer 31 and the conductive layer 20. Furthermore, the ferromagnetic layer 42 is disposed between the non-magnetic layer 41 and the conductive layer 21.

[0035] The group of lower electrode 30, selector material layer 31, and upper electrode 32 corresponds to selector element SE. The group of ferromagnetic layer 40, non-magnetic layer 41, and ferromagnetic layer 42 corresponds to variable resistor element VR.

[0036] Each of the ferromagnetic layers 40 and 42 is made of a ferromagnetic material and has a magnetization direction perpendicular to the film surface. In the magnetic memory device 1, for example, the magnetization direction of the ferromagnetic layer 40 is fixed, while the magnetization direction of the ferromagnetic layer 42 is variable. In this case, the ferromagnetic layer 40 functions as a reference layer of the MTJ element, and the ferromagnetic layer 42 functions as a storage layer of the MTJ element. The non-magnetic layer 41 is made of an insulator such as MgO and functions as a tunnel barrier layer. The ferromagnetic layers 40 and 42 together with the non-magnetic layer 41 form a magnetic tunneling junction. This variable resistance element VR functions as a vertically magnetized MTJ element utilizing the TMR (tunneling magnetoresistive) effect.

[0037] The ferromagnetic layer 40, for example, comprises at least one element selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni). The non-magnetic layer 41, for example, comprises an oxide of at least one element or compound selected from the group consisting of magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and LSM (lanthanum-strontium-manganese). The ferromagnetic layer 42, for example, comprises at least one element selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni).

[0038] The variable resistor element VR can take on either a low-resistance state or a high-resistance state depending on the relative magnetization directions of the ferromagnetic layers 40 and 42. Furthermore, the variable resistor element VR stores data based on the magnetization direction of the ferromagnetic layer 42 (memory layer). For example, a variable resistor element VR in which the magnetization directions of the reference layer and the memory layer are antiparallel (AP state) becomes a high-resistance state ("1" data). On the other hand, a variable resistor element VR in which the magnetization directions of the reference layer and the memory layer are parallel (P state) becomes a low-resistance state ("0" data).

[0039] In this example, the variable resistor element VR is in the AP state when the write current flows from the ferromagnetic layer 40 to the ferromagnetic layer 42, and in the P state when the write current flows from the ferromagnetic layer 42 to the ferromagnetic layer 40. The writing method that injects spin torque into the memory layer and reference layer by flowing a write current through the variable resistor element VR, thereby controlling the magnetization direction of the memory layer, is called a spin injection writing method. The variable resistor element VR is configured such that when a current of magnitude capable of reversing the magnetization direction of the ferromagnetic layer 42 flows through the variable resistor element VR, the magnetization direction of the ferromagnetic layer 40 does not change.

[0040] Furthermore, in this specification, "magnetization direction variable" means that the magnetization direction changes due to the write current. "Magnetization direction fixed" means that the magnetization direction does not change due to the write current. In the variable resistor element VR, the configuration of the memory layer and the reference layer can also be interchanged. Also, the variable resistor element VR may also have other layers. For example, the variable resistor element VR may also have a shift elimination layer to suppress the influence of the leakage magnetic field of the reference layer, or a SAF (Synthetic Anti-Ferromagnetic) structure, etc. Hereinafter, the memory cell MC of the variable resistor element VR containing the AP state will be referred to as the AP state memory cell MC, and the memory cell MC of the variable resistor element VR containing the P state will be referred to as the P state memory cell MC.

[0041] 1.1.4 Circuit Configuration of the Readout Circuit Referring to FIG5, an example of the circuit configuration of the readout circuit 17 provided in the magnetic memory device 1 of the first embodiment will be described. FIG5 is a circuit diagram showing the configuration of the readout circuit 17 of the magnetic memory device 1. FIG5 shows the readout circuit 17, a pair of bit lines BL and word lines WL included in the memory cell array 11, and memory cells MC.

[0042] As shown in Figure 5, the readout circuit 17 includes a constant current source CS, a power supply VH, a peak detection circuit 51, a delay circuit 52, a sensing amplifier SA, a pre-charge switch S1, a sink switch S2, and a sensing amplifier switch S3. The peak detection circuit 51 includes a comparator CP and a diode D1.

[0043] A constant current source CS is connected to the character line WL via a pre-charge switch S1. A power supply VH is connected to the constant current source CS.

[0044] The character line WL is connected to the first input terminal of the sense amplifier SA via the sense amplifier switch S3. A reference voltage Vref is supplied to the second input terminal of the sense amplifier SA. The sense amplifier SA compares the voltage Vm of the memory cell MC (or selector element SE) and the character line WL input to the first input terminal with the reference voltage Vref, and outputs a signal SO based on the comparison result.

[0045] The character line WL is connected to the positive input terminal (or non-inverting input terminal) of the comparator CP via diode D1. Furthermore, the character line WL is connected to the negative input terminal (or inverting input terminal) of the comparator CP.

[0046] The output terminal of comparator CP is connected to the input terminal of delay circuit 52. The output terminal of delay circuit 52 is connected to the control terminal of pull-down switch S2 and the control terminal of sense amplifier switch S3. The control terminal of pull-down switch S2 is used to control pull-down switch S2 to any of the following states: connected (or closed, on) or blocked (or open, off). The control terminal of sense amplifier switch S3 is used to control sense amplifier switch S3 to any of the following states: connected or blocked.

[0047] Bit line BL is connected to the ground voltage VSS node via pull-down switch S2. Ground voltage VSS is supplied to the ground voltage VSS node.

[0048] The memory cell MC is connected between the word line WL and the bit line BL. The memory cell MC includes a selector element SE and a variable resistor element VR connected in series. That is, one end of the selector element SE is connected to the word line WL, and one end of the variable resistor element VR is connected to the other end of the selector element SE. Furthermore, the other end of the variable resistor element VR is connected to the bit line BL.

[0049] A constant current source CS supplies a pre-charge current Ipc to the memory cell MC (or selector element SE) and word line WL via a pre-charge switch S1, charging the memory cell MC (or selector element SE) and word line WL. The pre-charge current Ipc is a constant current, and by supplying the pre-charge current Ipc, the voltage Vm of the memory cell MC (or selector element SE) and word line WL gradually increases. The voltage Vm of the memory cell MC (or selector element SE) and word line WL is the voltage between the terminals of the word line WL and the bit line BL of the memory cell MC, respectively, that is, the voltage between the word line WL and the bit line BL of the memory cell MC. Hereinafter, the voltage Vm of the memory cell MC (or selector element SE) and word line WL will be referred to as the voltage Vm of the memory cell MC and word line WL, or the voltage Vm of the memory cell MC.

[0050] When the peak detection circuit 51 supplies the pre-charge current Ipc to the memory cell MC, it detects the peak voltage Vm of the memory cell MC. The peak voltage Vm of the memory cell MC is equivalent to the threshold voltage Vth of the selector element SE of the memory cell MC.

[0051] The memory cell MC is charged by the pre-charge current Ipc supplied by the self-controlled current source CS, causing the voltage Vm of the memory cell MC to rise and reach the threshold voltage Vth. Then, the selector element SE switches to the ON (or ON) state. Here, the cell current Im begins to flow from the memory cell MC through the pull-down switch S2 to the ground voltage VSS node. Afterwards, the voltage Vm of the memory cell MC decreases due to the sudden-back characteristic of the selector element SE, and further decreases due to the cell current Im. Therefore, the threshold voltage Vth becomes the peak voltage of the memory cell MC's voltage Vm.

[0052] The peak detection circuit 51, as described above, includes a comparator CP and a diode D1. The voltage Vm of the memory cell MC is input to the positive input terminal of the comparator CP via the diode D1. The voltage between the cathode of the diode D1 and the positive input terminal of the comparator CP is set as voltage Vd. The voltage Vm of the memory cell MC is input to the negative input terminal of the comparator CP without passing through the diode. Hereinafter, the surge characteristics of the selector element SE of the memory cell MC will be explained with reference to FIG6. FIG6 is a current-voltage characteristic graph showing the surge characteristics of the selector element SE. The horizontal axis represents the voltage Vse applied to the selector element SE. The vertical axis represents the current Ise flowing to the selector element SE.

[0053] When the voltage Vse applied to the selector element SE rises from 0, a small current flows to the selector element SE and gradually increases. The selector element SE is in the off state until the voltage Vse reaches the threshold voltage Vth of the selector element SE.

[0054] The voltage Vse rises further, and when the voltage Vse reaches the threshold voltage Vth at point A, the selector element SE switches to the ON state. Therefore, the voltage Vse drops sharply to point B, and then rises again. The current Ise increases sharply from point B.

[0055] The phenomenon in which the voltage Vse applied to the selector element SE drops sharply when it reaches the threshold voltage Vth of the selector element SE is called a sudden drop characteristic. In this embodiment, using this sudden drop characteristic, the voltage Vm of the memory cell MC is detected to have reached the threshold voltage Vth based on the fact that when the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the voltage Vm immediately drops below the diode voltage Vd.

[0056] The comparator CP of the peak detection circuit 51 compares the voltage Vm of the memory cell MC with the voltage Vd, and determines whether the voltage Vm of the memory cell MC reaches the peak voltage, that is, whether the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE, based on the comparison result. The comparator CP outputs signal O1 based on the determination result.

[0057] When the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the selector element SE switches to the ON state. This initiates the discharge of the charge entering the memory cell MC, i.e., the cell current Im begins to flow from the memory cell MC through the pull-down switch S2 to the ground voltage VSS node.

[0058] For example, when the voltage Vd of diode D1 is lower than the voltage Vm of memory cell MC, the comparator CP outputs a low-level voltage (hereinafter referred to as "L") as a signal O1 indicating that the voltage Vm of memory cell MC has not reached the threshold voltage Vth. On the other hand, when the voltage Vm of memory cell MC reaches the threshold voltage Vth, and then the voltage Vm decreases due to the sudden return characteristic of selector element SE, and the voltage Vd becomes higher than the voltage Vm, the comparator outputs a high-level voltage (hereinafter referred to as "H") higher than "L" as a signal O1 indicating that the voltage Vm of memory cell MC has reached the threshold voltage Vth. Furthermore, the peak detection circuit 51 is set for each character line WL, for example.

[0059] The delay circuit 52 delays the signal O1 output from the comparator CP by a predetermined delay time and outputs a signal O2. Figure 7 is a circuit diagram showing an example of the configuration of the delay circuit 52. For example, as shown in Figure 7(a), the delay circuit 52 has a configuration in which an even number of converters IV are connected in series. Also, as shown in Figure 7(b), it has a configuration including two converters IV and a resistor element R1 and a capacitor element C1 connected between these converters.

[0060] The delay time of the delay circuit 52 is set to be shorter than the time from the moment the voltage Vm of the memory cell MC is detected to reach the threshold voltage Vth, that is, from the moment the cell current Im begins to flow, until the voltage Vm of the memory cell MC decreases to the holding voltage Vh. Furthermore, the holding voltage Vh is the voltage held by the memory cell MC when the cell current Im (or discharge current) stops flowing after the memory cell MC is charged to the threshold voltage Vth.

[0061] The sensing amplifier SA is configured to compare the voltage Vm of the memory cell MC with the reference voltage Vref when reading the data stored in the memory cell MC, and determine the data stored in the memory cell MC based on the comparison result.

[0062] The reference voltage Vref is the threshold voltage used to determine whether data is "0" or "1". For example, when the voltage Vm of the memory cell MC is above Vref, the sensing amplifier SA outputs a voltage corresponding to "1" data as signal SO. On the other hand, when the voltage Vm of the memory cell MC is below Vref, it outputs a voltage corresponding to "0" data as signal SO. Furthermore, the sensing amplifier SA is set for each character line WL, for example.

[0063] The precharge switch S1 is controlled by the control circuit 13 to switch between supplying a precharge current Ipc to the memory cell MC and stopping the supply of a precharge current Ipc to the memory cell MC. The precharge switch S1 is connected between the word line WL (or the memory cell MC) and the constant current source CS. The precharge switch S1, based on the control circuit 13, sets the relationship between the word line WL and the constant current source CS to any of the following states: connected (or closed, on) or blocked (or open, off).

[0064] For example, when the precharge switch S1 is set to the connected state, a precharge current Ipc is supplied from the constant current source CS to the memory cell MC and the word line WL. On the other hand, when the precharge switch S1 is set to the blocked state, the supply of the precharge current Ipc from the constant current source CS to the memory cell MC and the word line WL is stopped. The precharge switch S1 includes, for example, an n-type MOS field-effect transistor.

[0065] The pull-down switch S2 controls the cell current Im flowing from the memory cell MC to the ground voltage VSS node based on the signal O2 output by the self-delay circuit 52. That is, the pull-down switch S2 is a switch that switches between either releasing charge from the memory cell MC or stopping the release of charge from the memory cell MC. The pull-down switch S2 is connected between the bit line BL (or the memory cell MC) and the ground voltage VSS node. The pull-down switch S2 sets the relationship between the bit line BL and the ground voltage VSS node to either a connected state or a blocked state based on the signal O2 from the delay circuit 52. For example, when the pull-down switch S2 is set to the connected state, the cell current Im flows from the memory cell MC to the ground voltage VSS node, releasing the charge charged into the memory cell MC. On the other hand, when the pull-down switch S2 is set to the blocked state, the cell current Im does not flow from the memory cell MC to the ground voltage VSS node, stopping the release of charge charged into the memory cell MC. The pull-down switch S2 includes, for example, an n-type MOS field-effect transistor.

[0066] The sense amplifier switch S3 is set to a blocking state when data is read from the memory cell MC based on the signal O2 output from the delay circuit 52. On the other hand, it is set to a connected state when data is not read from the memory cell MC. The sense amplifier switch S3 is connected between the word line WL (or the memory cell MC) and the sense amplifier SA. The sense amplifier switch S3 sets the word line WL and the sense amplifier SA to either a connected state or a blocking state based on the signal O2 from the delay circuit 52. The sense amplifier switch S3 includes, for example, an n-type MOS field-effect transistor.

[0067] Furthermore, the relationship between the input and output of the positive and negative input terminals of the comparator CP, the order of the converter included in the delay circuit 52, and the polarity of the voltages used to set the pre-charge switch S1, pull-down switch S2, and sense amplifier switch S3 to either the connected or blocked state can be arbitrarily set as long as the configuration enables the operation. For example, when the relationship between the input and output of the positive and negative input terminals of the comparator CP is reversed, the order of the converter in the delay circuit 52 can be set to an odd number.

[0068] 1.2 Read-out Operation of the Magnetic Memory Device Referring to FIG8, the read-out operation of the magnetic memory device 1 according to the first embodiment will be described. FIG8 is a graph showing the voltage changes of the memory cell MC voltage Vm and the diode D1 voltage Vd during the read-out operation of the magnetic memory device 1. In FIG8, the horizontal axis represents time and the vertical axis represents voltage.

[0069] The voltage Vm of the memory cell MC is the voltage charged (or maintained) at the memory cell MC (or selector element SE) and the word line WL. In other words, the voltage Vm of the memory cell MC is the voltage obtained by subtracting the voltage of the bit line BL from the voltage of the word line WL. The read operation is controlled by the control circuit 13 and the read circuit 17.

[0070] First, a pre-charge current Ipc is supplied to the memory cell MC by a constant current source CS. As a result, the voltage Vm of the memory cell MC rises. When the voltage Vm of the memory cell MC rises to the threshold voltage Vth of the selector element SE at time t1, the selector element SE becomes on, and the cell current Im begins to flow to the memory cell MC.

[0071] Here, when the selector element SE is turned on, the voltage Vm, which has risen to the threshold voltage Vth, drops sharply due to the sudden return characteristic of the selector element SE. On the other hand, the voltage Vd of diode D1 is maintained at the peak voltage before the voltage Vm drops, i.e., the threshold voltage Vth, by means of the diode's anti-reverse current function.

[0072] At time t2, the peak detection circuit 51 detects that the voltage Vm of the memory cell MC drops below the voltage Vd of the diode D1, that is, it detects that the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE. In response to the detection that the voltage Vm has reached the threshold voltage Vth, the control circuit 13 sets the precharge switch S1 to the blocking state. Herein, the supply of precharge current Ipc is stopped, preventing excess precharge current Ipc from being supplied to the memory cell MC.

[0073] Subsequently, after a predetermined delay time Dt has elapsed since the voltage Vm reaches the threshold voltage Vth and is detected, the control circuit 13 reads out the memory cell MC at time t3.

[0074] For each memory cell, the above-mentioned precharge current Ipc supply, the detection that the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the cessation of the precharge current Ipc supply, and the reading of the memory cell MC are performed.

[0075] Furthermore, the voltage of the memory cell MC at time t4 shown in Figure 8 is the aforementioned holding voltage Vh. The holding voltage Vh is the voltage at which the pull-down switch S2 is maintained in the connected state until the cell current Im, i.e., the discharge current, stops flowing after the voltage Vm of the memory cell MC reaches the threshold voltage Vth. The control circuit 13 can also standby until the voltage Vm of the memory cell MC becomes the holding voltage Vh, and then read out the memory cell MC with the holding voltage Vh.

[0076] Hereinafter, the readout operation of the magnetic memory device 1 according to the first embodiment will be described in detail with reference to FIGS. 9 to 13. FIG. 9 is a flowchart showing the flow of the readout operation of the magnetic memory device 1. FIGS. 10 to 13 are graphs showing the state of the switch, the flow of current, and the voltage changes of voltage Vm and voltage Vd during the readout operation.

[0077] First, the readout circuit 17 supplies a pre-charge current Ipc(S1) to the memory cell MC through a constant current source CS.

[0078] Specifically, as shown in Figure 10(a), at time t0, the readout circuit 17 sets the pre-charge switch S1, the pull-down switch S2, and the sense amplifier switch S3 to the connected state. Herein, a pre-charge current Ipc is supplied from the constant current source CS to the memory cell MC, charging the memory cell MC (or the selector element SE) and the word line WL. As shown in Figure 10(b), the voltage Vm of the memory cell MC and the voltage Vd of the diode D1 gradually increase. Furthermore, at this point, the voltage Vm of the memory cell MC has not reached the threshold voltage Vth of the selector element SE.

[0079] Subsequently, the voltage Vm of the memory cell MC rises due to the supply of pre-charge current Ipc, as shown in Figure 11(b). At time t1, the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE. When the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the selector element SE switches to the ON state, as shown in Figure 11(a), and the cell current Im begins to flow to the memory cell MC.

[0080] Subsequently, the peak detection circuit 51 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE (S2).

[0081] Specifically, the voltage Vm of the memory cell MC is input to the positive input terminal of the comparator CP via diode D1. That is, the voltage Vm of the memory cell MC is input to the anode of diode D1, and the voltage Vd output from the cathode of diode D1 is input to the positive input terminal of the comparator CP. On the other hand, the voltage Vm of the memory cell MC is input to the negative input terminal of the comparator CP.

[0082] When the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE, the selector element SE switches to the ON state. Thus, as shown in Figure 12(b), after time t1, the voltage Vm drops sharply due to the sudden return characteristic of the selector element SE. On the other hand, the voltage Vd on the cathode side of diode D1 (or the voltage at the positive input terminal of comparator CP) is maintained at the threshold voltage Vth by means of the reverse current protection function of diode D1.

[0083] At time t2, comparator CP compares the voltage Vd input to the positive input terminal with the voltage Vm input to the negative input terminal. Since voltage Vd is higher than voltage Vm, comparator CP outputs "H" as signal O1. The "H" in signal O1 indicates that the voltage Vm of memory cell MC has reached the threshold voltage Vth.

[0084] Subsequently, when the peak detection circuit 51 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth, the readout circuit 17 stops supplying the pre-charge current Ipc to the memory cell MC according to the command from the control circuit 13 in response to the detection (S3).

[0085] Specifically, the signal O1 output from the comparator CP of the peak detection circuit 51 is sent to the control circuit 13. When the control circuit 13 receives the "H" signal as signal O1, it sends a signal to the readout circuit 17 to change the precharge switch S1 to the blocking state. According to the signal from the control circuit 13, as shown in FIG12(a), the readout circuit 17 sets the precharge switch S1 to the blocking state. The pull-down switch S2 and the sense amplifier switch S3 remain in the connected state.

[0086] Accordingly, the self-stressed current source CS stops supplying the pre-charge current Ipc to the memory cell MC. However, the cell current Im continues to flow from the memory cell MC and the word line WL through the pull-down switch S2 to the ground voltage node. The voltage Vm of the memory cell MC decreases below the threshold voltage Vth due to the backflow characteristic, and further decreases due to the flow of the cell current Im.

[0087] Subsequently, after a predetermined delay time Dt has elapsed since the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the readout circuit 17 stops the cell current Im flowing in the memory cell MC and the word line WL (S4).

[0088] Specifically, the signal O1 output from the comparator CP is input to the delay circuit 52. The delay circuit 52 delays the received signal O1 by a predetermined delay time Dt, and outputs the signal O2 to the control terminals of the pull-down switch S2 and the sense amplifier switch S3. As shown in Figure 13(a), when the pull-down switch S2 receives the "H" signal as O2, it changes from the connected state to the blocked state. Similarly, when the sense amplifier switch S3 receives the "H" signal as O2, it changes from the connected state to the blocked state. Thus, as shown in Figures 13(a) and (b), at time t3, the cell current Im from the memory cell MC and the word line WL stops. At this time, the voltage Vm of the memory cell MC remains at the sense amplifier SA.

[0089] Subsequently, the readout circuit 17 performs the readout of the memory cell MC (S5).

[0090] Specifically, the sensing amplifier SA compares the voltage Vm of the memory cell MC at time t3 with the reference voltage Vref, and determines the data stored in the memory cell MC based on the comparison result.

[0091] 1.3 Effects of the first embodiment According to the magnetic memory device 1 of the first embodiment, the discharge failure and reading disturbance failure during the reading operation can be reduced, and the operation performance can be improved.

[0092] The effects of the implementation method will be explained below.

[0093] For example, in the readout operation of a memory cell in a magnetic memory device, the memory cell is charged to a pre-charge voltage Vpc, and then the pre-charge voltage Vpc charged into the memory cell is discharged. Subsequently, the resistance value of the variable resistor element is read based on the voltage of the memory cell after discharge, or the voltage of the memory cell during discharge. Furthermore, the data is determined based on the read resistance value.

[0094] Therefore, the pre-charge voltage Vpc applied to each memory cell needs to be greater than or equal to the threshold voltage Vth of the selector element of each memory cell. Otherwise, a discharge defect will occur where the pre-charge voltage Vpc applied to the memory cell does not discharge.

[0095] However, the threshold voltage Vth of the selector element of the memory cell varies from selector element to selector element. Therefore, if the precharge voltage Vpc is to be set above the threshold voltage Vth of the selector element of all memory cells, the precharge voltage Vpc needs to be set to a voltage that is a certain degree higher than the average threshold voltage.

[0096] On the other hand, if the precharge voltage Vpc is set too high as to be excessively higher than the threshold voltage Vth of the selector element, the discharge current, i.e., the cell current, increases, which may sometimes lead to read interference defects. That is, if a voltage higher than the originally required precharge voltage Vpc is applied to the memory cell, read interference defects may occur. As described above, there is a trade-off between discharge defects and read interference defects during the read operation.

[0097] In this regard, the first embodiment includes: a constant current source CS that supplies a pre-charge current Ipc to the memory cell MC; and a peak detection circuit 51 that detects whether the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE, in other words, whether the voltage Vm charged into the memory cell MC (or the selector element SE) and the word line WL has risen to the threshold voltage Vth of the selector element SE.

[0098] Accordingly, the peak detection circuit 51 detects the time point at which the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE (hereinafter referred to as the threshold arrival time point). In response to the threshold arrival time point, the control circuit 13 switches the precharge switch S1 to the blocking state, thereby stopping the supply of the precharge current Ipc. This prevents excess precharge current Ipc from being supplied to the memory cell MC. Furthermore, it prevents the voltage Vm of the memory cell MC from being charged to a voltage higher than the threshold voltage Vth.

[0099] In the first embodiment, the voltage Vm charged into the memory cell MC can be set to the threshold voltage Vth of the selector element SE of the memory cell MC. In other words, based on the difference in the threshold voltage Vth of the selector element SE of each memory cell MC, the pre-charge voltage Vpc (i.e., voltage Vm) can be set to the threshold voltage Vth of the selector element SE for each selector element.

[0100] This reduces the occurrence of poor discharge where the discharge current (cell current) does not flow to the memory cell MC, without having to set the precharge voltage Vpc to a voltage that is a certain degree higher than the average threshold voltage.

[0101] Furthermore, it is possible to prevent the application of a voltage higher than the originally required pre-charge voltage Vpc to the memory cell MC. Therefore, it is possible to suppress the increase of cell current flowing to the variable resistor element (e.g., MTJ element) VR of the memory cell MC, thereby reducing the occurrence of read disturbances.

[0102] Furthermore, in the first embodiment, as described above, the amount of current accumulated in the variable resistor element VR can be reduced, thereby reducing the current load on the variable resistor element VR during the readout operation and extending the life of the variable resistor element VR until it fails.

[0103] Furthermore, in the first embodiment, during the readout operation, the discharge current (cell current) is stopped midway during the discharge after the memory cell MC (and word line WL) is charged to the pre-charge voltage Vpc, so the time required for the readout operation can be shortened compared to the case where the voltage of the memory cell MC is reached after the voltage of the memory cell MC is not stopped and the readout is performed.

[0104] As described above, the magnetic memory device 1 according to the first embodiment can improve the operation performance.

[0105] 2. Second Embodiment Next, the magnetic memory device of the second embodiment will be described. In the second embodiment, the signal O1 output from the peak detection circuit 51 is input to the control terminal of the precharge switch S1 to control the opening and closing state of the precharge switch S1. The configuration of the memory system, the circuit configuration of the memory cell array, and the structure of the memory cell array in the second embodiment are the same as those in the first embodiment described above. In the second embodiment, the differences from the first embodiment will be mainly described.

[0106] 2.1 Configuration of Magnetic Memory Device 2.1.1 Circuit Configuration of Readout Circuit Referring to FIG14, an example of the circuit configuration of the readout circuit 17 provided in the magnetic memory device 1 of the second embodiment will be described. FIG14 is a circuit diagram showing the configuration of the readout circuit 17 of the second embodiment.

[0107] As shown in Figure 5, in the readout circuit 17 of the second embodiment, the output terminal of the comparator CP of the peak detection circuit 51 is connected to the control terminal of the precharge switch S1. That is, the signal O1 output from the comparator CP is input to the control terminal of the precharge switch S1. The other configurations are the same as those of the readout circuit 17 in the first embodiment.

[0108] 2.2 Reading Operation of Magnetic Memory Device Next, referring to FIG9, the reading operation of the magnetic memory device 1 of the second embodiment will be described.

[0109] First, the readout circuit 17 supplies a pre-charge current Ipc to the memory cell MC via a constant current source CS (S1). With the supply of the pre-charge current Ipc, the voltage Vm of the memory cell MC rises, reaching the threshold voltage Vth of the selector element SE. The readout circuit 17 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE (S2). This is the same as in the first embodiment described above.

[0110] Subsequently, when the peak detection circuit 51 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth, the readout circuit 17 responds to the detection and stops supplying the pre-charge current Ipc to the memory cell MC (S3).

[0111] Specifically, the signal O1 output from the comparator CP of the peak detection circuit 51 is input to the control terminal of the precharge switch S1. When the precharge switch S1 receives "H" as signal O1, it changes from the connected state to the blocked state. The pull-down switch S2 and the sensing amplifier switch S3 remain in the connected state.

[0112] Accordingly, the supply of precharge current Ipc to memory cell MC is stopped, and cell current Im flows from memory cell MC and word line WL through pull-down switch S2 to ground voltage node. The voltage Vm of memory cell MC drops below the threshold voltage Vth due to the surge characteristic, and further decreases due to the flow of cell current Im.

[0113] Subsequently, similar to the first embodiment, after a predetermined delay time Dt elapses from the detection that the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the readout circuit 17 stops the cell current flowing from the memory cell MC and the word line WL (S4). Thereafter, the readout circuit 17 performs the readout of the memory cell MC (S5).

[0114] 2.3 Variations Next, a variation of the magnetic memory device according to the second embodiment will be described. In the variation, the peak detection circuit 51 has a configuration that takes into account the forward voltage drop in diode D1.

[0115] 2.3.1 Circuit Configuration of the Readout Circuit Referring to Figures 15 and 16, an example of the circuit configuration of the readout circuit 17 provided in the magnetic memory device 1 of the second embodiment will be described. Figure 15 is a circuit diagram showing the configuration of the readout circuit 17 of the variation example. Figure 16 is a graph showing the voltage changes of the memory cell MC, the diode D1, and the diode D1 during the readout operation of the magnetic memory device 1 of the variation example.

[0116] Here, a voltage drop Vf in diode D1 is assumed to be a positive voltage drop. To compensate for the voltage Vf corresponding to this voltage drop, in the peak detection circuit 51 of the variation example, as shown in FIG15, a constant voltage source VF is configured between the cathode of diode D1 and the positive input terminal of comparator CP. The constant voltage source VF generates a voltage equivalent to the voltage Vf corresponding to the voltage drop in diode D1. The voltage between the cathode of diode D1 and the constant voltage source VF is set as Vk, and the voltage between the constant voltage source VF and the positive input terminal of comparator CP is set as Vd.

[0117] The voltage Vm of the memory cell MC is input to the anode of diode D1. Diode D1 causes the voltage Vm to decrease by voltage Vf, and outputs voltage Vk from the cathode of diode D1. The voltage Vk output from diode D1 is increased by a constant voltage source VF and is used as voltage Vd input to the positive input terminal of comparator CP. Thus, as shown in Figure 16, the voltage Vd input to the positive input terminal of comparator CP remains at the same level as voltage Vm until the voltage Vm of the memory cell MC reaches the threshold voltage Vth.

[0118] The other circuit configurations and readout operations are the same as those in the second embodiment described above.

[0119] 2.4 Effects of the second embodiment According to the magnetic memory device 1 of the second embodiment, similar to the first embodiment, it is possible to reduce discharge defects and read disturbance defects during the readout operation, and improve the operation performance.

[0120] In the second embodiment, in addition to obtaining the effects of the first embodiment described above, the following effects can also be obtained.

[0121] In the configuration of the second embodiment, the signal O1 output from the comparator CP of the peak detection circuit 51 is input to the control terminal of the precharge switch S1. Then, based on the signal O1, the connection state and the blocking state of the precharge switch S1 are switched. Therefore, in the second embodiment, compared with the first embodiment, the circuit for controlling the precharge switch S1 can be simplified.

[0122] Furthermore, in the modified configuration, the forward voltage drop of diode D1 can be compensated, thus providing a circuit configuration that is more suitable for installation.

[0123] 3. Other In this specification, "connection" means electrical connection and does not exclude the possibility of other components being separated between them. The non-magnetic layer 41 may also be called an "oxide layer". The elements contained in each layer of the MTJ element can be determined, for example, by using electron energy loss spectroscopy (EELS) with a scanning transmission electron microscope (STEM).

[0124] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are similarly included in the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a block diagram showing the configuration of the memory system including the magnetic memory device of the first embodiment. Figure 2 is a circuit diagram showing the configuration of the memory cell array provided by the magnetic memory device of the first embodiment. Figure 3 is a perspective view showing the structure of the memory cell array provided by the magnetic memory device of the first embodiment. Figure 4 is a cross-sectional view of the memory cells in the memory cell array of the first embodiment. Figure 5 is a circuit diagram showing the configuration of the readout circuit of the magnetic memory device of the first embodiment. Figure 6 is a diagram showing the current-voltage characteristics of the sudden return characteristic of the selector element of the first embodiment. Figure 7 is a circuit diagram showing an example of the configuration of the delay circuit of the first embodiment. Figure 8 is a diagram showing the voltage changes of the memory cell voltage and the diode voltage during the readout operation of the first embodiment. Figure 9 is a flowchart showing the flow of the readout operation of the first embodiment. Figure 10 is a diagram showing the switch state, current flow, and voltage changes during the readout operation of the first embodiment. Figure 11 is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment. Figure 12 is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment. Figure 13 is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment. Figure 14 is a circuit diagram showing the configuration of the readout circuit of the second embodiment. Figure 15 is a circuit diagram showing the configuration of the readout circuit of a variation of the second embodiment. Figure 16 is a diagram showing the voltage changes of the memory cell voltage and the diode voltage during the readout operation of a variation of the second embodiment.

Claims

1. A magnetic memory device comprising: a memory cell including a variable resistor element and a selector element; a current source supplying a first current to the memory cell; a first switch connected between the memory cell and the current source; a second switch connected between a ground voltage node supplied with a ground voltage and the memory cell; a detection circuit including a comparator and a diode, wherein a first voltage charged into the memory cell is input to a first input terminal of the comparator via the diode, and the first voltage is input to a second input terminal of the comparator; a sensing amplifier comparing the first voltage charged into the memory cell with the second voltage; and a third switch connected between the memory cell and the sensing amplifier.

2. The magnetic memory device of claim 1, wherein the detection circuit outputs a first signal when the voltage input to the first input terminal is higher than the first voltage input to the second input terminal.

3. The magnetic memory device of claim 2, wherein the selector element turns on when the first voltage rises to a threshold voltage, and the first voltage decreases to a voltage below the threshold voltage after rising to the threshold voltage.

4. The magnetic memory device of claim 3, wherein the detection circuit detects that the first voltage rises to the threshold voltage and then drops to a voltage below the threshold voltage, and outputs the first signal.

5. The magnetic memory device of claim 2, wherein when the first signal is output from the detection circuit, the memory cell is blocked from the current source by the first switch.

6. The magnetic memory device of claim 2, wherein the output terminal of the detection circuit is electrically connected to the first switch, and when the first signal is output from the detection circuit, the first switch blocks the connection between the memory cell and the current source according to the first signal.

7. The magnetic memory device of claim 1 further includes a delay circuit, the delay circuit being electrically connected to the output terminal of the detection circuit, and the output terminal of the delay circuit being electrically connected to the second switch and the third switch. When the voltage input to the first input terminal is higher than the first voltage input to the second input terminal, the detection circuit outputs a first signal. The delay circuit delays the first signal by a first delay time and outputs a second signal to the second switch and the third switch.

8. The magnetic memory device of claim 1 further comprises: a first wiring connected to one end of the memory cell; and a second wiring connected to the other end of the memory cell; and the first voltage being the voltage between the first wiring and the second wiring.

9. The magnetic memory device of claim 1, further comprising: a first wiring connected to one end of the memory cell; and a second wiring connected to the other end of the memory cell; and the first wiring being connected to one end of the selector element, wherein a first current is supplied to the first wiring from the current source, and the first voltage is the voltage maintained by the first wiring.

10. The magnetic memory device of claim 1, wherein the variable resistive element comprises an MTJ (Magnetic Tunnel Junction) element.

11. A magnetic memory device comprising: a memory cell including a variable resistor element and a selector element; a current source supplying a first current to the memory cell; a first switch connected between the memory cell and the current source; a second switch connected between a ground voltage node supplied with a ground voltage and the memory cell; a detection circuit outputting a first signal when a second current flows from the memory cell to the second switch; a sensing amplifier comparing the first voltage and the second voltage charged into the memory cell; and a third switch connected between the memory cell and the sensing amplifier.

12. The magnetic memory device of claim 11, wherein the second current flows when the selector element is set to the on state.

13. The magnetic memory device of claim 11, wherein the selector element has a threshold voltage, and the second current flows when the first voltage of the memory cell rises to the threshold voltage.

14. The magnetic memory device of claim 11, wherein the selector element turns on when the first voltage rises to a threshold voltage, and the first voltage decreases to a voltage below the threshold voltage after rising to the threshold voltage.

15. The magnetic memory device of claim 14, wherein the detection circuit detects that the first voltage rises to the threshold voltage and then drops to a voltage below the threshold voltage, and outputs the first signal.

16. The magnetic memory device of claim 11, wherein the detection circuit includes a comparator and a diode, the first voltage is input to the first input terminal of the comparator via the diode, and the first voltage is input to the second input terminal of the comparator.

17. The magnetic memory device of claim 11, wherein when the first signal is output from the detection circuit, the memory cell is blocked from the current source by the first switch.

18. The magnetic memory device of claim 11, wherein the output terminal of the detection circuit is electrically connected to the first switch, and when the first signal is output from the detection circuit, the first switch blocks the connection between the memory cell and the current source according to the first signal.

19. The magnetic memory device of claim 11, further comprising a delay circuit electrically connected to the output terminal of the detection circuit, the output terminal of the delay circuit being electrically connected to the second switch and the third switch, the detection circuit outputting the first signal to the delay circuit, the delay circuit delaying the first signal by the first delay time, and outputting a second signal to the second switch and the third switch.

20. The magnetic memory device of claim 11, further comprising: a first wiring connected to one end of the memory cell; and a second wiring connected to the other end of the memory cell; and the first voltage being the voltage between the first wiring and the second wiring.

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