Charge pump circuit and charge pump device

Abstract

The charge pump circuit includes a pump unit and an output transistor for outputting the pump voltage generated by the pump unit. The pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and an auxiliary control unit. The first capacitor receives a first clock signal, and the second capacitor receives a second clock signal with a swing greater than the first clock signal. The first transistor has a first terminal coupled to an input, a second terminal coupled to the first capacitor, and a control terminal coupled to the second capacitor. The second transistor has a first terminal coupled to the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal coupled to the auxiliary control unit. When the first clock signal is high, the auxiliary control unit turns on the second transistor.

Description

[Technical Field]

[0001] This disclosure relates to a charge pump circuit, and more particularly to a charge pump circuit suitable for low-voltage environments. [Previous Technology]

[0002] To meet the demand for low power consumption in electronic devices, integrated circuits (ICs) have been designed to operate in low-voltage environments. While lower voltages are beneficial for reducing power consumption, there are still situations where higher voltages are required for operation. For example, flash memory may require high voltages (positive or negative) to perform write or erase operations, and these high voltages are typically supplied by charge pumps.

[0003] However, designing a charge pump that can operate in low-voltage environments can be extremely challenging. For example, special care may be needed to ensure that the transistors used in the circuit can operate within their safe operating areas (SOA). Furthermore, the effective charge transfer of each stage of the charge pump is also crucial when operating in low-voltage environments.

[0004] Figure 1 illustrates a conventional Dickson charge pump 90. The charge pump 90 generates a negative output voltage VO from a zero input voltage VI. The charge pump 90 includes diodes 92A and 92B, and capacitors 94A and 94B. Diodes 92A and 92B are connected in series between the input and output terminals. Capacitor 94A is coupled to diode 92A as a first-stage charge pump 90, while capacitor 94B is coupled to diode 92B as a second-stage charge pump 90.

[0005] To generate a negative output voltage VO, capacitor 94A receives the clock signal SIG CKA, while capacitor 94B receives the clock signal SIG CKB, which is complementary to SIG CKA. First, when the clock signal SIG CKA is at a high voltage (e.g., VDD), the voltage V1 at the anode of diode 92A is charged to the threshold voltage Vt of diode 92A. Then, when the clock signal SIG CKA drops to a low voltage (e.g., 0V), voltage V1 also drops by VDD, meaning voltage V1 becomes Vt-VDD. Furthermore, when the clock signal SIG CKA becomes low, the clock signal SIG CKB becomes high by VDD, and the voltage V2 at the anode of diode 92B is charged to a voltage higher than the threshold voltage Vt of voltage V1. That is, voltage V2 becomes 2Vt-VDD. Subsequently, when the clock signal SIG CKB becomes low, voltage V2 decreases by VDD to become 2Vt-2VDD.

[0006] In other words, each stage of the charge pump 90 can only provide the total voltage drop of VDD-Vt, not the full voltage drop VDD provided by the clock signals SIG CKA and SIG CKB. This inefficient charge transfer results in the need for more charge stages to generate the target negative voltage, and the situation worsens when the charge pump operates in a low-voltage environment where VDD is quite low. Therefore, how to design a high-efficiency charge pump that can operate in low-voltage environments has become an urgent problem to be solved.

[0007] This prior art section provides background information only. The statements in this prior art section are not an admission that the subject matter disclosed in this section constitutes prior art to this disclosure, and no part of this prior art section shall be used as an admission that any part of this application (including this prior art section) constitutes prior art to this disclosure. [Summary of the Invention]

[0008] One embodiment of this disclosure proposes a charge pump circuit. The charge pump circuit includes an input terminal, an output terminal, a first pump unit, and an output transistor. The input terminal receives an input voltage, and the output terminal outputs an output voltage. The pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and an auxiliary control unit. The first capacitor has a first terminal and a second terminal for receiving a first clock signal. The second capacitor has a first terminal and a second terminal for receiving a second clock signal. The first transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. The first auxiliary control unit is coupled to the control terminal of the second transistor. When the first clock signal is at a first high voltage, the first auxiliary control unit turns off the second transistor; when the first clock signal is at a low voltage, the first auxiliary control unit turns on the second transistor. The first output transistor has a first terminal coupled to a second terminal of the first transistor, a second terminal coupled to an output terminal, and a control terminal. A first clock signal and a second clock signal are in phase. The first clock signal oscillates between a low voltage and a first high voltage, while the second clock signal oscillates between a low voltage and a second high voltage higher than the first high voltage. When the first clock signal is at a low voltage, the first output transistor is turned on, and when the first clock signal is at the first high voltage, the first output transistor is turned off.

[0009] One embodiment of this disclosure proposes a charge pump device. The charge pump device includes a multi-stage charge pump circuit, with the input terminal of a subsequent stage charge pump circuit connected to an output terminal of a preceding stage charge pump circuit. The first stage charge pump circuit includes an input terminal, an output terminal, a first pump unit, a second pump unit, a first output transistor, and a second output transistor. The first pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a first auxiliary control unit. The first capacitor has a first terminal and a second terminal for receiving a first clock signal. The second capacitor has a first terminal and a second terminal for receiving a second clock signal. The first transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. A first auxiliary control unit is coupled to the control terminal of a second transistor, and is used to turn off the second transistor when the first clock signal is at a first high voltage, and to turn on the second transistor when the first clock signal is at a low voltage. The second pump unit includes a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a second auxiliary control unit. The third capacitor has a first terminal and a second terminal for receiving a third clock signal. The fourth capacitor has a first terminal and a second terminal for receiving a fourth clock signal. The third transistor has a first terminal coupled to an input terminal, a second terminal coupled to a second terminal of the third capacitor, and a control terminal coupled to a second terminal of the fourth capacitor. The fourth transistor has a first terminal coupled to a second terminal of the fourth capacitor, a second terminal coupled to a second terminal of the third transistor, and a control terminal. The second auxiliary control unit is coupled to the control terminal of the fourth transistor, and is used to turn off the fourth transistor when the third clock signal is at a first high voltage, and to turn on the fourth transistor when the third clock signal is at a low voltage. The first output transistor has a first terminal coupled to a second terminal of the first transistor, a second terminal coupled to an output terminal, and a control terminal coupled to a second terminal of a third transistor. The second output transistor has a first terminal coupled to a second terminal of the third transistor, a second terminal coupled to an output terminal, and a control terminal coupled to a second terminal of the first transistor. A first clock signal and a second clock signal are in phase, the first clock signal oscillates between a low voltage and a first high voltage, and the second clock signal oscillates between a low voltage and a second high voltage higher than the first high voltage. The first clock signal and a third clock signal are out of phase, and the third clock signal and a fourth clock signal are in phase. The third clock signal oscillates between a low voltage and a first high voltage, and the fourth clock signal oscillates between a low voltage and a second high voltage. The first output transistor is used to be turned on when the first clock signal is at a low voltage to generate an output voltage according to the voltage at the second terminal of the first transistor, and to be turned off when the first clock signal is at a first high voltage.The second output transistor is turned on when the third clock signal is at a low voltage to generate an output voltage based on the voltage at the second terminal of the third transistor, and turned off when the third clock signal is at a first high voltage.

Implementation Method

[0018] Figure 2 illustrates a charge pump circuit 100 according to an embodiment of the present disclosure. The charge pump circuit 100 includes an input terminal IN1, an output terminal OUT1, a pump unit 110, and an output transistor MO1. The input terminal IN1 receives an input voltage VIN, and the output terminal OUT1 outputs a negative output voltage VOUT.

[0019] Pump unit 110 can use two clock signals, SIG CLK0 and SIG ACLK0, to boost the input voltage VIN and generate a negative output voltage VOUT. The clock signals SIG CLK0 and SIG ACLK0 are in phase; however, the swing of the clock signal SIG ACLK0 is greater than that of the clock signal SIG CLK0. In this case, pump unit 110 can use the clock signal SIG CLK0 to boost the voltage and use the larger swing clock signal SIG ACLK0 to control the transistors, allowing the transistors to be fully turned on during charge transfer. Therefore, charge pump circuit 100 can fully transfer the voltage drop provided by clock signal SIG CLK0, thereby generating the boosted output voltage VOUT. In other words, charge pump circuit 100 can achieve complete charge transfer, making it suitable for low-power applications.

[0020] As shown in Figure 2, the pump unit 110 includes capacitor C1, capacitor C2, transistor M1, transistor M2, and auxiliary control unit 112. The first capacitor C1 has a first terminal and a second terminal for receiving the clock signal SIG CLK0. The second capacitor C2 has a first terminal and a second terminal for receiving the clock signal SIG CLK0. Transistor M1 has a first terminal coupled to the input terminal IN1, a second terminal coupled to the second terminal of capacitor C1, and a control terminal coupled to the second terminal of capacitor C2. Transistor M2 has a first terminal coupled to the second terminal of capacitor C2, a second terminal coupled to the second terminal of transistor M1, and a control terminal. The auxiliary control unit 112 is coupled to the control terminal of transistor M2. When the clock signal SIG CLK0 is at a low voltage, the auxiliary control unit 112 can turn on transistor M2, and when the clock signal SIG CLK0 is at a high voltage, the auxiliary control unit 112 can turn off transistor M2. The output transistor MO1 has a first terminal coupled to the second terminal of transistor M1, a second terminal coupled to the output terminal OUT1, and a control terminal. When the clock signal SIG CLK0 is at a low voltage VL, the output transistor MO1 can be turned on to output the output voltage VOUT, and when the clock signal SIG CLK0 is at a high voltage, the output transistor MO1 can be turned off.

[0021] Figure 3 illustrates the voltage and signal waveforms of a pump unit 110 according to an embodiment of the present disclosure. As shown in Figure 3, the clock signal SIG CLK0 oscillates between a low voltage VL and a high voltage VH1, while the clock signal SIG ACLK0 oscillates between a low voltage VL and a high voltage VH2, which is higher than VH1. In some embodiments, the difference between voltage VH2 and voltage VL can be twice the difference between voltage VH1 and voltage VL. For example, voltage VL can be 0V, and voltage VH2 can be 2VH1. In some embodiments, voltage VH1 can be the system operating voltage VDD. However, the present disclosure is not limited thereto.

[0022] During time period T1 shown in Figure 3, clock signal SIG CLK0 is at a high voltage VH1, and clock signal SIG ACLK0 is at a high voltage VH2. In this case, transistor M2 is turned off by auxiliary control unit 112, and as clock signal SIG ACLK0 rises from low voltage VL to high voltage VH2, the voltage VAPX at the second terminal of capacitor C2 is coupled to the high voltage. Therefore, voltage VAPX can fully turn on transistor M1. In this disclosure, since clock signal SIG ACLK0 is used to turn on transistor M1 to allow input voltage VIN to pass, clock signal SIG ACLK0 is also referred to as the turn-on clock signal.

[0023] Thus, although at the beginning of time period T1, as the clock signal SIG CLK0 rises from a low voltage VL to a high voltage VH1, the voltage VPX at the second terminal of transistor M1 may be coupled to a high voltage, but eventually the voltage VPX will be pulled down to be the same as the input voltage VIN. In this embodiment, the input voltage VIN can be 0V. Furthermore, during time period T1, the output transistor MO1 is turned off, so the voltage VPX will not be output to the output terminal OUT1.

[0024] Next, in time period T2 following time period T1, both clock signals SIG CLK0 and SIG ACLK0 become low voltage VL. In this case, as clock signals SIG CLK0 and SIG ACLK0 decrease, voltages VAPX and VPX are coupled to a lower voltage through capacitors C1 and C2, and therefore, voltages VAPX and VPX become negative voltages. Furthermore, since transistor M2 is turned on by auxiliary control unit 112 in time period T2, voltages VAPX and VPX drop to the same potential. Output transistor MO1 can be turned on to output a negative voltage VPX as output voltage VOUT. In this disclosure, since clock signal SIG CLK0 is used to boost voltage VPX to a negative voltage, clock signal SIG CLK0 is also referred to as a boost clock signal.

[0025] It can be noted that in this embodiment, since the output terminal OUT1 can be coupled to the load, the output voltage VOUT (i.e., voltage VPX) may gradually increase due to the load. With proper design, the clock signals SIG CLK0 and SIG ACLK0 will return to high voltages VH1 and VH2 respectively before the output voltage VOUT rises to an unacceptable voltage.

[0026] Since the pump unit 110 can only output a negative voltage VPX as the output voltage VOUT at fixed time intervals when the clock signal SIG CLK0 is at a low voltage VL, the charge pump circuit 100 may also include another pump unit 120 and another output transistor MO2 so that when the clock signal SIG CLK0 is at a high voltage VH1, it can output a negative output voltage VOUT, so that the charge pump circuit 100 can continuously output a negative output voltage VOUT.

[0027] Specifically, pump unit 120 and pump unit 110 may have the same structure, but may operate with complementary clock signal groups. Therefore, when the boost clock signal SIG CLK0 is at a low voltage VL, pump unit 110 can generate a negative output voltage VOUT, and when the boost clock signal SIG CLK0 is at a high voltage VH1 (i.e., when the boost clock signal SIG CLK1 is at a low voltage VL), pump unit 120 can generate a negative output voltage VOUT. The voltage and signal waveforms of pump unit 120 are also shown in Figure 3 along with the voltage and signal waveforms of pump unit 110.

[0028] As shown in Figure 2, the pump unit 120 includes capacitor C3, capacitor C4, transistor M3, transistor M4, and auxiliary control unit 122. Capacitor C3 has a first terminal and a second terminal for receiving clock signal SIG CLK1. Capacitor C4 has a first terminal and a second terminal for receiving clock signal SIG ACLK1. Clock signal SIG CLK1 is out of phase with clock signal SIG CLK1, and clock signal SIG CLK1 is in phase with clock signal SIG ACLK1. Furthermore, clock signal SIG CLK1 swings between low voltage VL and high voltage VH1, and clock signal SIG ACLK1 swings between low voltage VL and high voltage VH2. That is, the swing of the switching clock signal SIG ACLK1 is greater than the swing of the boost clock signal SIG CLK1.

[0029] Transistor M3 has a first terminal coupled to input terminal IN1, a second terminal coupled to the second terminal of capacitor C3, and a control terminal coupled to the second terminal of capacitor C4. Transistor M4 has a first terminal coupled to the second terminal of capacitor C4, a second terminal coupled to the second terminal of transistor M3, and a control terminal. Auxiliary control unit 122 is coupled to the control terminal of transistor M4. When clock signal SIG CLK1 is at a high voltage VH1, auxiliary control unit 122 can turn off transistor M4, and when clock signal SIG CLK1 is at a low voltage, auxiliary control unit 122 can turn on transistor M4.

[0030] In some embodiments, the auxiliary control unit 112 includes transistors M5 and M6, as shown in FIG2. The fifth transistor M5 has a first terminal coupled to input terminal IN1, a second terminal coupled to a control terminal of transistor M2, and a control terminal coupled to a second terminal of capacitor C2. Transistor M6 has a first terminal coupled to the control terminal of transistor M2, a second terminal coupled to a second terminal of capacitor C3, and a control terminal coupled to a second terminal of capacitor C4.

[0031] Refer to Figures 2 and 3. During time period T1, when clock signal SIG ACLK0 is at a high voltage VH2, clock signal SIG ACLK1 is at a low voltage VL. In this case, transistor M5 will be turned on by the high potential voltage VAPX, and transistor M6 will be turned off by the low potential voltage VAPY coupled to the second terminal of capacitor C4. Therefore, during time period T1, the control terminal of transistor M2 will receive the input voltage VIN and be turned off.

[0032] Furthermore, during time period T2, when clock signal SIG ACLK0 is at a low voltage VL, clock signal SIG ACLK1 is at a high voltage VH2. In this case, transistor M5 is coupled to the low potential voltage VAPX and turned off, while transistor M6 is coupled to the high potential voltage VAPY and turned on. Therefore, the control terminal of transistor M2 receives the voltage VPY coupled to the second terminal of capacitor C3 at the high potential, and thus transistor M2 is turned on during time period T2, making the voltage VAPX at the second terminal of capacitor C2 the same as the voltage VPX at the second terminal of capacitor C1.

[0033] Through transistors M5 and M6, the gate-to-source voltage and gate-to-drain voltage of transistor M2 can be maintained in its safe operating area (SOA). Therefore, transistor M2 can be implemented using a low-voltage transistor with a thin oxide layer.

[0034] The auxiliary control unit 122 and the auxiliary control unit 112 have the same structure. In this embodiment, the auxiliary control unit 122 includes transistor M7 and transistor M8. Transistor M7 has a first terminal coupled to input terminal IN1, a second terminal coupled to control terminal of transistor M4, and a control terminal coupled to second terminal of capacitor C4. Transistor M8 has a first terminal coupled to control terminal of transistor M4, a second terminal coupled to second terminal of capacitor C1, and a control terminal coupled to second terminal of capacitor C2.

[0035] Furthermore, output transistor MO1 has a first terminal coupled to the second terminal of transistor M1, a second terminal coupled to the output terminal OUT1, and a control terminal coupled to the second terminal of transistor M3. Output transistor MO2 has a first terminal coupled to the second terminal of transistor M3, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of transistor M3. Therefore, when the clock signal SIG CLK0 is at a low voltage and the voltage VPX becomes a negative voltage, output transistor MO1 can be turned on and output transistor MO2 can be turned off. In this way, the voltage VPX can be output as the output voltage VOUT through output transistor MO1. Furthermore, when the clock signal SIG CLK1 is at a low voltage and the voltage VPY becomes a negative voltage, output transistor MO2 can be turned on and output transistor MO1 can be turned off. In this way, the voltage VPY can be output as the output voltage VOUT through output transistor MO2.

[0036] In this embodiment, the charge pump circuit 100 may further include selector transistors MW1 and MW2 to ensure that the base terminals of output transistors MO1 and MO2 are at the lowest voltage (e.g., the lowest voltage is -VDD when the input voltage VIN is ground voltage), thereby preventing leakage current.

[0037] As shown in Figure 2, the well select transistor MW1 has a first terminal coupled to a first terminal of the output transistor MO1, a second terminal coupled to a second terminal of the capacitor C3 to receive voltage VPY, and a base terminal coupled to the second terminal of the well select transistor MW1. The well select transistor MW2 has a first terminal coupled to a first terminal of the output transistor MO2, a second terminal coupled to a second terminal of the well select transistor MW1, a control terminal coupled to a second terminal of the capacitor C1 to receive voltage VPX, and a base terminal coupled to the second terminal of the well select transistor MW2.

[0038] Therefore, the base terminals of the well select transistors MW1 and MW2 and the base terminals of the output transistors MO1 and MO2 will be coupled to the lower of the voltages VPX and VPY. However, this disclosure is not limited thereto. In some other instances, the base terminals of the output transistors MO1 and MO2 may be coupled to the output terminal OUT1, and the well select transistors MW1 and MW2 may be omitted.

[0039] FIG4 illustrates a charge pump circuit 200 according to another embodiment of the present disclosure. The charge pump circuit 200 differs from the charge pump circuit 100 in that the pump unit 210 of the charge pump circuit 200 further includes a voltage gap unit 214, and the pump unit 220 of the charge pump circuit 200 further includes a voltage gap unit 224.

[0040] Voltage gap unit 214 is coupled between the second terminal of capacitor C2 and the second terminal of transistor M1. Voltage gap unit 214 is used to ensure that when the clock signal SIG CLK1 is at a high voltage VH1, the voltage VAPX' at the second terminal of capacitor C2 is higher than the voltage VPX' at the second terminal of transistor M1 by a gap voltage VG. Voltage gap unit 224 is coupled between the second terminal of capacitor C4 and the second terminal of transistor M3. Voltage gap unit 224 is used to ensure that when the clock signal SIG CLK1 is at a high voltage VH1, the voltage VAPY' at the second terminal of capacitor C4 is higher than the voltage VPY' at the second terminal of transistor M3 by the gap voltage VG.

[0041] Figure 5 illustrates the voltage and signal waveforms of pump unit 210 and pump unit 220 according to an embodiment of the present disclosure. During time period T1', the clock signal SIG CLK0 is at a high voltage VH1, and transistor M2 is turned off. In this case, without voltage gap unit 214, the voltage VAPX in time period T1 shown in Figure 3 would remain at a high potential, which is higher than voltage VH1 than voltage VPX; however, due to voltage gap unit 214, the voltage VAPX' in time period T1' shown in Figure 5 would decrease to a level higher than voltage VPX' than gap voltage VG, where gap voltage VG is less than voltage VH1. Furthermore, in this embodiment, gap voltage VG is greater than the threshold voltage of transistor M1, so voltage VAPX' can still fully turn on transistor M1.

[0042] In this embodiment, with the help of the voltage gap unit 214, the voltage VAPX' will drop to a lower potential during time period T1'; therefore, during time period T2', when the clock signal SIG ACLK0 changes from high voltage VH2 to low voltage VL, it is expected that the voltage VAPX' will drop to a potential lower than the voltage VPX' (it is expected that the voltage VAPX' will reduce the voltage VH2, and it is expected that the voltage VPX' will reduce the voltage VH1, and the voltage VAPX' and the voltage VPX' will eventually be at the same potential due to the transistor M2 being turned on). As the transistor M2 is turned on during time period T2', this pull-down driving force helps the voltage VPX' to reach the target negative voltage potential more quickly.

[0043] Similarly, the voltage gap unit 224 can cause the voltage VAPY' to drop to a lower potential during time period T2'. Therefore, during time period T3', when the clock signal SIG ACLK1 changes from high voltage VH2 to low voltage VL, it can be expected that the voltage VAPY' will drop to a potential lower than the voltage VPY', thus helping the voltage VPY' to reach the target negative voltage potential more quickly.

[0044] In some embodiments, voltage gap units 214 and 224 may each include at least one diode or at least one diode-connected transistor to provide a gap voltage VG. As shown in FIG4, voltage gap unit 214 includes diode-connected transistors MD1 and MD2. Diode-connected transistor MD1 has a first terminal coupled to the second terminal of capacitor C2, a second terminal, and a control terminal coupled to the first terminal of diode-connected transistor MD1. Diode-connected transistor MD2 has a first terminal coupled to the second terminal of diode-connected transistor MD1, a second terminal coupled to the second terminal of transistor M1, and a control terminal coupled to the first terminal of diode-connected transistor MD2.

[0045] In this case, the gap voltage VG provided by the gap voltage unit 214 will be equal to the sum of the threshold voltages of the diode-connected transistors MD1 and MD2. In this embodiment, the threshold voltages of the diode-connected transistors MD1 and MD2 can be the same as the threshold voltage of transistor M1. In other words, transistors M1, MD1, and MD2 can be the same components, which makes the design easier. Therefore, at the end of time period T1', the voltage VAPX' will still be twice the threshold voltage of the voltage VPX', thus ensuring that transistor M1 can be fully turned on. In addition, in this embodiment, the diode-connected transistors MD1 and MD2 can also help ensure that the drain-to-source voltage of transistor M2 remains within its SOA range.

[0046] In this embodiment, the gap voltage unit 224 may have the same structure as the gap voltage unit 214. That is, the gap voltage unit 224 may also use two diodes connected in series to connect transistors MD3 and MD4. However, in some embodiments, diodes may be used to replace transistors MD1, MD2, MD3, and MD4.

[0047] Furthermore, unlike transistors M1 and M3, and output transistors MO1 and MO2, which are used to output a higher current output voltage VOUT, other transistors M2, M4, M5, M6, M7, M8, selector transistors MW1, MW2, and diode-connected transistors MD1, MD2, MD3, and MD4 are used to adjust a lower current voltage. Therefore, in some embodiments, the effective channel width of transistors M1 and M3, and output transistors MO1 and MO2, can be greater than the effective channel width of transistors M2, M4, M5, M6, M7, M8, selector transistors MW1, MW2, and diode-connected transistors MD1, MD2, MD3, and MD4. Transistors M2, M4, M5, M6, M7, M8, MW1, MW2, MD1, MD2, MD3, and MD4 with smaller effective channel widths can reduce the total area of ​​the charge pump.

[0048] In some embodiments, transistors M1 to M8, output transistors MO1, MO2, well selection transistors MW1, MW2, and diode connection transistors MD1, MD2, MD3, and MD4 are N-type transistors. Furthermore, since all transistors in charge pump circuits 100 and 200 can operate with gate-to-drain voltage, gate-to-source voltage, and drain-to-source voltage less than or equal to the system operating voltage VDD, all transistors in charge pump circuits 100 and 200 can be implemented using low-voltage transistors with a thin gate oxide layer.

[0049] Furthermore, in some embodiments, in order to improve the efficiency of the charge pump circuit 100 or 200, the time window of the clock signal SIG CLK0 at high voltage VH1 may include the time window of the clock signal SIG ACLK0 at high voltage VH2, and the time window of the clock signal SIG CLK1 at high voltage VH1 may include the time window of the clock signal SIG ACLK1 at high voltage VH2. Figure 6 illustrates the waveforms of the clock signals SIG CLK0, SIG ACLK0, SIG CLK1, and SIG ACLK1 according to an embodiment of the present disclosure. As shown in Figure 6, the rising edge RE1 of the clock signal SIG CLK0 leads the rising edge RE2 of the clock signal SIG ACLK0, and the falling edge FE1 of the clock signal SIG CLK0 lags the falling edge FE2 of the clock signal SIG ACLK0. Similarly, the rising edge RE3 of clock signal SIG CLK1 leads the rising edge RE4 of clock signal SIG ACLK1, and the falling edge FE3 of clock signal SIG CLK1 lags behind the falling edge FE4 of clock signal SIG ACLK1.

[0050] In some embodiments, charge pump circuits 100 and 200 may be connected in series to generate a lower potential negative output voltage. FIG7 illustrates a charge pump device 10 according to an embodiment of the present disclosure. The charge pump device 10 includes multi-stage charge pump circuits 1001 to 100N.

[0051] In this embodiment, each stage of charge pump circuit 1001 to 100N can be implemented using charge pump circuit 100 as shown in FIG. 2 or charge pump circuit 200 as shown in FIG. 4. In this embodiment, the input terminal IN1 of charge pump circuit 1001 can receive the input voltage VIN, the output terminal OUT1 of charge pump circuit 1001 is coupled to the input terminal IN2 of charge pump circuit 1002, the output terminal OUT2 of charge pump circuit 1002 is coupled to the input terminal IN3 of charge pump circuit 1003, and so on. Finally, charge pump circuit 100N can output the output voltage VOUT. In this embodiment, by means of the large swing switching clock signals SIG ACLK0 and SIG ACLK1, each stage of charge pump device 10 (i.e., each stage of charge pump circuit 1001 to 100N) can contribute the full voltage drop of VH1 provided by the boost clock signals SIG CLK0 and SIG CLK1. In other words, compared to a conventional charge pump 90, the charge pump device 10 achieves higher efficiency in charge transfer at each stage.

[0052] In summary, the charge pump circuit and charge pump device provided in the specific embodiments of this disclosure can utilize a two-phase boost clock signal and a turn-off clock signal, so that the voltage drop contributed by each stage can be the entire voltage drop provided by the boost clock signal. That is, the charge pump circuit and charge pump device in this disclosure can achieve better charge transfer efficiency, and therefore the charge pump circuit is particularly suitable for low-power designs. Furthermore, the charge pump circuit and charge pump device provided in the embodiments of this disclosure can utilize the voltage drop of the turn-off clock signal to assist in boosting the output voltage, thereby further improving the efficiency of the charge pump circuit and charge pump device. [Simplified Explanation of the Diagram]

[0010] The contents of this disclosure can be understood more fully by referring to the accompanying illustrations, detailed description and the claims, wherein similar element symbols in different illustrations may refer to similar elements.

[0011] Figure 1 illustrates a conventional Dickson charge pump.

[0012] Figure 2 illustrates a charge pump circuit according to an embodiment of the present disclosure.

[0013] Figure 3 illustrates the voltage and signal waveforms of the pump unit in Figure 2 according to an embodiment of the present disclosure.

[0014] Figure 4 illustrates a charge pump circuit according to another embodiment of the present disclosure.

[0015] Figure 5 illustrates the voltage and signal waveforms of the pump unit in Figure 4 according to an embodiment of the present disclosure.

[0016] Figure 6 illustrates the waveform of a clock signal according to an embodiment of the present disclosure.

[0017] FIG7 illustrates a charge pump device according to an embodiment of the present disclosure.

Claims

1. A charge pump circuit, comprising: an input terminal for receiving an input voltage; an output terminal for outputting an output voltage; a third capacitor having a first terminal and a second terminal for receiving a third clock signal; a fourth capacitor having a first terminal and a second terminal for receiving a fourth clock signal; a first pump unit, comprising: a first capacitor having a first terminal and a second terminal for receiving a first clock signal; a second capacitor having a first terminal and a second terminal for receiving a second clock signal; and a first transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. A second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal; a first auxiliary control unit is coupled to the control terminal, the input terminal, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor, and is configured to turn off the second transistor when the first clock signal is at a first high voltage, and to turn on the second transistor when the first clock signal is at a low voltage; and a first output transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the third capacitor; The first clock signal and the second clock signal are in phase, and the first clock signal oscillates between the low voltage and the first high voltage. The second clock signal oscillates between the low voltage and a second high voltage higher than the first high voltage. The first clock signal and the third clock signal are out of phase, and the third clock signal and the fourth clock signal are in phase. The third clock signal oscillates between the low voltage and the first high voltage, and the fourth clock signal oscillates between the low voltage and the second high voltage. The first output transistor is used to turn on when the first clock signal is at the low voltage and to turn off when the first clock signal is at the first high voltage.

2. The charge pump circuit as claimed in claim 1, wherein a difference between the second high voltage and the low voltage is twice a difference between the first high voltage and the low voltage.

3. The charge pump circuit as claimed in claim 1 further comprises: a second pump unit, including: the third capacitor; the fourth capacitor; a third transistor having a first terminal coupled to the input terminal, a second terminal coupled to the third capacitor and a control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor; A fourth transistor having a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal; and a second auxiliary control unit coupled to the control terminal, the input terminal, the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the fourth capacitor, and configured to turn off the fourth transistor when the third clock signal is at the first high voltage, and to turn on the fourth transistor when the third clock signal is at the low voltage; and a second output transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the first transistor; When the first output transistor is turned on, the first output transistor generates the output voltage based on a voltage at the second terminal of the first transistor; and the second output transistor is turned on when the third clock signal is at the low voltage to generate the output voltage based on a voltage at the second terminal of the third transistor, and is turned off when the third clock signal is at the first high voltage.

4. The charge pump circuit as claimed in claim 3, wherein the first auxiliary control unit comprises: a fifth transistor having a first terminal coupled to the input terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the second terminal of the second capacitor; and a sixth transistor having a first terminal coupled to the control terminal of the second transistor, a second terminal coupled to the second terminal of the third capacitor, and a control terminal coupled to the second terminal of the fourth capacitor.

5. The charge pump circuit as claimed in claim 4, wherein the second auxiliary control unit comprises: a seventh transistor having a first terminal coupled to the input terminal, a second terminal coupled to the control terminal of the fourth transistor, and a control terminal coupled to the second terminal of the fourth capacitor; and an eighth transistor having a first terminal coupled to the control terminal of the fourth transistor, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor.

6. The charge pump circuit as claimed in claim 3, wherein a base terminal of the first output transistor and a base terminal of the second output transistor are coupled to the output terminal.

7. The charge pump circuit as claimed in claim 3, further comprising: a first well select transistor having a first terminal coupled to the first terminal of the first output transistor, a second terminal coupled to the second terminal of the third capacitor, and a base terminal coupled to the second terminal of the first well select transistor and a base terminal of the first output transistor; and a second well select transistor having a first terminal coupled to the first terminal of the second output transistor, a second terminal coupled to the second terminal of the first well select transistor, a control terminal coupled to the second terminal of the first capacitor, and a base terminal coupled to the second terminal of the second well select transistor and a base terminal of the second output transistor.

8. The charge pump circuit as claimed in claim 1, wherein the first transistor and the second transistor are N-type transistors, and the output voltage is less than the ground voltage when the input voltage is ground voltage.

9. The charge pump circuit as claimed in claim 1, wherein the first pump unit further includes a voltage gap unit coupled between the second terminal of the second capacitor and the second terminal of the first transistor, and is configured to, when the first clock signal is at the first high voltage, make a voltage at the second terminal of the second capacitor higher than a voltage at the second terminal of the first transistor by a gap voltage, wherein the gap voltage is greater than a threshold voltage of the first transistor.

10. The charge pump circuit as claimed in claim 9, wherein the voltage gap unit comprises at least one diode or at least one diode-connected transistor.

11. The charge pump circuit as claimed in claim 9, wherein the voltage gap unit comprises: a first diode-connected transistor having a first terminal coupled to the second terminal of the second capacitor, a second terminal, and a control terminal coupled to the first terminal of the first diode-connected transistor; and a second diode-connected transistor having a first terminal coupled to the second terminal of the first diode-connected transistor, a second terminal coupled to the second terminal of the first transistor, and a control terminal coupled to the first terminal of the second diode-connected transistor.

12. The charge pump circuit as claimed in claim 11, wherein a threshold voltage of the first diode connected to the transistor, a threshold voltage of the second diode connected to the transistor, and a threshold voltage of the first transistor are equal.

13. The charge pump circuit as claimed in claim 11, wherein an effective channel width of the first transistor is greater than an effective channel width of the first diode-connected transistor.

14. The charge pump circuit as claimed in claim 1, wherein the first auxiliary control unit includes at least one transistor, the size of which is larger than the size of the second transistor and the size of each transistor in the first auxiliary control unit.

15. The charge pump circuit as claimed in claim 1, wherein a rising edge of the first clock signal leads a rising edge of the second clock signal, and a falling edge of the first clock signal lags a falling edge of the second clock signal.

16. A charge pump device, comprising: a multi-stage charge pump circuit, wherein an input terminal of a subsequent stage charge pump circuit is connected to an output terminal of a preceding stage charge pump circuit; wherein a first stage charge pump circuit comprises: an input terminal; an output terminal; a first pump unit comprising: a first capacitor having a first terminal and a second terminal for receiving a first clock signal; a second capacitor having a first terminal and a second terminal for receiving a second clock signal; and a first transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor; A second transistor having a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal; and a first auxiliary control unit coupled to the control terminal, the input terminal, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor, and configured to turn off the second transistor when the first clock signal is at a first high voltage, and to turn on the second transistor when the first clock signal is at a low voltage; a second pump unit comprising: a third capacitor having a first terminal and a second terminal for receiving a third clock signal; a fourth capacitor having a first terminal and a second terminal for receiving a fourth clock signal; and a third transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the third capacitor, and a control terminal coupled to the second terminal of the fourth capacitor; A fourth transistor has a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal; and a second auxiliary control unit coupled to the control terminal, the input terminal, the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the fourth capacitor, and configured to turn off the fourth transistor when the third clock signal is at the first high voltage, and to turn on the fourth transistor when the third clock signal is at the low voltage; a first output transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the third transistor; a second output transistor has a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the first transistor; The first clock signal is in phase with the second clock signal, the first clock signal oscillates between the low voltage and the first high voltage, and the second clock signal oscillates between the low voltage and a second high voltage higher than the first high voltage; the first clock signal is out of phase with the third clock signal, and the third clock signal is in phase with the fourth clock signal.The third clock signal oscillates between the low voltage and the first high voltage, and the fourth clock signal oscillates between the low voltage and the second high voltage; the first output transistor is turned on when the first clock signal is at the low voltage to generate an output voltage based on a voltage at the second terminal of the first transistor, and is turned off when the first clock signal is at the first high voltage; and the second output transistor is turned on when the third clock signal is at the low voltage to generate the output voltage based on a voltage at the second terminal of the third transistor, and is turned off when the third clock signal is at the first high voltage.

17. The charge pump device as claimed in claim 16, wherein the output of the first-stage charge pump circuit is coupled to an input of a second-stage charge pump circuit of the multi-stage charge pump circuit.

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