Vertical thin film transistor and manufacturing method thereof

Abstract

A vertical thin-film transistor includes a first semiconductor layer, a sacrificial layer, a second semiconductor layer, a third semiconductor layer, a first gate, a source, and a drain. The first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion. The sacrificial layer covers the extended portion of the first semiconductor layer and exposes the first heavily doped portion. The second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion. The third semiconductor layer covers and contacts a portion of the first heavily doped portion, the sidewalls of the sacrificial layer, and a portion of the second heavily doped portion. In a direction perpendicular to the substrate, the second heavily doped portion overlaps the extended portion, and the first gate overlaps the second heavily doped portion, the extended portion, and the third semiconductor layer. The source and drain are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

Claims

1. A vertical thin-film transistor, comprising: A first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion; A sacrificial layer is disposed on the substrate, the sacrificial layer covering the extension portion and exposing the first heavily doped portion; a second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion, wherein the second heavily doped portion overlaps with the extension portion of the first semiconductor layer in a direction perpendicular to the substrate; a third semiconductor layer covers and contacts a portion of the first heavily doped portion, a sidewall of the sacrificial layer, and a portion of the second heavily doped portion; a first gate is disposed on the substrate, wherein the first gate overlaps the second heavily doped portion, the extension portion, and the third semiconductor layer in a direction perpendicular to the substrate; and a source and a drain are disposed on the substrate and electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

2. The vertical thin-film transistor as described in claim 1, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer, wherein the first gate is disposed on the dielectric layer and overlaps the first heavily doped portion in the direction perpendicular to the substrate.

3. The vertical thin-film transistor as claimed in claim 2, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

4. The vertical thin-film transistor as described in claim 2, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; and a second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts the second heavily doped portion and the third semiconductor layer, wherein the source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

5. The vertical thin-film transistor as claimed in claim 4, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the projection of the first contact hole and the second contact hole onto the substrate along the direction perpendicular to the substrate lies within the projection of the first etch protection pattern and the second etch protection pattern onto the substrate along the direction perpendicular to the substrate.

6. The vertical thin-film transistor as claimed in claim 1, wherein the sacrificial layer has a first sublayer and a second sublayer, and the first gate is disposed between the first sublayer and the second sublayer.

7. The vertical thin-film transistor as claimed in claim 6, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

8. The vertical thin-film transistor as described in claim 6, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; and a second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts the second heavily doped portion and the third semiconductor layer, wherein the source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

9. The vertical thin-film transistor of claim 8, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the projections of the first contact hole and the second contact hole onto the substrate along the direction perpendicular to the substrate are located within the projections of the first etch protection pattern and the second etch protection pattern onto the substrate along the direction perpendicular to the substrate.

10. The vertical thin-film transistor as claimed in claim 6, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer; A second gate is disposed on the dielectric layer and overlaps the first heavily doped portion, the second heavily doped portion, the extension portion and the third semiconductor layer in the direction perpendicular to the substrate.

11. The vertical thin-film transistor of claim 1, wherein the extension of the first semiconductor layer has a surface connected to the sacrificial layer, and the angle between the sidewall of the sacrificial layer and the surface of the extension is less than 60 degrees.

12. A method for manufacturing a vertical thin-film transistor, comprising: A first semiconductor material layer is formed on a substrate; A sacrificial layer is formed on the first semiconductor material layer, the sacrificial layer covering a first portion of the first semiconductor material layer and exposing a second portion of the first semiconductor material layer; a second semiconductor material layer is formed on the sacrificial layer; a heavy doping process is performed on the second portion of the first semiconductor material layer and the second semiconductor material layer; after the heavy doping process is completed, a third semiconductor layer is formed on the first semiconductor material layer and the second semiconductor material layer; a laser annealing process is performed on the first semiconductor material layer and the second semiconductor material layer, wherein after the heavy doping process and the laser annealing process, the first portion and the second portion of the first semiconductor material layer respectively form an extension portion and a first heavily doped portion of the first semiconductor material layer, and the second semiconductor material layer forms a second heavily doped portion of the second semiconductor material layer; a gate is formed on the substrate; and a source and a drain are formed to electrically connect the first heavily doped portion and the second heavily doped portion, respectively.

13. The method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the laser annealing process is performed after the heavy doping process, and the step of forming the third semiconductor layer includes: Form a third semiconductor material layer; And perform the laser annealing process on the third semiconductor material layer.

14. A method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the laser annealing process precedes the heavy doping process, and the step of forming the third semiconductor layer includes: Form a third semiconductor material layer; And perform another laser annealing process on the third semiconductor material layer.

15. The method for manufacturing a vertical thin-film transistor as described in claim 12, further comprising: A dielectric layer is formed to cover the third semiconductor layer, wherein the gate is formed on the dielectric layer.

16. A method for manufacturing a vertical thin-film transistor as claimed in claim 12, wherein the step of forming the sacrificial layer includes: A first sub-sacrificial material layer and a second sub-sacrificial material layer are sequentially formed on the first semiconductor material layer, wherein the gate is formed after the formation of the first sub-sacrificial material layer and before the formation of the second sub-sacrificial material layer; and a patterning process is performed on the first sub-sacrificial material layer and the second sub-sacrificial material layer to form a first sub-layer and a second sub-layer of the sacrificial layer.

17. The method for manufacturing a vertical thin-film transistor as described in claim 12, further comprising: Before forming the third semiconductor layer, a first etch protection pattern and a second etch protection pattern are formed on the first semiconductor material layer and the second semiconductor material layer, respectively.

18. A method for manufacturing a vertical thin-film transistor as claimed in claim 17, wherein the first etch protection pattern and the second etch protection pattern are formed after the heavy doping process is completed.

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