Forward error correction synchronization method and forward error correction synchronization system capable of recovering synchronization of forward error correction blocks

Abstract

A forward error correction (FEC) synchronization method includes establishing a connection between a source terminal and a destination terminal; periodically transmitting a marker symbol from the source terminal to the destination terminal; after the destination terminal receives the marker symbol, identifying the marker symbol, collecting a plurality of symbols transmitted from the source terminal to generate a plurality of forward error correction (FEC) blocks received by the destination terminal, and synchronizing the plurality of FEC blocks between the source terminal and the destination terminal based on the marker symbol. The marker symbol contains a predefined pattern.

Description

[Technical Field]

[0001] This invention relates to a forward error correction synchronization method and system, and particularly to a method and system for restoring forward error correction block synchronization. [Previous Technology]

[0002] Forward error correction (FEC) is a mechanism that recovers erroneous packets on a link by sending additional parity padding to the packets. In other words, FEC codes can be considered as special codewords used to detect and correct errors. With the redundant information sent by the transmitter, the receiver can detect certain errors from the received data. Because FEC technology can resist errors and improve the robustness of signal communication, it is widely used in various high-speed multimedia communications to correct corrupted data.

[0003] However, when the receiving terminal (considered as the receiver) fails to detect the FEC-enabled sequence due to a large number of bit errors or severe channel interference, although the receiving terminal can maintain symbol synchronization, it may fail to synchronize the FEC block because it does not know when the source (considered as the transmitter) started sending FEC-enabled data.

[0004] Therefore, developing an FEC synchronization system capable of restoring FEC block synchronization in high-speed multimedia communication is an important design problem. [Summary of the Invention]

[0005] In one embodiment of the present invention, a forward error correction (FEC) synchronization method is disclosed. The FEC synchronization method includes establishing a connection between a source terminal and a destination terminal; periodically transmitting a marker symbol from the source terminal to the destination terminal; after the marker symbol is received by the destination terminal, the destination terminal identifies the marker symbol; after the marker symbol is successfully identified, collecting a plurality of symbols transmitted from the source terminal to generate a plurality of forward error correction (FEC) blocks received by the destination terminal; and synchronizing the plurality of FEC blocks between the source terminal and the destination terminal according to the marker symbol. The marker symbol contains a predefined pattern.

[0006] In another embodiment of the present invention, a forward error correction (FEC) synchronization system is disclosed. The FEC synchronization system includes a source terminal and a destination terminal connected to the source terminal. The source terminal includes an 8b / 10b encoder and an FEC encoder connected to the 8b / 10b encoder. The destination terminal includes a 10b / 8b decoder and an FEC decoder connected to the 10b / 8b decoder. After a connection is established between the source terminal and the destination terminal, the source terminal periodically transmits a marker symbol to the destination terminal. The destination terminal identifies the marker symbol upon receipt. After successful identification of the marker symbol, the destination terminal collects a plurality of symbols transmitted from the source terminal to generate a plurality of FEC blocks received by the destination terminal. The plurality of FEC blocks are synchronized between the source terminal and the destination terminal by the destination terminal based on the marker symbol. The marker symbol contains a predefined pattern.

[0007] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the various drawings and the preferred embodiments shown in the drawings.

Implementation Method

[0009] Figure 1 is a block diagram of a forward error correction (FEC) synchronization system 100 according to an embodiment of the present invention. The FEC synchronization system 100 includes a source terminal 10 and a destination terminal 11. The destination terminal 11 is connected to the source terminal 10. The source terminal 10 can be considered as a data transmitter, such as a graphics card. The destination terminal 11 can be considered as a data receiver, such as a display device or monitor. In order to perform high-speed data communication between the source terminal 10 and the destination terminal 11, the source terminal 10 can start a connection training phase at an appropriate connection rate and an appropriate number of channels. The destination terminal 11 can be trained to perform clock recovery, channel equalization, and symbol locking functions (i.e., M symbol bit alignment). Therefore, the connection L between the source terminal 10 and the destination terminal 11 can correspond to a high-speed media channel connection. The source terminal 10 includes an 8b / 10b encoder 10a and an FEC encoder 10b. The FEC encoder 10b is connected to the 8b / 10b encoder 10a. Here, the 8b / 10b encoder 10a is used to encode 8-bit data segments of data stream DS1 into 10-bit symbols to achieve DC balance and bounded difference. The FEC encoder 10b can be used to linearly encode a set of symbols using a generator matrix with parity information. The FEC encoder 10b can output multiple FEC blocks. However, the FEC synchronization system 100 is not limited to the 8b / 10b encoder 10a and FEC blocks of a specific size. For example, each FEC block can contain N symbols. Each symbol can contain M symbol bits. N and M are positive integers. Furthermore, the destination terminal 11 can include a 10b / 8b decoder 11b and an FEC decoder 11a. The FEC decoder 11a is connected to the 10b / 8b decoder 11b. The FEC decoder 11a can be used to decode each FEC block. The 10b / 8b decoder 11b can be used to decode each symbol encoded by the 8b / 10b encoder 10a to generate a decoded data stream DS2. In the FEC synchronization system 100, after the connection L between the source terminal 10 and the destination terminal 11 is established, the source terminal 10 can periodically transmit a marker symbol to the destination terminal 11. The destination terminal 11 can identify the marker symbol after receiving it. Then, the destination terminal 11 can collect multiple symbols transmitted from the source terminal 10 to generate multiple FEC blocks received by the destination terminal 11 after the marker symbol is successfully identified. Here, the multiple FEC blocks can be synchronized between the source terminal 10 and the destination terminal 11 according to the marker symbol. The marker symbol can contain a predefined pattern. The details of the FEC block synchronization performed by the FEC synchronization system 100 are described below.

[0010] Figure 2 is a schematic diagram of data communication between source terminal 10 and destination terminal 11 in the FEC synchronization system 100. In Figure 2, the x-axis represents the timeline. After the FEC encoder 10b of source terminal 10 is enabled, source terminal 10 can transmit an FEC enable sequence FEC_EN to destination terminal 11. Then, after the FEC enable sequence FEC_EN is generated, source terminal 10 can transmit P FEC blocks (e.g., FEC blocks FEC0_0 to FEC0_255) to destination terminal 11. P can be a positive integer, such as 256 or 512. In Figure 2, destination terminal 11 can receive a plurality of symbols transmitted from source terminal 10 and then determine whether the received symbols can be detected as the FEC enable sequence FEC_EN. For example, in Figure 2, the sequence UN_DET formed by the received symbols cannot be identified as the FEC enable sequence FEC_EN due to multiple bit errors or severe channel interference. Therefore, since the FEC enable sequence FEC_EN cannot be detected or recognized by the destination terminal 11, the synchronization of P FEC blocks within the first duration fails. In other words, although FEC blocks FEC0_0 to FEC0_255 are transmitted from the source terminal 10 to the destination terminal 11, the FEC decoder 11a of the destination terminal 11 is not enabled because the FEC enable sequence FEC_EN cannot be detected or recognized by the destination terminal 11. As a result, the destination terminal 11 processes FEC blocks FEC0_0 to FEC0_255 as "data symbols". It can be understood that the source terminal 10 can transmit a plurality of symbols to the destination terminal 11. The destination terminal 11 can still align the M symbol bits of each symbol to synchronize the plurality of symbols received by the destination terminal 11. However, since the destination terminal 11 processes FEC blocks FEC0_0 to FEC0_255 as "data symbols", FEC blocks FEC0_0 to FEC0_255 cannot be decoded by FEC decoder 11a during the first duration.

[0011] During the first duration, after the source terminal 10 generates P FEC blocks FEC0_0 to FEC0_255, the source terminal 10 can generate the marker symbol TG1. Therefore, at the start of the second duration, the source terminal 10 can transmit the marker symbol TG1 to the destination terminal 11. Then, after transmitting the marker symbol TG1 from the source terminal 10 to the destination terminal 11, the source terminal 10 can transmit P FEC blocks FEC1_0 to FEC1_255 to the destination terminal 11. As mentioned above, the marker symbol TG1 contains a predefined pattern. Therefore, after the destination terminal 11 obtains the predefined pattern, the destination terminal 11 can compare the predefined pattern with the marker symbol TG1 received by the destination terminal 11 to identify the marker symbol TG1. If the marker symbol TG1 is successfully identified by the destination terminal 11, this means that the start time of transmitting P FEC blocks FEC1_0 to FEC1_255 from the source terminal 10 can be aligned by the destination terminal 11. Therefore, although the destination terminal 11 loses synchronization of P FEC blocks FEC0_0 to FEC0_255 during the first duration, the destination terminal 11 can still "recover" synchronization of P FEC blocks FEC1_0 to FEC1_255 during the second duration based on the marker symbol TG1. After synchronization of P FEC blocks FEC1_0 to FEC1_255, the FEC decoder 11a of the destination terminal 11 can be enabled to decode the P FEC blocks FEC1_0 to FEC1_255. Similarly, after the source terminal 10 generates P FEC blocks FEC1_0 to FEC1_255 during the second duration, the source terminal 10 can generate the marker symbol TG2. The marker symbol TG1 and the marker symbol TG2 can be the same. In other words, the marker symbol TG1 can be generated periodically. The period of marker symbol TG1 can be defined as the transmission time difference between marker symbol TG1 and marker symbol TG2, which is equal to the time length for transmitting P FEC blocks FEC1_0 to FEC1_255. Similarly, if marker symbol TG2 is successfully recognized by the destination terminal 11, the subsequent FEC blocks following marker symbol TG2 can also be synchronized by the destination terminal 11.

[0012] Any hardware or technical modifications to the FEC synchronization system 100 are within the scope of this invention. For example, when the source terminal 10 terminates the FEC encoder 10b, the source terminal 10 can transmit an FEC disable sequence to the destination terminal 11. Then, the destination terminal 11 can receive the FEC disable sequence. After receiving the FEC disable sequence, the destination terminal 11 can disable the FEC decoder 11a to decode at least one FEC block. Furthermore, the marker symbols TG1 or TG2 can contain FEC parity marker (PM) information. The connection L between the source terminal 10 and the destination terminal 11 can be a display port (DP) connection or any high-speed media channel connection. The 8b / 10b encoder 10a and the 10b / 8b decoder 11b can be any pair of codecs used to achieve DC balance and finite difference. Furthermore, the marker symbols TG1 or TG2 can be any predefined symbols.

[0013] Figure 3 is a flowchart of the FEC synchronization method of the FEC synchronization system 100. The FEC synchronization method includes steps S301 to S305. Any technical or hardware modifications are within the scope of this invention.

[0014] Step S301: Establish a connection L between the source terminal 10 and the destination terminal 11;

[0015] Step S302: The source terminal 10 periodically sends the marker symbol TG1 to the destination terminal 11;

[0016] Step S303: After receiving the marker symbol TG1, the destination terminal 11 identifies the marker symbol TG1;

[0017] Step S304: Collect multiple symbols transmitted by the source terminal 10 to generate multiple FEC blocks FEC1_0 to FEC1_255 received by the destination terminal 11 after successfully identifying the tag symbol TG1.

[0018] Step S305: Synchronize multiple FEC blocks FEC1_0 to FEC1_255 between the source terminal 10 and the destination terminal 11 according to the marker symbol TG1.

[0019] The details of steps S301 to S305 have been previously described. Therefore, they are omitted here. In the FEC synchronization system 100, periodic marker symbols are introduced for synchronizing FEC blocks. Since the transmission time difference between two marker symbols is equal to the time length for transmitting P FEC blocks, the marker symbols can be used to align the start and end times of each P FEC block period. Therefore, even if the FEC enable sequence is not detected by the destination terminal 11, the destination terminal 11 can still recover the FEC block synchronization between the source terminal 10 and the destination terminal 11 based on the marker symbols. As a result, decoding errors or synchronization errors of incoming FEC blocks can be reduced.

[0020] In summary, this invention discloses an FEC synchronization method and an FEC synchronization system. The FEC synchronization system can use periodic marker symbols to align the start and end times of each FEC block cycle. Therefore, when the destination terminal does not detect an FEC enable sequence, FEC block synchronization can be restored. Since FEC block synchronization can be restored, decoding or synchronization errors of incoming FEC blocks can be reduced.

[0021] Those skilled in the art will readily observe that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the scope and limits of the appended claims. The above description is merely a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a block diagram of a forward error correction (FEC) synchronization system according to an embodiment of the present invention. Figure 2 illustrates the data communication between the source terminal and the destination terminal of the FEC synchronization system in Figure 1. Figure 3 illustrates a flowchart of the FEC synchronization system in Figure 1 performing the FEC synchronization method.

Claims

1. A forward error correction (FEC) synchronization method, comprising: Establish a connection between a source terminal and a destination terminal; A marker symbol is periodically transmitted from the source terminal to the destination terminal; After the marker symbol is received by the destination terminal, the destination terminal identifies the marker symbol. After the marker symbol is successfully identified, a plurality of symbols transmitted from the source terminal are collected to generate a plurality of forward error correction (FEC) blocks received by the destination terminal. Based on the marker symbol, the plurality of FEC blocks are synchronized between the source terminal and the destination terminal; an FEC disable sequence is transmitted from the source terminal to the destination terminal; Terminate the FEC encoder of the source terminal; And after the FEC disabled sequence is received by the destination terminal, disable the FEC decoder of the destination terminal to stop the destination terminal from decoding the at least one FEC block; wherein the marker symbol contains a predefined pattern.

2. The method as described in claim 1, further comprising: After the plurality of FEC blocks are synchronized, the destination terminal decodes the plurality of FEC blocks.

3. The method as described in claim 1, wherein each FEC block contains N symbols, each symbol contains M symbol bits, and the period of the symbol is equal to P FEC blocks, where N, M, and P are positive integers.

4. The method as described in claim 3, further comprising: The plurality of symbols are transmitted from the source terminal to the destination terminal; And the destination terminal aligns the M symbol bits of each symbol to synchronize the plurality of symbols received by the destination terminal.

5. The method as described in claim 3, further comprising: After the marker symbol is transmitted from the source terminal to the destination terminal, the P FEC blocks are transmitted from the source terminal to the destination terminal.

6. The method as described in claim 1, wherein the destination terminal identifies the marker symbol after the marker symbol is received by the destination terminal, comprising: The predefined pattern is obtained by the destination terminal; And compare the predefined pattern with the tag symbol received by the destination terminal to identify the tag symbol.

7. The method as described in claim 1, further comprising: An 8b / 10b encoder is used to encode the data stream by the source terminal to generate the plurality of symbols; wherein the connection between the source terminal and the destination terminal corresponds to a high-speed media channel.

8. A forward error correction (FEC) synchronization method, comprising: Establish a connection between a source terminal and a destination terminal; A marker symbol is periodically transmitted from the source terminal to the destination terminal; After the marker symbol is received by the destination terminal, the destination terminal identifies the marker symbol. After the marker symbol is successfully identified, a plurality of symbols transmitted from the source terminal are collected to generate a plurality of forward error correction (FEC) blocks received by the destination terminal. Based on the marking symbol, the plurality of FEC blocks are synchronized between the source terminal and the destination terminal; after the FEC encoder of the source terminal is enabled, an FEC enable sequence is transmitted from the source terminal to the destination terminal; And when the FEC enabled sequence is not detected by the destination terminal, the synchronization of the plurality of FEC blocks between the source terminal and the destination terminal is restored according to the marker symbol; wherein the marker symbol contains a predefined pattern.

9. The method as described in claim 1, wherein the marker symbol contains an FEC parity check marker (PM) information, and the link between the source terminal and the destination terminal is a display port (DP) link.

10. A forward error correction (FEC) synchronization system, comprising: A source terminal includes: an 8b / 10b encoder; and an FEC encoder connected to the 8b / 10b encoder; and a destination terminal connected to the source terminal, the destination terminal including: a 10b / 8b decoder; and an FEC decoder connected to the 10b / 8b decoder. After the connection between the source terminal and the destination terminal is established, the source terminal periodically transmits a marker symbol to the destination terminal. After the destination terminal receives the marker symbol, it identifies the marker symbol. After the marker symbol is successfully identified, the destination terminal collects a plurality of symbols transmitted from the source terminal to generate a plurality of FEC blocks received by the destination terminal. The plurality of FEC blocks are synchronized between the source terminal and the destination terminal according to the marker symbol, and the marker symbol contains a predefined pattern. In addition, the source terminal transmits an FEC disable sequence to the destination terminal, the source terminal terminates the FEC encoder, and after the FEC disable sequence is received by the destination terminal, the destination terminal disables the FEC decoder to stop the decoding of at least one FEC block by the destination terminal.

11. The system as described in claim 10, wherein the FEC decoder decodes the plurality of FEC blocks by the destination terminal after the plurality of FEC blocks are synchronized.

12. The system as described in claim 10, wherein each FEC block contains N symbols, each symbol contains M symbol bits, and the period of the symbol is equal to P FEC blocks, where N, M, and P are positive integers.

13. The system of claim 12, wherein the source terminal transmits a plurality of symbols to the destination terminal, and the destination terminal aligns M symbol bits of each symbol to synchronize the plurality of symbols received by the destination terminal.

14. The system as described in claim 12, wherein after the source terminal transmits a marker symbol from the source terminal to the receiving terminal, it transmits P FEC blocks to the receiving terminal.

15. The system of claim 10, wherein the destination terminal acquires a predetermined pattern, and the destination terminal compares the predetermined pattern with the marker symbol received by the destination terminal to identify the marker symbol.

16. The system of claim 10, wherein the source terminal uses an 8b / 10b encoder to encode the data stream to generate multiple symbols, the destination terminal uses a 10b / 8b decoder to decode the multiple symbols to generate a decoded data stream, and the connection between the source terminal and the destination terminal corresponds to a high-speed media channel.

17. A forward error correction (FEC) synchronization system, comprising: A source terminal includes: an 8b / 10b encoder; and an FEC encoder connected to the 8b / 10b encoder; and a destination terminal connected to the source terminal, the destination terminal including: a 10b / 8b decoder; and an FEC decoder connected to the 10b / 8b decoder. After the connection between the source terminal and the destination terminal is established, the source terminal periodically transmits a marker symbol to the destination terminal. After the destination terminal receives the marker symbol, it identifies the marker symbol. After the marker symbol is successfully identified, the destination terminal collects multiple symbols transmitted from the source terminal to generate multiple FEC blocks received by the destination terminal. The multiple FEC blocks are synchronized between the source terminal and the destination terminal according to the marker symbol, and the marker symbol contains a predefined pattern. In addition, after the source terminal enables the FEC encoder, it transmits an FEC enable sequence to the receiving terminal, and the receiving terminal restores the synchronization of multiple FEC blocks between the source terminal and the receiving terminal according to the marker symbol when the receiving terminal does not detect the FEC enable sequence.

18. The system as described in claim 17, wherein the marker symbol contains FEC parity marker (PM) information, and the connection between the source terminal and the destination terminal is a display port (DP) connection.

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