Integrated circuit device, read-only memory circuit and manufacturing method of integrated circuit device

Abstract

An IC device includes a first transistor and a second transistor. The first transistor includes a first gate coupled to a first word line and including a first work function configuration, a first metal boundary (MD) segment adjacent to the first gate and coupled to one of a bit line or a reference line, and a second MD segment adjacent to the first gate and coupled to the other of the bit line or reference line. The second transistor includes a second gate coupled to a second word line and including a second work function configuration different from the first work function configuration, a second MD segment adjacent to the second gate, and a third MD segment adjacent to the second gate and coupled to one of a bit line or a reference line.

Description

Technical Field

[0001] none Prior Technology

[0002] The ongoing trend towards miniaturization of integrated circuits (ICs) is resulting in smaller devices with lower power consumption, while offering more functionality at a higher speed than earlier technologies. This miniaturization has been achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify semiconductor device designs, while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The present invention discloses an embodiment of the features, which are best understood when read in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In practice, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic diagram of a memory circuit according to some embodiments. Figures 2A to 2D are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments. Figures 3A to 3D are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments. Figures 4A to 4D are plan views, side views, and cross-sectional views of an IC device and layout according to some embodiments. Figure 5A depicts memory circuit operating parameters according to some embodiments. Figures 5B to 5D are cross-sectional views of IC structures and layouts according to some embodiments. Figure 6 is a flowchart of a method for operating memory circuits according to some embodiments. Figure 7 is a flowchart of a method for manufacturing an IC device according to some embodiments. Figure 8 is a flowchart of a method for generating an IC layout diagram according to some embodiments. Figure 9 is a block diagram of a system for generating IC layout diagrams according to some embodiments. Figure 10 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, values, operations, materials, configurations, or the like are described below to simplify one embodiment of this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are also contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0007] In various embodiments, the integrated circuit (IC) device, read-only memory (ROM) circuit, and corresponding method include a transistor having one of a predetermined number of power function configurations. The multiple power function configurations and, in some embodiments, threshold voltages corresponding to the power function configurations represent encoding levels, enabling the ROM circuit to determine the encoding level by detecting the power function configuration of a single IC device transistor (e.g., by detecting threshold voltages) and output a complex number of bits based on the encoding level.

[0008] Therefore, compared to other methods, such as those that use a single transistor location to represent a binary code level based on the presence or absence of a working transistor, this IC device can achieve increased coding density by providing multi-level coding within a smaller area. Because the IC device includes a working transistor at each transistor location, it is also less susceptible to decoding via reverse engineering (e.g., by optical methods) compared to other methods, thereby providing enhanced coding security.

[0009] As described below, according to various embodiments, Figure 1 is a schematic diagram of memory circuit 100; Figures 2A to 2D, 3A to 3D, and 4A to 4D are plan views, side views, and cross-sectional views of the corresponding IC device, as well as layout diagrams 200 to 400; Figure 5A depicts the operating parameters of the memory circuit; Figures 5B to 5D are cross-sectional views of the IC structure and IC layout diagrams 500B to 500D; Figure 6 is a flowchart of a method 600 for operating the memory circuit; Figure 7 is a flowchart of a method 700 for manufacturing the memory circuit; and Figure 8 is a flowchart of a method 800 for generating an IC layout diagram, for example, using the IC layout diagram generation system 900 depicted in Figure 9 and / or according to the IC manufacturing process 1000 depicted in Figure 10.

[0010] For illustrative purposes, Figures 1 through 5D are simplified. In some embodiments, one or more of the memory circuit 100, IC device / layout diagrams 200-400, or IC structure / layout diagrams 500B-500D include features other than those depicted in Figures 1 through 5D, such as global control and / or input / output (I / O) circuitry for generating, propagating, and / or receiving one or more signals, including signals discussed below and / or other signals. Some circuit elements depicted in Figures 1 through 5D include corresponding input and / or output terminals, which are not labeled for clarity.

[0011] Figure 1 is a schematic diagram of a memory circuit 100 according to some embodiments. In some embodiments, the memory circuit 100 is some or all of an IC. In some embodiments, the memory circuit 100 is included in another IC circuit and / or package, such as digital circuitry, analog circuitry, compute-in-memory (CIM) circuitry, system-on-chip (SOC), circuitry located in a fan-out, 3D, 2.5D, or other IC package, and / or other suitable circuitry.

[0012] The memory circuit 100 includes an array 110 of memory cells 112 coupled to a word line driver 120 and a read interface 130, and control circuitry 140 coupled to the word line driver 120 and the read / write interface 130 via a control signal bus CTLLB. The memory circuit 100 is configured to perform some or all of the methods described below, such as the method 600 described with respect to Figure 6, wherein data is read from one or more instances of the memory cells 112, as described below.

[0013] The configuration and orientation features of the memory circuit 100 depicted in Figure 1 are provided as a non-limiting example for illustrative purposes. Configurations and orientations other than those depicted in Figure 1 are also within the scope of an embodiment disclosed herein.

[0014] Two or more circuit elements are considered coupled based on one or more direct signal connections between them and / or one or more indirect signal connections including one or more logic devices (e.g., inverters or logic gates). In some embodiments, signal communication between two or more coupled circuit elements can be modified by one or more logic devices, for example, by reversing or making it conditional.

[0015] In the embodiment depicted in Figure 1, the memory circuit 100 is configured as a ROM circuit, which includes a memory cell 112 configured as a ROM cell, wherein data storage is part of the manufacturing process used to construct the memory circuit 100, for example, based on one or more IC layout diagrams, such as generated according to the method 700 described below with respect to Figure 7, for example, according to the method 800 described below with respect to Figure 8.

[0016] Array 110 includes memory cells 112 arranged in columns and rows (unlabeled) (individual instances are labeled for clarity). Each memory cell 112 is coupled to an instance of one of word lines WL0 to WL3, one of bit lines BL0 to BL3, and a reference line VSS.

[0017] For clarity, in some embodiments, in addition to corresponding word lines, bit lines, and reference lines, reference indicators WL0~WL3 also represent word line signals, reference indicators BL0~BL3 also represent bit line signals, and reference indicator VSS also represents reference voltage level VSS, such as ground, as described below.

[0018] In the embodiment depicted in Figure 1, for illustrative purposes, array 110 includes a total of four columns and rows. In various embodiments, array 110 includes a total of less than or greater than four columns and / or rows.

[0019] In the embodiment depicted in Figure 1, array 110 includes columns and rows (not labeled) arranged along individual column and row dimensions. In some embodiments, array 110 has a three-dimensional (3D) configuration, also known as a stacked configuration, which includes one or more array layers (not shown) arranged perpendicular to the column and row dimensions of the individual layers depicted in Figure 1, such that array 110 includes columns and rows in addition to those depicted in Figure 1.

[0020] In the embodiment depicted in Figure 1, each memory cell 112 is a three-terminal transistor device, including at least one gate coupled to one of the corresponding word lines WL0-WL3, at least one source / drain (S / D) terminal coupled to one of the bit lines BL0-BL3, and at least one S / D terminal coupled to one of the reference lines VSS. In some embodiments, one or more of the memory cells 112 include a fourth terminal, for example, a body terminal or main terminal coupled to one of the reference lines VSS.

[0021] In some embodiments, the memory circuit 100 includes one or more signal lines other than those depicted in the first figure, or different from those depicted in the first figure, such as one or more control lines or power supply voltage lines. In some embodiments, one or more memory cells 112 include one or more terminals other than those described above, or as alternatives to those terminals.

[0022] In some embodiments, the transistor device of a given memory cell 112 includes a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, for example, having a nanosheet configuration, or another suitable configuration including at least one gate. In various embodiments, the transistor device of a given memory cell 112 includes an n-type transistor or a p-type transistor. In various embodiments, each memory cell 112 includes one of IC devices 200-400, as described below with reference to Figures 2A to 4D, and / or includes at least one of gate structures 500B to 500D, as described below with reference to Figures 5A to 5D.

[0023] As described below, each memory cell 112 includes at least one gate having one of a predetermined number of work function configurations, such as the work function configurations WF or WF1 to WF4 described below with respect to Figures 2A to 5D. In some embodiments, each memory cell 112 thereby includes a transistor having one of a predetermined number of threshold voltages corresponding to the work function configuration.

[0024] In some embodiments, the total number of work function configurations is the same as the total number of threshold voltages. In some embodiments, based on more than one work function configuration corresponding to a given threshold voltage, the total number of work function configurations is greater than the total number of threshold voltages.

[0025] In various embodiments, a given work function configuration includes one or more layers of work function material positioned within a transistor gate electrode adjacent to one or more dielectric materials, which are used to electrically isolate the gate electrode from one or more active channel regions included in the transistor.

[0026] Work function materials with one or more layers include n-type and / or p-type work function materials having one or more thicknesses, concentration levels, dopants, impurities, or the like, used to increase or decrease the work function of the gate electrode by a target value compared to the work function of an equivalent gate electrode that does not contain one or more layers of work function materials. Non-limiting examples of work function materials include Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

[0027] The threshold voltage of a transistor is a function of operating conditions (e.g., voltage bias level, and / or temperature) and the work function of the corresponding gate electrode. For a predetermined set of operating conditions, such as within a predetermined voltage and / or temperature range, a given target value for an increase or decrease in the work function is transformed into an increase or decrease in the threshold voltage of a transistor including the corresponding gate electrode, compared to the threshold voltage of an equivalent transistor having an equivalent gate electrode that does not include one or more layers of work function material.

[0028] Therefore, each work function configuration corresponds to a predetermined threshold voltage of the corresponding transistor, so that a complex number of work function configurations can be used to define a predetermined number of threshold voltages.

[0029] As the total number of threshold voltages increases, the corresponding number of coding levels for each memory cell 112 also increases, thereby increasing the coding density of each memory cell 112. In some embodiments, as the total number of threshold voltages increases, one or more differences between threshold voltages decrease and / or the total span of threshold voltages increases, which may impair the ability to reliably detect each threshold voltage among the total number of threshold voltages.

[0030] In some embodiments, the total number of threshold voltages is in the range of two to 32. In some embodiments, the total number of threshold voltages is equal to four, eight, or 16. In some embodiments, the total number of threshold voltages is greater than 32.

[0031] The character line driver 120 is an electronic circuit that responds to one or more of the control signals CTRL received from the control circuit 140 on the control signal bus CTLLB and / or from one or more circuits (not shown) outside the memory circuit 100, and outputs character line signals WL0 to WL3 on individual character lines WL0 to WL3.

[0032] In some embodiments, a signal (e.g., a control signal CTRL) is a time-based series of transitions between high and low voltage levels, for example, corresponding to high and low logic levels. A high voltage or logic level corresponds to a voltage within a predetermined range of power supply voltage levels, such as the VDD voltage level; a low voltage or logic level corresponds to a voltage within a predetermined range of reference voltage levels, such as the VSS voltage level.

[0033] During a read operation, the word line driver 120 responds to one or more control signals CTRL by outputting word line signals WL0-WL3 on one of the corresponding word lines WL0-WL3, for example, corresponding to a column or row address, including one or more voltage levels, also referred to in some embodiments as one or more read or bias voltages WL0-WL3, to combine one or more bit line voltage levels BL0-BL3 with the read interface 130 operation discussed below, to detect the threshold voltage of the corresponding memory cell 112 transistor based on the corresponding work function configuration.

[0034] In some embodiments, the read interface 130, also referred to as the area I / O circuit 130, is an electronic circuit that responds to one or more control signals CTRL received from the control circuit 140 on the control signal bus CTLLB and / or from one or more circuits (not shown) outside the memory circuit 100, and outputs bit line signals BL0-BL3 on bit lines BL0-BL3.

[0035] During a read operation, the read interface 130 responds to one or more of the control signals CTRL by outputting bit line signals BL0-BL3 on the corresponding bit lines BL0-BL3. In some embodiments, these signals are also referred to as one or more read or bias voltages BL0-BL3, for example, corresponding to row or column addresses, including one or more voltage levels. These voltage levels are used in conjunction with the aforementioned one or more word line voltage levels WL0-WL3 and the read interface 130 operation discussed below to detect the threshold voltage of the transistor corresponding to the memory cell 112.

[0036] The read interface 130 includes one or more signal detection circuits (not shown), such as a current detector and / or a sense amplifier, to perform one or more read operations based on one or more signals received on one or more bit lines BL0 to BL3 and / or reference line VSS or a combination thereof, such as measuring one or more currents, voltages, or voltage differences, wherein the threshold voltage of the transistor of the selected memory cell 112 is detected.

[0037] One or more signal detection circuits are used to determine the encoding level of the selected memory cell 112 based on the detected threshold voltage. In some embodiments, the encoding level is determined based on one or a combination of the detected threshold voltages, which are within one or more predetermined voltage levels, or are greater than and / or less than one or more predetermined voltage levels. In some embodiments, one or more signal detection circuits are used to determine the encoding level of the selected memory cell 112 based on one or more currents (e.g., channel currents) corresponding to one or more voltage levels of bit line signals BL0 to BL3, combined with the gate work function configuration of the gate of the transistor corresponding to the memory cell 112 as described above.

[0038] One or more signal detection circuits of the read interface 130 are used to generate one or more output signals, such as signals W1

[00] to W4

[11] discussed below, which include a complex number of bits having values ​​corresponding to the encoding level of the memory cell 112 corresponding to the threshold voltage.

[0039] In some embodiments, a given output signal is considered to correspond to a single memory cell 112, and the total number of bits N of a plurality of bits is given by 2N>= the total number of threshold voltages of a plurality of threshold voltages of memory cell 112. Non-limiting examples include a total number of bits N equal to two corresponding to a total of four threshold voltages, a total number of bits N equal to three corresponding to a total of eight threshold voltages, and a total number of bits N equal to four corresponding to a total of 16 threshold voltages.

[0040] According to the embodiments discussed herein, control circuitry 140 is an electronic circuit used to control the operation of memory circuitry 100 by generating one or more control signals CTRL on control signal bus CTRLB and receiving them by word line driver 120 and read interface 130. In various embodiments, control circuitry 140 includes hardware processor 142 and non-transitory computer-readable storage medium 144. Among other things, storage medium 144 is also encoded with computer program code, i.e., a set of executable instructions. The instructions executed by hardware processor 142 represent (at least partially) memory circuitry operation tools that implement part or all of the method 700 (hereinafter referred to as the referred process and / or method) as described below with respect to Figure 7.

[0041] Processor 142 is electrically coupled to non-transitory computer-readable storage medium 144, an I / O interface, and a network via a bus (details not shown). The network interface is connected to a network (not shown) so that processor 142 and non-transitory computer-readable storage medium 144 can be connected to external components via the network. Processor 142 is used to execute computer program code encoded in non-transitory computer-readable storage medium 144 so that control circuitry 140 and memory circuitry 100 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 142 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0042] In one or more embodiments, the non-transitory computer-readable storage medium 144 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium 144 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the non-transitory computer-readable storage medium 144 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0043] In one or more embodiments, the non-transitory computer-readable storage medium 144 stores computer program code that causes the control circuitry 140 to generate control signals so that it can be used to perform part or all of the mentioned processes and / or methods. In one or more embodiments, the non-transitory computer-readable storage medium 144 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods.

[0044] With the above configuration, the memory circuit 100 includes memory cells 112 with multiple work function configurations, thereby having multiple threshold voltages representing the encoding level, so that the memory circuit 100 can determine the encoding level by detecting the threshold voltage of a single IC device transistor and output multiple bits based on the encoding level.

[0045] Therefore, compared to other methods, such as methods that use a single transistor location to represent a binary code level based on the presence or absence of a working transistor, this given memory cell 112 can achieve increased coding density by providing multi-level coding within a smaller area. Because the memory cell 112 includes a working transistor at each cell location, the array 110 of the memory cell 112 is also less easily decoded by reverse engineering (e.g., by optical methods) compared to other methods, thereby providing improved coding security.

[0046] The IC layout diagrams / devices 200-400 and IC layout diagrams / structures 500B-500D discussed below include some or all of the configurations of at least one of semiconductor substrates, active regions / areas, S / D regions / structures, MD regions / segments, gate regions / structures, metal regions / segments, and / or via regions / structures, each of which is discussed below.

[0047] A semiconductor substrate is a semiconductor wafer (e.g., a silicon (Si) wafer) or a portion (e.g., a die) of an epitaxial Si layer suitable for forming one or more IC devices (e.g., IC devices 200-400). In each of the embodiments discussed below, the semiconductor substrate includes a front side and a back side. In the front side, a first subset of features of the IC device is formed via a first set of manufacturing processes, such as a front-end-of-line (FEOL) process, a middle-end-of-line (MEOL) process, and a back-end-of-line (BEOL) process. In the back side, a second subset of features of the IC device is formed via a second set of manufacturing processes, such as a back-side metallization process, which is performed after the first set of manufacturing processes.

[0048] An active region (e.g., active region / region AA) is a region in the IC layout that defines an active region (also known as oxide diffusion or definition, OD) in a semiconductor substrate. This active region is included in the manufacturing process and may be directly in the semiconductor substrate or within an n-well or p-well region / region, where one or more IC device features, such as an S / D structure, are formed. In some embodiments, the active region is a planar transistor, FinFET, GAA transistor, or an n-type or p-type active region of another transistor configuration including a gate region / structure.

[0049] In various embodiments, the active region (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or the like), a dopant material (e.g., boron (B), aluminum (Al), phosphorus (P), arsenic (As), gallium (Ga)), or another suitable material.

[0050] In some embodiments, the active region is a region included in the manufacturing process that defines a nanosheet structure (e.g., a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping) in an IC layout diagram. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple multilayers of a given semiconductor material.

[0051] An S / D region / structure (e.g., S / D region / structure SD) is a region included in the manufacturing process that defines an S / D structure (also referred to in some embodiments as a semiconductor structure, having a doping type opposite to the corresponding active region / region) in an IC layout diagram. In some embodiments, the S / D region / structure is designed to have a lower resistivity than adjacent channel features, such as a portion of the corresponding active region / region of a planar FET, the fin structure of a FinFET, or the gate structure of a GAA transistor. In some embodiments, the S / D region / structure includes one or more portions having a doping concentration greater than one or more doping concentrations present in the corresponding channel feature. In some embodiments, the S / D region / structure includes one or more epitaxial regions of a semiconductor material (e.g., Si, SiGe, and / or silicon carbide SiC). An S / D region / structure (also referred to in some embodiments as an S / D terminal) may refer individually or collectively to the source or drain, depending on the context.

[0052] A MD region / segment (e.g., MD region / segment MD) is a portion in an IC layout that defines a MD segment (also referred to as a conductive segment, MD wire, or trace) in and / or on a semiconductor substrate, and is included in the conductive region during the manufacturing process. In some embodiments, the MD region overlaps with the active region at the location of the S / D region in the IC layout, and the corresponding MD segment contacts and is electrically connected to the S / D structure of the active region.

[0053] In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) overlying and contacting the substrate, and has a thickness small enough to form an insulating layer between the MD segment and the overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing low-resistance (i.e., resistance levels below predetermined threshold values ​​corresponding to one or more tolerance levels for the effect of resistance on circuit performance) electrical connections between IC structural elements.

[0054] In various embodiments, the MD segment includes a portion of a semiconductor substrate and / or an epitaxial layer, having a doping level, for example, based on the implantation process, sufficient to give the segment a low resistance level. In various embodiments, the doped MD segment includes one or more dopant materials having a doping concentration of about 1*10¹⁶ per cubic centimeter (cm⁻³) or higher.

[0055] In some embodiments, the manufacturing process includes two MD layers, and an MD region / segment (e.g., MD region / segment MD) refers to either of the two MD layers in the manufacturing process.

[0056] A gate region / structure (e.g., gate region / structure G or DG) is a region included in the manufacturing process as a part defining the gate structure in an IC layout. A gate structure is a volume comprising one or more conductive segments (e.g., gate electrodes) comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, thereby controlling the voltage supplied at adjacent gate dielectric layers.

[0057] In some embodiments, a given gate region in the IC layout diagram is included in the manufacturing process as a portion defining the gate electrode. The gate electrode includes a plurality of work function configurations corresponding to work function configurations, such as work function configurations WF1 to WF4, as discussed above with respect to Figure 1.

[0058] The gate dielectric layer, for example, the gate dielectric layer of a gate structure G or DG (such as the dielectric layer GD described below), is a volume comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8 or 7.0, such as alumina (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable for providing high resistance between IC structural elements, i.e., resistance levels higher than predetermined threshold values ​​corresponding to one or more tolerance levels of resistance to circuit performance.

[0059] In some embodiments, the gate region / structure corresponds to a dummy gate region / structure, such as a dummy gate region / structure DG. In some embodiments, the dummy gate region / structure includes a gate electrode electrically connected (e.g., bound) to one or more features (e.g., power rails or other metal segments or adjacent instances of the S / D region / structure) to turn off the transistor corresponding to the dummy gate region / structure and overlapping / underlying the active region / region by design. In some embodiments, the dummy gate region / structure overlapping / overlying the edge of the active region / region is referred to as a continuous poly on oxide definition edge (CPODE) region / structure.

[0060] Metal lines or regions (e.g., character lines WL0~WL3 or bit lines BL0~BL3) are portions in the IC layout that define metal lines or segments and are included in the manufacturing process. They include one or more conductive materials in a given front or back metal layer of the manufacturing process, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials.

[0061] In some embodiments, the metal region / segment corresponds to a first front metal layer (also referred to in some embodiments as a metal zero layer or front metal zero layer) or a second or higher level front metal layer in the manufacturing process. In some embodiments, the second front metal layer is referred to as a metal monolayer or front metal monolayer.

[0062] In some embodiments, a metal region / segment (e.g., a reference line VSS) corresponds to a component of a power distribution network used to distribute one or both of a power supply voltage (e.g., power supply voltage VDD) and a reference or ground voltage (e.g., reference voltage VSS). The power distribution network component is electrically connected to one or more features, such as additional metal regions / segments and / or via regions / structures, for distributing the corresponding power supply or reference voltage and is electrically isolated from IC components outside the distribution network.

[0063] A via region / structure (e.g., via region / structure VG or VD) is a region included in the manufacturing process as a part defining the via structure in an IC layout. The via structure includes one or more conductive materials used to provide electrical connection between a first (e.g., overlay) conductive structure (e.g., word lines WL0~WL3, bit lines BL0~BL3, or reference line VSS) and a second (e.g., underlay) conductive structure (e.g., metal segment, gate electrode of gate structure G or DG, instance of MD segment MD, or S / D structure). These conductive structures are aligned with the first conductive structure in the Z direction.

[0064] In some embodiments, the via region / structure VG corresponds to the underlying conductive structure that serves as the gate electrode of the gate region / structure G or DG, and / or the via region / structure VD corresponds to the underlying conductive structure that serves as the S / D region / structure or the MD region / segment MD.

[0065] Figures 2A to 2D, 3A to 3D, and 4A to 4D are plan views, side views, and cross-sectional views of individual IC layout diagrams / devices 200-400. Figures 2A, 3A, and 4A are plan views, including the X and Y directions; Figures 2B, 3B, and 3C are side views based on line A-A' corresponding to Figures 2A, 3A, or 4A, including the X and Z directions; Figures 2C, 3C, and 4C are cross-sectional views along line B-B' corresponding to Figures 2A, 3A, or 4A, including the Y and Z directions; Figures 2D, 3D, and 4D are cross-sectional views along line C-C' corresponding to Figures 2A, 3A, or 4A, including the Y and Z directions.

[0066] IC layouts / devices 200-400 include non-limiting examples of the memory cell 112 described above with respect to Figure 1, and for illustrative purposes, correspond to n-type GAA transistors with nanosheet configurations. IC layouts / devices including memory cells 112 corresponding to other transistor types (e.g., p-type transistors and / or FinFETs or planar transistors) are also within the scope of an embodiment disclosed herein.

[0067] As depicted in Figures 2A to 4D, each of the IC layout diagrams / devices 200 to 400 includes an active region / area AA, an S / D region / structure SD, an MD region / segment MD, a via region / structure VD, a gate region / structure G including a work function configuration WF, a dummy gate region / structure DG, a via region / structure VG, a bit line BL corresponding to one of the aforementioned bit lines BL0 to BL3, a reference line VSS, and one or more instances of each of the word lines WL0 and WL1. Each of the IC layout diagrams / devices 300 and 400 also includes word lines WL2 and WL3. In some cases, for clarity, not all instances of each feature are marked in Figures 2A to 4D.

[0068] In each of the embodiments depicted in Figures 2A to 4D, the work function configuration WF represents any one of the plurality of work function configurations WF as described above with respect to Figure 1, and is illustrated in the non-limiting examples discussed below with respect to Figures 5A to 5D.

[0069] As depicted in Figures 2A to 2D, the IC layout / device 200 includes an active region / region AA extending between a first and a second edge, which intersects / underlies instances of a dummy gate region / region DG. A total of four instances of the gate region / structure G intersect / overlay the active region / region AA, and a total of five instances of each of the S / D region / structure SD and MD region / segment MD intersect / overlay the active region / region AA adjacent to instances of the gate region / structure DG and G.

[0070] Three instances of via region / structure VD overlap / overlay alternating instances of MD region / segment MD and overlap / under one of bit line BL or reference line VSS; two instances of via region / structure VD overlap / overlay instances of other MD region / segment MD and overlap / overlay another of bit line BL and reference line VSS; two instances of via region / structure VG overlap / overlay instances of via gate region / structure G and overlap / under one of word line WL1; and two instances of via region / structure VG overlap / overlay two instances of via gate region / structure G and overlap / under one of word line WL0.

[0071] The IC layout / device 200 is thus used to include a first instance (marked) of a memory cell 112 corresponding to a transistor comprising two instances of a gate region / structure G coupled to a word line WL1 via an instance of a via region / structure VG, two adjacent instances of each of the S / D region / structure SD and MD region / segment MD coupled to one of the bit line BL or the reference line VSS via an instance of a via region / structure VD, and a single instance of each of the S / D region / structure SD and MD region / segment MD coupled to the other of the bit line BL or the reference line VSS via an instance of a via region / structure VD.

[0072] A second instance (unlabeled) of memory cell 112 corresponds to a transistor comprising two instances of gate region / structure G coupled to word line WL0 via an instance of via region / structure VG, two adjacent instances of each of S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of via region / structure VD, and a single instance of each of S / D region / structure SD and MD segment MD coupled to the other of bit line BL or reference line VSS via an instance of via region / structure VD. One instance of each of S / D region / structure SD, MD segment MD, and via region / structure VD is shared by the instances of memory cell 112.

[0073] As depicted in Figures 2A to 2D and Figures 3A to 3D, each of the IC layout diagrams / devices 300 and 400 includes a first instance of an active region / region AA extending between a first and a second instance of a dummy gate region / region DG.

[0074] IC layout / device 300 includes a first instance of an active region / area AA that extends continuously beyond instances of a dummy gate region / structure DG in both the positive and negative X directions. A via region / structure VG covers / overlays each instance of the dummy gate DG and covers / underlays a reference line VSS, such that during operation, by applying a reference voltage VSS to each instance of the dummy gate region / structure DG, portions of the active region AA between instances of the dummy gate region / structure DG are electrically isolated from the extended portions.

[0075] IC layout / device 400 includes a first instance of an active region / region AA extending between the first and second edges of an instance of a cross / underlying dummy gate region / region DG, and a second and third instance of an active region / region AA extending beyond the instance of the dummy gate region / structure DG in the positive and negative X directions away from the first instance of the active region / region AA, thereby being electrically isolated from the first instance of the active region / region AA.

[0076] Each of the IC layout diagrams / devices 300 and 400 includes a total of two instances of gate region / structure G, which cross over / overlay instances of active region / region AA between instances of dummy gate region / structure DG; and a total of three instances of S / D region / structure SD and MD region / segment MD, which cross over / overlay instances of active region / region AA adjacent to instances of gate region / structure DG and G.

[0077] Two instances of via region / structure VD overlap / overlay alternating instances of MD region / segment MD and overlap / overlay one of bit line BL or reference line VSS; one instance of via region / structure VD overlaps / overlays another instance of MD region / segment MD and overlaps / underlays the other of bit line BL and reference line VSS; one instance of via region / structure VG overlaps / overlays an instance of via gate region / structure G and overlaps / overlays word line WL2; and one instance of via region / structure VG overlaps / overlays an instance of via gate region / structure G and overlaps / underlays word line WL1.

[0078] IC layout / device 200 is thus used to include a first instance (marked) of memory cell 112 corresponding to a transistor including an instance of gate region / structure G coupled to word line WL2 via an instance of via region / structure VG, an adjacent instance of each of S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of via region / structure VD, and an adjacent instance of each of S / D region / structure SD and MD region / segment MD coupled to the other of bit line BL or reference line VSS via an instance of via region / structure VD.

[0079] A second instance (unlabeled) of memory cell 112 corresponds to a transistor comprising an instance of a gate region / structure G coupled to word line WL1 via an instance of a via region / structure VG; an adjacent instance of each of the S / D region / structure SD and MD region / segment MD coupled to one of bit line BL or reference line VSS via an instance of a via region / structure VD; and an adjacent instance of each of the S / D region / structure SD and MD region / segment MD coupled to the other of bit line BL or reference line VSS via an instance of a via region / structure VD. An instance of each of the S / D region / structure SD, MD segment MD, and via region / structure VD is shared by the instances of memory cell 112.

[0080] In the embodiments depicted in Figures 3A to 4D, each of IC layout diagrams / devices 300 and 400 includes third and fourth instances of memory cells 112, which correspond to word lines WL3 and WL0 and are configured similarly to the first and second instances of memory cells 112. In some embodiments, one or both of IC layout diagrams / devices 300 or 400 may not include one or both of the third or fourth instances of memory cells 112.

[0081] With the above configuration, each of the IC layout diagrams / devices 200 to 400 includes one or more instances of memory cells 112 with multiple work function configurations, thereby having multiple threshold voltages representing encoding levels, so that the memory circuit including one or more of the IC layout diagrams / devices 200 to 400 can achieve the benefits discussed above regarding the memory circuit 100.

[0082] According to various embodiments, Figure 5A depicts the memory circuit operating parameters, and Figures 5B to 5D are cross-sectional views of the IC layout / structure 500B to 500D (also referred to as gate region / structure 500B to 500D in some embodiments). Each gate region / structure 500B to 500D can be used as one or more instances of the gate region / structure G described above with respect to Figures 2A to 4D.

[0083] Figure 5A includes a channel current Id plotted as a function of the source-drain voltage VD of the transistor (e.g., the memory cell 112 mentioned above), having one of the threshold voltages Vth1 to Vth4 corresponding to the gate work function configuration, and non-limiting examples of which are depicted in Figures 5B to 5D.

[0084] In the embodiments depicted in Figures 5A to 5D, a total of four work function configurations WF1 to WF4 (each corresponding to the aforementioned work function configuration WF) correspond to a total of four threshold voltages Vth1 to Vth4. The threshold voltages Vth1 to Vth4 are associated with individual two-bit signals W1

[00] to W4

[11] . Other numbers of work function configurations, threshold voltages, and signal bits are also within the scope of one embodiment disclosed herein. In some embodiments, signals WF1

[00] to WF4

[11] are examples of the output signals of the read interface 130 described above with respect to Figure 1.

[0085] In the embodiment depicted in Figure 5A, the increased threshold voltages Vth1 to Vth4 correspond to increased signal values ​​

[00] to

[11] . Other relationships between threshold voltages and signal values, such as an increased threshold voltage corresponding to a decreased signal value, are also within the scope of this embodiment.

[0086] As depicted in Figures 5B to 5D, each of the gate regions / structures 500B to 500D includes a gate region / structure G, which includes one or more work function configurations WF1 to WF4, adjacent to one or more gate dielectric layers GD, and each gate dielectric layer GD is adjacent to the channel region of the corresponding active region / region AA. The work function configurations WF1 to WF4 correspond to individual threshold voltages Vth1 to Vth4 and signals W1

[00] to W4

[11] .

[0087] As depicted in Figures 5B to 5D, gate region / structure 500B corresponds to the nanosheet configuration of GAA transistor, gate region / structure 500C corresponds to the gate configuration of FinFET, and gate region / structure 500D corresponds to the gate configuration of planar transistor.

[0088] As depicted in Figure 5A, the IC layout / device including one or more of the gate regions / structures 500B to 500D (e.g., the aforementioned IC layout or device 200 to 400) can thereby achieve the aforementioned benefits regarding the memory circuit 100 and the IC layout and device 200 to 400.

[0089] Figure 6 is a flowchart of a method 600 for operating a memory circuit according to some embodiments. Method 600 can be used with memory circuits, such as memory circuit 100 including examples of memory cells 112 described above with respect to Figures 1 through 5D. In some embodiments, operation of method 600 is a subset of operations of methods for operating an IC (e.g., a System-on-a-Chip).

[0090] In some embodiments, the operation of method 600 is repeated, for example, sequentially with respect to a plurality of memory cells (e.g., multiple instances of memory cells 112 described above with respect to Figures 1 through 5D). In some embodiments, the operation of method 600 is part of an initialization sequence of an IC or IC package.

[0091] The order of operations of method 600 described in Figure 6 is for illustrative purposes only; the operations of method 600 can be performed in a different order than that depicted in Figure 6. In some embodiments, operations other than those depicted in Figure 6 are performed before, between, during, and / or after the operations depicted in Figure 6.

[0092] At operation 602, in some embodiments, a ROM cell of the memory circuit is selected. Selecting a ROM cell includes outputting a combination of word line and bit line signals based on one or more location identifiers (e.g., addresses) corresponding to the ROM cell.

[0093] In some embodiments, selecting a ROM unit includes selecting an example of a memory unit 112 of the memory circuit 100 described above with respect to Figures 1 through 5D.

[0094] At operation 604, the threshold voltage of the selected memory cell is detected. Detecting the threshold voltage includes detecting one of a plurality of predetermined threshold voltages, each threshold voltage being based on a corresponding gate work function configuration in a plurality of work function configurations.

[0095] In some embodiments, detecting the threshold voltage includes detecting the threshold voltage of an instance of memory cell 112 including a gate G work function configuration, as described above with respect to Figures 1 to 5D. In some embodiments, detecting the threshold voltage includes detecting the threshold voltage based on the work function configuration WF described above with respect to Figures 2A to 4D and / or the work function configurations WF1 to WF4 described above with respect to Figures 5A to 5D.

[0096] In some embodiments, detecting the threshold voltage includes using a read circuit of memory circuitry, such as the read interface 130 described above with respect to Figure 1.

[0097] In some embodiments, detecting the threshold voltage includes detecting one of the threshold voltages Vth1 to Vth4 described above with respect to Figures 5A to 5D.

[0098] At operation 606, in some embodiments, a plurality of bits are output having a value based on the detected threshold voltage of the selected memory cell. The plurality of bits output includes a plurality of bits corresponding to a number of possible predetermined threshold voltages of the selected memory cell, for example, as described above with respect to Figure 1.

[0099] In some embodiments, outputting a plurality of bits includes a read circuit using memory circuitry, such as the read interface 130 described above with respect to Figure 1.

[0100] In some embodiments, the output of a plurality of bits includes outputting one of the signals W1

[00] to W4

[11] described above with respect to Figures 5A to 5D.

[0101] In some embodiments, outputting a complex number of bits includes circuitry that outputs the complex number of bits to a location outside the memory circuitry, such as a SOC or other IC.

[0102] By performing some or all of the operations of method 600, the encoding of the ROM cell of the memory circuit is determined, and a complex number of bits having a value based on the function configuration of the ROM cell are output, thereby achieving the benefits described above for memory circuit 100, IC layout / device 200~400, and IC layout / structure 500B~500D.

[0103] Figure 7 is a flowchart of a method 700 for manufacturing an IC device according to some embodiments. Method 700 is operable to form some or all of the IC devices 200-400 described above with respect to Figures 1 through 5D.

[0104] In some embodiments, some or all of the operations of performing method 700 are portions of constructing a plurality of integrated circuit devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing a plurality of manufacturing operations (e.g., lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing a plurality of IC devices in a semiconductor wafer).

[0105] In some embodiments, the operation of method 700 is performed in the order depicted in Figure 7. In some embodiments, the operation of method 700 is performed in a different order than depicted in Figure 7. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 700. In some embodiments, performing some or all of the operations of method 700 includes performing one or more of the operations described below with respect to IC manufacturing system 1000 and Figure 10.

[0106] At operation 702, an active region is formed in the semiconductor substrate. Forming the active region includes forming an active region extending in a first direction between a first edge and a second edge. In some embodiments, forming the active region includes forming an example of the active region AA described above with respect to Figures 1 through 5D.

[0107] In some embodiments, forming active regions includes forming a plurality of active regions, for example, corresponding to the memory cell array (such as array 110) described above with respect to Figure 1.

[0108] In some embodiments, forming an active region includes forming an active region according to a GAA transistor, FinFET, or planar transistor configuration, for example, as described above with respect to Figures 1 through 5D.

[0109] In some embodiments, forming an active region includes performing a plurality of manufacturing processes, including one or more of photolithography, diffusion, implantation, deposition, etching, planarization, or other suitable operations.

[0110] At operation 704, a first transistor including a first gate work function configuration and a second transistor including a second gate work function configuration different from the first work function configuration are constructed in the active region. Constructing the first and second transistors includes constructing corresponding gates having first and second work function configurations corresponding to the threshold voltages of each of the first and second transistors.

[0111] In some embodiments, constructing the first and second transistors includes constructing an example of the memory cell 112 described above with respect to Figures 1 through 5D.

[0112] In some embodiments, constructing the first and second transistors includes constructing an array of memory cells, such as the array 110 described above with respect to Figure 1.

[0113] In some embodiments, constructing the first and second transistors includes constructing one or more of IC devices 200 to 400, including instances of memory cells 112 as described above with respect to Figures 2A to 4D.

[0114] In some embodiments, constructing the gates of the first and second transistors includes constructing one or more of the gate structures G described above with respect to Figures 2A to 4D and / or the gate structures 500B to 500D described above with respect to Figures 5A to 5D.

[0115] In some embodiments, constructing the first and second transistors includes constructing a GAA transistor, a FinFET, or a planar transistor.

[0116] In some embodiments, constructing the first and second transistors including the first and second work function configurations includes constructing the first and second transistors including examples of the work function configurations WF described above with respect to Figures 2A to 4D and / or the work function states WF1 to WF4 described above with respect to Figures 5A to 5D.

[0117] In some embodiments, constructing the first and second transistors including the first and second work function configurations includes performing a plurality of manufacturing processes, including one or more of lithography, diffusion, implantation, deposition, plasma treatment, etching, planarization, spin coating, soft baking, exposure, post-baking, development, rinsing, drying, or other suitable operations.

[0118] At operation 706, an electrical connection is formed from the first and second transistors to at least one of the word line, bit line, and reference line. Forming the electrical connection includes forming a via structure on the gate and S / D terminal of each transistor, and forming at least one corresponding word line, bit line, and reference line on the via structure, such that each of the first and second transistors is a working transistor.

[0119] In some embodiments, forming an electrical connection includes forming some or all of the following: a via structure VG on the gate structure G, a via structure VD on the MD segment MD, word lines WL0~WL3 on the gate via structure VGA, bit lines BL0~BL3 on the via structure VD, and a reference line VSS, as described above with respect to Figures 1 to 5D.

[0120] In some embodiments, forming an electrical connection includes forming an electrical connection to a memory circuit assembly, such as the word line driver 120 and the read interface 130 described above with respect to Figure 1.

[0121] In some embodiments, forming an electrical connection includes performing a plurality of manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form a plurality of consecutive low-resistance structures.

[0122] By performing some or all of the operations of method 700, an IC device is manufactured, wherein the first and second transistors include different work function configurations, thereby enabling the benefits described above with respect to memory circuit 100, IC devices 200-400, and IC structures 500B-500D.

[0123] Figure 8 is a flowchart of a method 800 for generating IC layout diagrams (e.g., one or more IC layout diagrams 200-400 as described above with respect to Figures 2A to 5D) according to some embodiments.

[0124] In some embodiments, generating an IC layout diagram includes generating an IC layout diagram corresponding to an IC device manufactured based on the generated IC layout diagram (e.g., IC devices 200-400 described above with respect to Figures 2A to 5D).

[0125] In some embodiments, some or all of the methods 800 are executed by a computer processor, such as the processor 902 of the IC layout generation system 900, which will be discussed below with reference to Figure 9.

[0126] Some or all of the operations of method 800 can be performed as part of a design procedure executed in a design plant (e.g., design plant 1020 as described below with respect to Figure 10).

[0127] In some embodiments, the operations of method 800 are performed in the order depicted in Figure 8. In some embodiments, the operations of method 800 are performed simultaneously and / or in a different order than that shown in Figure 8. In some embodiments, one or more operations are performed before, between, during, and / or after the execution of one or more operations of method 800.

[0128] At operation 802, in some embodiments, a plurality of power function configurations are allocated according to a ROM encoding pattern. In some embodiments, allocating a plurality of power function configurations includes obtaining ROM cells from a cell library, for example, cell library 907 as described below with respect to Figure 9, wherein each ROM cell includes a specific power function configuration.

[0129] In some embodiments, allocating a plurality of work function configurations includes allocating examples of the work function configurations WF described above with respect to Figures 2A to 4D and / or the work function configurations WF1 to WF4 described above with respect to Figures 5A to 5D.

[0130] In some embodiments, the allocation of a plurality of work function configurations according to the ROM encoding mode includes a ROM encoding mode corresponding to the array (e.g., array 110 as described above with respect to Figure 1).

[0131] In some embodiments, allocating a plurality of work function configurations includes performing a compilation operation to generate a ROM encoding pattern.

[0132] At operation 804, the first and second transistors are configured to include different work function configurations among a plurality of work function configurations. In some embodiments, configuring the first and second transistors includes configuring one or more IC layouts 200-400, including instances of memory cells 112 as described above with respect to Figures 2A to 4D.

[0133] In some embodiments, configuring the first and second transistors includes configuring one or more of the gate region G described above with respect to Figures 2A to 4D and / or the gate regions 500B to 500D described above with respect to Figures 5A to 5D.

[0134] In some embodiments, configuring the first and second transistors includes configuring a GAA transistor, a FinFET, or a planar transistor.

[0135] At operation 806, the first and second transistors are overlapped with vias and metal regions. The overlapping vias and metal regions include overlapping via regions on the gate regions and S / D regions of each transistor, and overlapping the via regions with at least one corresponding word line, bit line, and reference line, such that each of the first and second transistors is a working transistor.

[0136] In some embodiments, overlapping vias and metal regions include overlapping some or all of the via regions VG with the gate region G, overlapping the via region VD with the MD region MD, overlapping the character lines WL0~WL3 with the gate via region VGA, and overlapping the bit lines BL0~BL3 and the reference line VSS with the via region VD, as described above with respect to Figures 1 to 5D.

[0137] In some embodiments, the overlapping vias and metal regions include electrical connections configured to memory circuit components (e.g., the character line driver 120 and read interface 130 described above with respect to Figure 1).

[0138] At operation 808, in some embodiments, an IC layout diagram including the first and second transistors is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing one or more of the IC layout diagrams 200 to 400 described above with respect to Figures 2A to 5D in the storage device.

[0139] In some embodiments, storing an IC layout diagram in a storage device includes storing the IC layout diagram in non-volatile computer-readable memory or a database, and / or includes storing the IC layout diagram via a network. In some embodiments, storing an IC layout diagram in a storage device includes storing an IC wiring diagram in layout diagram 909 of the IC layout diagram generation system 900 and / or via network 914, as will be discussed below with reference to Figure 9.

[0140] At operation 810, in some embodiments, one or more manufacturing operations and one or more lithography exposures are performed based on the IC layout diagram. Non-limiting examples of performing one or more manufacturing operations (e.g., one or more lithography exposures) based on the IC layout diagram are discussed above with reference to Figure 7 and below with reference to Figure 10.

[0141] By performing some or all of the operations of method 800, an IC layout diagram corresponding to the IC devices including different work function configurations of the first and second transistors is generated, thereby enabling the benefits described above regarding memory circuit 100, IC devices 200-400, and IC structures 500B-500D.

[0142] Figure 9 is a block diagram of an IC layout generation system 900 according to some embodiments. The method for designing IC layouts described herein is implementable according to one or more embodiments; for example, according to some embodiments, an IC layout generation system 900 is used.

[0143] In some embodiments, the IC layout generation system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Among other things, the storage medium 904 is also encoded (i.e., stores) with computer program code 906, i.e., a set of executable instructions. The instructions 906, executed by the hardware processor 902, represent (at least partially) an electronic design automation (EDA) tool that implements part or all of a method, such as the IC layout generation method 800 described above with respect to Figure 8 (hereinafter referred to as the mentioned process and / or method).

[0144] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is used to execute computer program code 906 encoded in computer-readable storage medium 904 so that IC layout generation system 900 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0145] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 904 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0146] In one or more embodiments, computer-readable storage medium 904 stores computer program code 906 that enables IC layout generation system 900 (wherein this execution representation (at least partially) EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 904 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods.

[0147] In one or more embodiments, computer-readable storage medium 904 stores a cell library 907 including the cells disclosed herein, such as memory cells 112 of IC layout diagrams 200-400 described above with respect to Figures 1 to 5D.

[0148] In one or more embodiments, computer-readable storage medium 904 stores layout diagram 909, including IC layout diagrams disclosed herein, such as IC layout diagrams 200-400 described above with respect to Figures 1 to 5D.

[0149] The IC layout generation system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit system. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or directional keys for transmitting information and commands to the processor 902.

[0150] The IC layout generation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more IC layout generation systems 900.

[0151] The IC layout generation system 900 receives information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 902. This information is transferred to processor 902 via bus 908. The IC layout generation system 900 also receives UI-related information via I / O interface 910. This information is stored as a user interface (UI) 942 in computer-readable media 904.

[0152] In some embodiments, a portion or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, a portion or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, a portion or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, a portion or all of the mentioned processes and / or methods are implemented as a software application used by an IC layout generation system 900. In some embodiments, a layout diagram including standard cells is generated using tools such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0153] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM, memory cards), and one or more of the like.

[0154] Figure 10 is a block diagram of an IC manufacturing system 1000 according to some embodiments, and an associated IC manufacturing process. In some embodiments, based on an IC layout diagram, the manufacturing system 1000 is used to manufacture at least one of (A) one or more semiconductor photomasks or (B) at least one component of a layer of semiconductor integrated circuits.

[0155] In Figure 10, the IC manufacturing system 1000 includes entities such as a design plant 1020, a photomask plant 1030, and an IC manufacturer / fab ("fab") 1050, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of the IC device 1060. These entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design plant 1020, photomask plant 1030, and IC fabrication plant 1050 are owned by a single, larger company. In some embodiments, two or more of the design plant 1020, photomask plant 1030, and IC manufacturing plant 1050 coexist in a common facility and use common resources.

[0156] Design plant (or design team) 1020 generates IC design layout 1022. IC design layout 1022 includes various geometric patterns, such as one or more of the IC layouts 200-400 described above with respect to Figures 1 to 5D. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers constituting various components of the IC device 1060 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 1022 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, vias for metal lines or interlayer interconnects, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design plant 1020 performs appropriate design procedures to form IC design layout 1022. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1022 is presented in one or more data files containing geometric pattern information. For example, IC design layout diagram 1022 can be expressed in GDSII file format or DFII file format.

[0157] The photomask fabrication plant 1030 includes data preparation 1032 and photomask fabrication 1044. The photomask fabrication plant 1030 uses an IC design layout 1022 to fabricate one or more photomasks 1045 for manufacturing various layers of an IC device 1060 according to the IC design layout 1022. The photomask fabrication plant 1030 performs photomask data preparation 1032, in which the IC design layout 1022 is translated into a representative data file (RDF). The photomask data preparation 1032 provides the RDF to the photomask fabrication plant 1044. The photomask fabrication plant 1044 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (master photomask) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by the photomask data preparation 1032 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fabrication plant 1050. In Figure 10, photomask data preparation 1032 and photomask manufacturing 1044 are illustrated as separate components. In some embodiments, photomask data preparation 1032 and photomask manufacturing 1044 may be collectively referred to as photomask data preparation.

[0158] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, other process effects, and similar image errors. OPC adjustment IC design layout diagram 1022 is shown. In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and similar techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0159] In some embodiments, mask data preparation 1032 includes checking the IC design layout 1022 using a mask rule checker (MRC) that has undergone processing in an OPC using a set of mask generation rules containing certain geometric and / or connectivity constraints to ensure sufficient margin, account for the variability of semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for constraints during mask manufacturing 1044, which may undo modifications performed by the OPC to satisfy the mask generation rules.

[0160] In some embodiments, mask data preparation 1032 includes lithography process checking (LPC), which simulates the process performed by IC manufacturer 1050 to manufacture IC device 1060. LPC simulates this process based on IC design layout 1022 to produce a simulated manufacturing device, such as IC device 1060. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitability factors, and similar or combinations thereof. In some embodiments, after the simulated manufacturing device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0161] It should be understood that the above description of photomask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in a variety of different sequences.

[0162] After photomask data preparation 1032 and during photomask fabrication 1044, photomask 1045 or a group of photomasks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, photomask fabrication 1044 includes performing one or more lithography exposures based on the IC design layout 1022. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to pattern the photomask (photomask or reticle) 1045 based on the modified IC design layout 1022. The photomask 1045 can be formed using various techniques. In some embodiments, the photomask 1045 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams or EUV beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer, are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of photomask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas. In another example, photomask 1045 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of photomask 1045, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The photomask produced by photomask fabrication 1044 is used in a variety of processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0163] IC manufacturing plant 1050 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturing plant 1050 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of a plurality of IC products, a second manufacturing facility that can provide back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry business.

[0164] IC manufacturing plant 1050 includes wafer fabrication equipment 1052 for performing various manufacturing operations on semiconductor wafers 1053 to manufacture IC devices 1060 based on photomasks (e.g., photomask 1045). In various embodiments, fabrication equipment 1052 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication equipment capable of performing one or more suitable manufacturing processes described herein.

[0165] IC manufacturing plant 1050 uses multiple photomasks 1045 manufactured by photomask plant 1030 to manufacture IC device 1060. Therefore, IC manufacturing plant 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturing plant 1050 using multiple photomasks 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 further includes various doped regions, dielectric features, multilevel interconnects, and one or more of the like (formed in subsequent manufacturing steps).

[0166] In some embodiments, the IC device includes a first transistor and a second transistor. The first transistor includes a first gate coupled to a first word line and including a first work function configuration, a first metal-like defined (MD) segment adjacent to the first gate and coupled to one of the bit line or reference line, and a second MD segment adjacent to the first gate and coupled to the other of the bit line or reference line. The second transistor includes a second gate coupled to a second word line and including a second work function configuration different from the first work function configuration, a second MD segment adjacent to the second gate, and a third MD segment adjacent to the second gate and coupled to one of the bit line or reference line.

[0167] In some embodiments, the ROM circuit includes a plurality of word lines, a plurality of bit lines, a plurality of reference lines, and a plurality of ROM cells. Each ROM cell in the plurality of ROM cells includes a transistor and a sense amplifier. The transistor includes a first gate, a first MD segment, and a second MD segment. The first gate is coupled to a corresponding word line in the plurality of word lines and includes a corresponding work function configuration in the plurality of work function configurations. The second MD segment is adjacent to the first gate and coupled to a corresponding reference line in the plurality of reference lines. The sense amplifier is selectively coupled to each ROM cell in the plurality of ROM cells. The sense amplifier is used to output a plurality of bits having a work function configuration based on the plurality of work function configurations.

[0168] In some embodiments, a method of manufacturing an IC device includes constructing a first transistor, the first transistor comprising constructing a first gate including a first work function configuration, and forming first and second MD segments adjacent to the first gate; constructing a second transistor, the second transistor comprising constructing a second gate adjacent to the second MD segment and including a second work function configuration different from the first work function configuration, and forming a third MD segment adjacent to the second gate; forming first to fifth via structures on individual first to third MD segments and the first and second gates, forming one of a bit line or a reference line on each of the first and third via structures and forming the other of a bit line or reference line on the second via; and forming first and second word lines on individual fourth and fifth via structures.

[0169] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of an embodiment disclosed herein. Those skilled in the art should understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent structures can be modified, substituted, and replaced in various ways without departing from the spirit and scope of an embodiment disclosed herein.

[0170] 100: Memory Circuit 110: Array 112: Memory Unit 120: Character line driver 130: Read Interface 140: Control Circuit 142: Processor 144: Storage Media 200~400: IC Device / Layout Diagram 500B~500D: IC Structure / Layout Diagram 600: Method 602~606: Operation 700: Method 702~706: Operation 800: Method 802~810: Operation 900: IC Layout Generation System 902: Processor 904: Computer-readable storage media 906: Instruction 907: Unit Library 908: Busbar 909: Layout Diagram 910:I / O interface 912: Network Interface 914: Internet 942:UI 1000: IC Manufacturing System 1020: Design Factory 1022: (IC) Design Layout Diagram 1030: Photomask Factory 1032: Data Preparation 1044: Photomask Manufacturing 1045: Light Mask 1050: (IC) Manufacturer 1052: Manufacturing equipment 1053: Semiconductor wafer 1060: IC device AA: Active Zone / Area DG / G: Gate Region / Structure MD:MD area / segment SD:S / D area / structure S VD / VG: Through-hole region / structure VTh1~VTh4: Threshold voltage WF: Work Function Configuration WF1~WF4: Work function configuration W1

[00] , W2

[01] : Signals W3

[10] , W4

[11] : Signals WL0~WL3: Character lines BL, BL0~BL3: Bit lines VSS: Reference Line CTRL: Control signal CTRLB: Control Signal Bus

[0171] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit (IC) device comprising: a first transistor comprising: a first gate coupled to a first word line and including a first work function configuration; a first metal boundary (MD) segment adjacent to the first gate and coupled to one of a bit line or a reference line; and a second metal boundary segment adjacent to the first gate and coupled to the other of the bit line or the reference line; and a second transistor comprising: a second gate coupled to a second word line and including a second work function configuration different from the first work function configuration; the second metal boundary segment adjacent to the second gate; and a third metal boundary segment adjacent to the second gate and coupled to the other of the bit line or the reference line.

2. The integrated circuit device as claimed in claim 1, wherein the first transistor further comprises: a third gate adjacent to and coupled to the first type-metal boundary segment; and a fourth type-metal boundary segment adjacent to and coupled to the other of the bit line or the reference line, and the second transistor further comprises: a fourth gate adjacent to and coupled to the second word line; and a fifth type-metal boundary segment adjacent to and coupled to the fourth gate, and coupled to the other of the bit line or the reference line.

3. The integrated circuit device as claimed in claim 2, further comprising: an active region extending between a first edge adjacent to the fourth type of metal defining segment and a second edge adjacent to the fifth type of metal defining segment; a fifth gate covering the first edge; and a sixth gate covering the second edge; wherein the first to fifth type of metal defining segments are positioned on the active region between the fifth and sixth gates.

4. The integrated circuit device as claimed in claim 1, further comprising: an active region; a third gate covering the active region adjacent to the first type of metal-defined segment and coupled to the reference line; and a fourth gate covering the active region adjacent to the third type of metal-defined segment and coupled to the reference line, wherein the first to third type of metal-defined segments are located on the active region between the third and fourth gates.

5. The integrated circuit device as claimed in claim 1, further comprising: an active region extending between a first edge adjacent to the first type of metal defining segment and a second edge adjacent to the third type of metal defining segment; a third gate covering the first edge; and a fourth gate covering the second edge, wherein the first to third type of metal defining segments are located on the active region between the third and fourth gates.

6. The integrated circuit device as claimed in claim 1, further comprising: a first via structure extending between the first type of metal-defined section and the bit line or the reference line; a second via structure extending between the second type of metal-defined section and the other of the bit line or the reference line; and a third via structure extending between the third type of metal-defined section and the bit line or the reference line.

7. The integrated circuit arrangement as claimed in claim 1, wherein each of the first and second transistors comprises: a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), or a planar transistor.

8. A read-only memory (ROM) circuit comprising: a plurality of word lines; a plurality of bit lines; a plurality of reference lines; a plurality of read-only memory cells, wherein one of the read-only memory cells comprises a first transistor, the first transistor comprising: a first gate coupled to a corresponding word line among the word lines, and comprising a corresponding work function configuration among a plurality of work function configurations; a first metal boundary (MD) segment adjacent to the first gate and coupled to a corresponding bit line among the bit lines; and a second metal boundary segment adjacent to the first gate and coupled to a corresponding reference line among the reference lines; wherein another of the read-only memory cells comprises a second transistor, the second transistor comprising: a second gate coupled to a second word line and comprising another corresponding work function configuration among a plurality of work function configurations; The second type of metal defining segment is adjacent to the second gate; and a third type of metal defining segment is adjacent to the second gate and coupled to the corresponding bit line among the bit lines; and a sense amplifier is selectively coupled to each read-only memory cell among the read-only memory cells, wherein the sense amplifier is used to output a complex number of bits having multiple values ​​based on the work function configuration among the work function configurations.

9. The read-only memory circuit as described in claim 8, wherein the total number of one of the work function configurations is equal to four, and the total number of one bit of the bits is equal to two.

10. A method of manufacturing an integrated circuit (IC) device, the method comprising the steps of: constructing a first transistor, the step of constructing the first transistor comprising the steps of: constructing a first gate including a first work function configuration; and forming first and second type-metal boundary (MD) segments adjacent to the first gate; constructing a second transistor, the step of constructing the second transistor comprising the steps of: constructing a second gate adjacent to the second type-metal boundary segment and including a second work function configuration different from the first work function configuration; and forming a third type-metal boundary segment adjacent to the second gate; forming first to fifth via structures individually on the first to third type-metal boundary segments and the first and second gates; forming one of a bit line or a reference line on each of the first and third via structures, forming the other of the bit line or the reference line on the second via structure; and forming first and second word lines individually on the fourth and fifth via structures.

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